STMicroelectronics-M24LR64E-RMC6T-2
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M24LR64E-R
Dynamic NFC/RFID tag IC with 64-Kbit EEPROM,
energy harvesting, I²C bus and ISO 15693 RF interface
Datasheet
–
production data
in low (6.6 kbit/s) or high (26 kbit/s) data rate
mode. Supports the 53 kbit/s data rate with
Fast commands
•
Internal tuning capacitance: 27.5 pF
SO8 (MN)
UFDFPN8 (MC)
•
64-bit unique identifier (UID)
TSSOP8 (DW)
2 x 3 mm
•
Read Block & Write (32-bit blocks)
Digital output pin
•
User configurable pin: RF write in progress or
RF busy mode
Energy harvesting
Wafer (SB12I)
Wafer (RUW20)
•
Analog pin for energy harvesting
•
Four sink current configurable ranges
Features
•
Belonging to ST25 family, which includes all
Temperature range
NFC/RF ID tag and reader products from ST
•
From –40 to 85 °C
I
2
C interface
Memory
2
•
Two-wires I
C serial interface supports
•
64-Kbit EEPROM organized into:
400 kHz protocol
2
– 8192
bytes in I
C mode
•
Single supply voltage:
– 2048
blocks of 32 bits in RF mode
– 1.8
V to 5.5 V
•
Write time
•
Byte and Page Write (up to 4 bytes)
•
Random and Sequential read modes
•
Self-timed programming cycle
•
Automatic address incrementing
•
Enhanced ESD/latch-up protection
•
I²C timeout
2
– I
C: 5 ms (max.)
– RF:
5.75 ms including the internal Verify
time
•
Write cycling endurance:
– 1
million write cycles at 25 °C
– 150
k write cycles at 85 °C
•
More than 40-year data retention
Contactless interface
•
Multiple password protection in RF mode
2
•
ISO 15693 and ISO 18000-3 mode 1 compatible
•
Single password protection in I
C mode
•
13.56 MHz ± 7 kHz carrier frequency
Package
•
To tag: 10% or 100% ASK modulation using 1/4 (26
Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding
®
•
SO8 (ECOPACK2
)
®
•
TSSOP8 (ECOPACK2
)
•
From tag: load modulation using Manchester
®
coding with 423 kHz and 484 kHz subcarriers
•
UFDFPN8 (ECOPACK2
)
July 2017
DocID022712 Rev 12
1/144
This is information on a product in full production.
1
Contents
M24LR64E-R
Contents
Signal descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Serial data (SDA)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Antenna coil (AC0, AC1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
V
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Supply voltage (V
CC
) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
CC .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
6
Power-up conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
I
C device operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
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Contents
Acknowledge bit (Ack)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
I²C timeout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Memory addressing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
Write operations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
Byte write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Page write
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
5.11 Read
operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
5.12 Random
Address Read
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
5.13 Current
Address Read
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
5.14 Sequential
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
5.15 Acknowledge
in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
2
2
RF device operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
Initial dialog for vicinity cards
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
Power transfer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Frequency .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Operating field
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Communication signal from VCD to M24LR64E-R . . . . . . . . . . . . . . . . 45
Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Data coding mode: 1 out of 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
VCD to M24LR64E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
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Contents
M24LR64E-R
Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Communication signal from M24LR64E-R to VCD . . . . . . . . . . . . . . . . 51
10.1
Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
10.2
Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
10.3
Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
Bit representation and coding
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1
Bit coding using one subcarrier
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
High data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2
Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
High data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
M24LR64E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1
SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
12.1.1 High
data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1.2 Low
data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.2 SOF
when using two subcarriers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
12.2.1 High
data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.2.2 Low
data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3 EOF
when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
12.3.1 High
data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.3.2 Low
data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.4 EOF
when using two subcarriers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
12.4.1 High
data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.4.2 Low
data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Unique identifier (UID)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.1
CRC .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
M24LR64E-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Contents
17.1 Power-off
state .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
17.2 Ready
state .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
17.3 Quiet
state .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
17.4 Selected
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
18.1
Addressed mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
18.3
Select mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
Request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
19.1 Request
flags .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
20.1 Response
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
20.2 Response
error code
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
21.1 Request
parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
Timing definition
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
25.2 t2:
VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Command codes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
26.1 Inventory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
26.2 Stay
Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
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Contents
M24LR64E-R
26.3 Read
Single Block
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
26.4 Write
Single Block
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
26.5 Read
Multiple Block
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
26.6 Select
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
26.7 Reset
to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
26.8 Write
AFI .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
26.9 Lock
AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
26.10 Write
DSFID .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
26.11 Lock
DSFID .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
26.12 Get
System Info
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
26.13 Get
Multiple Block Security Status
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
26.14 Write-sector
Password .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
26.15 Lock-sector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
26.16 Present-sector
Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
26.17 Fast
Read Single Block
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
26.18 Fast
Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
26.19 Fast
Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
26.20 Fast
Read Multiple Block
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
26.21 Inventory
Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
109
26.22 Initiate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
11
26.23 ReadCfg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
11
26.24 WriteEHCfg .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
26.25 WriteDOCfg .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
26.26 SetRstEHEn
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
26.27 CheckEHEn .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
2
I
C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Write cycle definition
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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Contents
31.1 SO8N
package information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
Part numbering
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
Appendix B
CRC (informative)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of tables
M24LR64E-R
List of tables
Address most significant byt
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
8
M24LR64E-R sector security protection after power-u
p
. . . . . . . . . . . . . . . . . . . . . . . . . . .
2
6
Operating modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10% modulation parameter
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
UID format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CRC transmission rules
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
M24LR64E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
General request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
7
Response error code definitio
n
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
0
Inventory request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1
Example of the addition of 0-bits to an 11-bit mask value
. . . . . . . . . . . . . . . . . . . . . . . . . 71
Inventory request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
9
Stay Quiet request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
1
Read Single Block request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Write Single Block request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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List of tables
Reset to Ready request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
Write AFI response format when Error_flag is set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Lock AFI response format when Error_flag is NOT set
. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Lock AFI response format when Error_flag is se
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
2
Write DSFID response format when Error_flag is NOT set
. . . . . . . . . . . . . . . . . . . . . . . . 94
Write DSFID response format when Error_flag is se
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4
Lock DSFID request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Error_flag is NOT set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Error_flag is NOT set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Write-sector Password response format when Error_flag is se
t
. . . . . . . . . . . . . . . . . . . .
1
00
Lock-sector request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
01
Present-sector Password response format when Error_flag is se
t
. . . . . . . . . . . . . . . . . .
1
03
Fast Read Single Block request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Fast Inventory Initiated response format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Fast Initiate request forma
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
07
Fast Initiate response format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DocID022712 Rev 12
9/144
List of tables
M24LR64E-R
Table 100.
Inventory Initiated response format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 101.
Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 102.
Initiate response format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 103.
ReadCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 104.
ReadCfg response format when Error_flag is NOT set
. . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 105.
ReadCfg response format when Error_flag is se
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
12
Table 106.
WriteEHCfg request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 107.
WriteEHCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 108.
WriteEHCfg response format when Error_flag is set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 109.
WriteDOCfg request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 110.
WriteDOCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 111.
WriteDOCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 112.
SetRstEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 113.
SetRstEHEn response format when Error_flag is NOT set
. . . . . . . . . . . . . . . . . . . . . . . 116
Table 114.
SetRstEHEn response format when Error_flag is se
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
16
Table 115.
CheckEHEn request format
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 116.
CheckEHEn response format when Error_flag is NOT se
t
. . . . . . . . . . . . . . . . . . . . . . . .
1
17
Table 117.
CheckEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 118.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 119.
I
C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 120.
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 121.
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 122.
I
C DC characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2
Table 123.
I
C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 124.
Write cycle endurance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 125.
RF characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 126.
Operating condition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
26
Table 127.
Energy harvesting
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
package mechanical dat
a
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
31
package mechanical dat
a
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
35
Table 131.
Ordering information scheme for packaged devices
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 132.
Ordering and marking information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 133.
CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 134.
AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 135.
Document revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10/144
DocID022712 Rev 12
M24LR64E-R
List of figures
List of figures
8-pin package connection
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
4
value versus bus parasitic
C
bus
cap
acitance (C
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
bus
2
I
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10.
Write cycle polling flowchart using Ac
k
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
6
Figure 11.
Read mode sequence
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
7
Figure 12.
I
C present password command
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2
Figure 13.
I
C write password comman
d
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
0
Figure 14.
100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15.
10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16.
1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17.
Detail of a time perio
d
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
8
Figure 18.
1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 19.
1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 20.
SOF to select 1 out of 256 data coding mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21.
SOF to select 1 out of 4 data coding mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22.
EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23.
Logic 0, high data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24.
Logic 0, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25.
Logic 1, high data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26.
Logic 1, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 27.
Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28.
Logic 0, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 29.
Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 30.
Logic 1, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 31.
Logic 0, high data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 32.
Logic 1, high data rate
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 33.
Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 34.
Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 35.
Start of frame, high data rate, one subcarrie
r
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
Figure 36.
Start of frame, high data rate, one subcarrier, fast commands. . . . . . . . . . . . . . . . . . . . . . 55
Figure 37.
Start of frame, low data rate, one subcarrier
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 38.
Start of frame, low data rate, one subcarrier, fast commands
. . . . . . . . . . . . . . . . . . . . . . 56
Figure 39.
Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 40.
Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 41.
End of frame, high data rate, one subcarrier
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 42.
End of frame, high data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 57
Figure 43.
End of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 44.
End of frame, low data rate, one subcarrier, Fast commands
. . . . . . . . . . . . . . . . . . . . . . 57
Figure 45.
End of frame, high data rate, two subcarrier
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
8
Figure 46.
End of frame, low data rate, two subcarriers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 47.
M24LR64E-R decision tree for AF
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
0
DocID022712 Rev 12
11/144
List of figures
M24LR64E-R
Figure 48.
M24LR64E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 49.
M24LR64E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 50.
Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 72
Figure 51.
Description of a possible anticollision sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 52.
M24LR64E RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . 80
Figure 53.
Stay Quiet frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . 81
Figure 54.
Read Single Block frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . 83
Figure 55.
Write Single Block frame exchange between VCD and M24LR64E-
R
. . . . . . . . . . . . . . . .
8
4
Figure 56.
M24LR64E RF-Busy management following Write command . . . . . . . . . . . . . . . . . . . . . . 85
Figure 57.
M24LR64E RF-Wip management following Write command . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 58.
Read Multiple Block frame exchange between VCD and M24LR64E-R
. . . . . . . . . . . . . . 88
Figure 59.
Select frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 60.
Reset to Ready frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . 90
Figure 61.
Write AFI frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 62.
Lock AFI frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 63.
Write DSFID frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 95
Figure 64.
Lock DSFID frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . . . . . . 96
Figure 65.
Get System Info frame exchange between VCD and M24LR64E-R
. . . . . . . . . . . . . . . . . 98
Figure 67.
Write-sector Password frame exchange between VCD and M24LR64E-R . . . . . . . . . . . 101
Figure 68.
Lock-sector frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 102
Figure 70.
Fast Read Single Block frame exchange between VCD and M24LR64E-R. . . . . . . . . . . 105
Figure 71.
Fast Initiate frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 107
Figure 73.
Initiate frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 74.
ReadCfg frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . 112
Figure 75.
WriteEHCfg frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 114
Figure 76.
WriteDOCfg frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . . . . . 115
Figure 77.
SetRstEHEn frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . 116
Figure 78.
CheckEHEn frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . . . . . 118
Figure 79.
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 80.
I
C AC waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 81.
ASK modulated signal
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 82.
Energy harvesting: Vout min vs. Isink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 83.
Energy harvesting: working domain range 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 84.
Energy harvesting: working domain range 10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 85.
Energy harvesting: working domain range 01
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 86.
Energy harvesting: working domain range 00
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 87.
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 131
package recommended footprint
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
dual flat package outlin
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
33
12/144
DocID022712 Rev 12
M24LR64E-R
Description
1
Description
The M24LR64E-R device is a Dynamic NFC/RFID tag IC with a dual-interface, electrically
2
erasable programmable memory (EEPROM). It features an I
C interface and can be
operated from a V
power supply. It is also a contactless memory powered by the received
CC
2
carrier electromagnetic wave. The M24LR64E-R is organized as 8192 × 8 bits in the I C
mode and as 2048 × 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode.
The M24LR64E-R also features an energy harvesting analog output, as well as a
user-configurable digital output pin toggling during either RF write in progress or RF busy
mode.
Figure 1. Logic diagram
9
&&
6&/
6’$
9
RXW
0ꢀꢁ/5ꢂꢁ(ꢃ5
$&ꢄ
$&ꢅ
5)ꢉ:,3ꢊ%86<
9
66
06Yꢆꢇꢈꢇꢁ9ꢅ
2
The I
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line.
The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the
2
I C
bus definition.
2
The device behaves as a slave in the I
C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
th
When writing data to the memory, the device inserts an acknowledge bit during the 9
bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master,
the bus master acknowledges the receipt of the data byte in the same way. Data transfers
are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64E-R is accessed via the
13.56 MHz carrier electromagnetic wave on which incoming data is demodulated from the
received signal amplitude modulation (ASK: Amplitude Shift Keying). When connected to an
antenna, the operating power is derived from the RF energy and no external power supply is
required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s
DocID022712 Rev 12
13/144
Description
M24LR64E-R
using the 1 out of 256 pulse coding mode, or a data rate of 26 Kbit/s using the 1 out of 4
pulse coding mode.
Outgoing data is generated by the M24LR64E-R load variation using Manchester coding
with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data is transferred from the
M24LR64E-R at 6.6 Kbit/s in low data rate mode and at 26 Kbit/s in high data rate mode.
The M24LR64E-R supports the 53 Kbit/s fast mode in high data rate mode using one
subcarrier frequency at 423 kHz.
The M24LR64E-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for
radio-frequency power and signal interface.
The M24LR64E-R provides an Energy harvesting mode on the analog output pin V
.
out
When the Energy harvesting mode is activated, the M24LR64E-R can output the excess
energy coming from the RF field on the V
analog pin. In case the RF field strength is
out
insufficient or when the Energy harvesting mode is disabled, the analog output pin V
goes
out
into high-Z state and the Energy harvesting mode is automatically stopped.
The M24LR64E-R features a user configurable digital out pin RF WIP/BUSY that can be
used to drive a microcontroller interrupt input pin (available only when the M24LR64E-R is
correctly powered on the V
pin).
CC
When configured in the RF write in progress mode (RF WIP mode), the RF WIP/BUSY pin is
driven low for the entire duration of the RF internal write operation. When configured in the
RF busy mode (RF BUSY mode), the RF WIP/BUSY pin is driven low for the entire duration
of the RF command progress.
The RF WIP/BUSY pin is an open drain output and must be connected to a pull-up resistor.
Table 1. Signal names
Signal name
Function
Direction
V
out
Energy harvesting Output
Serial Data
Analog output
SDA
I/O
SCL
Serial Clock
Input
AC0, AC1
V
CC
Antenna coils
Supply voltage
Digital signal
Ground
I/O
–
RF WIP/BUSY
V
SS
Digital output
–
Figure 2. 8-pin package connections
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14/144
DocID022712 Rev 12
M24LR64E-R
Signal descriptions
2
Signal descriptions
2.1
Serial clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
CC
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
2.3
2.4
Serial data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
CC
the value of the pull-up resistor can be calculated).
RF Write in progress / RF Busy (RF WIP/BUSY)
This configurable output signal is used either to indicate that the M24LR64E-R is executing
an internal write cycle from the RF channel or that an RF command is in progress. RF WIP
and signals are available only when the M24LR64E-R is powered by the Vcc pin. It is an
open drain output and a pull-up resistor must be connected from RF WIP/BUSY to V
.
CC
Energy harvesting analog output (V
out
)
This analog output pin is used to deliver the analog voltage V
available when the Energy
out
harvesting mode is enabled and the RF field strength is sufficient. When the Energy
harvesting mode is disabled or the RF field strength is not sufficient, the energy harvesting
analog voltage output Vout is in High-Z state.
2.5
Antenna coil (AC0, AC1)
These inputs are used to connect the device to an external coil exclusively. It is advised not
to connect any other DC or AC path to AC0 or AC1.
When correctly tuned, the coil is used to power and access the device using the ISO 15693
and ISO 18000-3 mode 1 protocols.
2.5.1
Device reset in RF mode
To
e
nsure a proper reset of the RF circuitry, the RF field must be turned off (100%
modulation) for a minimum t
period of time.
RF_OFF
DocID022712 Rev 12
15/144
Signal descriptions
M24LR64E-R
2.6
V
SS
ground
V
is the reference for the V
supply voltage and V
analog output voltage.
CC out
SS
2.7
Supply voltage (V
CC
)
This pin can be connected to an external DC supply voltage.
Note:
An internal voltage regulator allows the external voltage applied on V
to supply the
CC
M24LR64E-R, while preventing the internal power supply (rectified RF waveforms) to output
a DC voltage on the V
pin.
CC
2.7.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V
voltage
CC
CC
CC
suitable capacitor (usually around 10 nF) close to the V
/V package
pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal I²C write cycle (t
).
W
2.7.2
2.7.3
Power-up conditions
When the power supply is turned on, V
rises from V
to V
. The V
rise time must not
vary faster than 1V/µs.
CC
SS
CC
CC
Device reset in I²C mode
In order to prevent inadvertent write operations during power-up, a power-on reset (POR)
circuit is included. At power-up (continuous rise of V
), the device does not respond to any
CC
I²C instruction until V
has reached the power-on reset threshold voltage (this threshold is
CC
CC
CC
the device must not be accessed until V
has reached a valid and stable V
voltage
CC
CC
within the specified [V
(min), V
(max)] range.
CC
CC
In a similar way, during power-down (continuous decrease in V
), as soon as V
drops
CC
CC
below the power-on reset threshold voltage, the device stops responding to any instruction
sent to it.
2.7.4
Power-down conditions
During power-down (continuous decay of V
), the device must be in Standby power mode
CC
(mode reached after decoding a Stop condition, assuming that there is no internal write
cycle in progress).
16/144
DocID022712 Rev 12
M24LR64E-R
Signal descriptions
2
Figure 3. I
C Fast mode (f
= 400 kHz): maximum R
value versus bus parasitic
C
bus
capacitance (C
)
bus
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2
Figure 4. I C bus protocol
DocID022712 Rev 12
17/144
Signal descriptions
M24LR64E-R
Table 2. Device select code
Device type identifier
(1)
Chip Enable address
RW
–
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
1
0
1
0
E2
(2)
1
1
RW
1. The
most significant bit, b7, is sent first.
2. E2
is not connected to any external pin. It is however used to address the M24LR64E-R as
Table 3. Address most significant byte
b15
b7
b14
b6
b13
b12
b11
b10
b9
b1
b8
b0
Table 4. Address least significant byte
b5 b4 b3 b2
18/144
DocID022712 Rev 12
M24LR64E-R
User memory organization
3
User memory organization
Figure 6
shows the memory sector organization. Each sector can be individually read-
and/or write-protected using a specific password command. Read and write operations are
possible if the addressed data is not in a protected sector.
The M24LR64E-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user in RF device
operation and its value is written by ST on the production line.
The M24LR64E-R includes an AFI register that stores the application family identifier, and a
DSFID register that stores the data storage family identifier used in the anticollision
algorithm.
2
The M24LR64E-R has four 32-bit blocks that store an I
C password plus three RF password
codes.
Figure 5. Circuit diagram
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DocID022712 Rev 12
19/144
User memory organization
M24LR64E-R
Figure 6. Memory sector organization
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Sector details
The M24LR64E-R user memory is divided into 64 sectors. Each sector contains 1024 bits.
In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by
block. Read and write block accesses are controlled by a Sector Security Status byte that
defines the access rights to the 32 blocks contained in the sector. If the sector is not
protected, a Write command updates the complete 32 bits of the selected block.
2
In I
C mode, a sector provides 128 bytes that can be individually accessed in Read and
Write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is
2
write-protected.
T
o
a
ccess the user memory, the device select code used for any I
C
command must have the E2 Chip Enable address at 0.
20/144
DocID022712 Rev 12
M24LR64E-R
User memory organization
Table 5. Sector details
I
2
C byte
Sector
number
RF block
address
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
address
0
0
4
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
1
2
8
3
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
124
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
DocID022712 Rev 12
21/144
User memory organization
M24LR64E-R
Bits [7:0]
Table 5. Sector details (continued)
Sector
RF block
I
2
C byte
Bits [31:24]
Bits [23:16]
address
Bits [15:8]
number
address
32
33
34
35
36
37
38
39
128
132
136
140
144
148
152
156
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
1
22/144
DocID022712 Rev 12
M24LR64E-R
User memory organization
Table 5. Sector details (continued)
Sector
number
RF block
address
I
2
C byte
Bits [31:24]
Bits [23:16]
address
Bits [15:8]
Bits [7:0]
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
8064
8068
8072
8076
8080
8084
8088
8092
8096
8100
8104
8108
8112
8116
8120
8124
8128
8132
8136
8140
8144
8148
8152
8156
8160
8164
8168
8172
8176
8180
8184
8188
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
user
63
DocID022712 Rev 12
23/144
System memory area
M24LR64E-R
4
System memory area
4.1
M24LR64E-R block security in RF mode
The M24LR64E-R provides a special protection mechanism based on passwords. In RF
mode, each memory sector of the M24LR64E-R can be individually protected by one out of
three available passwords, and each sector can also have Read/Write access conditions
set.
Each memory sector of the M24LR64E-R is assigned with a Sector security status byte
including a Sector Lock bit, two Password Control bits and two Read/Write protection bits,
using the Read Single Block and Read Multiple Block commands with the Option_flag set
to 1.
On delivery, the default value of the SSS bytes is set to 00h.
Table 6. Sector security status byte area
I
2
C byte address
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
0
SSS 3
SSS 7
SSS 2
SSS 6
SSS 1
SSS 5
SSS 0
SSS 4
4
8
SSS 11
SSS 15
SSS 19
SSS 23
SSS 27
SSS 31
SSS 35
SSS 39
SSS 43
SSS 47
SSS 51
SSS 55
SSS 59
SSS 63
SSS 10
SSS 14
SSS 18
SSS 22
SSS 26
SSS 30
SSS 34
SSS 38
SSS 42
SSS 46
SSS 50
SSS 54
SSS 58
SSS 62
SSS 9
SSS 8
12
16
20
24
28
32
36
40
44
48
52
56
60
SSS 13
SSS 17
SSS 21
SSS 25
SSS 29
SSS 33
SSS 37
SSS 41
SSS 45
SSS 49
SSS 53
SSS 57
SSS 61
SSS 12
SSS 16
SSS 20
SSS 24
SSS 28
SSS 32
SSS 36
SSS 40
SSS 44
SSS 48
SSS 52
SSS 56
SSS 60
Table 7. Sector security status byte organization
b
7
b
6
b
5
b
4
b
3
b
2
Read / Write
protection bits
b
1
b
0
Sector
Lock
0
0
0
Password control bits
24/144
DocID022712 Rev 12
M24LR64E-R
System memory area
When the Sector Lock bit is set to 1, for instance by issuing a Lock-sector command, the
two Read/Write protection bits (b , b ) are used to set the Read/Write access of the sector
1
2
Table 8. Read/Write protection bit setting
Sector access
Sector access
when password not presented
Sector
b
2
, b
1
Lock
when password presented
0
1
1
1
1
xx
00
01
10
11
Read
Read
Read
Read
Read
Write
Write
Read
Read
Write
No Write
Write
Write
Read
Write
No Read
No Read
No Write
No Write
No Write
The next two bits of the Sector security status byte (b , b ) are the password control bits.
3
4
Table 9. Password control bits
b
4
, b
3
Password
00
01
10
11
The sector is not protected by a password.
The sector is protected by password 1.
The sector is protected by password 2.
The sector is protected by password 3.
The M24LR64E-R password protection is organized around a dedicated set of commands,
plus a system area of three password blocks where the password values are stored. This
Table 10. Password system area
Add
Password
1
2
3
Password 1
Password 2
Password 3
The dedicated commands for protection in RF mode are:
•
Write-sector password:
The Write-sector password command is used to write a 32-bit block into the password
system area. This command must be used to update password values. After the write
cycle, the new password value is automatically activated. It is possible to modify a
password value after issuing a valid Present-sector password command. On delivery,
the three default password values are set to 0000 0000h and are activated.
•
Lock-sector:
The Lock-sector command is used to set the sector security status byte of the selected
sector. Bits b
to b
of the sector security status byte are affected by the Lock-sector
4
1
DocID022712 Rev 12
25/144
System memory area
M24LR64E-R
command. The sector lock bit, b , is set to 1 automatically. After issuing a Lock-sector
0
command, the protection settings of the selected sector are activated. The protection of
a locked block cannot be changed in RF mode. A Lock-sector command sent to a
locked sector returns an error code.
•
•
Present-sector password:
The Present-sector password command is used to present one of the three passwords
to the M24LR64E-R in order to modify the access rights of all the memory sectors
password is correct, the access rights remain activated until the tag is powered off or
until a new Present-sector password command is issued. If the presented password
value is not correct, all the access rights of all the memory sectors are deactivated.
2
Sector security status byte area access conditions in I
C mode:
2
In I
C mode, read access to the sector security status byte area is always allowed.
2
Write access depends on the correct presentation of the I C password (see
2
To
a
ccess the Sector security status byte area, the device select code used for any I
C
command must have the E2 Chip Enable address at 1.
2
An I
C write access to a sector security status byte re-initializes the RF access
condition to the given memory sector.
4.1.1
Example of the M24LR64E-R security protection in RF mode
after power-up. After a valid Present-sector password command with password 1, the
Table 11. M24LR64E-R sector security protection after power-up
Sector security status byte
Sector
Sector features
address
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
0
1
2
3
4
Protection: standard
Protection: password 1
Protection: password 1
Protection: password 1
Protection: password 1
Read
Read
No Write
No Write
Write
xxx
xxx
xxx
xxx
xxx
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
1
1
1
1
1
Read
No Read
No Read
No Write
No Write
Table 12. M24LR64E-R sector security protection after a valid presentation of
password 1
Sector security status byte
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Sector
address
Sector features
0
1
2
Protection: standard
Read
Read
Read
No Write
Write
xxx
xxx
xxx
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
Protection: password 1
Protection: password 1
Write
26/144
DocID022712 Rev 12
M24LR64E-R
System memory area
Table 12. M24LR64E-R sector security protection after a valid presentation of
password 1 (continued)
Sector security status byte
Sector
address
Sector features
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
3
4
Protection: password 1
Protection: password 1
Read
Read
Write
xxx
xxx
0
0
1
1
1
1
0
1
1
1
No Write
4.2
M24LR64E-R block security in I²C mode (I2C_Write_Lock bit
area)
2
In the I
C mode only, it is possible to protect individual sectors against Write operations.
This feature is controlled by the I2C_Write_Lock bits stored in the 8 bytes of the
2
To
a
ccess the I2C_Write_Lock bit area, the device select code used for any I
C command
must have the E2 Chip Enable address at 1.
Using these 16 bits, it is possible to write-protect all the 64 sectors of the M24LR64E-R
2
2
is always possible to unprotect a sector in the I
C mode. When an I2C_Write_Lock bit is
reset to 0, the corresponding sector is unprotected. When the bit is set to 1, the
corresponding sector is write-protected.
2
In I
C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access
2
depends on the correct presentation of the I C password.
On delivery, the default value of the eight bytes of the I2C_Write_Lock bit area is reset to
00h.
Table 13. I2C_Write_Lock bit
I
2
C byte address
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
E2 = 1
E2 = 1
2048
2052
sectors 31-24
sectors 63-56
sectors 23-16
sectors 55-48
sectors 15-8
sectors 7-0
sectors 47-40
sectors 39-32
4.3
Configuration byte and Control register
The M24LR64E-R offers an 8-bit non-volatile Configuration byte located at I²C location 2320
of the system area used to store the RF WIP/BUSY pin and the energy harvesting
The M24LR64E-R also offers an 8-bit volatile Control register located at I²C location 2336 of
the system area used to store the energy harvesting enable bit as well as a FIELD_ON bit
4.3.1
RF WIP/BUSY pin configuration
The M24LR64E-R features a configurable open drain output RF WIP/BUSY pin used to
provide RF activity information to an external device.
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System memory area
M24LR64E-R
The RF WIP/BUSY pin functionality depends on the value of bit 3 of the Configuration byte.
RF busy mode
•
When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF
busy mode.
The purpose of this mode is to indicate to the I²C bus master whether the M24LR64E-R is
busy in RF mode or not.
In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF)
until the end of the command execution.
If a bad RF command is received, the RF WIP/BUSY pin is tied to 0 from the RF command
SOF until the reception of the RF command CRC. Otherwise, the RF WIP/BUSY pin is in
high-Z state.
When tied to 0, the RF WIP/BUSY signal returns to High-Z state if the RF field is cut-off.
During the execution of I²C commands, the RF WIP/BUSY pin remains in high-Z state.
•
RF Write in progress
When bit 3 of the Configuration byte is set to 1, the RF WIP/BUSY pin is configured in RF
Write in progress mode.
The purpose of this mode is to indicate to the I²C bus master that some data has been
changed in RF mode.
In this mode, the RF WIP/BUSY pin is tied to 0 for the duration of an internal write operation
(i.e. between the end of a valid RF write command and the beginning of the RF answer).
During the execution of I²C write operations, the RF WIP/BUSY pin remains in high-Z state.
4.3.2
Energy harvesting configuration
The M24LR64E-R features an Energy harvesting mode on the V
analog output.
out
The general purpose of the Energy harvesting mode is to deliver a part of the non-
necessary RF power received by the M24LR64E-R on the AC0-AC1 RF input in order to
supply an external device. The current consumption on the analog voltage output V
is
out
limited to ensure that the M24LR64E-R is correctly supplied during the powering of the
external device.
When the Energy harvesting mode is enabled and the power delivered on the AC0-AC1 RF
input exceeds the minimum required P
, the M24LR64E-R is able to deliver a
AC0-AC1_min
limited and unregulated voltage on the V
pin, assuming the current consumption on the
out
V
does not exceed the I
maximum value.
out
sink_max
If one of the conditions above is not met, the analog voltage output pin V
is set in High-Z
out
state.
For robust applications using the Energy harvesting mode, four current fan-out levels can be
chosen.
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M24LR64E-R
System memory area
•
V
sink current configuration
out
The sink current level is chosen by programming EH_cfg1 and EH_cfg0 into the
The minimum power level required on AC0-AC1 RF input P
, the delivered
AC0-AC1_min
voltage V
, as well as the maximum current consumption I
on the V
pin
out
sink_max
Table 14. Configuration byte
I
2
C byte address
Bit 7
Bit 6
Bit 5
Bit 4
E2=1 2320
X
(1)
X
(1)
X
(1)
X
(1)
1. Bit
7 to bit 4 are don’t care bits.
Bit 3
Bit 2
BIT 1
BIT 0
RF WIP/BUSY
EH_mode EH_cfg1 EH_cfg0
•
Energy harvesting enable control
Delivery of Energy harvesting analog output voltage on the V
pin depends on the value of
Table 15. Control register
I
2
C byte address
E2=1 2336
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
BIT 1
BIT 0
T-Prog
(1)
0
(1)
0
(1)
0
(1)
0
(1)
0
(1)
FIELD_ON
(1)
EH_enable
1. Bit
7 to bit 1 are read-only bits.
–
When set to 1, the EH_enable bit enables the Energy harvesting mode, meaning
that the V
analog output signal is delivered when the P
and I
sink_max
out
AC0-AC1_min
conditions corresponding to the chosen sink current configuration bit are met (see
–
–
When set to 0, the EH_enable bit disables the Energy harvesting mode and the
analog output V
remains in High-Z state.
out
The T_Prog flag indicates a correct duration of the I²C write time (tw). This bit is
reset to 0 after POR and at the beginning of each writing cycle; it is set to 1 only
after a correct completion of the writing cycle.
•
Energy harvesting default mode control
At power-up, in I²C or RF mode, the EH_enable bit is updated according to the value of the
the EH_mode bit is used to configure whether the Energy harvesting mode is enabled or not
by default.
Table 16. EH_enable bit value after power-up
Energy harvesting
EH_mode value
EH_enable after power-up
after power-up
0
1
1
0
enabled
disabled
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System memory area
M24LR64E-R
4.3.3
FIELD_ON indicator bit
The FIELD_ON indicator bit located as bit 1 of the Control register is a read-only bit used to
indicate when the RF power level delivered to the M24LR64E-R is sufficient to execute RF
commands.
•
•
When FIELD_ON = 0, the M24LR64E-R is not able to execute any RF commands.
When FIELD_ON =1, the M24LR64E-R is able to execute any RF commands.
Note:
During read access to the Control register in RF mode, the FIELD_ON bit is always read
at 1.
4.3.4
Configuration byte access in I²C and RF modes
In I²C mode, read and write accesses to the non-volatile Configuration byte are always
allowed.
T
o
a
ccess the Configuration byte, the device select code used for any I²C
command must have the E2 Chip enable address at 1.
The dedicated commands to access the Configuration byte in RF mode are:
•
Read configuration byte command (ReadCfg):
The ReadCfg command is used to read the eight bits of the Configuration byte.
Write energy harvesting configuration command (WriteEHCfg):
–
•
–
The WriteEHCfg command is used to write the EH_mode, EH_cfg1 and EH_cfg0
bits into the Configuration byte.
•
Write RF WIP/BUSY pin configuration command (WriteDOCfg):
–
The WriteDOCfg command is used to write the RF WIP/BUSY bit into the
Configuration byte.
After any write access to the Configuration byte, the new configuration is automatically
applied.
4.3.5
Control register access in I²C or RF mode
In I²C mode, read and write accesses to the volatile Control register are always allowed.
T
o
access the Control register, the device select code used for any I²C command must have
the E2 Chip enable address at 1.
The dedicated commands to access the Control register in RF mode are:
•
Check energy harvesting enable bit command (CheckEHEn):
–
The CheckEHEn command is used to read the eight bits of the Control register.
When it is run, the FIELD_ON bit is always read at 1.
•
Set/reset energy harvesting enable bit command (SetRstEHEn):
–
The SetRstEHEn command is used to set or reset the value of the EH_enable bit
into the Control register.
4.4
ISO 15693 system parameters
The M24LR64E-R provides the system area required by the ISO 15693 RF protocol, as
2
2
The first 32-bit block starting from I
C address 2304 stores the I
C password. This
2
password is used to activate/deactivate the write protection of the protected sector in I
C
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System memory area
mode. At power-on, all user memory sectors protected by the I2C_Write_Lock bits can be
2
read but cannot be modified.
T
o
r
emove the write protection, it is necessary to use the I C
is, when all the presented bits correspond to the stored ones — it is also possible to modify
2
2
The next three 32-bit blocks store the three RF passwords. These passwords are neither
2
read- nor write- accessible in the I
C mode.
The next byte stores the Configuration byte, at I²C location 2320. This Control register is
used to store the three energy harvesting configuration bits and the RF WIP/BUSY
configuration bit.
2
2
The next two bytes are used to store the AFI, at I
C location 2322, and the DSFID, at I C
location 2323. These two values are used during the RF inventory sequence. They are
read-only in the I
C mode.
2
The next eight bytes, starting from location 2324, store the 64-bit UID programmed by ST on
2
the production line. Bytes at I
C locations 2332 to 2335 store the IC Ref and the Mem_Size
data used by the RF Get_System_Info command. The UID, Mem_Size and IC ref values are
read-only data.
Table 17. System parameter sector
I
2
C byte address
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
E2 = 1
2304
2308
2312
2316
2320
2324
2328
2332
I
2
C password
(1)
RF password 1
(1)
RF password 2
(1)
RF password 3
(1)
DSFID (FFh)
UID
AFI (00h)
UID
ST reserved (Exh)
(2)
Configuration byte (F4h)
UID
UID
UID
UID
UID (E0h)
UID (02h)
Mem_Size (03 07FFh)
IC Ref (5Eh)
Prog. completion and
E2 = 1
2336
–
–
–
Energy harvesting status
(3)
1. Delivery
state: I
2
C password = 0000 0000h, RF password = 0000 0000h, Configuration byte =
F4h
2. The
product revision is the Most significant nibble of the byte located at address 0x911 (2321 d)
in the system area (Device select code E2 =1). From DS rev4, the product revision value is
0xE. The Least significant nibble is ST reserved.
3. Address
system 2336 (920h, E2=1) is the control register.
significant and set to 0.
Bits 2-6 are RFU and set to 0.
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2
I C
device operation
M24LR64E-R
2
5
I C
device operation
2
data to the bus is defined as a transmitter, and any device that reads data is defined as a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which also
provides the serial clock for synchronization. The M24LR64E-R device is a slave in all
communications.
5.1
5.2
Start condition
Start is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable
in the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a write cycle) the SDA and the SCL for a Start
condition, and does not respond unless one is given.
Stop condition
Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal write cycle.
5.3
Acknowledge bit (Ack)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether a bus master or a slave device, releases the serial data (SDA) after sending eight
th
bits of data. During the 9
clock pulse period, the receiver pulls the SDA low to
acknowledge the receipt of the eight data bits.
5.4
5.5
Data input
During data input, the device samples serial data (SDA) on the rising edge of the serial clock
(SCL). For correct device operation, the SDA must be stable during the rising edge of the
SCL, and the SDA signal must change
only
when the SCL is driven low.
I²C timeout
During the execution of an I²C operation, RF communications are not possible.
To
p
revent RF communication freezing due to inadvertent unterminated instructions sent to
the I²C bus, the M24LR64E-R features a timeout mechanism that automatically resets the
I²C logic block.
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M24LR64E-R
I C device operation
5.5.1
I²C timeout on Start condition
I²C communication with the M24LR64E-R starts with a valid Start condition, followed by a
device select code.
If the delay between the Start condition and the following rising edge of the Serial Clock
(SCL) that samples the most significant of the Device Select exceeds the t
time
START_OUT
until the next valid Start condition.
Figure 7. I²C timeout on Start condition
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5.5.2
I²C timeout on clock period
condition.
5.6
Memory addressing
To
s
tart a communication between the bus master and the slave device, the bus master
must initiate a Start condition. Following this, the bus master sends the device select code,
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
“Address” (E2,1,1).
T
o
a
ddress the memory array, the 4-bit device type identifier is 1010b.
The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
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2
I C
device operation
M24LR64E-R
Table 18. Operating modes
Bytes
Mode
RW bit
Initial sequence
Current address read
Random address read
1
0
1
1
0
0
1
1
Start, device select, RW = 1
Start, device select, RW = 0, address
reStart, device select, RW = 1
Sequential read
Byte write
≥
1
1
Similar to current or random address read
Start, device select, RW = 0
Page write
≤
4 bytes
Start, device select, RW = 0
Figure 8. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited)
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5.7
Write operations
Following a Start condition, the bus master sends a device select code with the Read/Write
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction
issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented does not
modify the memory contents, and the accompanying data bytes are
not
acknowledged, as
Each data byte in the memory has a 16-bit (two-byte wide) address. The most significant
the address of the byte in memory.
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M24LR64E-R
I C device operation
When the bus master generates a Stop condition immediately after the Ack bit (in the tenth-
bit time slot), either at the end of a byte write or a page write, the internal write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal write cycle.
After the Stop condition, the delay t
, and the successful completion of a Write operation,
W
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the
device does not respond to any requests.
5.8
5.9
Byte write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies
with NoAck, and the location is not modified. If the addressed location is not write-protected,
the device replies with Ack. The bus master terminates the transfer by generating a Stop
Page write
The Page write mode allows up to four bytes to be written in a single write cycle, provided
that they are all located in the same “row” in the memory: that is, the most significant
memory address bits (b12-b2) are the same. If more bytes are sent than fit up to the end of
the row, a condition known as “roll-over” occurs. This should be avoided, as data starts to
become overwritten in an implementation-dependent way.
The bus master sends from one to four bytes of data, each of which is acknowledged by the
device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the
I2C_Write_Lock_bit = 1 and the I2C_password are not presented, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
Figure 9. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled)
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I C
device operation
M24LR64E-R
Figure 10. Write cycle polling flowchart using Ack
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5.10
Minimizing system delays by polling on Ack
During the internal write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum I²C write time (t
w
) is
can be used by the bus master.
1. Initial
condition: a write cycle is in progress.
2. Step
1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3. Step
2: if the device is busy with the internal write cycle, no Ack is returned and the bus
master goes back to Step 1. If the device has terminated the internal write cycle, it
responds with an Ack, indicating that the device is ready to receive the second part of
the instruction (the first byte of this instruction having been sent during Step 1).
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M24LR64E-R
I C device operation
Figure 11. Read mode sequences
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1. The
seven most significant bits of the device select code of a random read (in the first and fourth bytes)
must be identical.
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2
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device operation
M24LR64E-R
5.11
Read operations
Read operations are performed independently of the state of the I2C_Write_Lock bit.
After the successful completion of a read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
5.12
Random Address Read
A dummy write is first performed to load the address into this address counter (as shown in
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must
not
acknowledge the byte, and terminates the transfer with a Stop condition.
5.13
5.14
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master
does
acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence.
T
o
t
erminate the stream of
bytes, the bus master must
not
acknowledge the last byte, and
must
generate a Stop
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls over”, and the device continues to output data from memory
address 00h.
5.15
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the ninth bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
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I C device operation
5.16
M24LR64E-R I
2
C password security
2
2
The M24LR64E-R controls I
C sector write access using the 32-bit-long I C password and
2
2
the 64-bit I2C_Write_Lock bit area. The I C password value is managed using two I
C
commands: I C present password and I C write password.
2
2
2
5.16.1
I C present password command description
2
2
The I
C present password command is used in I C mode to present the password to the
M24LR64E-R in order to modify the write access rights of all the memory sectors protected
by the I2C_Write_Lock bits, including the password itself. If the presented password is
correct, the access rights remain activated until the M24LR64E-R is powered off or until a
2
new I C present password command is issued.
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown
2
responds to each address byte with an acknowledge bit, and then waits for the four
password data bytes, the validation code, 09h, and a resend of the four password data
bytes. The most significant byte of the password is sent first, followed by the least significant
bytes.
It is necessary to send the 32-bit password twice to prevent any data corruption during the
sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64E-R
does not start the internal comparison.
When the bus master generates a Stop condition immediately after the Ack bit (during the
tenth bit time slot), an internal delay equivalent to the write cycle time is triggered. A Stop
condition at any other time does not trigger the internal delay. During that delay, the
2
M24LR64E-R compares the 32 received data bits with the 32 bits of the stored I C
password. If the values match, the write access rights to all protected sectors are modified
after the internal delay. If the values do not match, the protected sectors remain protected.
During the internal delay, the serial data (SDA) signal is disabled internally, and the device
does not respond to any requests.
2
Figure 12. I
C present password command
!CK
!CK
!CK
!CK
!CK
!CK
!CK
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DocID022712 Rev 12
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2
I C
device operation
M24LR64E-R
2
5.16.2
I C
write password command description
2
2
The I
C write password command is used to write a 32-bit block into the M24LR64E-R I C
2
2
password system area. This command is used in I
C mode to update the I C password
value. It cannot be used to update any of the RF passwords. After the write cycle, the new
I C
password value is automatically activated. The I
C password value can only be modified
2
2
2
after issuing a valid I C present password command.
2
On delivery, the I
C default password value is set to 0000 0000h and is activated.
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown
2
responds to each address byte with an acknowledge bit, and then waits for the four
password data bytes, the validation code, 07h, and a resend of the four password data
bytes. The most significant byte of the password is sent first, followed by the least significant
bytes.
It is necessary to send twice the 32-bit password to prevent any data corruption during the
write sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64E-
2
R does not modify the I C password value.
When the bus master generates a Stop condition immediately after the Ack bit (during the
tenth bit time slot), the internal write cycle is triggered. A Stop condition at any other time
does not trigger the internal write cycle.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the
device does not respond to any requests.
2
Figure 13. I C write password command
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DocID022712 Rev 12
M24LR64E-R
M24LR64E-R memory initial state
6
M24LR64E-R memory initial state
The device is delivered with all bits in the user memory array set to 1 (each byte contains
FFh).
The DSFID is programmed to FFh and the AFI is programmed to 00h.
Configuration byte set to F4h:
•
•
•
•
Bit 7 to bit 4: all set to 1
Bit 3: set to 0 (RF BUSY mode on RF WIP/BUSY pin)
Bit 2: set to 1 (Energy harvesting not activated by default)
Bit 1 and bit 0: set to 0
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RF device operation
M24LR64E-R
7
RF device operation
Each sector can be individually read- and/or write-protected using a specific lock or
password command.
Read and Write operations are possible if the addressed block is not protected. During a
Write, the 32 bits of the block are replaced by the new 32-bit value.
The M24LR64E-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user in RF device
operation and its value is written by ST on the production line.
The M24LR64E-R also includes an AFI register in which the application family identifier is
stored, and a DSFID register in which the data storage family identifier used in the
anticollision algorithm is stored.
The M24LR64E-R has three 32-bit blocks in which the password codes are stored and an 8-
bit Configuration byte in which the Energy harvesting mode and RF WIP/BUSY pin
configuration is stored.
7.1
RF communication and energy harvesting
As the current consumption can affect the AC signal delivered by the antenna, RF
communications with M24LR64E-R are not guaranteed during voltage delivery on the
energy harvesting analog output V
.
out
RF communication can disturb and possibly stop Energy Harvesting mode.
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DocID022712 Rev 12
M24LR64E-R
RF device operation
7.2
Commands
The M24LR64E-R supports the following commands:
•
•
Inventory
, used to perform the anticollision sequence.
Stay quiet
, used to put the M24LR64E-R in quiet mode, where it does not respond to
any inventory command.
•
Select
, used to select the M24LR64E-R. After this command, the M24LR64E-R
processes all Read/Write commands with Select_flag set.
•
•
•
Reset to ready
, used to put the M24LR64E-R in the ready state.
Read block
, used to output the 32 bits of the selected block and its locking status.
Write block
, used to write the 32-bit value in the selected block, provided that it is not
locked.
•
•
•
•
•
•
•
Read multiple blocks
, used to read the selected blocks and send back their value.
Write AFI
, used to write the 8-bit value in the AFI register.
Lock AFI
, used to lock the AFI register.
Write DSFID
, used to write the 8-bit value in the DSFID register.
Lock DSFID
, used to lock the DSFID register.
Get system info
, used to provide the system information value.
Get multiple block security status
, used to send the security status of the selected
block.
•
•
Initiate
, used to trigger the tag response to the Inventory initiated sequence.
Inventory initiated
, used to perform the anticollision sequence triggered by the Initiate
command.
•
•
•
Write-sector password
, used to write the 32 bits of the selected password.
Lock-sector
, used to write the sector security status bits of the selected sector.
Present-sector password
, enables the user to present a password to unprotect the
user blocks linked to this password.
•
•
Fast initiate
, used to trigger the tag response to the Inventory initiated sequence.
Fast inventory initiated
, used to perform the anticollision sequence triggered by the
Initiate command.
•
•
Fast read single block
, used to output the 32 bits of the selected block and its locking
status.
Fast read multiple blocks
, used to read the selected blocks and send back their
value.
•
•
ReadCfg,
used to read the 8-bit Configuration byte and send back its value.
WriteEHCfg
, used to write the energy harvesting configuration bits into the
Configuration byte.
•
WriteDOCfg
, used to write the RF WIP/BUSY pin configuration bit into the
Configuration byte.
•
•
SetRstEHEn
, used to set or reset the EH_enable bit into the volatile Control register.
CheckEHEn
, used to send back the value of the volatile Control register.
DocID022712 Rev 12
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RF device operation
M24LR64E-R
7.3
Initial dialog for vicinity cards
The dialog between the vicinity coupling device or VCD (commonly the “RF reader”) and the
vicinity integrated circuit card or VICC (M24LR64E-R) takes place as follows:
•
•
•
activation of the M24LR64E-R by the RF operating field of the VCD
transmission of a command by the VCD
transmission of a response by the M24LR64E-R.
These operations use the RF power transfer and communication signal interface described
(Reader talks first).
7.3.1
Power transfer
Power is transferred to the M24LR64E-R by radio frequency at 13.56 MHz via coupling
antennas in the M24LR64E-R and the VCD. The RF operating field of the VCD is
transformed on the M24LR64E-R antenna to an AC voltage which is rectified, filtered and
internally regulated.
During communications, the amplitude modulation (ASK) on this received signal is
demodulated by the ASK demodulator.
7.3.2
7.3.3
Frequency
The ISO 15693 standard defines the carrier frequency (
f
) of the operating field as
13.56 MHz ±7 kHz.
C
Operating field
The M24LR64E-R operates continuously between the minimum and maximum values of the
limits.
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DocID022712 Rev 12
M24LR64E-R
Communication signal from VCD to M24LR64E-R
8
Communication signal from VCD to M24LR64E-R
Communications between the VCD and the M24LR64E-R take place using the modulation
principle of ASK (Amplitude shift keying). Two modulation indexes are used, 10% and
100%. The M24LR64E-R decodes both. The VCD determines which index is used.
The modulation index is defined as [a – b]/[a + b], where a is the peak signal amplitude, and
b the minimum signal amplitude of the carrier frequency.
The M24LR64E-R is operational for the 100% modulation index or for any degree of
Figure 14. 100% modulation waveform
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Symbol
Parameter definition
Value
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max
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Communication signal from VCD to M24LR64E-R
M24LR64E-R
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DocID022712 Rev 12
M24LR64E-R
Data rate and data coding
9
Data rate and data coding
The data coding implemented in the M24LR64E-R uses pulse position modulation. Both
data coding modes that are described in the ISO15693 are supported by the M24LR64E-R.
The selection is made by the VCD and indicated to the M24LR64E-R within the start of
frame (SOF).
9.1
Data coding mode: 1 out of 256
The value of a single byte is represented by the position of one pause. The position of the
pause on one of 256 successive time periods of 18.88 µs (256/
f
) determines the value of
C
the byte. In this case, the transmission of one byte takes 4.833 ms and the resulting data
rate is 1.65 Kbits/s (
f
/8192).
C
Figure 16
illustrates this pulse position modulation technique. In this figure, data E1h (225
decimal) is sent by the VCD to the M24LR64E-R.
The pause occurs during the second half of the position of the time period that determines
A pause during the first period transmits the data value 00h. A pause during the last period
transmits the data value FFh (255 decimal).
Figure 16. 1 out of 256 coding mode
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DocID022712 Rev 12
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Data rate and data coding
M24LR64E-R
Figure 17. Detail of a time period
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9.2
Data coding mode: 1 out of 4
The value of two bits is represented by the position of one pause. The position of the pause
on one of four successive time periods of 18.88 µs (256/
f
) determines the value of the two
C
bits. Four successive pairs of bits form a byte, where the least significant pair of bits is
transmitted first.
In this case, the transmission of one byte takes 302.08 µs and the resulting data rate is
48/144
DocID022712 Rev 12
M24LR64E-R
Data rate and data coding
Figure 18. 1 out of 4 coding mode
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9.3
VCD to M24LR64E-R frames
Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are
implemented using code violation. Unused options are reserved for future use.
The M24LR64E-R is ready to receive a new command frame from the VCD 311.5 µs after
sending a response frame to the VCD.
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Data rate and data coding
M24LR64E-R
The M24LR64E-R takes a power-up time of 0.1 ms after being activated by the powering
field. After this delay, the M24LR64E-R is ready to receive a command frame from the VCD.
9.4
Start of frame (SOF)
The SOF defines the data coding mode the VCD is to use for the following command frame.
Figure 20. SOF to select 1 out of 256 data coding mode
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DocID022712 Rev 12
M24LR64E-R
Communication signal from M24LR64E-R to VCD
10
Communication signal from M24LR64E-R to VCD
The M24LR64E-R has several modes defined for some parameters, so that it can operate in
various noise environments and meet various application requirements.
10.1
Load modulation
The M24LR64E-R is capable of communicating to the VCD via an inductive coupling area
whereby the carrier is loaded to generate a subcarrier with frequency
f
. The subcarrier is
S
generated by switching a load in the M24LR64E-R.
The load-modulated amplitude received on the VCD antenna must be of at least 10 mV
when measured, as described in the test methods defined in International Standard
ISO10373-7.
10.2
10.3
Subcarrier
The M24LR64E-R supports the one-subcarrier and two-subcarriers response formats.
These formats are selected by the VCD using the first bit in the protocol header. When one
subcarrier is used, the frequency
f
of the subcarrier load modulation is 423.75 kHz (
f
/32).
S1
C
When two subcarriers are used, the frequency
f
is 423.75 kHz (
f
/32), and frequency
f
S1
C
S2
is 484.28 kHz (
f
/28). When using the two-subcarriers mode, the M24LR64E-R generates a
C
continuous phase relationship between
f
and
f
.
S1
S2
Data rates
The M24LR64E-R can respond using the low or the high data rate format. The selection of
the data rate is made by the VCD using the second bit in the protocol header. For fast
rates produced by the M24LR64E-R using the different response format combinations.
Table 20. Response data rates
Data rate
One subcarrier
Two subcarriers
Standard commands
Fast commands
6.62 Kbit/s (
f
c
/2048)
13.24 Kbit/s (
f
c
/1024)
26.48 Kbit/s (
f
c
/512)
52.97 Kbit/s (
f
c
/256)
6.67 Kbit/s (
f
c
/2032)
Not applicable
Low
Standard commands
Fast commands
26.69 Kbit/s (
f
c
/508)
Not applicable
High
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Bit representation and coding
M24LR64E-R
11
Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For
the low data rate, same subcarrier frequency or frequencies is/are used. In this case, the
number of pulses is multiplied by 4 and all times increase by this factor. For the Fast
commands using one subcarrier, all pulse numbers and times are divided by 2.
11.1
Bit coding using one subcarrier
11.1.1
High data rate
A logic 0 starts with eight pulses at 423.75 kHz (f
/32) followed by an unmodulated time of
C
Figure 23. Logic 0, high data rate
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C
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A logic 1 starts with an unmodulated time of 18.88 µs followed by eight pulses at 423.75 kHz
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For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by
C
Figure 26. Logic 1, high data rate, fast commands
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DocID022712 Rev 12
M24LR64E-R
Bit representation and coding
11.1.2
Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (f
/32) followed by an unmodulated time of
C
Figure 27. Logic 0, low data rate
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For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (f
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C
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A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz
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Figure 30. Logic 1, low data rate, fast commands
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Bit representation and coding
M24LR64E-R
11.2
Bit coding using two subcarriers
11.2.1
High data rate
A logic 0 starts with eight pulses at 423.75 kHz (f
/32) followed by nine pulses at
C
C
for the Fast commands.
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A logic 1 starts with nine pulses at 484.28 kHz (f
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for the Fast commands.
Figure 32. Logic 1, high data rate
ϯϳ͘ϰϲꢀђƐ
ĂŝϭϮϬϳϯ
11.2.2
Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (f
/32) followed by 36 pulses at 484.28 kHz
C
C
commands.
Figure 33. Logic 0, low data rate
ꢌ
ꢁ
ꢇ
ꢅ
ꢁ
ꢉ
ꢊ
ꢋ
ꢇ
ꢆ
ꢌ
ꢈꢂ
ꢂ
ꢈ
A logic 1 starts with 36 pulses at 484.28 kHz (f
/28) followed by 32 pulses at 423.75 kHz
C
C
commands.
Figure 34. Logic 1, low data rate
ꢌ
ꢁ
ꢀ
ꢇ
ꢁ
ꢂ
ꢉ
ꢍ
ꢃ
ꢅ
ꢌ
ꢈꢂꢆ
ꢆ
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DocID022712 Rev 12
M24LR64E-R
M24LR64E-R to VCD frames
12
M24LR64E-R to VCD frames
Frames are delimited by an SOF and an EO
F
.
T
hey are implemented using code violation.
Unused options are reserved for future use. For the low data rate, the same subcarrier
frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4.
For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.
12.1
SOF when using one subcarrier
12.1.1
High data rate
The SOF includes an unmodulated time of 56.64 µs, followed by 24 pulses at 423.75 kHz
(f /32),
and a logic 1 that consists of an unmodulated time of 18.88 µs followed by eight
C
Figure 35. Start of frame, high data rate, one subcarrier
ꢌꢌ
ꢀ
ꢇ
ꢈ
ꢁ
ꢉ
ꢂ
ꢃ
ꢀꢁꢂꢁꢃꢄꢅꢆ
ꢅ
ꢌ
ꢈꢂ
ꢆ
ꢁ
For the Fast commands, the SOF comprises an unmodulated time of 28.32 µs, followed by
12 pulses at 423.75 kHz (f
/32), and a logic 1 that consists of an unmodulated time of
C
Figure 36. Start of frame, high data rate, one subcarrier, fast commands
ϱϲ͘ϲϰꢀђƐ
ϭϴ͘ϴϴꢀђƐ
ĂŝϭϮϬϳϵ
12.1.2
Low data rate
The SOF comprises an unmodulated time of 226.56 µs, followed by 96 pulses at 423.75
kHz (
f
/32), and a logic 1 that consists of an unmodulated time of 75.52 µs followed by 32
C
Figure 37. Start of frame, low data rate, one subcarrier
ϰϱϯ͘ϭϮꢀђƐ
ϭϱϭ͘ϬϰꢀђƐ
ĂŝϭϮϬϴϬď
DocID022712 Rev 12
55/144
M24LR64E-R to VCD frames
M24LR64E-R
For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by
48 pulses at 423.75 kHz (
f
/32), and a logic 1 that includes an unmodulated time of
C
Figure 38. Start of frame, low data rate, one subcarrier, fast commands
ꢈꢈ
ꢇ
ꢄ ꢉ
ꢊ
ꢋ
ꢆ
ꢇ
ꢄ ꢉ
ꢊ
ꢋ
ꢇ
ꢆ
ꢌ
ꢈꢂ
ꢁ
ꢌ
12.2
SOF when using two subcarriers
12.2.1
High data rate
The SOF comprises 27 pulses at 484.28 kHz (
f
/28), followed by 24 pulses at 423.75 kHz
C
(
f
/32), and a logic 1 that includes nine pulses at 484.28 kHz followed by eight pulses at
C
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 39. Start of frame, high data rate, two subcarriers
ϭϭϮ͘ϯϵꢀђƐ
ϯϳ͘ϰϲꢀђƐ
ĂŝϭϮϬϴϮ
12.2.2
Low data rate
The SOF comprises 108 pulses at 484.28 kHz (
f
/28), followed by 96 pulses at 423.75 kHz
C
(
f
/32), and a logic 1 that includes 36 pulses at 484.28 kHz followed by 32 pulses at
C
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 40. Start of frame, low data rate, two subcarriers
ϰϰϵ͘ϱϲꢀђƐ
ϭϰϵ͘ϴϰꢀђƐ
ĂŝϭϮϬϴϯ
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DocID022712 Rev 12
M24LR64E-R
M24LR64E-R to VCD frames
12.3
EOF when using one subcarrier
12.3.1
High data rate
The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and an unmodulated
time of 18.88 µs, followed by 24 pulses at 423.75 kHz (
f
/32), and by an unmodulated time
C
Figure 41. End of frame, high data rate, one subcarrier
ꢅꢆ
ꢇ
ꢆ
ꢇ
ꢉ
ꢍ
ꢁ
ꢌꢌ
ꢀ
ꢇ
ꢈ
ꢀ
ꢉ
ꢍ
ꢁ
ꢃ
ꢌ
ꢈꢂ
ꢀ
ꢄ
For the Fast commands, the EOF comprises a logic 0 that includes four pulses at
423.75 kHz and an unmodulated time of 9.44 µs, followed by 12 pulses at 423.75 kHz
C
Figure 42. End of frame, high data rate, one subcarrier, fast commands
ꢀ
ꢇꢂꢇ
ꢁ
ꢄꢈꢉ
ꢂ
ꢌꢂꢌꢌꢄꢈꢉ
ꢊꢋ
ꢂꢃꢄ
ꢌ
ꢀ
12.3.2
Low data rate
The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and an unmodulated
time of 75.52 µs, followed by 96 pulses at 423.75 kHz (
f
/32) and an unmodulated time of
C
Figure 43. End of frame, low data rate, one subcarrier
ꢀꢁꢂ
ꢂ
ꢃꢄ
ꢄꢍ
ꢅ
ꢃꢁꢃ
ꢂ
ꢈꢀ
ꢄꢍ
ꢅ
ꢆꢇꢃꢄꢈꢉꢊ
For the Fast commands, the EOF comprises a logic 0 that includes 16 pulses at 423.75 kHz
and an unmodulated time of 37.76 µs, followed by 48 pulses at 423.75 kHz (
f
/32) and an
C
Figure 44. End of frame, low data rate, one subcarrier, Fast commands
ꢅꢁ
ꢂ
ꢁꢃ
ꢄꢈꢉ
ꢄꢄ
ꢀ
ꢂ
ꢁꢀ
ꢄꢈꢉ
ꢊꢋ
ꢂꢃꢄ
ꢌ
ꢅ
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M24LR64E-R to VCD frames
M24LR64E-R
12.4
EOF when using two subcarriers
12.4.1
High data rate
The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and nine pulses at
484.28 kHz, followed by 24 pulses at 423.75 kHz (
f
/32) and 27 pulses at 484.28 kHz
C
C
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 45. End of frame, high data rate, two subcarriers
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ꢀꢀꢁꢂꢃꢄꢅV
06ꢆꢇꢈꢀꢉ9ꢀ
12.4.2
Low data rate
The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and 36 pulses at
484.28 kHz, followed by 96 pulses at 423.75 kHz (
f
/32) and 108 pulses at 484.28 kHz
C
C
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 46. End of frame, low data rate, two subcarriers
ϭϰϵ͘ϴϰꢀђƐ
ϰϰϵ͘ϱϲꢀђƐ
ĂŝϭϮϬϴϵ
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DocID022712 Rev 12
M24LR64E-R
Unique identifier (UID)
13
Unique identifier (UID)
The M24LR64E-R is uniquely identified by a 64-bit unique identifier (UID). This UID
complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and
comprises:
•
•
•
eight MSBs with a value of E0h,
the IC manufacturer code “ST 02h” on 8 bits (ISO/IEC 7816-6/AM1),
a unique serial number on 48 bits.
Table 21. UID format
MSB
63
LSB
0
56 55
48 47
0xE0
0x02
Unique serial number
With the UID, each M24LR64E-R can be addressed uniquely and individually during the
anticollision loop and for one-to-one exchanges between a VCD and an M24LR64E-R.
DocID022712 Rev 12
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Application family identifier (AFI)
M24LR64E-R
14
Application family identifier (AFI)
The AFI (application family identifier) represents the type of application targeted by the VCD
and is used to identify, among all the M24LR64E-Rs present, only those that meet the
required application criteria.
Figure 47. M24LR64E-R decision tree for AFI
)NVENTORY REQUEST
RECEIVED
.O
!&) FLAG
SET ꢅ
9
E
S
.O
!&) VALUE
ꢄ ꢃ ꢅ
9
E
S
!&) VALUE
ꢄ )NTERNAL
VALUE ꢅ
.O
9
E
S
!NSWER GIVEN BY THE -ꢆꢇ2&ꢈꢇ
TO THE )NVENTORY REQUEST
.O ANSWER
!)ꢀꢁꢀꢂꢃ
The AFI is programmed by the M24LR64E-R issuer (or purchaser) in the AFI register. Once
programmed and locked, it can no longer be modified.
The most significant nibble of the AFI is used to code one specific or all application families.
The least significant nibble of the AFI is used to code one specific or all application
subfamilies. Subfamily codes different from 0 are proprietary.
See also ISO 15693-3 documentation.
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DocID022712 Rev 12
M24LR64E-R
Data storage format identifier (DSFID)
15
Data storage format identifier (DSFID)
The data storage format identifier indicates how the data is structured in the M24LR64E-R
memory. The logical organization of data can be known instantly using the DSFID. It can be
programmed and locked using the Write DSFID and Lock DSFID commands.
15.1
CRC
The CRC used in the M24LR64E-R is calculated as per the definition in ISO/IEC 13239. The
initial register contents are all 1s: “FFFF”.
The two-byte CRC is appended to each request and response, within each frame, before
the EO
F
.
T
he CRC is calculated on all the bytes after the SOF up to the CRC field.
Upon reception of a request from the VCD, the M24LR64E-R verifies that the CRC value is
valid. If it is invalid, the M24LR64E-R discards the frame and does not answer the VCD.
Upon reception of a response from the M24LR64E-R, it is recommended that the VCD
verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the
VCD designer judgment.
The CRC is transmitted least significant byte first. Each byte is transmitted least significant
bit first.
Table 22. CRC transmission rules
LSByte
LSByte
LSBit
MSBit LSBit
MSBit
CRC 16 (8 bits)
CRC 16 (8 bits)
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M24LR64E-R protocol description
M24LR64E-R
16
M24LR64E-R protocol description
The transmission protocol (or simply “the protocol”) defines the mechanism used to
exchange instructions and data between the VCD and the M24LR64E-R in both directions.
It is based on the concept of “VCD talks first”.
This means that an M24LR64E-R does not start transmitting unless it has received and
properly decoded an instruction sent by the VCD. The protocol is based on an exchange of:
•
•
a request from the VCD to the M24LR64E-R,
a response from the M24LR64E-R to the VCD.
Each request and each response are contained in a frame. The frame delimiters (SO
F
,
Each request consists of:
•
•
•
•
•
•
•
flags,
a command code,
parameters depending on the command,
application data,
a 2-byte CRC,
Each response consists of:
•
•
•
•
•
•
flags,
parameters depending on the command,
application data,
a 2-byte CRC,
The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight
(8), that is an integer number of bytes.
A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is
transmitted least significant byte (LSByte) first and each byte is transmitted least significant
bit (LSBit) first.
The setting of the flags indicates the presence of the optional fields. When the flag is set (to
one), the field is present. When the flag is reset (to zero), the field is absent.
Table 23. VCD request frame format
Request
SOF
Request
EOF
Request_flags Command
code Parameters
Data
2-byte CRC
Table 24. M24LR64E-R Response frame format
Response
SOF
Response
EOF
Response_flags
Parameters
Data
2-byte CRC
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M24LR64E-R states
M24LR64E-R
17
M24LR64E-R states
An M24LR64E-R can be in one of four states:
•
•
•
•
Power-off
Ready
Quiet
Selected
17.1
17.2
Power-off state
The M24LR64E-R is in the Power-off state when it does not receive enough energy from the
VCD.
Ready state
The M24LR64E-R is in the Ready state when it receives enough energy from the VCD.
When in the Ready state, the M24LR64E-R answers any request where the Select_flag is
not set.
17.3
17.4
Quiet state
When in the Quiet state, the M24LR64E-R answers any request except for Inventory
requests with the Address_flag set.
Selected state
•
•
•
Request in Select mode with the Select_flag set
Request in Addressed mode if the UID matches
Request in Non-Addressed mode as it is the mode for general requests
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DocID022712 Rev 12
M24LR64E-R
M24LR64E-R states
Table 25. M24LR64E-R response depending on Request_flags
Address_flag Select_flag
Flags
1
0
1
0
Addressed
Non addressed
Selected
Non selected
M24LR64E-R in Ready or
Selected state (Devices in Quiet
state do not answer)
–
–
X
X
–
–
X
–
X
–
M24LR64E-R in Selected state
M24LR64E-R in Ready, Quiet or
Selected state (the device which
matches the UID)
X
X
X
–
Error (03h)
–
X
Figure 49. M24LR64E-R state transition diagram
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$QꢅRWKHUꢅFRPPDQG
$,ꢉꢊꢊꢋꢀE
1. The
M24LR64E-R returns to the Power Off state if the tag is out of the RF field for at least t
RF_OFF
. Refer to
application note AN4125 for more information.
2. The
intention of the state transition method is that only one M24LR64E-R should be in the Selected state at
a time.
DocID022712 Rev 12
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Modes
M24LR64E-R
18
Modes
The term “mode” refers to the mechanism used in a request to specify the set of
M24LR64E-Rs that answers the request.
18.1
Addressed mode
When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID
(UID) of the addressed M24LR64E-R.
Any M24LR64E-R that receives a request with the Address_flag set to 1 compares the
received Unique ID to its own. If it matches, then the M24LR64E-R executes the request (if
possible) and returns a response to the VCD as specified in the command description.
If the UID does not match, then it remains silent.
18.2
18.3
Non-addressed mode (general request)
When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain
a Unique ID. Any M24LR64E-R receiving a request with the Address_flag cleared to 0
executes it and returns a response to the VCD as specified in the command description.
Select mode
When the Select_flag is set to 1 (Select mode), the request does not contain an M24LR64E-
R Unique ID. The M24LR64E-R in the Selected state that receives a request with the
Select_flag set to 1 executes it and returns a response to the VCD as specified in the
command description.
Only M24LR64E-Rs in the Selected state answer a request where the Select_flag is set to
1.
The system design ensures in theory that only one M24LR64E-R can be in the Select state
at any given time.
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M24LR64E-R
Request format
19
Request format
The request consists of:
•
•
•
•
•
•
an SO
F
,
flags,
a command code,
parameters and data,
a CRC,
an EO
F
.
Table 26. General request format
Command code
Parameters
S
O
F
E
O
F
Request_flags
Data
CRC
19.1
Request flags
In a request, the “flags” field specifies the actions to be performed by the M24LR64E-R and
whether corresponding fields are present or not.
The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the
contents of the four MSBs (bits 5 to 8). When bit 3 is reset (0), bits 5 to 8 define the
M24LR64E-R selection criteria. When bit 3 is set (1), bits 5 to 8 define the M24LR64E-R
Inventory parameters.
Table 27. Definition of request flags 1 to 4
Bit No.
Flag
Level
Description
A single subcarrier frequency is used by the
M24LR64E-R
0
Bit 1
Subcarrier_flag
(1)
1
0
1
0
1
0
1
Two subcarriers are used by the M24LR64E-R
Low data rate is used
Bit 2
Data_rate_flag
(2)
Bit 3
Inventory_flag
High data rate is used
No Protocol format extension
Bit 4
Protocol_extension_flag
(3)
Protocol format extension
1. Subcarrier_flag
refers to the M24LR64E-R-to-VCD communication.
2. Data_rate_flag
refers to the M24LR64E-R-to-VCD communication.
3. Protocol_extension_flag
must be set to 1 for Read Single Block, Read Multiple Block, Fast
Read Multiple Block, Write Single Block, and Get Multiple Block Security Status commands.
Get System Info command supports two options: a standard response format when
Protocol_extension_flag is set to 0, and a rich response when protocol extension is set to 1.
DocID022712 Rev 12
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Request format
M24LR64E-R
.
Table 28. Request flags 5 to 8 when Bit 3 = 0
Bit No.
Flag
Level
Description
The request is executed by any M24LR64E-R according to the
setting of Address_flag
0
Bit 5
Bit 6
Select flag
(1)
The request is executed only by the M24LR64E-R in Selected
state
1
0
The request is not addressed. UID field is not present. The request
is executed by all M24LR64E-Rs.
Address flag
(1)
The request is addressed. UID field is present. The request is
executed only by the M24LR64E-R whose UID matches the UID
specified in the request.
1
0
1
0
Option not activated.
Bit 7
Bit 8
Option flag
RFU
Option activated.
–
1. If
the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the
request.
Table 29. Request flags 5 to 8 when Bit 3 = 1
Bit No.
Flag
Level
Description
0
1
0
1
0
0
AFI field is not present
Bit 5
AFI flag
AFI field is present
16 slots
Bit 6
Nb_slots flag
1 slot
Bit 7
Bit 8
Option flag
RFU
–
–
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M24LR64E-R
Response format
20
Response format
The response consists of:
•
•
•
•
•
an SO
F
,
flags,
parameters and data,
a CRC,
an EO
F
.
Table 30. General response format
S
E
O
F
Response_flags
Parameters
Data
CRC
O
F
20.1
Response flags
In a response, the flags indicate how actions have been performed by the M24LR64E-R and
whether corresponding fields are present or not. The response flags consist of eight bits.
Table 31. Definitions of response flags 1 to 8
Bit No.
Flag
Error_flag
Level
Description
0
1
0
0
0
0
0
0
0
No error
Bit 1
Error detected. Error code is in the “Error” field.
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
RFU
–
RFU
–
Extension flag
RFU
No extension
–
–
–
–
RFU
RFU
RFU
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Response format
M24LR64E-R
20.2
Response error code
If the Error_flag is set by the M24LR64E-R in the response, the Error code field is present
and provides information about the error that occurred.
Table 32. Response error code definition
Error code
Meaning
03h
0Fh
10h
11h
12h
13h
14h
15h
The option is not supported.
Error with no information given.
The specified block is not available.
The specified block is already locked and thus cannot be locked again.
The specified block is locked and its contents cannot be changed.
The specified block was not successfully programmed.
The specified block was not successfully locked.
The specified block is read-protected.
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M24LR64E-R
Anticollision
21
Anticollision
The purpose of the anticollision sequence is to inventory the M24LR64E-Rs present in the
VCD field using their unique ID (UID).
The VCD is the master of communications with one or several M24LR64E-Rs. It initiates an
M24LR64E-R communication by issuing the Inventory request.
The M24LR64E-R sends its response in the determined slot or does not respond.
21.1
Request parameters
When issuing the Inventory Command:
•
•
The VCD sets the Nb_slots_flag as desired.
The VCD adds the mask length and the mask value after the command field:
–
–
The mask length is the number of significant bits of the mask value.
The mask value is contained in an integer number of bytes. The mask length
indicates the number of significant bits. LSB is transmitted first.
•
•
If the mask length is not a multiple of 8 (bits), as many 0-bits as required are added to
the mask value MSB, so that the mask value is contained in an integer number of
bytes.
The next field starts at the next byte boundary.
Table 33. Inventory request format
MSB
SOF Request_flags Command
Optional AFI
Mask length
Mask value
8 bits
8 bits
8 bits
8 bits
0 to 8 bytes
LSB
EOF
–
CRC
–
16 bits
are added to the mask value MSB. The 11-bit mask and the current slot number are
compared to the UID.
Table 34. Example of the addition of 0-bits to an 11-bit mask value
MSB (b
15
)
LSB (b
0
)
0000 0
100 1100 1111
0-bits added
11-bit mask value
DocID022712 Rev 12
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Anticollision
M24LR64E-R
Figure 50. Principle of comparison between the mask, the slot number and the UID
-3″
,3″
-ASK VALUE RECEIVED IN THE )NVENTORY COMMAND
ꢃꢃꢃꢃ ꢃꢀꢃꢃ
ꢀꢀꢃꢃ ꢀꢀꢀꢀ
ꢀꢈ BITS
B
-3″
,3″
4HE -ASK VALUE LESS THE PADDING ꢃS IS LOADED
INTO THE 4AG COMPARATOR
ꢀꢃꢃ ꢀꢀꢃꢃ
ꢀꢀꢀꢀ ꢀꢀ
BITS
B
-3
“
,
3″
4HE 3LOT COUNTER IS CALCULATED
.B?SLOTS?FLAGS ꢄ ꢃ ꢊꢀꢈ SLOTSꢋꢌ 3LOT #OUNTER IS ꢇ BITS
XXXX
ꢇ BITS
4HE 3LOT COUNTER IS CONCATENED TO THE -ASK VALUE
.B?SLOTS?FLAGS ꢄ ꢃ
-3″
,3″
XXXX ꢀꢃꢃ
ꢀꢀꢃꢃ ꢀꢀꢀꢀ
ꢀꢁ BITS
B
5)$
Bꢈꢂ
Bꢃ
4HE CONCATENATED RESULT IS COMPARED WITH
THE LEAST SIGNIFICANT BITS OF THE
4
A G
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The AFI field is present if the AFI_flag is set.
The pulse is generated according to the definition of the EOF in ISO/IEC 15693-2.
The first slot starts immediately after the request EOF is received.
T
o
s
witch to the next slot,
the VCD sends an EO
F
.
The following rules and restrictions apply:
•
If no M24LR64E-R answer is detected, the VCD may switch to the next slot by sending
an EO
F
.
•
If one or more M24LR64E-R answers are detected, the VCD waits until the complete
frame has been received before sending an EOF for switching to the next slot.
72/144
DocID022712 Rev 12
M24LR64E-R
Request processing by the M24LR64E-R
22
Request processing by the M24LR64E-R
Upon reception of a valid request, the M24LR64E-R performs the following algorithm:
•
•
•
•
•
•
NbS is the total number of slots (1 or 16)
SN is the current slot number (0 to 15)
LSB (value, n) function returns the n Less Significant Bits of value
MSB (value, n) function returns the n Most Significant Bits of value
“&” is the concatenation operator
Slot_Frame is either an SOF or an EOF
SN = 0
if (Nb_slots_flag)
then NbS = 1
SN_length = 0
endif
else NbS = 16
SN_length = 4
endif
label1:
if LSB(UID, SN_length + Mask_length) =
LSB(SN,SN_length)&LSB(Mask,Mask_length)
then answer to inventory request
endif
wait (Slot_Frame)
if Slot_Frame = SOF
then Stop Anticollision
decode/process request
exit
endif
if Slot_Frame = EOF
if SN < NbS-1
then SN = SN + 1
goto label1
exit
endif
endif
DocID022712 Rev 12
73/144
Explanation of the possible cases
M24LR64E-R
23
Explanation of the possible cases
Figure 51
summarizes the main possible cases that can occur during an anticollision
sequence when the number of slots is 16.
The sequence of steps is as follows:
•
•
The VCD sends an Inventory request, in a frame terminated by an EO
F
.
T
he number of
slots is 16.
M24LR64E-R_1 transmits its response in Slot 0. It is the only one to do so, therefore no
collision occurs and its UID is received and registered by the VCD.
•
•
The VCD sends an EOF in order to switch to the next slot.
In Slot 1, two M24LR64E-Rs (M24LR64E-R_2 and M24LR64E-R_3) transmit a
response, thus generating a collision. The VCD records the event and registers that a
collision was detected in Slot 1.
•
•
The VCD sends an EOF in order to switch to the next slot.
In Slot 2, no M24LR64E-R transmits a response. Therefore the VCD does not detect
any M24LR64E-R SOF and switches to the next slot by sending an EO
F
.
•
•
•
In Slot 3, another collision occurs due to responses from M24LR64E-R_4 and
M24LR64E-R_5.
The VCD sends a request (for instance a Read Block) to M24LR64E-R_1 whose UID
has already been correctly received.
All M24LR64E-Rs detect an SOF and exit the anticollision sequence. They process this
request and since the request is addressed to M24LR64E-R_1, only M24LR64E-R_1
transmits a response.
•
All M24LR64E-Rs are ready to receive another request. If it is an Inventory command,
the slot numbering sequence restarts from 0.
Note:
The decision to interrupt the anticollision sequence is made by the VCD. EOFs could have
been sent until Slot 16, and the request to M24LR64E-R_1 sent then.
74/144
DocID022712 Rev 12
Figure 51. Description of a possible anticollision sequence
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Inventory Initiated command
M24LR64E-R
24
Inventory Initiated command
The M24LR64E-R provides a special feature to improve the inventory time response of
moving tags using the Initiate_flag value. This flag, controlled by the Initiate command,
allows tags to answer Inventory Initiated commands.
For applications in which multiple tags are moving in front of a reader, it is possible to miss
tags using the standard inventory command. The reason is that the inventory sequence has
to be performed on a global tree search. For example, a tag with a particular UID value may
have to wait the run of a long tree search before being inventoried. If the delay is too long,
the tag may be out of the field before it has been detected.
Using the Initiate command, the inventory sequence is optimized. When multiple tags are
moving in front of a reader, the ones which are within the reader field are initiated by the
Initiate command. In this case, a small batch of tags answers to the Inventory Initiated
command, which optimizes the time necessary to identify all the tags. When finished, the
reader has to issue a new Initiate command in order to initiate a new small batch of tags
which are new inside the reader field.
It is also possible to reduce the inventory sequence time using the Fast Initiate and Fast
Inventory Initiated commands. These commands allow the M24LR64E-Rs to increase their
response data rate by a factor of 2, up to 53 Kbit/s.
76/144
DocID022712 Rev 12
M24LR64E-R
Timing definition
25
Timing definition
25.1
t
1
: M24LR64E-R response delay
Upon detection of the rising edge of the EOF received from the VCD, the M24LR64E-R
waits for a t
time before transmitting its response to a VCD request or switching to the
1nom
1
25.2
t
2
: VCD new request delay
t is
the time after which the VCD may send an EOF to switch to the next slot when one or
2
more M24LR64E-R responses have been received during an Inventory command. It starts
from the reception of the EOF from the M24LR64E-Rs.
The EOF sent by the VCD may be either 10% or 100% modulated regardless of the
modulation index used for transmitting the VCD request to the M24LR64E-R.
t is
also the time after which the VCD may send a new request to the M24LR64E-R, as
2
2
25.3
t
3
: VCD new request delay when no response is received
from the M24LR64E-R
t is
the time after which the VCD may send an EOF to switch to the next slot when no
3
M24LR64E-R response has been received.
The EOF sent by the VCD may be either 10% or 100% modulated regardless of the
modulation index used for transmitting the VCD request to the M24LR64E-R.
From the time the VCD has generated the rising edge of an EOF:
•
If this EOF is 100% modulated, the VCD waits for a time at least equal to t
sending a new EO
F
.
before
3min
•
If this EOF is 10% modulated, the VCD waits for a time at least equal to the sum of
+ the M24LR64E-R nominal response time (which depends on the M24LR64E-R
t
3min
data rate and subcarrier modulation mode) before sending a new EO
F
.
(1)
Table 35. Timing values
Minimum (min) values
Nominal (nom) values
Maximum (max) values
t
1
t
2
t
3
318.6 µs
309.2 µs
320.9 µs
No t
nom
No t
nom
323.3 µs
No t
max
No t
max
t
1max
(2)
+ t
SOF
(3)
1. The
tolerance of specific timings is ± 32/fC.
2.
1max
does not apply for write-alike requests. Timing conditions for write-alike requests are
t
defined in the command description.
3. t
SOF
is the time taken by the M24LR64E-R to transmit an SOF to the VCD. t
SOF
depends on
the current data rate: High data rate or Low data rate.
DocID022712 Rev 12
77/144
Command codes
M24LR64E-R
26
Command codes
The M24LR64E-R supports the commands described in this section. Their codes are given
–
Table 36. Command codes
Command code
standard
Command code
custom
Function
Function
01h
02h
20h
21h
23h
25h
26h
27h
28h
29h
2Ah
2Bh
–
Inventory
2Ch
B1h
B2h
B3h
C0h
C1h
C2h
C3h
D1h
D2h
A0h
A1h
A2h
A3h
A4h
Get Multiple Block Security Status
Write-sector Password
Lock-sector
Stay Quiet
Read Single Block
Write Single Block
Read Multiple Block
Select
Present-sector Password
Fast Read Single Block
Fast Inventory Initiated
Fast Initiate
Reset to Ready
Write AFI
Fast Read Multiple Block
Inventory Initiated
Initiate
Lock AFI
Write DSFID
Lock DSFID
Get System Info
–
ReadCfg
WriteEHCfg
SetRstEHEn
–
–
CheckEHEn
–
–
WriteDOCfg
78/144
DocID022712 Rev 12
M24LR64E-R
Command codes
26.1
Inventory
When receiving the Inventory request, the M24LR64E-R runs the anticollision sequence.
The request contains:
•
•
•
•
•
•
the flags,
the AFI if the AFI flag is set,
the mask length,
the mask value,
the CRC.
The M24LR64E-R does not generate any answer in case of error.
Table 37. Inventory request format
Request
SOF
Optional
AFI
Mask
length
Mask
value
Request
EOF
Request_flags Inventory
8 bits
01h
CRC16
–
8 bits
8 bits
0 – 64 bits
16 bits
–
The response contains:
•
•
the flags,
the Unique ID.
Table 38. Inventory response format
Response
Response
EOF
Response_flags
DSFID
UID
CRC16
16 bits
SOF
–
8 bits
8 bits
64 bits
–
During an Inventory process, if the VCD does not receive an RF M24LR64E-R response, it
waits for a time t
before sending an EOF to switch to the next slot. t
starts from the rising
3
3
edge of the request EOF sent by the VCD.
•
If the VCD sends a 100% modulated EO
F
,
t
he minimum value of t
is:
3
t min = 4384/f
(323.3µs) + t
3
C
SOF
•
If the VCD sends a 10% modulated EO
F
,
t
he minimum value of t
is:
3
t min = 4384/f
(323.3µs) + t
3
C
NRT
where:
•
•
t
t
is the time required by the M24LR64E-R to transmit an SOF to the VCD,
is the nominal response time of the M24LR64E-R.
SOF
NRT
t
and t
are dependent on the M24LR64E-R-to-VCD data rate and subcarrier
SOF
NRT
modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF
starting the inventory command to the end of the M24LR64E-R response. If the
M24LR64E-R does not receive the corresponding slot marker, the RF WIP/BUSY pin
remains at 0 until the next RF power-off.
DocID022712 Rev 12
79/144
Command codes
M24LR64E-R
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
Figure 52. M24LR64E RF-Busy management following Inventory command
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80/144
DocID022712 Rev 12
M24LR64E-R
Command codes
26.2
Stay Quiet
Command code = 0x02
On receiving the Stay Quiet command, the M24LR64E-R enters the Quiet state if no error
occurs, and does NOT send back a response. There is NO response to the Stay Quiet
command even if an error occurs.
When in the Quiet state:
•
•
the M24LR64E-R does not process any request if the Inventory_flag is set,
the M24LR64E-R processes any Addressed request.
The M24LR64E-R exits the Quiet state when:
•
•
•
it is reset (power off),
receiving a Select request. It then goes to the Selected state,
receiving a Reset to Ready request. It then goes to the Ready state.
Table 39. Stay Quiet request format
Request
SOF
Request
EOF
Request flags
Stay Quiet
UID
CRC16
–
8 bits
02h
64 bits
16 bits
–
The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset
to 0 and Address_flag is set to 1).
Figure 53. Stay Quiet frame exchange between VCD and M24LR64E-R
Stay Quiet
request
VCD
SOF
EOF
M24LR64E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 during the Stay
Quiet command.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
DocID022712 Rev 12
81/144
Command codes
M24LR64E-R
26.3
Read Single Block
On receiving the Read Single Block command, the M24LR64E-R reads the requested block
and sends back its 32-bit value in the response. The Protocol_extension_flag should be set
to 1 for the M24LR64E-R to operate correctly. If the Protocol_extension_flag is at 0, the
M24LR64E-R answers with an error code. The Option_flag is supported.
Table 40. Read Single Block request format
Request
SOF
Read Single
Block
Request
EOF
Request_flags
UID
(1)
Block number
CRC16
–
8 bits
20h
64 bits
16 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
Request flags
UID (optional)
Block number
Table 41. Read Single Block response format when Error_flag is NOT set
Response
Sector security
status
(1)
Response
Response_flags
Data
CRC16
SOF
EOF
–
8 bits
8 bits
32 bits
16 bits
–
1. Gray
color means that the field is optional.
Response parameters:
•
•
Four bytes of block data
Table 42. Sector security status
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Reserved for future use.
All at 0.
0: Current sector not locked
1: Current sector locked
Password control
bits
Read / Write
protection bits
Table 43. Read Single Block response format when Error_flag is set
Response
Response
EOF
Response_flags
Error code
CRC16
SOF
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set
•
–
–
10h: the specified block is not available
15h: the specified block is read-protected
82/144
DocID022712 Rev 12
M24LR64E-R
Command codes
Figure 54. Read Single Block frame exchange between VCD and M24LR64E-R
Read Single Block
VCD
SOF
EOF
request
Read Single Block
response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Read Single Block command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.4
Write Single Block
On receiving the Write Single Block command, the M24LR64E-R writes the data contained
in the request to the requested block and reports whether the write operation was
successful in the response. The Protocol_extension_flag should be set to 1 for the
M24LR64E-R to operate correctly. If the Protocol_extension_flag is at 0, the M24LR64E-R
answers with an error code. The Option_flag is supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not program correctly the data into the memory. The W
t
time is equal to t
+ 18 × 302 µs.
1nom
Table 44. Write Single Block request format
Request
SOF
Write Single
Block
Block
number
Request
EOF
Request_flags
UID
(1)
Data
CRC16
–
8 bits
21h
64 bits
16 bits
32 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
•
Request flags
UID (optional)
Block number
Data
Table 45. Write Single Block response format when Error_flag is NOT set
Response SOF
Response_flags
CRC16
Response EOF
–
8 bits
16 bits
–
Response parameter:
•
No parameter. The response is sent back after the writing cycle.
DocID022712 Rev 12
83/144
Command codes
M24LR64E-R
Table 46. Write Single Block response format when Error_flag is set
Response
Response
EOF
Response_flags
Error code
CRC16
SOF
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
–
–
0Fh: error with no information given
10h: the specified block is not available
12h: the specified block is locked and its contents cannot be changed
13h: the specified block was not successfully programmed
Figure 55. Write Single Block frame exchange between VCD and M24LR64E-R
Write Single
Block request
VCD
SOF
EOF
Write Single
Block response
Write sequence when
error
M24LR64E-R
<-t
1
-> SOF
EOF
Write Single
EOF
M24LR64E-R
<——————- W
t
—————> SOF
Block response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write Single Block command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid write single block command to the
beginning of the M24LR64E-R response).
84/144
DocID022712 Rev 12
M24LR64E-R
Command codes
Figure 56. M24LR64E RF-Busy management following Write command
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DocID022712 Rev 12
85/144
Command codes
M24LR64E-R
When configuring in the RF Write in progress mode, the RF WIP/BUSY pin is tied to 0
Figure 57. M24LR64E RF-Wip management following Write command
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)
,UHSO
0ꢁꢆ/5ꢊꢆ[
5)B:LS
06ꢀꢄꢇꢊꢁ9ꢁ
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Command codes
26.5
Read Multiple Block
When receiving the Read Multiple Block command, the M24LR64E-R reads the selected
blocks and sends back their value in multiples of 32 bits in the response. The blocks are
numbered from 00h to 1FFh in the request and the value is minus one (–1) in the field. For
example, if the “Number of blocks” field contains the value 06h, seven blocks are read. The
maximum number of blocks is fixed at 32 assuming that they are all located in the same
sector. If the number of blocks overlaps sectors, the M24LR64E-R returns an error code.
The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 0, the M24LR64E-R answers with an error code. The
Option_flag is supported.
Table 47. Read Multiple Block request format
Request Request_ Read
Multiple
First block
Number
Request
EOF
UID
(1)
CRC16
SOF
flags
Block
number
of blocks
–
8 bits
23h
64 bits
16 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
•
Request flags
UID (optional)
First block number
Number of blocks
Table 48. Read Multiple Block response format when Error_flag is NOT set
Response Response_
Sector security
status
(1)
Response
EOF
Data
CRC16
SOF
flags
–
8 bits
8 bits
(2)
32 bits
(2)
16 bits
–
1. Gray
color means that the field is optional.
2. Repeated
as needed.
Response parameters:
•
•
N blocks of data
Table 49. Sector security status
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Reserved for future use.
All at 0.
Password control
bits
Read / Write
protection bits
0: Current sector not locked
1: Current sector locked
Table 50. Read Multiple Block response format when Error_flag is set
Response SOF
Response_flags
8 bits
Error code
CRC16
Response EOF
–
8 bits
16 bits
–
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Command codes
M24LR64E-R
Response parameter:
Error code as Error_flag is set:
•
–
–
–
0Fh: error with no information given
10h: the specified block is not available
15h: the specified block is read-protected
Figure 58. Read Multiple Block frame exchange between VCD and M24LR64E-R
Read Multiple
Block request
VCD
SOF
EOF
Read Multiple
Block response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Read Multiple Block command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.6
Select
When receiving the Select command:
•
If the UID is equal to its own UID, the M24LR64E-R enters or stays in the Selected
state and sends a response.
•
If the UID does not match its own UID, the selected M24LR64E-R returns to the Ready
state and does not send a response.
The M24LR64E-R answers an error code only if the UID is equal to its own UID. If not, no
response is generated. If an error occurs, the M24LR64E-R remains in its current state.
Table 51. Select request format
Request
SOF
Request
EOF
Request_flags
Select
UID
CRC16
–
8 bits
25h
64 bits
16 bits
–
Request parameter:
UID
•
Table 52. Select Block response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
CRC16
–
8 bits
16 bits
–
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Command codes
Response parameter:
No parameter
•
Table 53. Select response format when Error_flag is set
Response
Response
EOF
Response_flags
8 bits
Error code
CRC16
SOF
–
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
03h: the option is not supported
•
–
Figure 59. Select frame exchange between VCD and M24LR64E-R
Select
request
VCD
SOF
EOF
Select
response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Select command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.7
Reset to Ready
On receiving a Reset to Ready command, the M24LR64E-R returns to the Ready state if no
error occurs. In the Addressed mode, the M24LR64E-R answers an error code only if the
UID is equal to its own UID. If not, no response is generated.
Table 54. Reset to Ready request format
Request
SOF
Request
EOF
Request_flags Reset
to Ready
8 bits
26h
UID
(1)
CRC16
–
64 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
UID (optional)
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Command codes
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Table 55. Reset to Ready response format when Error_flag is NOT set
Response
Response
EOF
Response_flags
CRC16
SOF
–
8 bits
16 bits
–
Response parameter:
No parameter
•
Table 56. Reset to ready response format when Error_flag is set
Response
Response
EOF
Response_flags
Error code
CRC16
SOF
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
03h: the option is not supported
•
–
Figure 60. Reset to Ready frame exchange between VCD and M24LR64E-R
Reset to
VCD
SOF
Ready
EOF
request
Reset to
Ready
M24LR64E-R
<-t
1
-> SOF
EOF
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Reset to ready command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.8
Write AFI
On receiving the Write AFI request, the M24LR64E-R programs the 8-bit AFI value to its
memory. The Option_flag is supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not write correctly the AFI value into the memory. The W
t
time is equal to t
+ 18 × 302 µs.
1nom
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Command codes
Table 57. Write AFI request format
Request
SOF
Request
CRC16
Request_flags
Write AFI
UID
(1)
AFI
EOF
–
8 bits
27h
64 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
•
Request flags
UID (optional)
AFI
Table 58. Write AFI response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
CRC16
–
8 bits
16 bits
–
Response parameter:
No parameter
•
Table 59. Write AFI response format when Error_flag is set
Response Response_
Response
EOF
Error code
CRC16
SOF
flags
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set
•
–
–
12h: the specified block is locked and its contents cannot be changed
13h: the specified block was not successfully programmed
Figure 61. Write AFI frame exchange between VCD and M24LR64E-R
Write AFI
request
VCD
SOF
EOF
Write AFI
response
Write sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
Write AFI
EOF
M24LR64E-R
<—————— W
t
————–> SOF
response
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Command codes
M24LR64E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write AFI command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write AFI command to the
beginning of the M24LR64E-R response).
26.9
Lock AFI
On receiving the Lock AFI request, the M24LR64E-R locks the AFI value permanently. The
Option_flag is supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not lock correctly the AFI value in memory. The W
time is
t
equal to t
+ 18 × 302 µs.
1nom
Table 60. Lock AFI request format
Request
SOF
Request
EOF
Request_flags
Lock AFI
UID
(1)
CRC16
–
8 bits
28h
64 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
Request Flags
UID (optional)
Table 61. Lock AFI response format when Error_flag is NOT set
Response
Response
EOF
Response_flags
CRC16
SOF
–
8 bits
16 bits
–
Response parameter:
No parameter
•
Table 62. Lock AFI response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set
•
–
–
11h: the specified block is already locked and thus cannot be locked again
14h: the specified block was not successfully locked
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Command codes
Figure 62. Lock AFI frame exchange between VCD and M24LR64E-R
Lock AFI
request
VCD
SOF
EOF
Lock AFI
response
Lock sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
Lock AFI
response
M24LR64E-R
<—————– W
t
———–> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Lock AFI command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
entire duration of the internal write cycle (from the end of valid Lock AFI command to the
beginning of the M24LR64E-R response).
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Command codes
M24LR64E-R
26.10
Write DSFID
On receiving the Write DSFID request, the M24LR64E-R programs the 8-bit DSFID value to
its memory. The Option_flag is supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not write correctly the DSFID value in memory. The W
t
time is equal to t
+ 18 × 302 µs.
1nom
Table 63. Write DSFID request format
Request
SOF
Request
EOF
Request_flags Write
DSFID
8 bits
29h
UID
(1)
DSFID
CRC16
–
64 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
•
Request flags
UID (optional)
DSFID
Table 64. Write DSFID response format when Error_flag is NOT set
Response
Response
EOF
Response_flags
CRC16
SOF
–
8 bits
16 bits
–
Response parameter:
No parameter
•
Table 65. Write DSFID response format when Error_flag is set
Response
Response
EOF
Response_flags
Error code
CRC16
SOF
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set
•
–
–
12h: the specified block is locked and its contents cannot be changed
13h: the specified block was not successfully programmed
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Command codes
Figure 63. Write DSFID frame exchange between VCD and M24LR64E-R
Writ
e
D
SFID EO
VCD
SOF
request
F
SO Write
DSFID EO
Write sequence
when error
M24LR64E-R
<-t
1
->
F
response
F
SO Writ
e
D
SFID
M24LR64E-R
<—————- W
t
———->
EOF
F
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write DSFID command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write DSFID command to the
beginning of the M24LR64E-R response).
26.11
Lock DSFID
On receiving the Lock DSFID request, the M24LR64E-R locks the DSFID value
permanently. The Option_flag is supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not lock correctly the DSFID value in memory. The W
time
t
is equal to t
+ 18 × 302 µs.
1nom
Table 66. Lock DSFID request format
Request
SOF
Request
EOF
Request_flags
Lock DSFID
UID
(1)
CRC16
–
8 bits
2Ah
64 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
Request flags
UID (optional)
Table 67. Lock DSFID response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
CRC16
–
8 bits
16 bits
–
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Command codes
M24LR64E-R
Response parameter:
No parameter.
•
Table 68. Lock DSFID response format when Error_flag is set
Response
Response
EOF
Response_flags
Error code
CRC16
SOF
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
11h: the specified block is already locked and thus cannot be locked again
14h: the specified block was not successfully locked
Figure 64. Lock DSFID frame exchange between VCD and M24LR64E-R
Lock
VCD
SOF
DSFID
EOF
request
Lock DSFID
response
Lock sequence
when error
M24LR64E-R
M24LR64E-R
<-t
1
-> SOF
EOF
Lock
<—————- W
t
————-> SOF
DSFID
EOF
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Lock DSFID command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Lock DSFID command to the
beginning of the M24LR64E-R response).
26.12
Get System Info
When receiving the Get System Info command, the M24LR64E-R sends back its
information data in the response. The Option_flag is not supported. The Get System Info
can be issued in both Addressed and Non Addressed modes.
R response to the Get System Info command depending on the value of the
Protocol_extension_flag.
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Command codes
Request
Table 69. Get System Info request format
Request
SOF
Request_flags Get
System Info
8 bits
2Bh
UID
(1)
CRC16
EOF
–
64 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
Request flags
UID (optional)
Table 70. Get System Info response format when Protocol_extension_flag = 0 and
Error_flag is NOT set
Response Response_ Information
Response
EOF
UID
DSFID
AFI
IC ref.
CRC16
5Eh 16
bits
SOF
flags
flags
–
00h
0Bh
64 bits
8 bits
8 bits
–
Response parameters:
•
•
•
•
•
Information flags set to 0Ch. DSFID, AFI and IC reference fields are present.
UID code on 64 bits
DSFID value
AFI value
M24LR64E-R IC reference: the 8 bits are significant.
Table 71. Get System Info response format when Protocol_extension_flag = 1 and
Error_flag is NOT set
Response Response Information
Memory IC
size ref
Response
EOF
UID DSFID
AFI
CRC16
SOF
_flags
flags
–
00h
0Fh
64 bits
8 bits
8 bits
03 07FFh
5Eh 16
bits
–
Response parameters:
•
Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are
present.
•
•
•
•
•
UID code on 64 bits
DSFID value
AFI value
Memory size. The M24LR64E-R provides 2048 blocks (07FFh) of 4 bytes (03h)
IC reference: the 8 bits are significant.
Table 72. Get System Info response format when Error_flag is set
Response
Response
EOF
Response_flags Error
code
CRC16
SOF
–
01h
8 bits
16 bits
–
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Command codes
M24LR64E-R
Response parameter:
•
Error code as Error_flag is set:
03h: Option not supported
–
.
Figure 65. Get System Info frame exchange between VCD and M24LR64E-R
Get System Info
VCD
SOF
EOF
request
Get System Info
response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Get System Info command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.13
Get Multiple Block Security Status
When receiving the Get Multiple Block Security Status command, the M24LR64E-R sends
back the sector security status. The blocks are numbered from 00h to 01FFh in the request
and the value is minus one (–1) in the field. For example, a value of ’06’ in the “Number of
blocks” field requests to return the security status of seven blocks.
The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 0, the M24LR64E-R answers with an error code.
During the M24LR64E-R response, if the internal block address counter reaches 01FFh, it
rolls over to 0000h and the Sector Security Status bytes for that location are sent back to the
reader.
Table 73. Get Multiple Block Security Status request format
Request Request Get
Multiple Block
First block
Number
Request
EOF
UID
(1)
CRC16
SOF
_flags
Security Status
number
of blocks
–
8 bits
2Ch
64 bits
16 bits
16 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
•
•
Request flags
UID (optional)
First block number
Number of blocks
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Command codes
Table 74. Get Multiple Block Security Status response format when Error_flag is NOT
set
Response
SOF
Response
EOF
Response_flags
Sector security status
CRC16
–
8 bits
8 bits
(1)
16 bits
–
1. Repeated
as needed.
Response parameters:
•
Table 75. Sector security status
b
4
b
3
b
2
b
1
b
7
b
6
b
5
b
0
0: Current sector not locked
1: Current sector locked
Reserved for future use
All at 0
Password control
bits
Read / Write
protection bits
Table 76. Get Multiple Block Security Status response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
03h: the option is not supported
10h: the specified block is not available
Figure 66. Get Multiple Block Security Status frame exchange between VCD and
M24LR64E-R
Get Multiple Block
Security Status
VCD
SOF
EOF
Get Multiple Block
Security Status
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Get Multiple Block Security Status command to the end of the M24LR64E-R
response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
M24LR64E-R
26.14
Write-sector Password
On receiving the Write-sector Password command, the M24LR64E-R uses the data
contained in the request to write the password and reports whether the operation was
successful in the response. The Option_flag is supported.
During the RF write cycle time, W , there must be no modulation at all (neither 100% nor
t
10%), otherwise the M24LR64E-R may not correctly program the data into the memory.
The W
time is equal to t
+ 18 × 302 µs. After a successful write, the new value of the
1nom
t
selected password is automatically activated. It is not required to present the new password
value until M24LR64E-R power-down.
Table 77. Write-sector Password request format
Request Request Write-sector IC
Mfg
Password
number
Request
EOF
UID
(1)
Data
CRC16
SOF
_flags
password
code
–
8 bits
B1h
02h
64 bits
8 bits
32 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
•
•
Request flags
UID (optional)
Password number (01h = Pswd1, 02h = Pswd2, 03h = Pswd3, other = Error)
Data
Table 78. Write-sector Password response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
CRC16
–
8 bits
16 bits
–
Response parameter:
no parameter.
•
Table 79. Write-sector Password response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
–
–
10h: the password number is incorrect
12h: the session was not opened before the password update
13h: the specified block was not successfully programmed
0Fh: the presented password is incorrect
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Command codes
Figure 67. Write-sector Password frame exchange between VCD and M24LR64E-R
Write-
sector
Password
request
VCD
SOF
EOF
Write-sector
Password
response
Write sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
Write-
sector
Password
M24LR64E-R
<—————- W
t
————-> SOF
EOF
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write-sector Password command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write sector password command
to the beginning of the M24LR64E-R response).
26.15
Lock-sector
On receiving the Lock-sector command, the M24LR64E-R sets the access rights and
permanently locks the selected sector. The Option_flag is supported.
A sector is selected by giving the address of one of its blocks in the Lock-sector request
(Sector number field). For example, addresses 0 to 31 are used to select sector 0 and
addresses 32 to 63 are used to select sector 1. Care must be taken when issuing the Lock-
sector command as all the blocks belonging to the same sector are automatically locked by
a single command.
The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 0, the M24LR64E-R answers with an error code.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not correctly lock the memory block. The W
time is equal
t
to t
+ 18 × 302 µs.
1nom
Table 80. Lock-sector request format
Request Request
Lock- IC
Mfg
Sector Secto
r
s
ecurity
Request
EOF
UID
(1)
CRC16
SOF
_flags
sector
code
number
status
–
8 bits
B2h
02h
64 bits
16 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
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Command codes
M24LR64E-R
Request parameters:
•
•
•
•
Request flags
(optional) UID
Sector number
Table 81. Sector security status
b
4
b
3
b
2
Password control bits
Read / Write protection bits
b
7
0
b
6
0
b
5
0
b
1
b
0
1
Table 82. Lock-sector response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
CRC16
–
8 bits
16 bits
–
Response parameter:
No parameter
•
Table 83. Lock-sector response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
–
10h: the specified block is not available
11h: the specified block is already locked and thus cannot be locked again
14h: the specified block was not successfully locked
Figure 68. Lock-sector frame exchange between VCD and M24LR64E-R
Lock-sector
request
VCD
SOF
EOF
Lock-sector
response
Lock sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
Lock-sector
EOF
M24LR64E-R
<————— W
t
———–> SOF
response
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Command codes
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Lock-sector command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Lock sector command to the
beginning of the M24LR64E-R response).
26.16
Present-sector Password
On receiving the Present-sector Password command, the M24LR64E-R compares the
requested password with the data contained in the request and reports whether the
operation has been successful in the response. The Option_flag is supported.
During the comparison cycle equal to W , there should be no modulation (neither 100% nor
t
10%), otherwise the M24LR64E-R Password value may not be correctly compared. The W
t
time is equal to t
+ 18 × 302 µs.
1nom
After a successful command, the access to all the memory blocks linked to the password is
Table 84. Present-sector Password request format
Present-
Request Request
IC Mfg
code
Password
number
Request
EOF
sector
UID
(1)
Password CRC16
SOF
_flags
Password
–
8 bits
B3h
02h
64 bits
8 bits
32 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameter:
•
•
•
•
Request flags
UID (optional)
Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error)
Password
Table 85. Present-sector Password response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
CRC16
–
8 bits
16 bits
–
Response parameter:
No parameter. The response is sent back after the write cycle.
•
Table 86. Present-sector Password response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
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Command codes
M24LR64E-R
Response parameter:
Error code as Error_flag is set:
•
–
–
10h: the password number is incorrect
0Fh: the present password is incorrect
Figure 69.
Present-sector Password frame exchange between VCD and M24LR64E-R
Present-
sector
password
VCD
SOF response EOF
OR error
0F (bad
password)
Present-
sector
password
response
Sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
Present-
sector
password
response
M24LR64E-R
<—————- W
t
————> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Present Sector Password command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY remains in high-Z
state.
26.17
Fast Read Single Block
On receiving the Fast Read Single Block command, the M24LR64E-R reads the requested
block and sends back its 32-bit value in the response. The Option_flag is supported. The
data rate of the response is multiplied by 2.
The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 0, the M24LR64E-R answers with an error code.
The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error
code.
Table 87. Fast Read Single Block request format
Request
SOF
Fast Read
I
C
M
fg
Single Block
code
Block
number
Request
EOF
Request_flags
UID
(1)
CRC16
–
8 bits
C0h
02h
64 bits
16 bits
16 bits
–
1. Gray
color means that the field is optional.
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Command codes
Request parameters:
•
•
•
Request flags
UID (optional)
Block number
Table 88. Fast Read Single Block response format when Error_flag is NOT set
Response
Sector security
status
(1)
Response
Response_flags
Data
CRC16
SOF
EOF
–
8 bits
8 bits
32 bits
16 bits
–
1. Gray
color means that the field is optional.
Response parameters:
•
•
Four bytes of block data
Table 89. Sector security status
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Reserved for future use
All at 0
0: Current sector not locked
1: Current sector locked
Password control
bits
Read / Write
protection bits
Table 90. Fast Read Single Block response format when Error_flag is set
Response
Response
EOF
Response_flags
Error code
CRC16
SOF
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
10h: the specified block is not available
15h: the specified block is read-protected
Figure 70. Fast Read Single Block frame exchange between VCD and M24LR64E-R
Fast Read Single
Block request
VCD
SOF
EOF
Fast Read Single
Block response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Fast Read Single block command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
M24LR64E-R
26.18
Fast Inventory Initiated
Before receiving the Fast Inventory Initiated command, the M24LR64E-R must have
received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the
M24LR64E-R does not answer the Fast Inventory Initiated command.
The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error
code.
On receiving the Fast Inventory Initiated request, the M24LR64E-R runs the anticollision
sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is shown in
The request contains:
•
•
•
•
•
•
the flags,
the Inventory command code,
the AFI if the AFI flag is set,
the mask length,
the mask value,
the CRC.
The M24LR64E-R does not generate any answer in case of error.
Table 91. Fast Inventory Initiated request format
Request Request Fast
Inventory IC
Mfg Optional
Mask
Mask
Request
EOF
CRC16
SOF
_flags
Initiated
code
AFI
length value
0 – 64
8 bits
–
8 bits
C1h
02h
8 bits
16 bits
–
bits
The Response contains:
•
•
the flags,
the Unique ID.
Table 92. Fast Inventory Initiated response format
Response
Response
EOF
Response_flags
8 bits
DSFID
UID
CRC16
16 bits
SOF
–
8 bits
64 bits
–
During an Inventory process, if the VCD does not receive an RF M24LR64E-R response, it
waits for a time t
before sending an EOF to switch to the next slot. t
starts from the rising
3
3
edge of the request EOF sent by the VCD.
•
If the VCD sends a 100% modulated EO
F
,
t
he minimum value of t
is:
3
t min = 4384/f
(323.3µs) + t
3
C
SOF
•
If the VCD sends a 10% modulated EO
F
,
t
he minimum value of t
is:
3
t min = 4384/f
(323.3µs) + t
3
C
NRT
where:
•
•
t
t
is the time required by the M24LR64E-R to transmit an SOF to the VCD
is the nominal response time of the M24LR64E-R
SOF
NRT
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Command codes
t
and t
are dependent on the M24LR64E-R-to-VCD data rate and subcarrier
SOF
NRT
modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is driven to 0 from the SOF
starting the inventory command to the end of the M24LR64E-R response. If the M24LR64E-
R does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 until
the next RF power-off.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.19
Fast Initiate
On receiving the Fast Initiate command, the M24LR64E-R sets the internal Initiate_flag and
sends back a response only if it is in the Ready state. The command has to be issued in the
Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an
error occurs, the M24LR64E-R does not generate any answer. The Initiate_flag is reset after
a power-off of the M24LR64E-R. The data rate of the response is multiplied by 2.
The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error
code.
The request contains:
•
No data
Table 93. Fast Initiate request format
Request
SOF
Request
EOF
Request_flags
Fast Initiate
IC Mfg Code
CRC16
–
8 bits
C2h
02h
16 bits
–
The response contains:
•
•
the flags,
the Unique ID.
Table 94. Fast Initiate response format
Response
Response
EOF
Response_flags
8 bits
DSFID
UID
CRC16
16 bits
SOF
–
8 bits
64 bits
–
Figure 71. Fast Initiate frame exchange between VCD and M24LR64E-R
Fast Initiate
request
VCD
SOF
EOF
Fast Initiate
response
M24LR64E-R
<-t
1
-> SOF
EOF
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Command codes
M24LR64E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Fast Initiate command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z state.
26.20
Fast Read Multiple Block
On receiving the Fast Read Multiple Block command, the M24LR64E-R reads the selected
blocks and sends back their value in multiples of 32 bits in the response. The blocks are
numbered from 00h to 1FFh in the request and the value is minus one (–1) in the field. For
example, if the “Number of blocks” field contains the value 06h, seven blocks are read. The
maximum number of blocks is fixed to 32 assuming that they are all located in the same
sector. If the number of blocks overlaps sectors, the M24LR64E-R returns an error code.
The Protocol_extension_flag should be set to 1 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 0, the M24LR64E-R answers with an error code.
The Option_flag is supported. The data rate of the response is multiplied by 2.
The subcarrier_flag should be set to 0, otherwise the M24LR64E-R answers with an error
code.
Table 95. Fast Read Multiple Block request format
Fast Read
Multiple
Block
First
block
number blocks
Number
of
Request Request_
I
C
M
fg
code
Request
EOF
UID
(1)
CRC16
SOF
flags
–
8 bits
C3h
02h
64 bits
16 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
•
Request flag
UID (Optional)
First block number
Number of blocks
Table 96. Fast Read Multiple Block response format when Error_flag is NOT set
Response
SOF
Sector security
status
(1)
Response
EOF
Response_flags
Data
CRC16
–
8 bits
8 bits
(2)
32 bits
(2)
16 bits
–
1. Gray
color means that the field is optional.
2. Repeated
as needed.
Response parameters:
•
•
N block of data
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Command codes
Table 97. Sector security status if Option_flag is set
b
5
b
4
b
3
b
2
b
1
b
0
b
7
b
6
Reserved for future use
All at 0
Password
control bits
Read / Write
0: Current sector not locked
protection bits
1: Current sector locked
Table 98. Fast Read Multiple Block response format when Error_flag is set
Response SOF
Response_flags
8 bits
Error code
CRC16
Response EOF
–
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
•
–
–
–
03h: the option is not supported
10h: block address not available
15h: block read-protected
Figure 72. Fast Read Multiple Block frame exchange between VCD and M24LR64E-R
Fast Read
VCD
SOF Multiple
Block EOF
request
Fast Read
<-t
1
-> SOF
Multiple Block
EOF
response
M24LR64E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Fast Read Multiple Block command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.21
Inventory Initiated
Before receiving the Inventory Initiated command, the M24LR64E-R must have received an
Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64E-R
does not answer the Inventory Initiated command.
On receiving the Inventory Initiated request, the M24LR64E-R runs the anticollision
sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is given in
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Command codes
M24LR64E-R
The request contains:
•
•
•
•
•
•
the flags,
the Inventory Command code,
the AFI if the AFI flag is set,
the mask length,
the mask value,
the CRC.
The M24LR64E-R does not generate any answer in case of error.
Table 99. Inventory Initiated request format
Request Request Inventory IC
Mfg Optional
Mask
Mask value
Request
EOF
CRC16
16 bits
SOF
_flags
Initiated
code
AFI
length
–
8 bits
D1h
02h
8 bits
8 bits
0 – 64 bits
–
The response contains:
•
•
the flags,
the Unique ID.
Table 100. Inventory Initiated response format
Response
Response
EOF
Response_flags
8 bits
DSFID
UID
CRC16
16 bits
SOF
–
8 bits
64 bits
–
During an Inventory process, if the VCD does not receive an RF M24LR64E-R response, it
waits for a time t
before sending an EOF to switch to the next slot. t
starts from the rising
3
3
edge of the request EOF sent by the VCD.
•
If the VCD sends a 100% modulated EO
F
,
t
he minimum value of t
is:
3
t min = 4384/f
(323.3µs) + t
3
C
SOF
•
If the VCD sends a 10% modulated EO
F
,
t
he minimum value of t
is:
3
t min = 4384/f
(323.3µs) + t
3
C
NRT
where:
•
•
t
t
is the time required by the M24LR64E-R to transmit an SOF to the VCD
is the nominal response time of the M24LR64E-R
SOF
NRT
t
and t
are dependent on the M24LR64E-R-to-VCD data rate and subcarrier
SOF
NRT
modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF
starting the inventory command to the end of the M24LR64E-R response. If the M24LR64E-
R does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 until
the next RF power-off.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
26.22
Initiate
On receiving the Initiate command, the M24LR64E-R sets the internal Initiate_flag and
sends back a response only if it is in the ready state. The command has to be issued in the
Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an
error occurs, the M24LR64E-R does not generate any answer. The Initiate_flag is reset after
a power-off of the M24LR64E-R.
The request contains:
•
No data
Table 101. Initiate request format
Request
SOF
Request
EOF
Request_flags
Initiate
IC Mfg code
CRC16
–
8 bits
D2h
02h
16 bits
–
The response contains:
•
•
the flags,
the Unique ID.
Table 102. Initiate response format
Response
Response
EOF
Response_flags
8 bits
DSFID
UID
CRC16
16 bits
SOF
–
8 bits
64 bits
–
Figure 73. Initiate frame exchange between VCD and M24LR64E-R
Initiate
request
VCD
SOF
EOF
Initiate
response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Initiate command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.23
ReadCfg
On receiving the ReadCfg command, the M24LR64E-R reads the Configuration byte and
sends back its 8-bit value in the response.
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Command codes
M24LR64E-R
The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 1, the M24LR64E-R answers with an error code. The
Option_flag is not supported. The Inventory_flag must be set to 0.
Table 103. ReadCfg request format
Request
SOF
Request
EOF
Request_flags
ReadCfg
IC Mfg code
UID
(1)
CRC16
–
8 bits
A0h
02h
64 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
UID (optional)
Table 104. ReadCfg response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
Data
CRC16
–
8 bits
8 bits
16 bits
–
Response parameters:
One byte of data: Configuration byte
•
Table 105. ReadCfg response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set
•
–
–
03h: the option is not supported
0Fh: error with no information given
Figure 74. ReadCfg frame exchange between VCD and M24LR64E-R
VCD
SOF
ReadCfg request
EOF
M24LR64E-R
<-t
1
-> SOF ReadCfg
response EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the ReadCfg command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
26.24
WriteEHCfg
On receiving the WriteEHCfg command, the M24LR64E-R writes the data contained in the
request to the Configuration byte and reports whether the write operation was successful in
the response. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to
operate correctly. If the Protocol_extension_flag is at 1, the M24LR64E-R answers with an
error code.
The Option_flag is supported, the Inventory_flag is not supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not program correctly the data into the Configuration byte.
The W
time is equal to t
+ 18 × 302 µs.
t
1nom
Table 106. WriteEHCfg request format
Request
SOF
Request
EOF
Request_flags WriteEHCfg IC
Mfg code
8 bits
A1h 02h
UID
(1)
Data CRC16
–
64 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
Request flags
UID (optional)
Table 107. WriteEHCfg response format when Error_flag is NOT set
Response SOF
Response_flags
8 bits
CRC16
Response EOF
–
16 bits
–
Response parameter:
No parameter. The response is sent back after the writing cycle.
•
Table 108. WriteEHCfg response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
13h: the specified block was not successfully programmed
•
–
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Command codes
M24LR64E-R
Figure 75. WriteEHCfg frame exchange between VCD and M24LR64E-R
WriteEHCfg
request
VCD
SOF
EOF
WriteEHCfg
response
WriteEHCfg sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
WriteEHCfg
EOF
M24LR64E-R
<——————- W
t
—————> SOF
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the WriteEHCfg command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
entire duration of the internal write cycle (from the end of a valid WriteEHCfg command to
the beginning of the M24LR64E-R response).
26.25
WriteDOCfg
On receiving the WriteDOCfg command, the M24LR64E-R writes the data contained in the
request to the Configuration byte and reports whether the write operation was successful in
the response. The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate
correctly. If the Protocol_extension_flag is at 1, the M24LR64E-R answers with an error code.
The Option_flag is supported, the Inventory_flag is not supported.
During the RF write cycle W , there should be no modulation (neither 100% nor 10%),
t
otherwise the M24LR64E-R may not program correctly the data into the Configuration byte.
The W
time is equal to t
+ 18 × 302 µs.
t
1nom
Table 109. WriteDOCfg request format
Request_ flags
WriteDOCfg IC
Mfg code
UID
(1)
Request
SOF
Request
EOF
Data CRC16
–
8 bits
A4h
02h
64 bits
8 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
Request flag
UID (optional)
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Command codes
Table 110. WriteDOCfg response format when Error_flag is NOT set
Response SOF
Response_flags
8 bits
CRC16
Response EOF
–
16 bits
–
Response parameter:
No parameter. The response is sent back after the writing cycle.
•
Table 111. WriteDOCfg response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
13h: the specified block was not successfully programmed
•
–
Figure 76. WriteDOCfg frame exchange between VCD and M24LR64E-R
WriteDOCfg
request
VCD
SOF
EOF
WriteDOCfg
response
WriteDOCfg sequence
when error
M24LR64E-R
<-t
1
-> SOF
EOF
WriteDOCfg
EOF
M24LR64E-R
<—————– W
t
————–> SOF
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the WriteEHCfg command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
entire duration of the internal write cycle (from the end of a valid WriteDOCfg command to
the beginning of the M24LR64E-R response).
26.26
SetRstEHEn
On receiving the SetRstEHEn command, the M24LR64E-R sets or resets the EH_enable bit
in the volatile Control register. The Protocol_extension_flag should be set to 0 for the
M24LR64E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR64E-R
answers with an error code. The Option_flag and the Inventory_flag are not supported.
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Command codes
M24LR64E-R
Request
Table 112. SetRstEHEn request format
Request
SOF
Request_flags SetRstEHEn IC
Mfg code
8 bits
A2h 02h
UID
(1)
Data CRC16
8 bits
16 bits
EOF
–
64 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
•
•
Request flags
UID (optional)
Data: during a SetRstEHEn command, bits 7 to 1 are ignored. Bit 0 is the EH_enable
bit.
Table 113. SetRstEHEn response format when Error_flag is NOT set
Response SOF
Response_flags
8 bits
CRC16
Response EOF
–
16 bits
–
Response parameter:
No parameter. The response is sent back after t .
•
1
Table 114. SetRstEHEn response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set:
03h: the option is not supported
•
–
Figure 77. SetRstEHEn frame exchange between VCD and M24LR64E-R
SetRstEHEn
VCD
SOF
EOF
request
SetRstEHEn
response
WriteEHCfg sequence
when no error
M24LR64E-R
<-t
1
-> SOF
<-t
1
-> SOF
EOF
EOF
SetRstEHEn
response
WriteEHCfg sequence
when error
M24LR64E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the SetRstEHEn command to the end of the M24LR64E-R response.
116/144
DocID022712 Rev 12
M24LR64E-R
Command codes
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.27
CheckEHEn
On receiving the CheckEHEn command, the M24LR64E-R reads the Control register and
sends back its 8-bit value in the response.
The Protocol_extension_flag should be set to 0 for the M24LR64E-R to operate correctly. If
the Protocol_extension_flag is at 1, the M24LR64E-R answers with an error code. The
Option_flag is not supported. The Inventory_flag must be set to 0.
Table 115. CheckEHEn request format
Request
SOF
Request
EOF
Request_flags CheckEHEn IC
Mfg code
8 bits
A3h 02h
UID
(1)
CRC16
–
64 bits
16 bits
–
1. Gray
color means that the field is optional.
Request parameters:
•
UID (optional)
Table 116. CheckEHEn response format when Error_flag is NOT set
Response
SOF
Response
EOF
Response_flags
Data
CRC16
–
8 bits
8 bits
16 bits
–
Response parameters:
•
Table 117. CheckEHEn response format when Error_flag is set
Response
SOF
Response
EOF
Response_flags
Error code
CRC16
–
8 bits
8 bits
16 bits
–
Response parameter:
Error code as Error_flag is set
03h: the option is not supported
•
–
DocID022712 Rev 12
117/144
Command codes
M24LR64E-R
Figure 78. CheckEHEn frame exchange between VCD and M24LR64E-R
VCD
SOF CheckEHEn
request EOF
CheckEHEn
response
M24LR64E-R
<-t
1
-> SOF
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the CheckEHEn command to the end of the M24LR64E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
118/144
DocID022712 Rev 12
M24LR64E-R
Maximum ratings
27
Maximum ratings
the device. These are stress ratings only and operation of the device, at these or any other
conditions above those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
the device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
Table 118. Absolute maximum ratings
Symbol
Parameter
Ambient operating temperature
Min.
Max.
Unit
T
A
-40
15
–
85
25
°C
°C
T
STG
,
Sawn wafer
on UV tape
9
(1)
months
Storage conditions
h
ST
G
, t
STG
Kept in its original
packing form
UFDFPN8 (MLP8),
SO8, TSSOP8
T
STG
Storage temperature
-65
150
°C
UFDFPN8 (MLP8),
SO8, TSSOP8
T
LEAD
Lead temperature during soldering
See note
(2)
°C
V
IO
I
2
C input or output range
I
2
C supply voltage
-0.50
6.5
6.5
V
V
V
CC
-0.50
DC output current on pin SDA or RF WIP/BUSY (when
equal to 0)
I
OL_MAX
–
–
5
mA
mA
(3)
I
CC
RF supply current AC0 – AC1
50
RF input voltage amplitude peak to
peak between AC0 and AC1, GND
pad left floating
(3)
V
MAX_1
VAC0-VAC1
–
27
11
V
V
AC voltage between AC0 and GND,
VAC0-GND,
(3)
V
MAX_2
-1
or AC1 and GND
or VAC1-GND
AC0, AC1
–
–
1000
3500
Electrostatic discharge voltage
(human body model)
(4)
Other pads
V
ESD
V
Electrostatic discharge voltage
on antenna
(5)
AC0, AC1
–
4000
1. Counted
from ST shipment date.
2. Compliant
with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST
ECOPACK
®
7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS) 2002/95/EU.
3. Based
on characterization, not tested in production.
4. AEC-Q100-002
(compliant with JEDEC Std JESD22-A114, C1 = 100 p
F
,
R
1 = 1500
Ω
,
R2 = 500
Ω
)
5. Compliant
with IEC 61000-4-3 method. (M24LRxxE packaged in S08N is mounted on ST’s
reference antenna ANT1- M24LRxxE)
DocID022712 Rev 12
119/144
2
I C
DC and AC parameters
M24LR64E-R
2
28
I C
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
2
characteristics of the device in I
C mode. The parameters in the DC and AC characteristic
tables that follow are derived from tests performed under the measurement conditions
summarized in the relevant tables. Designers should check that the operating conditions in
their circuit match the measurement conditions when relying on the quoted parameters.
2
Table 119. I
C operating conditions
Symbol
Parameter
Min.
Max.
Unit
V
CC
T
A
Supply voltage
Ambient operating temperature
1.8
-40
5.5
85
V
°C
Table 120. AC test measurement conditions
Symbol
Parameter
Min.
Max.
Unit
C
L
Load capacitance
100
pF
ns
V
t
r,
t
f
Input rise and fall times
Input levels
–
50
V
hi-lo
V
ref(t)
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
Input and output timing reference levels
V
Figure 79. AC test measurement I/O waveform
)NPUT ,EVELS
)NPUT AND /UTPUT
4IMING 2EFERENCE ,EVELS
ꢃꢍꢉ6
##
ꢃꢍꢎ6
##
ꢃꢍꢂ6
##
ꢃꢍꢆ6
##
!)ꢃꢃꢉꢆꢁ”
Table 121. Input parameters
Parameter
Symbol
Min.
Max.
Unit
C
IN
C
IN
Input capacitance (SDA)
–
–
–
8
6
pF
pF
ns
Input capacitance (other pins)
(1)
t
NS
Pulse width ignored (Input filter on SCL and SDA)
80
1. Characterized
only.
120/144
DocID022712 Rev 12
2
M24LR64E-R
I C DC and AC parameters
2
Table 122. I
C DC characteristics
Symbol
Parameter
Test condition
Min.
Max.
Unit
Input leakage current
(SCL, SDA)
V
IN
= V
SS
or V
CC
device in Standby mode
I
LI
–
± 2
µA
External voltage applied on
V
out
: V
SS
or V
CC
I
LO_Vout
V
out
output leakage current
–
–
–
–
–
± 5
± 2
50
µA
µA
SDA in Hi-Z, external voltage
applied on SDA: V
SS
or V
CC
I
LO
Output leakage current
Supply current (Read)
(1)
V
CC
= 1.8
V
,
f
c
= 100 kHz
(rise/fall time < 50 ns)
V
CC
= 1.8
V
,
f
c
= 400 kHz
(rise/fall time < 50 ns)
100
200
I
CC
µA
V
CC
= 2.5
V
,
f
c
= 400 kHz
(rise/fall time < 50 ns)
V
CC
= 5.5
V
,
f
c
= 400 kHz
(rise/fall time < 50 ns)
–
–
–
400
220
30
I
CC0
Supply current (Write)
(1)
Standby supply current
V
CC
= 1.8 – 5.5 V
µA
µA
V
IN
= V
SS
or V
CC
V
CC
= 1.8 V
V
IN
= V
SS
or V
CC
V
CC
= 2.5 V
I
CC1
–
–
30
V
IN
= V
SS
or V
CC
V
CC
= 5.5 V
100
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 5.5 V
-0.45
-0.45
-0.45
0.25V
CC
0.25V
CC
0.3V
CC
Input low voltage
(SDA, SCL)
V
IL
V
V
CC
= 1.8 V
V
CC
= 2.5 V
CC
= 5.5 V
0.75V
CC
V
CC
+1
0.75V
CC
V
CC
+1
0.7V
CC
V
CC
+1
Input high voltage
(SDA, SCL)
V
IH
V
V
V
I
OL
= 2.1 mA, V
CC
= 1.8 V or
I
OL
= 3 mA, V
CC
= 5.5 V
V
OL
Output low voltage
–
0.4
1. SCL,
SDA connected to Ground or V
CC.
SDA connected to V
CC
through a pull-up resistor.
DocID022712 Rev 12
121/144
2
I C
DC and AC parameters
M24LR64E-R
2
Table 123. I
C AC characteristics
Symbol
Alt.
f
SCL
Clock frequency
Parameter
Min.
Max.
Unit
f
C
t
CHCL
25
400
kHz
t
HIGH
Clock pulse width high
t
LOW
Clock pulse width low
0.6 20000
(1)
µs
1.3 20000
(2)
µs
t
CLCH
t
START_OUT
–
I²C timeout on Start condition
Input signal rise time
Input signal fall time
40
20
–
300
300
100
–
ms
ns
ns
ns
ns
ns
ns
ns
ns
(3)
t
XH1XH2
t
R
t
F
t
F
(3)
t
XL1XL2
20
t
DL1DL2
t
DXCX
t
CLDX
SDA (out) fall time
20
t
SU:DAT
Data in set up time
t
HD:DAT
Data in hold time
100
0
–
(4)
t
CLQX
t
DH
t
AA
Data out hold time
100
100
600
–
(5)
t
CLQV
Clock low to next data valid (access time)
900
(6)
t
CHDX
t
SU:STA
Start condition set up time
t
HD:STA
Start condition hold time
t
SU:STO
Stop condition set up time
–
t
DLCL
t
CHDH
t
DHDL
t
W
0.6 35000
(7)
µs
600
–
–
ns
ns
t
BUF
Time between Stop condition and next Start condition
1300
I²C write time
–
–
5
ms
1. t
CHCL
timeout.
2. t
CLCH
timeout.
3. Values
recommended by the I²C-bus Fast-Mode specification.
4.
T
o
a
void spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V
CC
in
a compatible way with the I
2
C specification (which specifies t
SU:DAT
(min) = 100 ns), assuming
6. For
a reStart condition, or following a write cycle.
7. t
DLCL
timeout.
122/144
DocID022712 Rev 12
2
M24LR64E-R
I C DC and AC parameters
2
Figure 80. I C AC waveforms
T8,ꢀ8,ꢆ
T#(#,
T#,#(
T8(ꢀ8(ꢆ
3#,
T$,#,
T8,ꢀ8,ꢆ
3$! )N
T#($8
3TART
CONDITION
T#,$8
T$8#8
3$!
#HANGE
T8(ꢀ8(ꢆ
T#($( T$($,
3TART
3$!
)NPUT
3TOP
CONDITION
CONDITION
3#,
3$! )N
T7
7RITE CYCLE
T#($(
T#($8
3TOP
CONDITION
3TART
CONDITION
T#(#,
3#,
T#,16
T#,18
$ATA VALID
T$,ꢀ$,ꢆ
$ATA VALID
3$! /UT
!)ꢃꢃꢎꢏꢁE
DocID022712 Rev 12
123/144
Write cycle definition
M24LR64E-R
29
Write cycle definition
(1)
Table 124. Write cycle endurance
Test conditions
Symbol
Parameter
Min
Max
Unit
T
A
≤
+ 25 °C
V
CC(min)
< V
CC
< V
CC(max)
–
–
1000000
150000
Write cycle
(2)
N
cycle
Write cycle
endurance
(3)
T
A
≤
+ 85 °C
V
CC(min)
< V
CC
< V
CC(max)
1. A
write cycle means the simultaneous writing of one byte, two bytes, three bytes or four bytes (one page).
2. Indicates
the total number of write/erase cycles for one memory cell or the overall number of write/erase
cycles decoded by the whole memory.
3. Write
cycle endurance is defined by characterization and qualification.
124/144
DocID022712 Rev 12
M24LR64E-R
RF electrical parameters
30
RF electrical parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device in RF mode.
The parameters in the DC and AC characteristics tables that follow are derived from tests
performed under the Measurement Conditions summarized in the relevant tables.
Designers should check that the operating conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
(1) (2)
Table 125. RF characteristics
Symbol
Parameter
Condition
Min
Typ
Max Unit
f
CC
External RF signal frequency
–
13.553 13.56 13.567
MHz
mA/
H_ISO
Operating field according to ISO
T
A
= -40 °C to 85 °C
150
–
5000
m
150 mA/m > H_ISO > 1000
mA/m
10% carrier modulation index
(3)
MI=(A-B)/(A+B)
15
–
30
MI
CARRIER
%
H_ISO > 1000 mA/m
10
0.5
7.1
95
0.5
7
–
–
–
–
–
–
30
3.0
t
RFR
, t
RFF
10% rise and fall time
–
µs
µs
%
t
RFSBL
10% minimum pulse width for bit
–
9.44
100
3.5
MI
CARRIER
100% carrier modulation index
t
RFR
, t
RFF
100% rise and fall time
MI=(A-B)/(A+B)
(4)
–
–
µs
µs
t
RFSBL
t
MIN CD
100% minimum pulse width for bit
9.44
Minimum time from carrier
generation to first data
From H-field min
–
–
1
ms
f
SH
f
SL
t
1
Subcarrier frequency high
Subcarrier frequency low
Time for M24LR64E-R response
Time between commands
f
CC
/32
f
CC
/28
–
–
423.75
484.28
–
–
kHz
kHz
µs
4224/f
S
4224/f
S
318.6 320.9 323.3
t
2
309
–
311.5
5.75
314
–
µs
RF write time (including internal
Verify)
W
t
–
ms
I
CC_RF
C
TUN
Operating current (Read)
(5)
VAC0-VAC1 (4 V peak to peak)
f = 13.56 MHz
–
20
–
µA
pF
Internal tuning capacitor in SO8
(6)
24.8
27.5
30.2
Backscattered level as defined by
ISO test
V
BACK
ISO10373-7
10
–
–
–
–
mV
RF input voltage amplitude
between AC0 and AC1, GND pad
left floating, VAC0-VAC1 peak to
peak
(7)
(3)
V
MAX_1
–
–
–
20
8.5
V
AC voltage between AC0 and
GND or between AC1 and GND
(3)
V
MAX_2
-1
V
DocID022712 Rev 12
125/144
RF electrical parameters
M24LR64E-R
Max Unit
(1) (2)
Table 125. RF characteristics
(continued)
Symbol
Parameter
Condition
Min
Typ
RF input voltage amplitude
between AC0 and AC1, GND pad
left floating, VAC0-VAC1 peak to
peak
(7)
Inventory and Read operations
–
4
4.5
5
V
V
(3)
V
MIN_1
Write operations
–
4.5
Inventory and Read operations
Write operations
–
–
1.8
2
2
2.2
–
V
V
AC voltage between AC0 and
GND or between AC1 and GND
(3)
V
MIN_2
t
RF_OFF
RF OFF time
Chip reset
2
–
ms
1. T
A
= –40 to 85 °C. Characterized only.
2. All
timing characterizations were performed on a reference antenna with the following characteristics:
External size: 75 mm x 48 mm
Number of turns: 5
Width of conductor: 0.5 mm
Space between two conductors: 0.3 mm
Value of the tuning capacitor in SO8: 27.5 pF (M24LR64E-R)
Value of the coil: 5 µH
Tuning frequency: 13.56 MHz.
3. 15%
(or more) carrier modulation index offers a better signal/noise ratio and therefore a wider operating
range with a better noise immunity.
4.
T
e
mperature
range 0 °C to 90 °C.
5. Characterized
on bench.
6. Characterized
only, at room temperature only, measured at VAC0-VAC1 = 1 V peak to peak.
7. Characterized
only, at room temperature only.
Table 126. Operating conditions
Symbol
Parameter
Min.
Max.
Unit
T
A
Ambient operating temperature
-40
85
°C
Figure 81
shows an ASK modulated signal from the VCD to the M24LR64E-R. The test
conditions for the AC/DC parameters are:
•
•
•
Close coupling condition with tester antenna (1 mm)
M24LR64E-R performance measured at the tag antenna
M24LR64E-R synchronous timing, transmit and receive
126/144
DocID022712 Rev 12
M24LR64E-R
RF electrical parameters
Figure 81. ASK modulated signal
W
5))
$
%
W
5)5
I
&&
W
5)6%/
W
0,1ꢅ&’
-3ꢀꢏꢎꢉꢇ6ꢀ
AC0-AC1_min
required for
the Energy harvesting mode, the corresponding maximum current consumption
, and the variation of the analog voltage V
for the various Energy harvesting
I
sink_max
out
fan-out configurations defined by bits b0 and b1 of the Configuration byte.
(1) (2)
Table 127. Energy harvesting
(3)
(4)
Range
H
min
P
min
V
out
@I=0
V
out
@I
sink_max
I
sink_max
@P
min
2.7 V min
4.5 V max
00
3.5 A/m
2.4 A/m
1.6 A/m
1.0 A/m
100 mW
60 mW
30 mW
16 mW
1.7 V
6 mA
2.7 V min
4.5 V max
01
10
11
1.9 V
2.1 V
2.3 V
3 mA
1 mA
2.7 V min
4.5 V max
2.7 V min
4.5 V max
300 µA
1. Characterized
only.
2. Valid
from -40 °C to +85 °C.
3. H
min
characterized according to ISO10373-7 test method.
4. P
min
calculated from DC measurements.
Note:
It is recommended to choose the Energy Harvesting Range according to the
maximum current requested by the application to avoid any disabling of Energy
Harvesting mode (for example, choose Range 01 for a max consumption of
2 mA).
DocID022712 Rev 12
127/144
RF electrical parameters
M24LR64E-R
Figure 82. Energy harvesting: V
min vs. I
out
sink
7PVU
ꢀꢁꢂꢃ7
ꢀꢁꢄꢃ7
ꢀꢁꢅꢃ7
ꢅꢁꢆꢃ7
ꢅꢁꢂꢃ7
ꢈꢃN”
ꢅꢃN”
ꢇꢁꢄꢃN”
ꢄꢃN”
*TJOL
-3ꢀꢏꢎꢎꢎ6ꢀ
Figure 83. Energy harvesting: working domain range 11
)DQꢄRXW
ꢅ$ꢆ
ꢊꢅP$
:RUNLQJꢅGRPDLQꢅZKHQ
5DQJHꢅꢀꢀꢅLVꢅVHOHFWHG
ꢃꢅP$
ꢀꢅP$
ꢉꢂꢃꢅP$
)LHOG
ꢅ+UPVꢆ
ꢀꢅ$ꢐP ꢀꢂꢊꢅ$ꢐP
ꢁꢂꢆꢅ$ꢐP
ꢃꢂꢈꢅ$ꢐP
ꢈꢅ$ꢐP
06ꢀꢄꢇꢄꢉ9ꢀ
128/144
DocID022712 Rev 12
M24LR64E-R
RF electrical parameters
Figure 84. Energy harvesting: working domain range 10
)DQꢄRXW
ꢅ$ꢆ
ꢊꢅP$
:RUNLQJꢅGRPDLQꢅZKHQ
5DQJHꢅꢀꢉꢅLVꢅVHOHFWHG
ꢃꢅP$
ꢀꢅP$
ꢉꢂꢃꢅP$
)LHOG
ꢅ+UPVꢆ
ꢀꢅ$ꢐP ꢀꢂꢊꢅ$ꢐP
ꢁꢂꢆꢅ$ꢐP
ꢃꢂꢈꢅ$ꢐP
ꢈꢅ$ꢐP
06ꢀꢄꢇꢄꢀ9ꢀ
Figure 85. Energy harvesting: working domain range 01
)DQꢄRXW
ꢅ$ꢆ
ꢊꢅP$
:RUNLQJꢅGRPDLQꢅZKHQ
5DQJHꢅꢉꢀꢅLVꢅVHOHFWHG
ꢃꢅP$
ꢀꢅP$
ꢉꢂꢃꢅP$
)LHOG
ꢅ+UPVꢆ
ꢀꢅ$ꢐP ꢀꢂꢊꢅ$ꢐP
ꢁꢂꢆꢅ$ꢐP
ꢃꢂꢈꢅ$ꢐP
ꢈꢅ$ꢐP
06ꢀꢄꢇꢄꢁ9ꢀ
DocID022712 Rev 12
129/144
RF electrical parameters
M24LR64E-R
Figure 86. Energy harvesting: working domain range 00
)DQꢄRXW
ꢅ$ꢆ
:RUNLQJꢅGRPDLQꢅZKHQ
5DQJHꢅꢉꢉꢅLVꢅVHOHFWHG
ꢊꢅP$
ꢃꢅP$
ꢀꢅP$
ꢉꢂꢃꢅP$
)LHOG
ꢅ+UPVꢆ
ꢀꢅ$ꢐP ꢀꢂꢊꢅ$ꢐP
ꢁꢂꢆꢅ$ꢐP
ꢃꢂꢈꢅ$ꢐP
ꢈꢅ$ꢐP
06ꢀꢄꢇꢄꢃ9ꢀ
130/144
DocID022712 Rev 12
M24LR64E-R
Package information
31
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages,
depending on their level of environmental compliance. ECOPACK
®
ECOPACK is
an ST trademark.
31.1
SO8N package information
Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
H X
ꢁ
ꢆ
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!
C
CCC
B
E
ꢀꢁꢂꢃꢄPP
*$8*(ꢄ3/$1(
$
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ꢅ
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62ꢌ$B9ꢁ
1. Drawing
is not to scale.
Table 128. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data
millimeters
Typ.
inches
(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
–
–
1.750
0.250
–
–
–
0.0689
0.0098
–
0.100
1.250
0.280
0.170
4.800
5.800
3.800
–
–
0.0039
0.0492
0.0110
0.0067
0.1890
0.2283
0.1496
–
–
–
–
–
0.480
0.230
5.000
6.200
4.000
–
–
0.0189
0.0091
0.1969
0.2441
0.1575
–
c
–
4.900
6.000
3.900
1.270
–
–
D
E
0.1929
0.2362
E1
e
0.1535
0.0500
h
0.250
0°
0.500
8°
0.0098
0°
–
–
–
0.0197
8°
k
–
L
0.400
–
1.270
0.0157
0.0500
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Package information
M24LR64E-R
Table 128. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data (continued)
millimeters
inches
(1)
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
L1
–
–
1.040
–
–
–
–
0.0409
–
–
ccc
0.100
0.0039
1. Values
in inches are converted from mm and rounded to four decimal digits.
Figure 88. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint
ꢉꢂꢊꢅꢍ[ꢋꢎ
ꢀꢂꢁꢇ
2ꢇB62ꢋ1B)3B9ꢀ
1. Dimensions
are expressed in millimeters.
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M24LR64E-R
Package information
31.2
UFDFN8 package information
Figure 89. UFDFN8 – 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package outline
$
‘
%
1
$
$ꢀ
FFF
ꢃ
3LQꢅꢑꢀꢅ
,’ꢅPDUNLQJ
&
(
HHH &
6HDWLQJꢅSODQH
$ꢃ
6LGHꢅYLHZ
DDD
&
ꢁ[
ꢀ
ꢁ
ꢁ[
DDD &
7
R
SꢅYLHZ
‘ꢁ
H
‘DWXPꢅ$
E
ꢀ
ꢁ
/ꢀ
/ꢃ
3LQꢅꢑꢀꢅ
/
/ꢃ
(ꢁ
.
,’ꢅPDUNLQJ
Hꢐꢁ
/ꢀ
7
H
UPLQDOꢅWLS
H
‘HWDLOꢅ³$´
/
(YHQꢅWHUPLQDO
1’ꢌꢀꢅ
[
H
%RWWRPꢅYLHZ
6HHꢅ’HWDLOꢅ³$´
=:EB0(B9ꢀ
1. Max.
package warpage is 0.05 mm.
2. Exposed
copper is not systematic and can appear partially or totally according to the cross section.
3. Drawing
is not to scale.
4. The
central pad (E2 by D2 in the above illustration) is internally pulled to V
SS
. It must not be connected to
any other voltage or signal line on the PCB, for example during the soldering process.
Table 129. UFDFN8 – 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package mechanical data
millimeters
Typ
inches
(1)
Symbol
Min
Max
Min
Typ
Max
A
0.450
0.000
0.200
1.900
1.200
2.900
0.550
0.020
0.250
2.000
–
0.600
0.050
0.300
2.100
1.600
3.100
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0217
0.0008
0.0098
0.0787
–
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
A1
b
(2)
D
D2
E
3.000
0.1181
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Package information
M24LR64E-R
Table 129. UFDFN8 – 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package mechanical data (continued)
millimeters
Typ
inches
(1)
Symbol
Min
Max
Min
Typ
Max
E2
1.200
–
1.600
–
0.0472
–
0.0630
e
–
0.500
0.0197
K
0.300
–
–
–
–
–
–
–
–
–
–
0.0118
–
–
–
–
–
–
–
–
–
–
L
0.300
0.500
0.150
–
0.0118
0.0197
0.0059
–
L1
–
–
L3
0.300
0.0118
aaa
bbb
ccc
ddd
eee
(3)
–
–
–
–
–
0.150
0.100
0.100
0.050
0.080
–
–
–
–
–
0.0059
0.0039
0.0039
0.0020
0.0031
1. Values
in inches are converted from mm and rounded to four decimal digits.
2. Dimension
b applies to plated terminal and is measured between 0.15 and 0.30 mm from the
terminal tip.
3. Applied
for exposed die paddle and terminals. Exclude embedding part of exposed die paddle
from measuring.
31.3
TSSOP8 package information
Figure 90.TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package outline
ꢄ
ϴ
ϱ
Đ
ꢁϭ
ꢁ
ϭ
ϰ
ɲ
>
ꢂϭ
ꢂϮ
ꢂ
>ϭ
ꢃW
ď
Ğ
76623ꢋ$0B9ꢁ
1. Drawing
is not to scale.
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M24LR64E-R
Package information
Table 130. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package mechanical data
millimeters
Typ.
inches
(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
–
–
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
–
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
–
–
0.0020
0.0315
0.0075
0.0035
–
–
1.000
–
0.0394
–
c
–
–
CP
D
–
–
2.900
–
3.000
0.650
6.400
4.400
0.600
1.000
–
0.1142
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
–
e
E
6.200
4.300
0.450
–
6.600
4.500
0.750
–
0.2441
0.1693
0.0177
–
0.2598
0.1772
0.0295
–
E1
L
L1
α
0°
8°
0°
8°
1. Values
in inches are converted from mm and rounded to four decimal digits.
DocID022712 Rev 12
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Part numbering
M24LR64E-R
32
Part numbering
Table 131. Ordering information scheme for packaged devices
Example:
M24LR64E-R
MN
6
T
/2
Device type
M24LR = dynamic NFC/RFID tag IC
64 = memory size in Kbit
E = support for energy harvesting
Operating voltage
(1)
R = V
CC
= 1.8 to 5.5 V
Package
MN = SO8N (150 mils width)
MC
= UFDFPN8
(MLP8)
DW = TSSOP8
SB12I = 120 µm ± 15 µm bumped and sawn
inkless wafer on 8-inch frame
(2)
RUW20 = 725 µm ± 25 µm unsawn inkless
Device grade
(1)
6 = industrial: device tested with standard
test flow over –40 to 85 °C
Option
(1)
T =
T
a
pe and reel packing
Capacitance
(1)
/2 = 27.5 pF
1. For
packaged devices only.
2. Delivery
type: wafer tested. Bad chip identification by STIF wafer maps available on
STMicroelectronics inkless central transfer server.
Note:
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
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M24LR64E-R
Part numbering
Table 132. Ordering and marking information
First line marking
Reference
Package
Ordering code
Initial revision
(0xF)
Actual revision
(0xE and below)
TSSOP08
MLP
M24LR64E-RDW6T/2
M24LR64E-RMC6T/2
M24LR64E-RMN6T/2
M24LR64E-SB12I/2
M24LR64E-RUW20/2
464EU
4FEUB
464E
4FEB
M24LR64E-R
SO8N
24L64ER
24LFERB
SB12I
–
–
–
–
RUW20
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Anticollision algorithm (informative)
M24LR64E-R
Appendix A
Anticollision algorithm (informative)
The following pseudocode describes how anticollision could be implemented on the VCD,
using recursivity.
A.1
Algorithm for pulsed slots
function push (mask, address); pushes on private stack
function pop (mask, address); pops from private stack
function pulse_next_pause; generates a power pulse
function store(M24LR64E-R_UID); stores M24LR64E-R_UID
function poll_loop (sub_address_size as integer)
pop (mask, address)
mask = address & mask; generates new mask
; send the request
mode = anticollision
send_Request (Request_cmd, mode, mask length, mask value)
for sub_address = 0 to (2^sub_address_size – 1)
pulse_next_pause
if no_collision_is_detected ; M24LR64E-R is inventoried
then
store (M24LR64E-R_UID)
else ; remember a collision was detected
push(mask,address)
endif
next sub_address
if stack_not_empty ; if some collisions have been detected and
then
poll_loop (sub_address_size); recursively to process the last
stored collision
; not yet processed, the function calls itself
endif
end poll_loop
main_cycle:
mask = null
address = null
push (mask, address)
poll_loop(sub_address_size)
end_main_cycle
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CRC (informative)
Appendix B
CRC (informative)
B.1
CRC error detection method
The cyclic redundancy check (CRC) is calculated on all data contained in a message, from
the start of the flags through to the end of Data. The CRC is used from VCD to M24LR64E-
R and from M24LR64E-R to VCD.
Table 133. CRC definition
CRC type
Length
Polynomial
Direction
Preset
Residue
ISO/IEC 13239
16 bits
X
16
+ X
12
+ X
5
+ 1 = 8408h
Backward
FFFFh
F0B8h
To
a
dd extra protection against shifting errors, a further transformation on the calculated
CRC is made. The one’s complement of the calculated CRC is the value attached to the
message for transmission.
To
c
heck received messages, the two CRC bytes are often also included in the re-
calculation, for ease of use. In this case, the expected value for the generated CRC is the
residue F0B8h.
B.2
CRC calculation example
This example in C language illustrates one method of calculating the CRC on a given set of
bytes comprising a message.
C-example to calculate or check the CRC16 according to ISO/IEC 13239
#define POLYNOMIAL0x8408// x^16
+ x^12 + x^5 + 1
#define PRESET_VALUE0xFFFF
#define CHECK_VALUE0xF0B8
#define NUMBER_OF_BYTES4//
Example: 4 data bytes
#define CALC_CRC1
#define CHECK_CRC0
void main()
{
unsigned int
current_crc_value;
unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3, 4, 0x91,
0x39};
int
int
int
number_of_databytes = NUMBER_OF_BYTES;
calculate_or_check_crc;
i, j;
calculate_or_check_crc = CALC_CRC;
// calculate_or_check_crc = CHECK_CRC;// This could be an other example
if (calculate_or_check_crc == CALC_CRC)
{
number_of_databytes = NUMBER_OF_BYTES;
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CRC (informative)
M24LR64E-R
}
else
{
// check CRC
number_of_databytes = NUMBER_OF_BYTES + 2;
}
current_crc_value = PRESET_VALUE;
for (i = 0; i < number_of_databytes; i++)
{
current_crc_value = current_crc_value ^ ((unsigned
int)array_of_databytes[i]);
for (j = 0; j < 8; j++)
{
if (current_crc_value & 0x0001)
{
current_crc_value = (current_crc_value >> 1) ^ POLYNOMIAL;
}
else
{
current_crc_value = (current_crc_value >> 1);
}
}
}
if (calculate_or_check_crc == CALC_CRC)
{
current_crc_value = ~current_crc_value;
printf (“Generated CRC is 0x%04Xn”, current_crc_value);
// current_crc_value is now ready to be appended to the data stream
// (first LSByte, then MSByte)
}
else
{
// check CRC
if (current_crc_value == CHECK_VALUE)
{
printf (“Checked CRC is ok (0x%04X)n”, current_crc_value);
}
else
{
printf (“Checked CRC is NOT ok (0x%04X)n”, current_crc_value);
}
}
}
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Application family identifier (AFI) (informative)
Appendix C
Application family identifier (AFI)
(informative)
The AFI (application family identifier) represents the type of application targeted by the VCD
and is used to extract from all the M24LR64E-Rs present only the one meeting the required
application criteria.
It is programmed by the M24LR64E-R issuer (the purchaser of the M24LR64E-R). Once
locked, it cannot be modified.
The most significant nibble of the AFI is used to code one specific or all application families,
The least significant nibble of the AFI is used to code one specific or all application
subfamilies. Subfamily codes different from 0 are proprietary.
(1)
Table 134. AFI coding
AFI most
significant
nibble
AFI least
significant
nibble
Meaning VICCs respond from
Examples / Note
‘0’
‘X’
‘X
‘0’
‘1
‘0’
All families and subfamilies
All subfamilies of family X
Only the Y
th
subfamily of family X
Proprietary subfamily Y only
Transport
No applicative preselection
‘0
Wide applicative preselection
‘‘Y’
–
‘Y’
–
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘‘0’, ‘Y’
‘0’, ‘Y’
Mass transit, bus, airline,…
‘2
Financial
IE
P
,
b
anking, retail,…
‘3
Identification
Access control,…
‘4
T
e
lecommunication
Medical
Public telephony, GSM,…
‘5’
‘6
–
Multimedia
Internet services….
‘7
Gaming
–
8
Data Storage
Portable files,…
‘9
Item management
Express parcels
Postal services
Airline bags
–
–
–
–
–
–
–
‘A
‘B
‘C
‘D
‘E
‘F’
RFU
RFU
RFU
1. X
= ‘1’ to ‘F’, Y = ‘1’ to ‘F’
DocID022712 Rev 12
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Revision history
M24LR64E-R
Revision history
Table 135. Document revision history
Changes
Date
Revision
12-Apr-2012
1
Initial release.
08-Jun-2012
19-Jun-2012
2
3
21-Feb-2013
4
07-Mar-2013
12-Jun-2013
5
6
Removed MB package from
Figure 88: UFDFPN8 (MLP8) – 8-lead ultra
thin fine pitch dual flat package no lead 2 × 3mm, package outline
.
21-Nov-2014
06-Nov-2015
7
8
Updated figure on Cover page with new wafer code SB12I.
27-Apr-2016
09-May-2016
9
10
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Revision history
Table 135. Document revision history (continued)
Revision Changes
Date
Updated image on cover page with introduction of RUW20 wafer option.
13-Mar-2017
11
12
20-Jul-2017
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M24LR64E-R
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of S
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A
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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