STMicroelectronics-ST25DV02K-W2R8T3

ST25DV02K-W1 ST25DV02K-W2  

Datasheet  

Dynamic NFC/RFID tag IC with up to two PWM outputs and 2-Kbit EEPROM  

Features  

Pulse width modulation outputs  

•

Two independent outputs: 1x PWM output on ST25DV02K-W1, 2x PWM outputs  

on ST25DV02K-W2  

SO8  

•

•

From 488 Hz to 31250 Hz  

62.5 ns pulse width resolution: from 15-bit resolution at 488 Hz to 9-bit resolution  

at 31.25 kHz  

•

•

•

•

Accuracy: ±10% over temperature range  

No need for external oscillator  

Supply voltage from 1.8 V to 5.5

V

,

i

ndependent from contactless interface  

Independent push-pull outputs  

TSSOP8  

–

–

Up to 4 mA drive capability per output  

Adjustable output drive for low power and low noise application  

•

Live update of PWM parameters controlled by contactless interface  

Contactless interface  

•

•

Based on ISO/IEC 15693 and NFC Forum Type 5

T

a

g  

Supports all ISO/IEC 15693 modulations, coding, sub-carrier modes and data  

rates  

•

•

Single and multiple blocks read  

Internal tuning capacitance: 28.5 pF  

Product status link  

Memory  

•

•

•

•

•

2-kbit of EEPROM  

Accessible in blocks of 4x bytes  

5 ms typical write time (one block)  

Data retention: 40 years  

Write cycles endurance: 100k write cycles at 85 ºC  

Data protection  

•

Up to four independent areas, including the PWM control area, with flexible  

protection mechanism based on 32/64-bits passwords  

System configuration: write protection by 32-bit password  

TruST25™ Digital signature mechanism for authentication  

•

•

Temperature range  

•

•

From -40°C to +85°C (Contactless interface)  

From -40 °C to +105 °C (PWM interface)  

Package  

•

•

SO8N and TSSOP8  

ECOPACK2 (RoHS compliant)  

DS12114

–

Rev 6

–

August 2019  

For further information contact your local STMicroelectronics sales office.  

ST25DV02K-W1 ST25DV02K-W2  

Description  

1

Description  

The ST25DV02K-W1/2 is an ISO 15693 and NFC Forum Type 5 tag, with one or two pulse width modulation  

(PWM) outputs and 2 Kbits of electrically erasable programmable memory (EEPROM).  

It offers two interfaces. The first delivers up to 2x independent PWM output signals and the second is an RF link  

activated by the received carrier electromagnetic wave.  

The PWM outputs are configured at boot time, and can be updated live through RF link. RF and PWM are  

independently powered and can work in stand-alone mode.  

The ST25DV02K-W1/2 contains 256 bytes (64 blocks) of memory for User data. This memory is accessible  

through the RF interface, following ISO/IEC 15693 or NFC Forum Type 5

T

a

g recommendations.  

The device is based on technology and design solutions for which there are pending patents.  

1.1  

Block diagram  

Figure 1.

Block diagram  

EEPROM  

ANALOG FRONT END  

AC0  

AC1  

VCC  

PWM1  

PWM2  

VSS  

RF INTERFACE  

28.5pF tuning  

capacitance  

User data  

memory  

DIGITAL UNIT  

CONTROL  

Pulse width  

Modulation  

ISO/IEC 15693  

PROTOCOL  

AND CONTROL  

PWM Control  

registers  

MEMORY  

CONTROL  

System registers  

Note:  

PWM2 is available only on ST25DV02K-W2.  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

Package connections  

1.2  

Package connections  

ST25DV02K-W1/2 is provided in two different packages:  

•

•

SO8N  

TSSOP8  

Table 1.

Signal names  

Function  

Signal name  

Direction  

AC0  

AC1  

Antenna coils  

I/O  

Antenna coils  

PWM supply voltage  

PWM output  

PWM output  

Ground  

I/O  

V

Power  

Output  

Output  

–

CC  

PWM1  

PWM2

V

SS  

1. Available

 

only on ST25DV02K-W2.  

Figure 2.

ST25DV02K-W1/2 8-pin package connections  

1

2

3

4

8

7

6

5

NC  

AC0  

AC1  

NC  

VCC  

NC/PWM2  

PWM1  

VSS  

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ST25DV02K-W1 ST25DV02K-W2  

Signal description  

2

Signal description  

2.1  

Pulse width modulation output (PWM1)  

This signal provides a pulse width modulation output. It is a push-pull output signal, driven between V

SS

and V

CC  

.

PWM1 output is in high impedance state, as long as it is disabled.  

2.2  

2.3  

Pulse width modulation output (PWM2)  

This signal provides a pulse width modulation output. It is a push-pull output signal, driven between V

SS

and V

CC  

PWM2 is independent from PWM1. PWM2 output is available on ST25DV02K-W2 only, and it is in high  

impedance state, as long as it is disabled.  

.

PWM power supply (V

 

)  

CC  

This pin must be connected to an external DC supply voltage to have the PWM output(s) working.  

PWM power supply is independent from the RF NFC tag part: The RF NFC tag works whatever V

CC

power supply  

state is. On the other side, PWM outputs work as soon as V

CC

power is supplied, and whatever RF field state is.  

2.4  

2.5  

PWM ground reference (V

 

)  

SS  

V

SS

is the reference for the V

CC

and PWM pins.  

Antenna coil (AC0, AC1)  

These inputs are used exclusively to connect the ST25DV02K-W1/2 device to an external coil. It is advised not to  

connect any other DC or AC path to AC0 or AC1.  

When correctly tuned, the coil is used to power and access the device using the ISO/IEC 15693 and ISO 18000-3  

mode 1 protocols.  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

Power management  

3

Power management  

3.1  

Wired interface  

Operating supply voltage V

CC  

A valid and stable V

CC

voltage within the specified [V

CC

(min), V

CC

(max)] range must be applied to guarantee  

PWM outputs within expected range (clock stability, jitter).

T

o

m

aintain a stable DC supply voltage, it is  

recommended to decouple the V

CC

line with a suitable capacitor (usually one ~10 nF capacitor plus one ~100 pF  

capacitor) close to the V

CC

/V

SS

package pins.  

Power-up conditions  

When the power supply is turned on, V

CC

rises from V

SS

to V

CC

. The V

CC

rise time must not vary faster than  

1V/µs.  

At power-up (continuous rise of V

CC

), the ST25DV02K-W enter PWM boot, as soon as V

CC

reaches the power-on  

reset threshold voltage.  

t_boot_PWM time applies to complete PWM boot and get valid PWM output signals.  

In case of contactless interface access to EEPROM, the PWM boot is waiting for the end of EEPROM accesses  

to start.  

Power-down conditions  

At power-down (continuous decrease of V

CC

), as soon as V

CC

drops below the power-on reset threshold voltage,  

the PWM output states are not guaranteed anymore.  

Figure 3.

Power-up/down sequence  

V

CC

(min)  

V

CC  

t

BOOT_PWM  

PWM1/  

PWM2  

Hz  

X

Hz  

Valid  

X

Hz  

Note:  

Valid when RF interface is OF

F

,

o

therwise the priorities described in

apply.  

DS12114

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page 5/74  

ST25DV02K-W1 ST25DV02K-W2  

Contactless interface  

3.2  

Contactless interface  

Device set in RF mode  

To

e

nsure a proper boot of the RF circuitry, the RF field must be turned ON without any modulation for a minimum  

period of time t

RF_ON

. Before this time, ST25DV02K-W1/2 ignores all received RF commands (see

).  

Device reset in RF mode  

To

e

nsure a proper reset of the RF circuitry, the RF field must be turned off for a minimum t

RF_OFF

period of time.  

Figure 4.

RF power-up sequence  

RF Field:  

t

BOOT_RF  

OFF  

ON = RF interface ready  

RF State:  

Boot  

No RF access  

allowed  

1.  

Valid when PWM power supply (V

CC

) is stable since t_boot_PWM, otherwise the priorities described in  

apply.  

3.3  

RF and PWM boots priority  

RF and PWM interfaces are independent, but the following boots priorities apply:  

•

If PWM boot (V

CC

rising edge) occurs while RF is booting, or RF is in use, the PWM boot is delayed upon  

end of RF boot, or end of RF activity (EOF).  

•

•

If RF boot (Field On) occurs while PWMs are booting, the RF boot is delayed upon PWM boot completion.  

If RF boot (Field On) occurs while PWMs are running (valid PWM output signals), RF boot starts as  

described in

.  

Note:  

It is recommended to run RF sequences (RF Field On, set of RF commands, RF Field Off) either before PWM  

boot (V

CC

power supply is OFF and stable), or after PWM boot is completed (V

CC

power supply is ON and  

stable).  

DS12114

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Rev 6  

page 6/74  

ST25DV02K-W1 ST25DV02K-W2  

Memory management  

4

Memory management  

4.1  

Memory organization  

The ST25DV02K-W1/2 memory is organized as follows:  

•

User memory: it is composed of four different areas, as described in

. It contains  

areas for user’s data, area for PWM control and area to store NFC T5 CC file if required.  

•

System configuration memory: it is composed of different configuration registers, among which the device  

configuration, the ISO15693 AFI & DSFID registers. It also contains the UID and different protection  

registers. Refer to

for more details  

Figure 5.

Memory organization  

AREA0  

(CC File)  

AREA1  

User memory  

AREA2

(1)  

PWM_CTRL  

CFG  

System configuration  

1. Can be merged with AREA1  

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ST25DV02K-W1 ST25DV02K-W2  

User memory  

4.2  

User memory  

User memory is addressed as blocks (= pages) of 4 bytes, starting at address 0.  

All the blocks of the user memory are initialized to 00h in the factory.  

The ST25DV02K-W1/2 user memory areas are defines as follow:  

•

AREA0 starts at address 00h. It is composed of 1x block (4x bytes) which is always readable, and can be  

locked. AREA0 has been though for the CC file content according to NFC Type 5 formalism. However an  

application, which does not require to be NFC Type5 compliant, can do any other usage of this block.  

•

•

AREA1 starts at address 01h. It is composed of 31x blocks (124x bytes). It can be read and/or write-  

protected by dedicated 1×32-bit password. AREA1 is dedicated to user’s data.  

AREA2 starts at address 20h. It is composed of 32x blocks (128x bytes). It can be read, and/or write-  

protected by dedicated 1×32-bit password. AREA2 is dedicated to user’s data.  

Note:  

AREA1 and AREA2 can be merged in a single area of 63x blocks (252x bytes), which can be read – and/or –  

write-protected by 1×64-bit password.  

•

PWM CTRL area starts at address F8h. It is composed of 2x blocks, one per PWM, and is dedicated to  

PWM control (Enable, Period value and Pulse Width value). It can be individually read – and/or – write-  

protected by 32-bit password.  

Areas definition are fixed and can not be changed (expect the merge of AREA1 and AREA2)  

and

show the user area mode explained above.  

Table 2.

User memory 4x areas configuration  

Block addr. (hex)  

Data bits [31:1]  

Comment  

RF command  

0

1

User 0 (4x bytes)  

AREA0 = CC file in case of NFC T5 application  

2

…

1E  

1F  

20  

…

…

…

3F  

–

User area (124x bytes)  

AREA1  

AREA2  

Read Single Block  

Read Multiple Blocks  

Write Single Block  

User area (128x bytes)  

–

–

F8  

F9  

PWM1 control  

PWM2 control  

PWM_CTRL  

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page 8/74  

ST25DV02K-W1 ST25DV02K-W2  

User memory  

Table 3.

User memory 3x areas configuration  

Block addr. (hex)  

Data bits [31:0]  

Comment  

RF command  

0

1

User 0 (4x bytes)  

AREA0 = CC file in case of NFC T5 application  

2

…

1E  

1F  

20  

…

…

…

3F  

–

User area (252x bytes)  

AREA1 merged with AREA2  

Read Single Block  

Read Multiple Blocks  

Write Single Block  

–

–

F8  

F9  

PWM1 control  

PWM2 control  

PWM_CTRL  

DS12114

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Rev 6  

page 9/74  

ST25DV02K-W1 ST25DV02K-W2  

System configuration memory  

4.3  

System configuration memory  

In addition to user memory, ST25DV02K-W1/2 includes a set of registers located in the system configuration  

memory. Registers content is read during the boots sequences and define basic ST25DV02K-W1/2 behaviour.  

Some of those registers can be accessed via Read Configuration and Write Configuration commands, with an  

identifier acting as the register address.  

shows the complete map of the system configuration registers,  

including their accessibility (Read / Write) and related conditions. More details are available in related registers  

table descriptions.  

Table 4.

System configuration memory map  

RF access  

Static Register  

Address  

Type  

RW

RW

RW

RW

RW

Name  

Function  

AREA1 security attributes  

00h  

01h  

02h  

03h  

04h  

AREA2 security attributes  

Area PWM_CTRL security attributes  

PWM Configuration and coexistence with RF interface  

Configuration registers permanent lock  

R

W

NA  

Blocks Write protection (1x lock bit per block)  

WO

WO

RW

RW

RO  

NA  

NA  

NA  

NA  

NA  

NA  

NA  

NA  

NA  

NA  

DSFID lock status  

AFI lock status  

DSFID value  

AFI value  

IC reference value  

RO  

Unique identifier, 8 bytes  

WO

WO

WO

WO

PWM Control area security session password, 4 bytes  

User AREA1 security session password, 4 bytes  

User AREA2 security session password, 4 bytes  

Configuration security session password, 4 bytes  

1. Write

 

access is granted if RF configuration security session is open and configuration is not locked (LOCK_CFG register  

equals to 0).  

2. LOCK_BLOCK

 

content is only readable through reading the Block Security Status of blocks.  

3. Write

 

access if the blocks are not already locked (=corresponding security session is open + block not already locked by a  

previous LOCK_BLOCK command).  

4. Write

 

access if DSFID is not already locked by a previous LOCK_DSFID command.  

5. Write

 

access if AFI is not already locked by a previous LOCK_AFI command.  

6. Write

 

access only if corresponding security session is open.  

DS12114

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Rev 6  

page 10/74  

ST25DV02K-W1 ST25DV02K-W2  

Specific features  

5

Specific features  

ST25DV02K-W1/2 offers the following features:  

•

•

•

•

Pulse width modulation output  

Data protection  

TruST25 digital signature  

Device parameter registers  

For some of them, the control registers are located in System Configuration area, and require the use of  

Read_Configuration or Write_Configuration commands. Update is only possible when the access right has been  

granted by presenting the configuration password (PWD_CFG), and if the system configuration was not  

previously locked (by LOCK_CFG=1).  

After any valid write access to the configuration registers, the new configuration is immediately applied.  

DS12114

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Rev 6  

page 11/74  

ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

5.1  

Pulse width modulation output  

The chip provides up to 2x Pulse width modulation (PWM) outputs. This chapter describes how to configure and  

use each PWM.  

5.1.1  

Control and configuration registers  

PWM control registers define the basic PWM settings for each PWM output: Enable, Period and Pulse width, as  

described in

.  

Table 5.

PWM1_CTRL access  

RF  

Command  

Type  

Read Single Block (cmd code 20h) @F8h  

Read Multiple Blocks (cmd code 23h) @F8h  

Lock Single Block (cmd code 22h) @ F8h  

Write Single Block (cmd code 21h) @F8h  

Read and Write protectable depending on APSA register content,  

on block lock status and on security session status (opened or  

closed)  

Table 6.

PWM1_CTRL  

Bit  

b14-b0  

b15  

Name  

PWM1_PERIOD  

RFU  

Function  

Factory Value  

PWM period value

The period of the PWM1 output signal is calculated using the following formula:  

0000h  

0b  

Period = ‘PWM1_PERIOD’ x PWMres (see

).  

PWM1_PERIOD value must be within the [512 : 32767] range.  

Reserved for future usage  

PWM pulse width value

:

The pulse width duration of the PWM1 output signal is calculated using the  

following formula:  

b30-b16  

b31  

PWM1_PULSEW  

00000h  

0b  

Pulse width = ‘PWM1_PULSEW’ x PWMres (see

). PWM1_PULSEW value must be within the [0 : 32767] range.  

PWM1_ENABLE Enable

 

of PWM output signal  

1. Refer

 

to

for details on PWM1_PERIOD and  

PWM1_PULSEW values.  

DS12114

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Rev 6  

page 12/74  

ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

PWM2_CTRL register only applies with ST25DV02K-W2 chip version (2x PWM outputs). In case of single PWM  

output device version (ST25DV02K-W1), PWM2_CTRL register value has to be kept to its factory value (all bits =  

0).  

Table 7.

PWM2_CTRL access  

RF  

Command  

Type  

Read Single Block (cmd code 20h) @F9h  

Read Multiple Blocks (cmd code 23h) @F9h  

Lock Single Block (cmd code 22h) @ F9h  

Write Single Block (cmd code 21h) @F9h  

R & W protectable depending on APSA register content, on block  

lock status and on security session status (opened or closed)  

Table 8.

PWM2_CTRL  

Bit  

b14-b0  

b15  

Name  

PWM2_PERIOD  

RFU  

Function  

Factory Value  

PWM period value

:

The period of the PWM2 output signal is calculated using following formula:  

Period = ‘PWM2_PERIOD’ x PWMres (see

)  

PWM2_PERIOD value must be within the [512 : 32767] range.  

0000h  

0b  

Reserved for future usage  

PWM pulse width value

:

The pulse width duration of the PWM2 output signal is calculated using the  

following formula:  

b30-b16  

b31  

PWM2_PULSEW  

PWM2_ENABLE  

00000h  

0b  

Pulse Width = ‘PWM2_PULSEW’ x PWMres (see

)  

PWM2_PULSEW value must be within the [0 : 32767] range.  

Enable of PWM output signal  

1. Refer

 

to

for details on PWM2_PERIOD and  

PWM2_PULSEW values.  

DS12114

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Rev 6  

page 13/74  

ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

PWM Configuration register defines the expert PWM settings: Drive and coexistence parameters, as described in  

.  

Table 9.

PWM_CFG access  

RF  

Command  

Type  

Read Configuration (cmd code A0h) @03h  

Write Configuration (cmd code A1h) @03h  

R always  

W if configuration security session is open and configuration not locked  

Table 10.

PWM_CFG  

Bit  

Name  

Function  

Factory Value  

b1-b0  

PWM1_DRIVE  

PWM output driver trimming:  

00b  

•

•

•

•

00: Full power output available  

01: ¾ of full power output available  

10: ½ of full power output available  

11: ¼ of full power output available  

b3-b2  

PWM2_DRIVE  

00b  

PWM and RF interface coexistence (applies to both PWM):  

•

•

•

000: Full coexistence of PWM output and RF interface  

1xx: PWM output set in HiZ during RF commands

b6-b4  

b7  

DUALITY_MNGT  

000b  

0b  

01x: Power of PWM output reduced to ¼ of full power during RF  

commands

0x1: PWM frequency reduced below Low_Freq

during RF  

commands

, while keeping PWM duty cycle  

•

RFU  

Reserved for future usage  

1. During

 

RF command period starts from SOF (Start of Frame) and ends at the end of the Answer.  

2. Refer

 

to

.  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

5.1.2  

Pulse width modulation feature description  

A PWM output is characterized by two parameters:  

•

•

its period (or frequency)  

its duty cycle, representing the percentage of time the signal is in high state  

Figure 6.

PWM output  

T

H

= Pulse width  

T

H  

T

α =  

= Duty Cycle  

T = Period  

Period and pulse width are used to define and control the PWM output, in addition to an enable signal, allowing to  

put the PWM output in HiZ state.  

PWM stage is supplied by V

CC

/V

SS

power pins. It is not supplied by RF interface. PWM works even when RF  

interface is OF

F

,

a

s long as power is supplied through V

CC

/V

SS

pins. Similarly, RF interface works without V

CC  

V

SS  

The PWM output stage is a push pull.  

/

.

Refer to

for details on V

CC

Power-on/power-off and related PWM output states.  

PWM control (PWM1_CTRL and PWM2_CTRL)  

PWM control registers are located in a dedicated user area (PWM_CTRL), which is protected by a dedicated  

password (PWD_PWM) and its own access right register (APSA). Each PWM output is controlled by an  

independent register: PWM1_CTRL and PWM2_CTRL.  

Each PWM control register provides user access to period value, pulse width value and an enable bit of the  

corresponding PWM output. Period and pulse width parameters are coded on 15 bits each: PWMx_PERIOD and  

PWMx_PULSEW.  

PWM output state is defined from these three parameters as follows:  

Table 11.

PWM output parameters  

PWM_EN  

PWMx_PERIOD  

PWMx_PULSEW  

PWM output state  

Comments  

0

x

x

HiZ  

0

Disabled  

< V  

0

OL  

P

1

0 < W < P  

≥ P  

PWM w. Duty Cycle  

[512 : 32767]  

> V  

1

OH  

An internal oscillator fixes the PWM resolution to PWMres (see

). The PWM  

output period and pulse width are defined as multiples of this resolution value:  

•

•

Period =

 

PWMres x PWMx_PERIOD  

Pulse Width = PWMres x PWMx_PULSEW  

PWM output functionality is guaranteed over PWMx_PERIOD range from 512 to 32767, which implies a Period  

range from 32 to 2048 µs (corresponding to a frequency from 31250 to 488.3 Hz). Over this range, the PWM  

output resolution is as follows:  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

Table 12.

PWM output resolution  

PWM output frequency  

(Hz)  

Number of bits used  

for PWMx_PERIOD  

PWM resolution  

(number of bits available to code PWMx_PULSEW)  

31250  

15625  

7813  

3906  

1953  

977  

9

9

10  

11  

12  

13  

14  

15  

10  

11  

12  

13  

14  

15  

488  

When PWM_CTRL registers are updated by a successful RF command (Write Single Block @ F8h/F9h with  

response), the related PWM output change applies as follows:  

Figure 7.

PWM output change  

Write single  

block new setup

 

EOF  

@ PWM_CTRL  

ST25DV02K-W  

response  

SOF  

SOF  

EOF  

RF  

t

PWM-UPD  

PWM out  

Previous setup  

New setup  

There is no anti-tearing mechanism on PWM_CTRL registers. Write access to PWM_CTRL registers must be  

done with stable RF field and constant V

CC

state (either ON or OFF). Otherwise the RF write operation may not  

complete properly, implying a loss/corruption of register content, requiring a new Write operation.  

PWM Configuration (PWM_CFG)  

PWM configuration register is located in System Configuration area.  

It provides access to output driver level adjustment, in addition to extended coexistence modes between RF and  

PWM interfaces.  

Configuration of PWM output driver trimming: the PWM push-pull output stage is able to drive up to I

MAX

(refer to  

) by default. If the application does not require full power it is possible to reduce the  

output drive capability independently through PWM_CFG trimming registers (PWM_CFG bits b1-b0 for PWM1  

and PWM_CFG bits b3-b2 for PWM2).  

DS12114

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Rev 6  

page 16/74  

ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

Table 13.

PWM output driver trimming  

PWM_CFG[1:0]/PWM_CFG[3:2]/  

PWM1/PWM2 output drive capability (sink and source)  

I

(default setup)

00b  

MAX  

75% of I  

50% of I  

25% I  

01b  

MAX  

MAX  

10b  

11b  

MAX  

1. Refer

 

to

.  

Configuration of PWM output coexistence with RF: a PWM_CFG Duality_Mngt register (PWM_CFG bits b6-b4)  

allows to reduce the impact of PWM noise over RF interface, and then help the coexistence. This register applies  

to both PWM outputs (when applicable).  

Table 14.

PWM output coexistence with RF interface  

PWM_CFG[6:4]  

000b  

Coexistence setting  

PWM and RF working normally and simultaneously (default setup)  

Put PWM outputs in HiZ state during RF commands.  

1xxb  

Reduce PWM outputs drive to minimum power level (25% of the maximum output power level), during RF  

commands.  

01xb  

0x1b  

Reduce PWM outputs frequencies (while keeping duty cycles), in order to move them below a predefined  

value (Low_Freq, see

), and then move out of the VCD RF sensitivity  

region. This option only applies if PWM output frequencies are above the predefined frequency value  

The option 1xxb = “Put PWM outputs in HiZ state” is exclusive option, whereas “Reduced PWM drive” and  

“Reduced frequency” options can be cumulated if needed.  

Coexistence options only applies “during RF commands”, in order to minimize impact on PWM output signals.  

“During RF commands” period is defined from Start-of-Frame of the request command, up to the End-of-Frame of  

the corresponding answer:  

Figure 8.

PWM answer  

Command1  

request from  

VCD  

Command1  

response from  

ST25DV02K-Wx  

Field  

ON  

Field  

OFF  

SOF  

EOF  

SOF  

EOF  

…  

…  

= “During RF commands”  

When PWM_CFG register is updated by a successful RF command (Write_Config @ 03h with response), PWM  

outputs change applies as follow:  

DS12114

–

Rev 6  

page 17/74  

ST25DV02K-W1 ST25DV02K-W2  

Pulse width modulation output  

Figure 9.

PWM output change  

Write Config  

New cfg @ 03h  

ST25DV02K-W  

response  

SOF  

EOF  

SOF  

EOF  

RF  

t

PWM-CFG  

Previous configuration  

New configuration  

PWM out  

There is no anti-tearing mechanism on PWM_CFG register. Write access to PWM_CFG registers shall be done  

with stable RF field and constant VCC state (either ON or OFF). Otherwise the RF write operation may not  

complete properly, and could imply a loss/corruption of register content, requiring a new Write config operation.  

DS12114

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Rev 6  

page 18/74  

ST25DV02K-W1 ST25DV02K-W2  

Data protection  

5.2  

Data protection  

ST25DV02K-W1/2 provides a special data protection mechanism based on passwords that unlock security  

sessions. 4 x 32 bits passwords are stored in EEPROM, covering:  

•

•

Password for AREA1  

Password for AREA2 (If AREA1 and AREA2 are merged, the corresponding area will be protected by a  

64 bits password),  

•

•

Password for PWM control area  

Password for System Configuration area  

User memory can be protected from read and/or write access. The system configuration is always protected from  

write access.  

Other lock mechanisms are supported (lock block, lock AFI, lock DSFID), as described in the following sections.  

5.2.1  

Data protection registers  

Registers described in this chapter are all located in System configuration memory. Refer to

for more details.  

Table 15.

A1SA access  

RF  

Command  

Type  

Read Configuration (cmd code A0h) @00h  

Write Configuration (cmd code A1h) @00h  

R always  

W if configuration security session is open and configuration not locked  

Table 16.

A1SA  

Bit  

Name  

Function  

Factory Value  

AREA1 access rights:  

00: Read always is allowed / Write always allowed  

01: Read always is allowed / Write allowed only if AREA1 user security session  

is opened (= the proper AREA1 password has been presented)  

b1-b0  

RW_PROTECTION_A1  

00b  

10: Read and Write is allowed only if AREA1 user security session is opened  

(the proper AREA1 password has been presented)  

11: Read is only allowed if AREA1 user security session is opened (the proper  

AREA1 password has been presented) / Write always forbidden  

User memory split:  

0: user memory is split in four areas (AREA0/1/2 & PWM_CTRL)  

b2  

MEM_ORG  

RFU  

1b  

1: user memory is split in three areas (AREA0/1 & PWM_CTRL) = AREA1 &  

AREA2 are merged in a single AREA1. In case of merged areas,  

RW_PROTECTION_A1 register applies as access rights.  

b7-b3  

–

00000b  

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ST25DV02K-W1 ST25DV02K-W2  

Data protection  

Table 17.

A2SA access  

RF  

Command  

Type  

Read Configuration (cmd code A0h) @01h  

Write Configuration (cmd code A1h) @01h  

R always  

W if configuration security session is open and configuration not locked  

Table 18.

A2SA  

Bit  

Name  

RW_PROTECTION_A2  

RFU  

Function  

Factory Value  

AREA2 access rights:  

00: Read is always allowed / Write always allowed  

01: Read always is allowed. Write is only allowed if AREA2 user security  

session is opened (= the proper AREA2 password has been presented)  

10: Read and Write is only allowedif AREA2 user security session is opened  

(the proper AREA2 password has been presented)  

b1-b0  

b7-b2  

00b  

11: Read is only allowed if AREA2 user security session is opened (the proper  

AREA2 password has been presented), Write is always forbidden.  

In case of merged AREA1 + AREA2 in a single AREA1, the  

RW_PROTECTION_A2 bits are not used.  

–

00000b  

Table 19.

APSA access  

RF  

Command  

Type  

Read Configuration (cmd code A0h) @02h  

Write Configuration (cmd code A1h) @02h  

R always  

W if configuration security session is open and configuration not locked  

Table 20.

APSA  

Bit  

Name  

Function  

Factory Value  

Area PWM_CTRL access rights:  

00: Read and Write are always allowed.  

01: Read is always allowed. Write is only allowed if Area PWM_CTRL user  

security session is opened (= the proper Area PWM_CTRL password has been  

presented)  

b1-b0  

b7-b2  

RW_PROTECTION_AP  

00b  

10: Read and Write are only allowed if Area PWM_CTRL user security session  

is opened (the proper area PWM_CTRL password has been presented)  

11: Read is only allowed if Area PWM_CTRL user security session is opened  

(the proper area PWM_CTRL password has been presented). Write is always  

forbidden.  

RFU  

–

00000b  

DS12114

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Rev 6  

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ST25DV02K-W1 ST25DV02K-W2  

Data protection  

Table 21.

LOCK_CFG access  

RF  

Command  

Type  

Read Configuration (cmd code A0h) @04h  

Write Configuration (cmd code A1h) @04h  

R always  

W if configuration security session is open and configuration not locked  

Table 22.

LOCK_CFG  

Bit  

b0  

Name  

LOCK_CFG  

RFU  

Function  

Factory Value  

Lock configuration register:  

0: Configuration registers are unlocked  

1: Configuration registers are permanently locked in write.  

0b  

It only concerns configuration registers accessible by Write_Config command.  

Passwords, AFI, DSFID, Block lock, AFI lock & DSFID lock are not concerned  

by this mechanism.  

b7-b1  

–

0000000b  

Table 23.

LOCK_BLOCK of AREA0/1/2 and PWM_CTRL access  

RF  

Command  

Type  

Read Block (cmd code 20h) @Block addr  

Read Multi Block (cmd code 23h) @Block addr  

Get Multi Block Security Status (cmd code 2Ch) @Block addr  

Lock single Block (cmd code 22h) @Block addr  

R always  

W only if corresponding Block is not locked  

Table 24.

LOCK_BLOCK of AREA0/1/2 and PWM_CTRL  

Bit  

Name  

Function  

Factory Value  

Lock write access of corresponding block:  

0: Block not locked in Write  

N/A  

LOCK_BLOCK  

0b  

1: Block permanently locked in write  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

Data protection  

Table 25.

PWD_PWM access  

RF  

Command  

Type  

No Read  

Write password (cmd code B1h) with Pwd_Id = 00h  

No Read  

W only if PWM_CTRL Area security session is opened  

Table 26.

PWD_PWM  

Bit  

Name  

Function  

Factory Value  

bit31-b0  

PWD_PWM  

Password value for PWM_CTRL area  

00000000h  

Table 27.

PWD_A1 access  

RF  

Command  

Type  

No Read  

Write password (cmd code B1h) with Pwd_Id = 01h  

No Read  

W only if AREA1 security session is opened.  

Table 28.

PWD_A1  

Bit  

Name  

Function  

Factory Value  

When MEM_ORG=0: Password value for user AREA1  

b31-b0  

PWD_A1  

00000000h  

When MEM_ORG=1: LSB password value (32bits out of 64) for user  

AREA1 (merged with AREA2)  

Table 29.

PWD_A2 access  

RF  

Command  

Type  

No Read  

W only if:  

No Read  

Write password (cmd code B1h) with Pwd_Id = 02h  

•

•

AREA2 security session is opened (when MEM_ORG=0)  

AREA1 security session is opened (when MEM_ORG=1,  

AREA1+AREA2 are merged)  

Table 30.

PWD_A2  

Bit  

Name  

Function  

Factory Value  

When MEM_ORG = 0: Password value for user AREA2  

b31-b0  

PWD_A2  

00000000h  

When MEM_ORG = 1: MSB password value (32 bits out of 64) for user  

area 1 (merged with AREA2)  

DS12114

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Rev 6  

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ST25DV02K-W1 ST25DV02K-W2  

Data protection  

Table 31.

PWD_CFG access  

RF  

Command  

Type  

No Read  

Write password (cmd code B1h) with Pwd_Id = 03h  

No Read  

W only if the System Configuration Area security session is opened.  

Table 32.

PWD_CFG  

Bit  

Name  

Function  

Password value for configuration area  

Factory Value  

00000000h  

b31-  

b0  

PWD_CFG  

5.2.2  

Passwords and security sessions  

ST25DV02K-W1/2 provides protection of user memory and system configuration registers. User can access to  

the protected data by opening security sessions thanks to the help of corresponding password.  

There is two types of security sessions, as shown in

:  

Table 33.

Security session type  

Security session  

Open by presenting  

Right granted when security session is open, and until it is closed  

PWD_A1  

PWD_A2  

PWD_PWM  

User can access to corresponding user memory as defined in AiSA registers  

User can update the password corresponding to the opened session.  

user  

User can write configuration registers (if not permanently locked)  

User can update PWM_CFG password  

configuration  

PWD_CFG  

If AREA1 and AREA2 are independent (MEM_ORG = 0b), each of the AREA1 and 2 passwords is 32-bit long.  

If AREA1 and AREA2 are merged in a single area (MEM_ORG = 1b), the merged area password is 64-bit long  

(made with 32-bit AREA1 password + 32-bit AREA2 password).  

The ST25DV02K-W1/2 passwords management is based on two commands:  

•

•

Write Password (code B1h) (see

).  

Present Password (code B3h) (See

).  

For any of the 4x passwords available, three actions are possible:  

•

Open Security Session: use Present_Password command, with password identifier (00h for PWD_PWM,  

01h for PWD_A1, 02h for PWD_A2 and 03h for PWD_CFG) and the valid corresponding password.  

•

Write password: use Present_Password command, with password identifier (00h for PWD_PWM, 01h for  

PWD_A1, 02h for PWD_A2 and 03h for PWD_CFG) and the valid corresponding password. Then use  

Write_Password command, with same password identifier and the new password.  

•

Close Security Session: to close the current security session, user can choose one of the following options:  

–

–

–

Remove tag from RF field  

Use Present_Password command with a wrong password  

Use Present_Password command to open security session of another Area (using a different password  

identifier). Opening a new security session (user or configuration) automatically close the previously  

opened one (even if the new opening fails)  

Note:  

In case of merged AREA1 + AREA2 (MEM_ORG=1b), the Security session opening is different:  

•

•

The 64-bit password is presented with one Present_Password operation,  

Write_Password command still applies on 32-bit password, hence update of the 64-bit password must be  

done by 2x Write_Password operations, with AREA1 password Id and with AREA2 password Id,  

DS12114

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Rev 6  

page 23/74  

ST25DV02K-W1 ST25DV02K-W2  

Data protection  

describes the mechanism to open/close the security sessions.  

Figure 10.

Security sessions management  

ST25DV02K-W  

out of RF field  

Field ON  

Field OFF  

All security  

sessions  

closed  

Any other  

command  

Present any  

password not OK  

Present  

PWD_x OK  

Security  

session x  

opened  

(y closed)  

Any other  

command  

Present  

PWD_x OK  

Present  

PWD_y OK  

Security  

session y  

opened  

Any other  

command  

(x closed)  

5.2.3  

User memory protection  

•

AREA0 (composed of a single block= block0):  

–

–

It is always readable,  

It can only be individually write locked by issuing a Lock Single Block command. This lock is  

permanent,  

–

–

User needs no password to lock block 0,  

Locking block 0 is possible even if the configuration is locked (LOCK_CFG=1).  

•

AREA1, AREA2 and PWM_CTRL areas:  

–

–

–

Protections are independently defined by corresponding AiSA registers (A1SA, A2SA, APSA). See  

,

and

for details about available read and write protections.  

When updating AiSA registers, the new protection value is effective immediately after the register write  

completion.  

In addition to the password protection mechanism, each block composing AREA1, AREA2 &  

PWM_CTRL can be individually locked by issuing a Lock Single Block command (permanently lock the  

write access to the corresponding block).  

DS12114

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Rev 6  

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ST25DV02K-W1 ST25DV02K-W2  

TruST25 digital signature  

On factory delivery, user areas protection are all disabled.  

Retrieve the security status of a user memory block or byte  

User can read a block security status by issuing following commands:  

•

•

•

Get Multiple Blocks Security Status command  

Read Single Block with option flag set to 1  

Read Multiple Blocks with option flag set to 1  

ST25DV02K-W1/2will respond with a Block security status containing a Lock_bit flag as specified in ISO 15693  

standard. This lock_bit flag is set to one if block is locked against write.  

Such lock against write can be obtained by different ways:  

•

•

•

Either the Lock_Block bit of the block has been set (permanent)  

Or security session is closed with protection in Write (RW_PROTECTION_Ax = 01b or 10b or 11b)  

Or security session is opened with protection on Write always forbidden (RW_PROTECTION_Ax = 11b)  

5.2.4  

System configuration memory protection  

By default, system memory is write protected.  

To

e

nable write access to system configuration registers, user must open the configuration security session by  

presenting a valid password PWD_CFG (Id=03h) and system configuration must not be permanently locked  

(LOCK_CFG=00h).  

By default, user can read every system configuration registers, except passwords, LOCK_DSFID and LOCK_AFI.  

Configuration lock:  

•

•

•

•

Write access to system configuration registers can be permanently locked by writing 01h in the LOCK_CFG  

register.  

User cannot unlock system configuration if LOCK_CFG=01h, even after opening configuration security  

session (Lock is definitive).  

When system configuration is locked (LOCK_CFG=01h), it is still possible to change passwords (PWD_A1,  

PWD_A2, PWD_PWM, PWD_CFG).  

When system configuration is locked (LOCK_CFG=01h), it is still possible to lock AFI & DSFID registers (as  

described here after).  

Device identification registers:  

•

AFI and DFSID registers can be independently locked by user, issuing respectively a Lock AFI and a Lock  

DSFID command. Lock is definitive: once locked, AFI and DSFID registers cannot be unlocked.  

•

Other device identification registers (IC_RE

F

,

U

ID) are read only registers.  

5.3  

TruST25 digital signature  

The ST25DV02K-W devices support the TruST25 digital signature feature, which allows the user to verify the  

authenticity of the device, thanks to a unique digital signature.  

TruST25 solution encompasses secure industrialization processes and tools deployed by STMicroelectronics to  

generate, store and check the signature in the device.  

Refer to “AN5149 – TruST25 digital signature for ST25DV02K-W series Dynamic NFC

T

a

gs”, available under  

NDA, for more details on how to use it. Contact your STMicroelectronics sales office to get this document.  

DS12114

–

Rev 6  

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ST25DV02K-W1 ST25DV02K-W2  

Device parameter registers  

5.4  

Device parameter registers  

Registers described in this chapter are located in System configuration memory. Refer to

for more details.  

Table 34.

LOCK_DSFID access  

RF  

Command  

Type  

Type  

Type  

Lock DSFID (cmd code 2Ah)  

WO if DSFID not locked  

Table 35.

LOCK_DSFID  

Bit  

b0  

Name  

LOCK_DSFID  

RFU  

Function  

Factory Value  

0b  

0: DSFID is not locked  

1: DSFID is locked  

–

b7-b1  

0000000b  

Table 36.

LOCK_AFI access  

RF  

Command  

Lock AFI (cmd code 28h)  

WO if AFI not locked  

Table 37.

LOCK_AFI  

Function  

Bit  

b0  

Name  

LOCK_AFI  

RFU  

Factory Value  

0b  

0: AFI is not locked  

1: AFI is locked  

–

b7-b1  

0000000b  

Table 38.

DSFID access  

RF  

Command  

Inventory (cmd code 01h)  

R always  

Get System Info (cmd code 2Bh)  

Write DSFID (cmd code 28h)  

W if DSFID not locked  

Table 39.

DSFID  

Function  

Bit  

Name  

Factory Value  

b7-b0  

DSFID  

ISO/IEC 15693 Data Storage Format Identifier  

00h  

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ST25DV02K-W1 ST25DV02K-W2  

Device parameter registers  

Table 40.

AFI access  

RF  

Command  

Type  

Inventory (cmd code 01h)  

R always  

Get System Info (cmd code 2Bh)  

Write AFI (cmd code 27h)  

W if AFI not locked  

Table 41.

AFI  

Bit  

Name  

Function  

Factory Value  

b7-b0  

AFI  

ISO/IEC 15693 Application Family Identifier  

00h  

Table 42.

IC_REF access  

RF  

Command  

Get System Info (cmd code 2Bh)  

Type  

RO  

Table 43.

IC_REF  

Bit  

Name  

Function  

Factory Value  

38/39h

b7-b0  

IC_REF  

ISO/IEC 15693 IC Reference  

1. 38h

 

applies to ST25DV02K-W1, 39h applies to ST25DV02K-W2.  

Table 44.

UID access  

RF  

Command  

Type  

Inventory (cmd code 01h)  

Get System Info (cmd code 2Bh)  

RO  

Table 45.

UID  

Function  

Bit  

Name  

Factory Value  

b7-b0  

ISO/IEC 15693 UID byte 0 (LSB)  

b15-b8  

b23-b16  

b31-b24  

b39-b32  

b47-b40  

b55-b48  

b63-b56  

ISO/IEC 15693 UID byte 1  

IC manufacturer  

serial number  

ISO/IEC 15693 UID byte 2  

ISO/IEC 15693 UID byte 3  

UID  

ISO/IEC 15693 UID byte 4  

38/39h

02h  

ISO/IEC 15693 UID byte 5: ST Product code  

ISO/IEC 15693 UID byte 6: IC Mfg code  

ISO/IEC 15693 UID byte 7 (MSB)  

E0h  

1. 38h

 

applies to ST25DV02K-W1, 39h applies to ST25DV02K-W2  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

RF operation  

6

RF operation  

Contactless exchanges are performed as specified by ISO/IEC 15693 and NFC Forum Type 5

T

a

g. The device  

communicates via the 13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the  

received signal amplitude modulation (ASK: amplitude shift keying). The received ASK wave is 10% or 100%  

modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the  

1/4 pulse coding mode.  

Outgoing data are generated by the ST25DV02K-W1/2 load variation using Manchester coding with one or two  

subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the ST25DV02K-W1/2 at 6.6 Kbit/s in  

low data rate mode and 26 Kbit/s in high data rate mode.  

The device follows ISO/IEC 15693 and NFC Forum Type 5

T

a

g recommendation for radio-frequency power and  

signal interface and for anticollision and transmission protocol.  

6.1  

RF communication  

6.1.1  

Access to an ISO/IEC 15693 device  

The dialog between the reader and the ST25DV02K-W1/2 takes place as follows:  

•

•

•

activation of the ST25DV02K-W1/2 by the operating field of the reader  

transmission of a command by the reader (ST25DV02K-W1/2 detects carrier amplitude modulation)  

transmission of a response by the ST25DV02K-W1/2 using load modulation.  

These operations use the power transfer and communication signal interface described below. This technique is  

called RTF (reader talk first).  

Operating field  

The ST25DV02K-W1/2 operates continuously between the minimum and maximum values of the electromagnetic  

field H defined in

. The reader has to generate a field within these limits.  

Power transfer  

Power is transferred to the ST25DV02K-W1/2 by radio frequency at 13.56 MHz via coupling antennas in the  

ST25DV02K-W1/2 and the reader. The operating field of the reader is transformed on the ST25DV02K-W1/2  

antenna to an AC voltage that is rectified, filtered and internally regulated. During communications, the amplitude  

modulation (ASK) on this received signal is demodulated by the ASK demodulator.  

Frequency  

The ISO 15693 standard defines the carrier frequency (f

C

) of the operating field as 13.56 MHz ± 7 kHz.  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

RF protocol  

6.2  

RF protocol  

6.2.1  

Protocol description  

The transmission protocol (or simply “the protocol”) defines the mechanism used to exchange instructions and  

data between the VCD (vicinity coupling device) and the VICC (vicinity integrated circuit card) in both directions. It  

is based on the concept of “VCD talks first”. The device acts as the VICC.  

This means that a ST25DV02K-W1/2 does not start transmitting unless it has received and properly decoded an  

instruction sent by the VCD. The protocol is based on an exchange of:  

•

•

a request from the VCD to the ST25DV02K-W1/2  

a response from the ST25DV02K-W1/2 to the VCD.  

Each request and each response are contained in a frame. The frames are delimited by a Start of Frame (SOF)  

and End of Frame (EOF).  

The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight (8), that is an integer  

number of bytes.  

A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is transmitted least  

significant byte (LSByte) first and each byte is transmitted least significant bit (LSBit) first.  

Figure 11.

ST25DV02K-W1/2 protocol timing  

Request  

frame  

Request  

frame  

VCD  

Response  

frame  

Response  

frame  

ST25DV02K-W1/2  

Timing  

t

1  

t

2  

t

1  

t

2  

6.2.2  

Supported states  

•

•

•

•

Power-off  

Ready  

Quiet  

Selected  

Transitions between these states are specified in

and

.  

Power-off state  

The ST25DV02K-W1/2 is in RF Power-off state when it does not receive enough energy from the VCD.  

Ready state  

The ST25DV02K-W1/2 is in the Ready state when it receives enough energy from the VCD. When in the Ready  

state, the ST25DV02K-W1/2 answers any request where the Select_flag is not set.  

Quiet state  

When in the Quiet state, the ST25DV02K-W1/2 answers any request with the Address_flag set, except for  

Inventory requests.  

DS12114

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ST25DV02K-W1 ST25DV02K-W2  

RF protocol  

Selected state  

In the Selected state, the ST25DV02K-W1/2 answers any request in all modes (see

):  

•

•

•

Request in Select mode with the Select_flag set  

Request in Addressed mode if the UID matches  

Request in Non-Addressed mode as it is the mode for general requests  

Table 46.

Device response depending on Request_flags  

Address_flag  

Select_flag  

1 0  

Flags  

1

0

Addressed Non

 

addressed Selected Non

 

selected  

ST25DV02K-W1/2 in Ready or Selected state (devices in Quiet  

state do not answer)  

–

–

X

X

–

–

X

–

X

–

ST25DV02K-W1/2 in Selected state  

ST25DV02K-W1/2 in Ready, Quiet or Selected state (the device  

matching the UID)  

X

X

X

–

Error (03h) or no response (command dependent)  

–

X

Figure 12.

Device state transition diagram  

Power off  

Out of field  

after t

RF_OFF  

In RF field  

Any other command  

where Select_Flag  

is not set  

Ready  

Inventory  

Out of RF field  

after t

RF_OFF  

Out of RF field  

after t

RF_OFF  

Select (UID)  

Quiet  

Selected  

Stay quiet(UID)  

Any other command where the  

Address_Flag is set AND where  

the Inventory_Flag is not set  

Any other command  

The ST25DV02K-W1/2 returns to the power-off state if the tag is out of the field for at least t

RF_OFF  

.

The intention of the state transition method is that only one ST25DV02K-W1/2 must be in the Selected state at  

any given time.  

When the Select_flag is set to 1, the request must NOT contain a unique ID.  

When the Address_flag is set to 0, the request must NOT contain a unique ID.  

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ST25DV02K-W1 ST25DV02K-W2  

RF protocol  

6.2.3  

Modes  

The term “mode” refers to the mechanism used in a request to specify the set of ST25DV02K-W1/2 devices that  

must execute the request.  

Addressed mode  

When the Address_flag is set to 1 (Addressed mode), the request contains the UID (unique ID) of the addressed  

ST25DV02K-W1/2.  

Any ST25DV02K-W1/2 receiving a request with the Address_flag set to 1 compares the received UID to its own. If  

it matches the device executes the request (if possible) and returns a response to the VCD as specified in the  

command description.  

If the UID does not match the device remains silent.  

Non-addressed mode (general request)  

When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain a UID.  

Select mode  

When the Select_flag is set to 1 (Select mode), the request does not contain a unique ID. The ST25DV02K-W1/2  

in the Selected state that receives a request with the Select_flag set to 1 executes it and returns a response to the  

VCD as specified in the command description.  

Only the ST25DV02K-W1/2 in the Selected state answers a request where the Select_flag is set to 1.  

The system design ensures that only one ST25DV02K-W1/2 can be in the Select state at a given time.  

6.2.4  

Request format  

The request consists of:  

•

•

•

•

•

•

an SOF  

flags  

a command code  

parameters and data  

a CRC  

an EO

F

.  

Table 47.

General request format  

SOF  

Request_flags  

Command code  

Parameters  

Data  

2 byte CRC  

EOF  

6.2.5  

Request flags  

In a request, the “flags” field specifies the actions to be performed by the ST25DV02K-W1/2 and whether  

corresponding fields are present or not.  

The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the contents of the four  

MSBs (bits 5 to 8). When bit 3 is reset (0), bits 5 to 8 define the ST25DV02K-W1/2 selection criteria. When bit 3 is  

set (1), bits 5 to 8 define the ST25DV02K-W1/2 Inventory parameters.  

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ST25DV02K-W1 ST25DV02K-W2  

RF protocol  

Table 48.

Definition of request flags 1 to 4  

Bit No  

Flag  

Level  

Description  

A single subcarrier frequency is used by the ST25DV02K-W1/2  

Two subcarriers are used by the ST25DV02K-W1/2  

Low data rate is used  

0

1

0

1

Subcarrier_flag

Bit 1  

Data_rate_flag

Bit 2  

High data rate is used  

The meaning of flags 5 to 8 is described in

0

1

Bit 3

 

Inventory_flag  

The meaning of flags 5 to 8 is described in

0

1

No Protocol format extension  

Bit 4

 

Protocol_extension_flag  

Protocol format extension. Reserved for future use.  

1. Subcarrier_flag

 

refers to the ST25DV02K-W1/2-to-VCD communication.  

2. Data_rate_flag

 

refers to the ST25DV02K-W1/2-to-VCD communication.  

Table 49.

Request flags 5 to 8 when inventory_flag, Bit 3 = 0  

Bit nb  

Flag  

Level  

Description  

0

1

The request is executed by any ST25DV02K-W1/2 according to the setting of Address_flag  

The request is executed only by the ST25DV02K-W1/2 in Selected state  

Select flag

Bit 5  

The request is not addressed. UID field is not present. The request is executed by all  

ST25DV02K-W1/2s.  

0

1

Bit 6  

Address flag  

The request is addressed. UID field is present. The request is executed only by the  

ST25DV02K-W1/2 whose UID matches the UID specified in the request.  

0

1

0

Option not activated.  

Bit 7  

Bit 8  

Option flag  

RFU  

Option activated.  

–

1. If

 

the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the request.  

Table 50.

Request flags 5 to 8 when inventory_flag, Bit 3 = 1  

Bit nb  

Flag  

Level  

Description  

0

1

0

1

0

0

AFI field is not present  

Bit 5  

AFI flag  

AFI field is present  

16 slots  

Bit 6  

Nb_slots flag  

1 slot  

Bit 7  

Bit 8  

Option flag  

RFU  

–

–

6.2.6  

Response format  

The response consists of:  

•

•

•

•

•

an SO

F

,  

flags,  

parameters and data,  

a CRC,  

an EO

F

.  

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ST25DV02K-W1 ST25DV02K-W2  

RF protocol  

Table 51.

General response format  

SOF  

Response_flags  

Parameters  

Data  

2 byte CRC  

EOF  

6.2.7  

Response flags  

Table 52.

Definitions of response flags 1 to 8  

Bit Nb  

Flag  

Error_flag  

Level  

Description  

0

1

0

0

0

0

0

0

0

No error  

Bit 1  

Error detected. Error code is in the “Error” field.  

Bit 2  

Bit 3  

Bit 4  

Bit 5  

Bit 6  

Bit 7  

Bit 8  

RFU  

RFU  

RFU  

RFU  

RFU  

RFU  

RFU  

–

–

–

–

–

–

–

In a response, the flags indicate how actions have been performed by the ST25DV02K-W1/2 and whether  

corresponding fields are present or not. The response flags consist of eight bits.  

6.2.8  

Response and error code  

If the Error_flag is set by the ST25DV02K-W1/2 in the response, the Error code field is present and provides  

information about the error that occurred.  

Error codes not specified in

are reserved for future use.  

Table 53.

Response error code definition  

Error code  

Meaning  

01h  

02h  

03h  

0Fh  

10h  

11h  

12h  

13h  

14h  

15h  

Command is not supported.  

Command is not recognized (format error).  

The option is not supported.  

Error with no information given.  

The specified block is not available.  

The specified block is already locked and thus cannot be locked again.  

The specified block is locked and its contents cannot be changed.  

The specified block was not successfully programmed.  

The specified block was not successfully locked.  

The specified block is protected in read.  

No response  

It could indicate illegal programming.  

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ST25DV02K-W1 ST25DV02K-W2  

Timing definition  

6.3  

Timing definition  

t

1

: VICC response delay  

Upon detection of the rising edge of the EOF received from the VCD, the ST25DV02K-W1/2 waits for a t

1nom

time  

before transmitting its response to a VCD request or switching to the next slot during an inventory process. Values  

of t

1

are given in

.  

t

2

: VCD new request delay  

t

2

is the time after which the VCD may send an EOF to switch to the next slot when one or more ST25DV02K-  

W1/2 responses have been received during an Inventory command. It starts from the reception of the EOF from  

the ST25DV02K-W1/2s.  

The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for  

transmitting the VCD request to the ST25DV02K-W1/2.  

t

2

is also the time after which the VCD may send a new request to the ST25DV02K-W1/2, as described in  

.  

Values of t

2

are given in

.  

t

3

: VCD new request delay when no response is received from the VICC  

t

3

is the time after which the VCD may send an EOF to switch to the next slot when no ST25DV02K-W1/2  

response has been received.  

The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for  

transmitting the VCD request to the ST25DV02K-W1/2.  

From the time the VCD has generated the rising edge of an EOF:  

•

If this EOF is 100% modulated, the VCD waits for a time at least equal to t

3min

for 100% modulation before  

sending a new EO

F

.  

•

If this EOF is 10% modulated, the VCD waits for a time at least equal to t

3min

for 10% modulation before  

sending a new EO

F

.  

Table 54.

Timing values  

Minimum (min) values  

Nominal (nom) values  

Maximum (max) values  

100% modulation  

10% modulation  

4384 / f

 

= 323.3 µs

t

4320 / f

 

= 318.6 µs  

4352 / f

 

= 320.9 µs  

1

c

c

c

t

2

t

3

4192 / f

 

= 309.2 µs  

No t  

No t  

No t  

No t  

c

nom  

nom  

max  

max  

t

t

1max  

SOF  

1max  

NRT 2min  

1. VCD

 

request will not be interpreted during the first milliseconds following the field rising.  

2.  

3.  

4.  

t

does not apply for write-alike requests. Timing conditions for write-alike requests are defined in the  

1max  

command description.  

is the time taken by the ST25DV02K-W1/2 to transmit an SOF to the VCD. t  

t

depends on the  

SOF  

SOF  

current data rate: High data rate or Low data rate.  

is the nominal response time of the ST25DV02K-W1/2. t  

t

depends on VCD to ST25DV02K-W1/2  

NRT  

NRT  

data rate and subcarrier modulation mode.  

Note:  

The tollerance of specific timing is ± 32/f

C

.  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

6.4  

RF commands  

The ST25DV02K-W1/2 supports the following RF command set:  

•

•

Inventory

, used to perform the anticollision sequence.  

Stay Quiet

, used to put the ST25DV02K-W1/2 in quiet mode, where it does not respond to any inventory  

command.  

•

•

Read Single Block

, used to output the 32 bit of the selected block and its locking status.  

Write Single Block

, used to write and verify the new content for an update of a 32 bit block, provided that it  

is not in a locked memory area.  

•

•

•

Lock Block

, used to write the blocks security status bits (protect against writing).  

Read Multiple Blocks

, used to read the selected blocks in a unique area, and send back their value.  

Select

, used to select the ST25DV02K-W1/2. After this command, the ST25DV02K-W1/2 processes all  

Read/Write commands with Select_flag set.  

•

•

•

•

•

•

•

•

•

•

•

Reset to Ready

, used to put the ST25DV02K-W1/2 in the ready state.  

Write AFI

, used to write the 8-bit value in the AFI register.  

Lock AFI

, used to lock the AFI register.  

Write DSFID

, used to write the 8-bit value in the DSFID register.  

Lock DSFID

, used to lock the DSFID register.  

Get System information

, used to provide the standard system information values.  

Get multiple block security status

, used to send the security status of the selected block.  

Read Configuration

, used to read configuration registers.  

Write Configuration

, used to write configuration registers.  

Write Password

, used to change password of an opened security session.  

Present Password

, used to present a password and to open a security session.  

Their codes are given in

.  

Table 55.

Command codes  

Command code  

Function  

Command code  

Function  

01h  

02h  

20h  

21h  

22h  

23h  

25h  

26h  

27h  

28h  

29h  

2Ah  

2Bh  

2Ch  

A0h  

A1h  

B1h  

B3h  

Following paragraphs describe the expected behaviour for each valid command.  

In case of an invalid command, in a general manner, the ST25DV02K-W1 ST25DV02K-W2 behaves as follow:  

1.  

If flag usage is incorrect, the error code 03h is issued only if the right UID is used in the command, otherwise  

no response will be issued.  

2.  

The code error 02h is issued if the custom command is used with the manufacturer code different from the  

ST one  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

6.4.1  

Inventory  

Upon receiving the Inventory request, the ST25DV02K-W1/2 runs the anticollision sequence. The Inventory_flag  

is set to 1. The meaning of flags 5 to 8 is shown in

.  

•

•

•

•

•

•

The Request flags  

the Inventory command code (001)  

AFI if the AFI flag is set  

Mask length  

Mask value if mask length is different from 0  

the CRC  

The ST25DV02K-W1/2 does not generate any answer in case of error.  

Table 56.

Inventory request format  

Request SOF  

Request_flags  

Inventory  

Optional AFI  

Mask length  

Mask value

 

CRC16 Request

 

EOF  

–

8 bits  

01h  

8 bits  

8 bits  

0 – 64 bits  

16 bits  

–

The response contains:  

•

•

the flags  

the Unique ID  

Table 57.

Inventory response format  

Response SOF  

Response_flags  

DSFID  

UID  

CRC16  

Response EOF  

–

8 bits  

8 bits  

64 bits  

16 bits  

–

During an Inventory process, if the VCD does not receive an RF ST25DV02K-W1/2 response, it waits for a time t

3  

before sending an EOF to switch to the next slot. t

3

starts from the rising edge of the request EOF sent by the  

VCD.  

•

If the VCD sends a 100% modulated EO

F

,

t

he minimum value of t

3

is:  

t

3

min = 4384/f

C

(323.3µs) + t

SOF  

•

If the VCD sends a 10% modulated EO

F

,

t

he minimum value of t

3

is:  

t

3

min = 4384/f

C

(323.3µs) +

 

t

NRT

+ t

2min  

where:  

•

•

t

SOF

is the time required by the ST25DV02K-W1/2 to transmit an SOF to the VCD,  

t

NRT

is the nominal response time of the ST25DV02K-W1/2.  

t

NRT

and t

SOF

are dependent on the ST25DV02K-W1/2-to-VCD data rate and subcarrier modulation mode.  

Note:  

In case of error, no response is sent by ST25DV02K-W1 ST25DV02K-W2.  

6.4.2  

Stay Quiet  

On receiving the Stay Quiet command, the ST25DV02K-W1/2 enters the Quiet state if no error occurs, and does  

NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs. The  

Option_flag is not supported. The Inventory_flag must be set to 0.  

When in the Quiet state:  

•

•

the ST25DV02K-W1/2 does not process any request if the Inventory_flag is set,  

the ST25DV02K-W1/2 processes any request with Address_flag set.  

The ST25DV02K-W1/2 exits the Quiet state when:  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

•

•

•

it is reset (power off),  

receiving a Select request. It then goes to the Selected state,  

receiving a Reset to Ready request. It then goes to the Ready state.  

Table 58.

Stay Quiet request format  

Request SOF  

Request flags  

Stay Quiet  

UID  

CRC16  

Request EOF  

–

8 bits  

02h  

64 bits  

16 bits  

–

The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset to 0 and  

Address_flag is set to 1).  

Figure 13.

Stay Quiet frame exchange between VCD and ST25DV02K-W1/2  

Stay Quiet  

request  

SOF  

EOF  

VCD  

ST25DV02K-W1/2  

6.4.3  

Read Single Block  

On receiving the Read Single Block command, the ST25DV02K-W1/2 reads the requested block and sends back  

its 32-bit value in the response. The Option_flag is supported, when set response include the Block Security  

Status. The Inventory_flag must be set to 0.  

Block number is coded on 1 Byte.  

Table 59.

Read Single Block request format  

UID

Request SOF  

Request_flags  

Read Single Block  

Block number  

CRC16  

Request EOF  

–

8 bits  

20h  

64 bits  

8 bits  

16 bits  

–

1. The

 

field is optional.  

Request parameters:  

•

•

•

Request flags  

UID (optional)  

Block number  

Table 60.

Read Single Block response format when Error_flag is NOT set  

Block security status

Response SOF  

Response_flags  

Data  

CRC16  

Response EOF  

–

8 bits  

8 bits  

32 bits  

16 bits  

–

1. The

 

field is optional.  

Response parameters:  

•

•

Block security status if Option_flag is set (see

)  

Four bytes of block data  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

Table 61.

Block security status  

b

7

b

b

5

b

4

b

3

b

b

1

b

0

6

2

Reserved for future use.  

All at 0.  

0: Current block not locked  

1: Current block locked  

Table 62.

Read Single Block response format when Error_flag is set  

Response SOF  

Response_flags  

Error code  

CRC16  

Response EOF  

–

8 bits  

8 bits  

16 bits  

–

Response parameter:  

•

Error code as Error_flag is set  

–

–

–

–

03h: command option not supported  

0Fh: error with no information  

10h: the specified block is not available  

15h: the specified block is read-protected  

Figure 14.

Read Single Block frame exchange between VCD and ST25DV02K-W1/2  

Read Single Block  

VCD  

SOF  

EOF  

request  

Read Single Block  

response  

ST25DV02K-W1/2  

t

1  

SOF  

EOF  

6.4.4  

Write Single Block  

On receiving the Write Single Block command, the ST25DV02K-W1/2 writes the data contained in the request to  

the targeted block and reports whether the write operation was successful in the response. When the Option_flag  

is set, wait for EOF to respond. The Inventory_flag must be set to 0.  

During the RF write cycle W

t

, there should be no modulation (neither 100% nor 10%), otherwise the ST25DV02K-  

W1/2 may not program correctly the data into the memory. Block number is coded on 1 Byte.  

Table 63.

Write Single Block request format  

UID

Request SOF  

Request_flags  

Write Single Block  

Block number  

Data  

CRC16 Request

 

EOF  

–

8 bits  

21h  

64 bits  

8 bits  

32 bits

 

16 bits  

–

1. The

 

field is optional.  

Request parameters:  

•

•

•

•

Request flags  

UID (optional)  

Block number  

Data  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

Table 64.

Write Single Block response format when Error_flag is NOT set  

Response SOF  

Response_flags  

CRC16  

Response EOF  

–

8 bits  

16 bits  

–

Response parameter:  

•

No parameter. The response is sent back after the writing cycle.  

Table 65.

Write Single Block response format when Error_flag is set  

Response SOF  

Response_flags  

Error code  

CRC16  

Response EOF  

–

8 bits  

8 bits  

16 bits  

–

Response parameter:  

Error code as Error_flag is set

•

–

–

–

–

–

03h: command option not supported  

0Fh: error with no information given  

10h: the specified block is not available  

12h: the specified block is locked or protected and its contents cannot be changed  

13h: the specified block was not successfully programmed  

1. For

 

more details, see

.  

Figure 15.

Write Single Block frame exchange between VCD and ST25DV02K-W1/2  

Write Single  

Block request  

VCD  

SOF  

EOF  

Write Single  

Block response  

Write sequence  

when error  

ST25DV02K-W1/2  

t

1  

SOF  

EOF  

SOF  

Write Single  

Block  

response  

ST25DV02K-W1/2  

W

t  

EOF  

6.4.5  

Lock Block  

On receiving the Lock block request, the ST25DV02K-W1/2 locks the corresponding block value permanently and  

protects its content against new writing.  

Lock block command is applicable and successful, if and only if the block is not protected in Write (ie, the block is  

not already locked, or protected in Write by password).  

The Option_flag is supported, when set wait for EOF to respond. The Inventory_flag must be set to 0.  

During the RF write cycle W

t

, there should be no modulation (neither 100% nor 10%), otherwise the ST25DV02K-  

W1/2 may not lock correctly the block value in memory.  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

Table 66.

Lock Block request format  

UID

Request SOF  

Request_flags  

Lock block  

block number  

CRC16  

Request EOF  

–

8 bits  

22h  

64 bits  

8 bits  

16 bits  

–

1. The

 

field is optional.  

Request parameter:  

•

•

•

Request Flags  

UID (optional)  

Block number  

Table 67.

Lock block response format when Error_flag is NOT set  

Response SOF  

Response_flags  

CRC16  

Response EOF  

–

8 bits  

16 bits  

–

Response parameter:  

•

No parameter  

Table 68.

Lock single block response format when Error_flag is set  

Response SOF  

Response_flags  

Error code  

CRC16  

Response EOF  

–

8 bits  

8 bits  

16 bits  

–

Response parameter:  

Error code as Error_flag is set  

•

–

–

–

–

03h: command option not supported  

10h: block not available  

11h: the specified block is already locked and thus cannot be locked again  

14h: the specified block was not successfully locked  

Figure 16.

Lock single block frame exchange between VCD and ST25DV02K-W1/2  

Lock Block  

request  

VCD  

SOF  

EOF  

Lock Block  

response  

Lock sequence  

when error  

ST25DV02K-W1/2  

ST25DV02K-W1/2  

t

1  

SOF  

EOF  

SOF  

Lock block  

response  

W

t  

EOF  

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ST25DV02K-W1 ST25DV02K-W2  

RF commands  

6.4.6  

Read Multiple Blocks  

When receiving the Read Multiple Block command, the ST25DV02K-W1/2 reads the selected blocks and sends  

back their value in multiples of 32 bits in the response. The blocks are numbered from 00h to FFh in the request  

and the value is minus one (-1) in the field. For example, if the “Number of blocks” field contains the value 06h,  

seven blocks are read. If the number of blocks overlaps areas, the ST25DV02K-W1/2 returns an error code.  

When the Option_flag is set, the response returns the Block Security Status. The Inventory_flag must be set to 0.  

Block number is coded on 1 byte.  

Table 69.

Read Multiple Block request format  

Read Multiple  

Block  

First block  

number  

UID

Request SOF

 

Request_flags  

8 bits  

Number of blocks

 

CRC16 Request

 

EOF  

–

23h  

64 bits  

8 bits  

8 bits  

16 bits  

–

1. The

 

field is optional.  

Request parameters:  

•

•

•

•

Request flags  

UID (optional)  

First block number  

Number of blocks  

Table 70.

Read Multiple Block response format when Error_flag is NOT set  

Response_  

Block security status

Response SOF  

Data  

CRC16  

Response EOF  

flags  

8 bits

32 bits

–

8 bits  

16 bits  

–

1. The

 

field is optional.  

2. Repeated

 

as needed.  

Response parameters:  

•

•

Block security status if Option_flag is set (see

)  

N blocks of data  

Table 71.

Block security status  

b

7

b

6

b

5

b

b

3

b

2

b

1

b

0

4

Reserved for future use.  

All at 0.  

0: Current block not locked  

1: Current block locked  

Table 72.

Read Multiple Block response format when Error_flag is set  

Response SOF  

Response_flags  

Error code  

CRC16  

Response EOF  

–

8 bits  

8 bits  

16 bits  

–

Response parameter:  

DS12114

–

Rev 6  

page 41/74  

ST25DV02K-W1 ST25DV02K-W2  

RF commands  

•

Error code as Error_flag is set:  

–

–

–

–

03h: command option is not supported  

0Fh: error with no information given  

10h: the specified block is not available  

15h: the specified block is read-protected  

Figure 17.

Read Multiple Block frame exchange between VCD and ST25DV02K-W1/2  

Read Multiple  

VCD  

SOF  

EOF  

Block request  

Read Multiple  

ST25DV02K-W1/2  

t

1  

SOF  

EOF  

Block response  

6.4.7  

Select  

When receiving the Select command:  

•

If the UID is equal to its own UID, the ST25DV02K-W1/2 enters or stays in the Selected state and sends a  

response.  

•

If the UID does not match its own UID, the selected ST25DV02K-W1/2 returns to the Ready state and does  

not send a response.  

The ST25DV02K-W1/2 answers an error code only if the UID is equal to its own UID. If not, no response is  

generated. If an error occurs, the ST25DV02K-W1/2 remains in its current state. The Option_flag is not  

supported. The Inventory_flag must be set to 0.  

Table 73.

Select request format  

Request SOF  

Request_flags  

Select  

UID  

CRC16  

Request EOF  

–

8 bits  

25h  

64 bits  

16 bits  

–

Request parameter:  

•

•

Request flags  

UID  

Table 74.

Select Block response format when Error_flag is NOT set  

Response SOF  

Response_flags  

CRC16  

Response EOF  

–

8 bits  

16 bits  

–

Response parameter:  

No parameter  

•

DS12114

–

Rev 6  

page 42/74  

ST25DV02K-W1 ST25DV02K-W2  

RF commands  

Table 75.

Select response format when Error_flag is set  

Response SOF  

Response_flags  

Error code  

CRC16  

Response EOF  

–

8 bits  

8 bits  

16 bits  

–

Response parameter:  

•

Error code as Error_flag is set:  

–

–

03h: the option is not supported  

0Fh: error with no information given  

Figure 18.

Select frame exchange between VCD and ST25DV02K-W1/2  

VCD  

SOF  

Select request  

EOF  

ST25DV02K-W1/2  

t

1  

SOF  

Select response  

EOF  

6.4.8  

Reset to Ready  

On receiving a Reset to Ready command, the ST25DV02K-W1/2 returns to the Ready state if no error occurs. In  

the Addressed mode, the ST25DV02K-W1/2 answers an error code only if the UID is equal to its own UID. If not,  

no response is generated.The Option_flag is not supported. The Inventory_flag must be set to 0.  

Table 76.

Reset to Ready request format  

UID

Request SOF  

Request_flags  

Reset to Ready  

CRC16  

Request EOF  

–

8 bits  

26h  

64 bits  

16 bits  

–

1. The

 

field is optional.  

Request parameter:  

•

•

Request flags  

ID (optional)  

Table 77.

Reset to Ready response format when Error_flag is NOT set  

Response SOF  

Response_flags  

CRC16  

Response EOF  

–

8 bits  

16 bits  

–

Response parameter:  

No parameter  

•

DS12114

–

Rev 6  

page 43/74  

ST25DV02K-W1 ST25DV02K-W2  

RF commands  

Table 78.

Reset to ready response format when Error_flag is set  

Response SOF  

Response_flags  

Error code  

CRC16  

Response EOF  

–

8 bits  

8 bits  

16 bits  

–

Response parameter:  

•

Error code as Error_flag is set:  

–

–

03h: the option is not supported  

0Fh: error with no information given  

Figure 19.

Reset to Ready frame exchange between VCD and ST25DV02K-W1/2  

Reset to Ready  

VCD  

SOF  

EOF  

request  

Reset to Ready  

response  

ST25DV02K-W1/2