STMicroelectronics-ST25DV04K-JFR8D3

ST25DV04K ST25DV16K ST25DV64K  

Datasheet  

Dynamic NFC/RFID tag IC with 4-Kbit, 16-Kbit or 64-Kbit EEPROM, and fast  

transfer mode capability  

Features  

I2C interface  

•

•

•

Two-wire I

2

C serial interface supports 1MHz protocol  

Single supply voltage: 1.8V to 5.5V  

TSSOP8  

WLCSP10  

UFDFPN12  

SO8  

Multiple byte write programming (up to 256 bytes)  

Contactless interface  

•

•

•

Based on ISO/IEC 15693  

UFDFPN8  

NFC Forum Type 5 tag certified by the NFC Forum  

Supports all ISO/IEC 15693 modulations, coding, sub-carrier modes and data  

rates  

•

•

•

•

Custom fast read access up to 53 Kbit/s  

Single and multiple blocks read (same for Extended commands)  

Single and multiple blocks write (up to 4) (same for Extended commands)  

Internal tuning capacitance: 28.5 pF  

Wafer  

Memory  

•

Up to 64-kbits of EEPROM (depending on version)  

•

•

•

I

2

C interface accesses bytes  

RF interface accesses blocks of 4 bytes  

Write time:  

Product status link  

–

–

From I

2

C: typical 5ms for 1 byte  

From RF: typical 5ms for 1 block  

•

•

Data retention: 40 years  

Write cycles endurance:  

–

–

–

–

1 million write cycles at 25 °C  

600k write cycles at 85 °C  

500k write cycles at 105 °C  

400k write cycles at 125 °C  

Fast transfer mode  

•

•

Fast data transfer between I

2

C and RF interfaces  

Half-duplex 256-byte dedicated buffer  

Energy harvesting  

Analog output pin to power external components  

•

Data protection  

•

•

User memory: 1 to 4 configurable areas, protectable in read and/or write by  

three 64-bit passwords in RF and one 64-bit password in I

2

C  

System configuration: protected in write by a 64-bit password in RF and a 64-bit  

password in I

2

C  

DS10925

–

Rev 9

–

February 2021  

For further information contact your local STMicroelectronics sales office.  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

•

Interruption pin configurable on multiple RF events (field change, memory write,  

activity, Fast Transfer end, user set/reset/pulse)  

•

Open Drain or CMOS output (depending on version)  

Low power mode (10-ball and 12-pin package only)  

Input pin to trigger low power mode  

•

RF management  

•

RF command interpreter enabled/disabled from I

2

C host controller  

Temperature range  

•

Range 6:  

–

From -40 to 85 °C  

•

Range 8:  

–

–

–

From -40 to 105 °C  

(UDFPN8 and UDFPN12 only)  

From -40 to 125 °C (SO8N and TSSOP8 only, 105 °C max on RF interface)  

Package  

•

•

8-pin, 10-ball and 12-pin packages  

ECOPACK2

®

(RoHS compliant)  

DS10925

–

Rev 9  

page 2/200  

ST25DV04K ST25DV16K ST25DV64K  

Description  

1

Description  

The

,

and

devices are NFC RFID tags offering respectively 4 Kbit,  

16 Kbit, and 64 Kbit of electrically erasable programmable memory (EEPROM).

,

and  

offer two interfaces. The first one is an I

2

C serial link and can be operated from a DC power supply.  

The second one is a RF link activated when

,

or

act as a contactless  

memory powered by the received carrier electromagnetic wave.  

In I

2

C mode, the

,

and

user memory contains up to 512 bytes, 2048 bytes  

and 8192 bytes, which could be split in 4 flexible and protectable areas.  

In RF mode, following ISO/IEC 15693 or NFC forum type 5 recommendations,

,

and  

user memory contains respectively up to 128 blocks, 512 blocks and 2048 blocks of 4 bytes which  

could be split in 4 flexible and protectable areas.  

,

and

offer a fast transfer mode between the RF and contact worlds, thanks  

to a 256 bytes volatile buffer (also called Mailbox). In addition, the GPO pin of the

,

and  

provide data informing the contact world about incoming events, like RF field detection, RF activity in  

progress or mailbox message availability. An energy harvesting feature is also proposed when external conditions  

make it possible.  

Herein after all concerned devices (

,

and

) are mentioned as ST25DVxxx.  

1.1  

ST25DVxxx block diagram  

Figure 1.

ST25DVxxx block diagram  

1.8V VOLTAGE  

REGULATOR  

DIGITAL UNIT CONTROL  

FAST TRANSFER  

CONTROL  

LPD

1  

VDCG

1  

ENERGY  

HARVESTING  

CONTROL  

GPO  

ANALOG FRONT END  

256 Bytes  

BUFFER  

ENERGY  

HARVESTING  

V_EH  

AC0  

MEMORY  

CONTROL  

Vcc  

Vss  

ISO/IEC 15693  

PROTOCOL  

AND CONTROL  

RF INTERFACE  

28.5pF tuning  

capacitance  

Dynamic  

registers  

I2C CONTROL  

AC1  

SDA  

SCL  

EEPROM  

I2C  

INTERFACE  

System  

registers  

Up to 64Kbits User memory  

1.  

V

DCG

and LPD are included in 10 balls and 12 pins package only.  

DS10925

–

Rev 9  

page 3/200  

ST25DV04K ST25DV16K ST25DV64K  

ST25DVxxx packaging  

1.2  

ST25DVxxx packaging  

ST25DVxxx is provided in different packages:  

•

•

8 pins (S08N or TSSPOP8 or UFDFPN8) for the open drain version of Interrupt output  

10 balls (WLCSP) and 12 pins (UFDFPN12) for a CMOS interrupt output. This package includes an  

additional element that minimizes standby consumption.  

Table 1.

Signal names  

Signal name  

Function  

Direction  

V_EH  

GPO  

SDA  

SCL  

Energy Harvesting  

Interrupt Output  

Serial Data  

Power output  

Output  

I/O  

Serial Clock  

Input  

–

AC0, AC1  

Antenna coils  

Supply voltage  

V

Power  

CC  

V

Ground  

–

SS  

LPD

Low power down mode  

Input  

Power  

V

Supply voltage for GPO driver  

Not connected  

DCG  

NC  

Must be left floating  

Must be left floating  

EP

Exposed Pad  

1. Available

 

only on 10-ball and 12-pin packages.  

2. Available

 

only on UFDPN8 and UFDFPN12 packages.  

Figure 2.

ST25DVxxx 8-pin packages connections with open drain Interruption Output  

1

2

3

4

8

7

6

5

V_EH  

AC0  

AC1  

VSS  

VCC  

GPO (OD)  

SCL  

EP

1  

SDA  

1.  

Exposed Pad is only present on UFDFPN8 package.  

DS10925

–

Rev 9  

page 4/200  

ST25DV04K ST25DV16K ST25DV64K  

ST25DVxxx packaging  

Figure 3.

ST25DVxxx 12-pin package connections with Cmos interrupt output (GPO)  

1

2

12  

11  

LPD  

NC  

VCC  

GPO (CMOS)  

V_EH  

AC0  

3

4

10  

9

VDCG  

NC  

EP

1  

5

6

8

7

AC1  

VSS  

SCL  

SDA  

1.  

Exposed Pad is only present on UFDFPN12 package.  

Figure 4.

ST25DVxxx 10-ball WLCSP package connections with Cmos interrupt output (GPO)  

1

2

3

4

4

3

2

1

A

B

C

D

E

A

B

C

D

E

VCC  

VDCG  

SDA  

V_EH  

LPD  

V_EH  

LPD  

VCC  

VDCG  

SDA  

AC0  

AC1  

AC0  

AC1  

GPO  

SCL  

GPO  

SCL  

VSS  

VSS  

Marking side  

(top view)  

Bump side  

(bottom view)  

DS10925

–

Rev 9  

page 5/200  

ST25DV04K ST25DV16K ST25DV64K  

Signal descriptions  

2

Signal descriptions  

2.1  

Serial link (SCL, SDA)  

2.1.1  

Serial clock (SCL)  

This input signal is used to strobe all data in and out of the ST25DVxxx. In applications where this signal is used  

by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a  

pull-up resistor must be connected from Serial Clock (SCL) to V

CC

. See

to know how to calculate the value of this pull-up resistor  

2.1.2  

Serial data (SDA)  

This bidirectional signal is used to transfer data in or out of the ST25DVxxx. It is an open drain output that may  

be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected  

from Serial Data (SDA) to V

CC

. (

C Fast mode (f

= 1 MHz): maximum R

value versus bus parasitic  

)

indicates how the value of the pull-up resistor can be calculated).  

2.2  

Power control (V

 

, LPD,V

 

)  

CC  

SS  

2.2.1  

Supply voltage (V  

CC  

)

This pin can be connected to an external DC supply voltage.  

Note:  

An internal voltage regulator allows the external voltage applied on V

CC

to supply the ST25DVxxx, while  

preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V

CC

pin.  

2.2.2  

Low Power Down (LPD)  

This input signal is used to control an internal 1.8 V regulator delivering ST25DVxxx internal supply. When LPD  

is high, this regulator is shut off and its consumption is reduced below 1µA. This regulator has a turn on time in  

range of 100us, to be added to the boot duration, before the device becomes fully operational. The impedance on  

LDP pin when set high doesn’t exceed 5kΩ.  

This feature is only available on the 10-ball and 12-pin ST25DVxxx package. The LPD pin is internally pulled-  

down.  

2.2.3  

Ground (V  

)

SS  

V

SS

is the reference for the V

CC

and V

DCG

supply voltages and V_EH analog output voltage.  

DS10925

–

Rev 9  

page 6/200  

ST25DV04K ST25DV16K ST25DV64K  

RF link (AC0 AC1)  

2.3  

RF link (AC0 AC1)  

2.3.1  

Antenna coil (AC0, AC1)  

These inputs are used to connect the ST25DVxxx device to an external coil exclusively. It is advised not to  

connect any other DC or AC path to AC0 or AC1.  

When correctly tuned, the coil is used to power and access the device using the ISO/IEC 15693 and ISO 18000-3  

mode 1 protocols.  

2.4  

Process control (V  

, GPO)  

DCG  

2.4.1  

Driver Supply voltage (V  

)

DCG  

This pin, available only with ST25DVxx-JF version, can be connected to an external DC supply voltage. It only  

supplies the GPO driver block. ST25DVxxx cannot be powered by V

DCG

. If V

DCG

is left floating, no information  

will be available on GPO pin.  

2.4.2  

General purpose output (GPO)  

The ST25DVxxx features a configurable output GPO pin used to provide RF activity information to an external  

device. ST25DVxx-IE offers a GPO open drain. This GPO pin must be connected to an external pull-up resistor  

(> 4.7 KΩ) to operate.  

The interrupt consists in pulling the state to a low level or outputting a low-level pulse on GPO pin.  

ST25DVxx-JF offers a GPO CMOS output, which requires to connect V

DCG

pin to an external power supply. The  

interrupt consists in setting the state to a high level or outputting a positive pulse on the GPO pin.  

GPO pin is a configurable output signal, and can mix several Interruption modes. By default, the GPO register  

sets the interruption mode as a RF Field Change detector. It is able to raise various events like RF Activity,  

Memory Write completion, or fast transfer actions. It can authorize the RF side to directly drive GPO pin using the  

Manage GPO command to set the output state or emit a single pulse (for example, to wake up an application.).  

See

for details.  

2.5  

Energy harvesting analog output (V_EH)  

This analog output pin is used to deliver the analog voltage V_EH available when the Energy harvesting mode  

is enabled and if the RF field strength is sufficient. When the Energy harvesting mode is disabled or the RF field  

strength is not sufficient, V_EH pin is in High-Z state (See

for details).  

Energy harvesting voltage output is not regulated.  

DS10925

–

Rev 9  

page 7/200  

ST25DV04K ST25DV16K ST25DV64K  

Power management  

3

Power management  

3.1  

Wired interface  

Operating supply voltage V

CC  

In contact mode, prior to selecting the memory and issuing instructions to it, a valid and stable V

CC

voltage within  

the specified [V

CC

(min), V

CC

(max)] range must be applied (see

C operating conditions

).

T

o

m

aintain  

a stable DC supply voltage, it is recommended to decouple the V

CC

line with a suitable capacitor (usually of the  

order of 10 nF and 100 nF) close to the V

CC

/V

SS

package pins.  

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write  

instruction, until the completion of the internal I²C write cycle (t

W

). Instructions are not taken into account until  

completion of ST25DVxxx’s boot sequence (see

or package without LPD pin)

).  

Figure 5.

ST25DVxxx power-up sequence (No RF field, LPD pin tied to V

SS

or package without LPD pin)  

I

2

C interface ready  

V

cc

Pin  

Vint_supply  

Power-Up by V

cc  

(No V

cc

; V

DCG  

)

None  

Access  

Allowed  

RF or I

2

C  

I

2

C Start  

I

2

C Stop  

RF Access not allowed  

* When RF Field is present before V

CC

set up

 

boot is  

performed after RF field rising .  

* If LPD pin follow V

CC

before to goes low

 

, t

boot

will  

start only when LPD reach the low level  

t

boot  

*

I

2

C  

Power-up conditions  

When the power supply is turned on, V

CC

rises from V

SS

to V

CC

. The V

CC

rise time must not vary faster than  

1V/µs.  

Device reset in I²C mode  

In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At  

power-up (continuous rise of V

CC

), the ST25DVxxx does not respond to any I²C instruction until V

CC

has reached  

the power-on reset threshold voltage (this threshold is lower than the minimum V

CC

operating voltage defined in  

C operating conditions

). When V

CC

passes over the POR threshold, the device is reset and enters  

the Standby power mode. However, the device must not be accessed until V

CC

has reached a valid and stable  

V

CC

voltage within the specified [V

CC(min)

, V

CC(max)

] range and t_boot time necessary to ST25DVxxx set-up has  

passed. In the version supporting LPD pin, the boot will take place only when LPD goes low.  

In a similar way, during power-down (continuous decrease in V

CC

), as soon as V

CC

drops below the power-on  

reset threshold voltage, the device stops responding to any instruction sent to it, and I

2

C address counter is reset.  

DS10925

–

Rev 9  

page 8/200  

ST25DV04K ST25DV16K ST25DV64K  

Contactless interface  

Power-down mode  

During power-down (continuous decay of V

CC

), the device must be in Standby power mode (mode reached after  

decoding a Stop condition, assuming that there is no internal write cycle in progress).  

3.2  

Contactless interface  

Device set in RF mode  

To

e

nsure a proper boot of the RF circuitry, the RF field must be turned ON without any modulation for a  

minimum period of time t

RF_ON

. Before this time, ST25DVxxx will ignore all received RF commands. (See  

).  

Device reset in RF mode  

To

e

nsure a proper reset of the RF circuitry, the RF field must be turned off (100% modulation) for a minimum  

t

RF_OFF

period of time.  

The RF access can be temporarily or indefinitely disabled by setting the appropriate value in the RF disable  

register.  

Figure 6.

ST25DVxxx RF power-up sequence (No DC supply)  

RF interface ready  

RFfield  

None Access  

RF REQUEST  

RF ANSWER  

Allowed  

RF or I2C  

t

boot  

Power-Up by RF  

(No Vcc ; V

DCG  

GPO CMOS Version  

Vint_supply  

)

tminCD  

GPO = RF_ACTIVITY  

ANS  

EOF  

REQ  

EOF  

GPO = FIELD

 

CHANGE  

IT duration  

GPO = FIELD CHANGE AND RF_ACTIVITY  

No answer to RF  

Request if any  

DS10925

–

Rev 9  

page 9/200  

ST25DV04K ST25DV16K ST25DV64K  

Memory management  

4

Memory management  

4.1  

Memory organization overview  

The ST25DVxxx memory is divided in four main memory areas:  

•

•

•

•

User memory  

Dynamic registers  

Fast transfer mode buffer  

System configuration area  

The ST25DVxxx user memory can be divided into 4 flexible user areas. Each area can be individually read –  

and/or – write-protected with one out of three specific 64-bit password.  

The ST25DVxxx dynamic registers are accessible by RF or I

2

C host and provide dynamic activity status or allow  

temporary activation or deactivation of some ST25DVxxx features.  

The ST25DVxxx also provides a 256 byte fast transfer mode buffer, acting as a mailbox between RF and I

2

C  

interface, allowing fast data transfer between contact and contactless worlds.  

Finally, the ST25DVxxx system configuration area contains static registers to configure all ST25DVxxx features,  

which can be tuned by user. Its access is protected by a 64 bit configuration password.  

This system configuration area also includes read only device information such as IC reference, memory size or  

IC revision, as well as a 64-bit block that is used to store the 64-bit unique identifier (UID), and the AFI (default  

00h) and DSFID (default 00h) registers. The UID is compliant with the ISO 15693 description, and its value is  

used during the anticollision sequence (Inventory). The UID value is written by ST on the production line. The AFI  

register stores the application family identifier. The DSFID register stores the data storage family identifier used in  

the anticollision algorithm.  

The system configuration area includes five additional 64-bit blocks that store an I

2

C password plus three RF user  

area access passwords and a RF configuration password.  

DS10925

–

Rev 9  

page 10/200  

ST25DV04K ST25DV16K ST25DV64K  

User memory  

Figure 7.

Memory organization  

CC File  

Area 1  

Always readable  

Area 2  

User memory  

(EEPROM up to 64-Kbits)  

Password protected  

Area 3  

Area 4  

Dynamic configuration  

and activity status  

Dynamic registers  

Fast Transfer Mode  

256 Bytes buffer  

Fast Transfer Mode mailbox  

Static configuration registers  

Device information  

UID, AFI, DSFID  

System configuration  

(EEPROM)  

Password protected  

Passwords  

4.2  

User memory  

User memory is accessible from both RF contactless interface and I

2

C wired interface.  

From RF interface, user memory is addressed as Blocks of 4 bytes, starting at address 0. RF extended read and  

write commands can be used to address all ST25DVxxx memory blocks. Other read and write commands can  

only address up to block FFh.  

From I

2

C interface, user memory is addressed as Bytes, starting at address 0. Device select must be set with  

E2=0.  

User memory can be read in continuity. Unlike the RF interface, there is no roll-over when the requested address  

reaches the end of the memory capacity.  

shows how memory is seen from RF interface and from I

2

C interface.  

DS10925

–

Rev 9  

page 11/200  

ST25DV04K ST25DV16K ST25DV64K  

User memory  

Table 2.

User memory as seen by RF and by I

2

C  

2

RF command  

I C command  

User memory  

(block addressing)  

(byte addressing)  

RF block (00)00h  

2

2

2

2

I C

 

byte  

I C

 

byte  

0002h  

I C

 

byte  

0001h  

I C byte  

0003h  

0000h  

Read Single Block  

Read Multiple Blocks  

RF block (00)01h  

2

2

2

2

I C byte  

I C byte  

I C byte  

I C byte  

Fast Read Single Block  

Fast Read Multiple Blocks  

Write Single Block  

0007h  

0006h  

0005h  

0004h  

RF block (00)02h  

2

2

2

2

I C byte  

I C byte  

I C byte  

I C byte  

Write Multiple Blocks  

000Bh  

000Ah  

0009h  

0008h  

Ext Read Single Block  

Ext Read Multiple Blocks  

Fast Ext Read Single Block  

Fast Ext Read Multi. Blocks  

Ext Write Single Block  

Ext Write Multiple Blocks  

….  

RF block (00)7Fh

2

2

2

2

I C

 

byte  

I C

 

byte  

01FEh  

I C

 

byte  

01FDh  

I C

 

byte  

01FFh  

01FCh  

2

I C Read command  

….  

2

I C

 

Write command  

RF block (00)FFh

Device select E2=0  

2

2

2

2

I C

 

byte  

I C

 

byte  

I C

 

byte  

03FDh  

I C

 

byte  

03FFh  

03FEh  

03FCh  

RF block 0100h  

2

2

2

2

I C

 

byte  

I C

 

byte  

I C

 

byte  

I C

 

byte  

0403h  

0402h  

0401h  

0400h  

Ext Read Single Block  

Ext Read Multiple Blocks  

Fast Ext Read Single Block  

Fast Ext Read Multi. Blocks  

Ext Write Single Block  

….  

RF block 01FFh

2

2

2

2

I C

 

byte  

I C

 

byte  

07FEh  

I C

 

byte  

07FDh  

I C

 

byte  

07FFh  

07FCh  

….  

Ext Write Multiple Blocks  

RF block 07FFh

2

2

2

2

I C

 

byte  

I C

 

byte  

1FFEh  

I C

 

byte  

1FFDh  

I C

 

byte  

1FFFh  

1FFCh  

1. Last

 

block of user memory in ST25DV04K

‑

XX..  

2. Last

 

block accessible with Read Single Block, Read Multiple Blocks, Fast Read Single Block, Fast Read  

Multiple Blocks, Write Single Block and Write Multiple Blocks RF commands.  

3. Last

 

block of user memory in ST25DV16K

‑

XX.  

4. Last

 

block of user memory in ST25DV64K

‑

XX.  

Note:  

In the factory all blocks of user memory are initialized to 00h.  

DS10925

–

Rev 9  

page 12/200  

ST25DV04K ST25DV16K ST25DV64K  

User memory  

4.2.1  

User memory areas  

The user memory can be split into different areas, each one with a distinct access privilege.  

RF and I

2

C read and write commands are legal only within a same zone:  

•

In R

F

, a

m

ultiple read or a multiple write command is not executed and returns the error code 0Fh if  

addresses cross the area borders.  

•

In I

2

C, a read data always return FFh after crossing an area border. A write command is not acknowledged  

and not executed if the command crosses the area border.  

Each user memory area is defined by its ending block address ENDA

i

. The starting block address is defined by  

the end of the preceding area.  

There are three ENDA

i

registers in the configuration system memory, used to define the end block addresses of  

Area 1, Area 2 and Area 3. The end of Area 4 is always the last block of memory and is not configurable.  

Figure 8.

ST25DVxxx user memory areas  

ST25DV user memory  

Block/Byte 0000h  

Areas limit  

Area1  

registers  

(8 Blocks/32 Bytes minimum)  

ENDA1  

Area2  

Area3  

Area4  

ENDA2  

ENDA3  

Last Block/Byte  

of user memory  

On factory delivery all ENDA

i

are set to maximum value, only Area1 exists and includes the full user memory.  

A granularity of 8 Blocks (32 Bytes) is offered to code area ending points.  

An area’s end limit is coded as followed in ENDA

i

registers:  

•

Last RF block address of area = 8 x ENDA

i

+ 7 => ENDA

i

= int(Last Area

i

RF block address / 8)  

•

•

Last I

2

C byte address of area = 32 * ENDA

i

+ 31 => ENDA

i

= int(Last Area

i

I

2

C byte address / 32)  

As a consequence, ENDA1 = 0 minimum size of Area 1 is 8 blocks (32 Bytes).  

Table 3.

Maximum user memory Block and Byte addresses and ENDA

i

value  

Last user memory byte address seen  

Last user memory block address  

seen by RF  

Maximum ENDA

 

value  

Device  

i

2

by I C  

ST25DV04K-xx  

ST25DV16K-xx  

ST25DV64K-xx  

007Fh  

01FFh  

07FFh  

01FFh  

07FFh  

1FFFh  

0Fh  

3Fh  

FFh  

DS10925

–

Rev 9  

page 13/200  

ST25DV04K ST25DV16K ST25DV64K  

User memory  

Table 4.

Areas and limit calculation from ENDA

i

registers  

2

Area  

Seen from RF interface  

Seen from I C interface  

Block 0000h  

…

Byte 0000h  

…

Area 1  

Block (ENDA1*8)+7  

Byte (ENDA1*32)+31  

Block (ENDA1+1)*8  

…

Byte (ENDA1+1)*32  

…

Area 2  

Area 3  

Area 4  

Block (ENDA2*8)+7  

Byte (ENDA2*32)+31  

Block (ENDA2+1)*8  

…

Byte (ENDA2+1)*32  

…

Block (ENDA3*8)+7  

Byte (ENDA3*32)+31  

Block (ENDA3+1)*8  

…

Byte (ENDA3+1)*32  

…

Last memory Block  

Last memory Byte  

Organization of user memory in areas have the following characteristics:  

•

At least one area exists (Area1), starting at Block/Byte address 0000h and finishing at ENDA1, with ENDA1  

= ENDA2 = ENDA3 = End of user memory (factory setting).  

•

•

•

•

Two Areas could be defined by setting ENDA1 < ENDA2 = ENDA3 = End of user memory.  

Three Areas may be defined by setting ENDA1 < ENDA2 < ENDA3 = End of user memory.  

A maximum of four areas may be defined by setting ENDA1 < ENDA2 < ENDA3 < End of user memory.  

Area 1 specificities  

–

–

–

Start of Area1 is always Block/Byte address 0000h.  

Area1 minimum size is 8 Blocks (32 Bytes) when ENDA1 = 00h.  

Area1 is always readable.  

•

•

The last area always finishes on the last user memory Block/Byte address (ENDA4 doesn’t exist).  

All areas are contiguous: end of Area(n) + one Block/Byte address is always start of Area(n+1).  

Area size programming  

RF user must first open the RF configuration security session to write ENDAi registers.  

I

2

C host must first open I

2

C security session to write ENDAi registers.  

When programming an ENDAi register, the following rule must be respected:  

•

ENDAi-1 < ENDAi ≤ ENDAi+1 = End of memory.  

This means that prior to programming any ENDAi register, its successor (ENDAi+1) must first be programmed to  

the last Block/Byte of memory:  

•

•

•

Successful ENDA3 programming condition: ENDA2 < ENDA3 ≤ End of user memory  

Successful ENDA2 programming condition: ENDA1 < ENDA2 ≤ ENDA3 = End of user memory  

Successful ENDA1 programming condition: ENDA1 ≤ ENDA2 = ENDA 3 = End of user memory  

If this rule is not respected, an error 0Fh is returned in R

F

,

N

oAck is returned in I2C, and programming is not  

done.  

In order to respect this rule, the following procedure is recommended when programming Areas size (even for  

changing only one Area size):  

DS10925

–

Rev 9  

page 14/200  

ST25DV04K ST25DV16K ST25DV64K  

User memory  

1.  

2.  

Ends of Areas 3 and 2 must first be set to the end of memory while respecting the following order:  

a.  

b.  

If ENDA3 ≠ end of user memory, then set ENDA3 = end of memory; else, do not write ENDA3.  

If ENDA2 ≠ end of user memory, then set ENDA2 = end of memory; else, do not write ENDA2.  

Then, desired area limits can be set respecting the following order:  

a.  

b.  

c.  

Set new ENDA1 value.  

Set new ENDA2 value, with ENDA2 > ENDA1  

Set new ENDA3 value, with ENDA3 > ENDA2  

Example of successive user memory area setting (for a ST25DV64K-xx):  

1. Initial

 

state, 2 Areas are defined:  

a.  

b.  

c.  

ENDA1 = 10h (Last block of Area 1: (10h x 8) + 7 = 0087h)  

ENDA2 = FFh (Last block of Area 2: (FFh x 8) + 7 = 07FFh)  

ENDA3 = FFh (No Area 3)  

◦

◦

◦

◦

Area 1 from Block 0000h to 0087h (136 Blocks)  

Area 2 from Block 0088h to 07FFh (1912 Blocks)  

There is no Area 3  

There is no Area 4  

2.  

Split of user memory in four areas:  

a.  

b.  

c.  

d.  

e.  

ENDA3 is not updated as it is already set to end of memory  

ENDA2 is not updated as it is already set to end of memory  

Set ENDA1 = 3Fh (Last block of Area 1: (3Fh x 8) + 7 = 01FFh)  

Set ENDA2 = 5Fh (Last block of Area 1: (5Fh x 8) + 7 = 02FFh)  

Set ENDA3 = BFh (Last block of Area 1: (BFh x 8) + 7 = 05FFh)  

◦

◦

◦

◦

Area1 from Block 0000h to 01FFh (512 Blocks)  

Area2 from Block 0200h to 02FFh (256 Blocks)  

Area3 from Block 0300h to 05FFh (768 Blocks)  

Area4 from Block 0600h to 07FFh (512 Blocks).  

3.  

Return to a split in two equal areas:  

a.  

b.  

c.  

Set ENDA3 = FFh  

Set ENDA2 = FFh  

Set ENDA1 = 7Fh (Last block of Area 1: (7Fh x 8) + 7 = 03FFh)  

◦

◦

◦

◦

Area1 from Block 0000h to 03FFh (1024 Blocks)  

Area2 from Block 0400h to 07FFh (1024 Blocks)  

There is no Area3  

There is no Area 4  

Programming ENDA3 to FFh in step 2.a would have resulted in into an error, since rule ENDAi-1 < ENDAi would  

not been respected (ENDA2 = ENDA3 in that case).  

Registers for user memory area configuration  

Table 5.

ENDA1 access  

RF  

I2C  

Command  

Type  

Address  

Type  

Read Configuration (cmd code A0h) @05h  

Write Configuration (cmd code A1h) @05h  

R always, W if RF configuration security  

session is open and configuration not locked  

R always, W if I2C security  

session is open  

E2 = 1, 0005h  

DS10925

–

Rev 9  

page 15/200  

ST25DV04K ST25DV16K ST25DV64K  

User memory  

Table 6.

ENDA1  

Bit  

Name  

Function  

Factory Value  

ST25DV04K-xx: 0Fh  

End Area 1 = 8*ENDA1+7 when expressed in blocks (RF)  

b7-b0  

ENDA1  

ST25DV16K-xx: 3Fh  

ST25DV64K-xx: FFh  

2

End Area 1 = 32*ENDA1+31 when expressed in bytes (I

 

C)  

Note:  

Refer to

for ENDA1 register.  

Table 7.

ENDA2 access  

RF  

I2C  

Command  

Type  

Address  

Type  

Read Configuration (cmd code A0h) @07h  

Write Configuration (cmd code A1h) @07h  

R always, W if RF configuration security  

session is open and configuration not locked  

R always, W if I2C security  

session is open  

E2 = 1, 0007h  

Table 8.

ENDA2  

Bit  

Name  

Function  

Factory Value  

ST25DV04K-xx: 0Fh  

ST25DV16K-xx: 3Fh  

ST25DV64K-xx: FFh  

End Area 2 = 8 x ENDA2 + 7 when expressed in blocks (RF)  

b7-b0  

ENDA2  

2

End Area 2 = 32*ENDA2 + 31 when expressed in bytes (I

 

C)  

Note:  

Refer to

for ENDA2 register.  

Table 9.

ENDA3 access  

RF  

I2C  

Command  

Type  

Address  

Type  

Read Configuration (cmd code A0h) @09h  

Write Configuration (cmd code A1h) @09h  

R always, W if RF configuration security  

session is open and configuration not locked  

R always, W if I2C security  

session is open  

E2 = 1, 0009h  

Table 10.

ENDA3  

Function  

Bit  

Name  

Factory Value  

ST25DV04K-xx: 0Fh  

ST25DV16K-xx: 3Fh  

ST25DV64K-xx: FFh  

End Area 3 = 8 x ENDA3 + 7 when expressed in blocks (RF)  

b7-b0  

ENDA3  

2

End Area 3 = 32 x ENDA3 + 31 when expressed in bytes (I

 

C)  

Note:  

Refer to

for ENDA3 register.  

DS10925

–

Rev 9  

page 16/200  

ST25DV04K ST25DV16K ST25DV64K  

System configuration area  

4.3  

System configuration area  

In addition to EEPROM user memory, ST25DVxxx includes a set of static registers located in the system  

configuration area memory (EEPROM nonvolatile registers). Those registers are set during device configuration  

(i.e.: area extension), or by the application (i.e.: area protection). Static registers content is read during the boot  

sequence and define basic ST25DVxxx behavior.  

In R

F

,

t

he static registers located in the system configuration area can be accessed via dedicated Read  

Configuration and Write Configuration commands, with a pointer acting as the register address.  

The RF configuration security session must first be open, by presenting a valid RF configuration password, to  

grant write access to system configuration registers.  

The system configuration area write access by RF can also be deactivated by I

2

C host.  

In I

2

C static registers located in the system configuration area can be accessed with I

2

C read and write  

commands with device select E2=1. Readable system areas could be read in continuity.  

I

2

C security session must first be open, by presenting a valid I

2

C password, to grant write access to system  

configuration registers.  

shows the complete map of the system configuration area, as seen  

by RF and I

2

C interface.  

Table 11.

System configuration memory map  

2

RF access  

Static Register  

Function  

I C

 

access  

Address  

0000h  

0001h  

0002h  

0003h  

0004h  

0005h  

0006h  

0007h  

0008h  

0009h  

000Ah  

000Bh  

000Ch  

000Dh  

Address  

00h  

Type  

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Name  

Device select  

E2=1  

Type  

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Enable/disable I

T

s

o

n GPO  

Interruption pulse duration  

Energy Harvesting default strategy after Power ON  

RF interface state after Power ON  

Area1 RF access protection  

Area 1 ending point  

01h  

E2=1  

02h  

E2=1  

03h  

E2=1  

04h  

E2=1  

05h  

E2=1  

06h  

Area2 RF access protection  

Area 2 ending point  

E2=1  

07h  

E2=1  

08h  

Area3 RF access protection  

Area 3 ending point  

E2=1  

09h  

E2=1  

0Ah  

Area4 RF access protection  

E2=1  

2

No access  

E2=1  

Area 1 to 4 I

 

C access protection  

RW

RW

N/A  

Blocks 0 and 1 RF Write protection  

E2=1  

0Dh  

Fast transfer mode state after power ON  

E2=1  

Maximum time before the message is automatically  

released  

RW

RW

0Eh  

E2=1  

000Eh  

RW

WO

WO

RW

RW

RO  

RW

RO  

RO  

RO  

RO  

RO  

RO  

RO  

0Fh  

N/A  

NA  

Protect RF Write to system configuration registers  

E2=1  

E2=1  

E2=1  

E2=1  

E2=1  

E2=1  

E2=1  

E2=1  

000Fh  

0010h  

DSFID lock status  

AFI lock status  

0011h  

N/A  

N/A  

DSFID value  

0012h  

AFI value  

0013h  

Memory size value in blocks, 2 bytes  

Block size value in bytes  

IC reference value  

0014h to 0015h  

0016h  

N/A  

N/A  

RO  

RO  

0017h  

DS10925

–

Rev 9  

page 17/200  

ST25DV04K ST25DV16K ST25DV64K  

System configuration area  

2

RF access  

Static Register  

Function  

I C

 

access  

Address  

NA  

Type  

Name  

Device select  

E2=1  

Address  

0018h to 001Fh  

0020h  

Type  

RO  

RO  

Unique identifier, 8 bytes  

IC revision  

–

E2=1  

RO  

ST Reserved  

E2=1  

0021h  

RO  

–

ST Reserved  

E2=1  

0022h  

RO  

No access  

–

ST Reserved  

E2=1  

0023h  

RO  

R/W

2

E2=1  

0900h to 0907h  

I C

 

security session password, 8 bytes  

WO

WO

WO

WO

N/A  

N/A  

N/A  

N/A  

RF configuration security session password, 8 bytes  

RF user security session password 1, 8 bytes  

RF user security session password 2, 8 bytes  

RF user security session password 3, 8 bytes  

No access  

1. Write

 

access is granted if RF configuration security session is open and configuration is not locked  

(LOCK_CFG register equals to 0).  

2

2.  

Write access if I

 

C security session is open.  

3. Write

 

access to bit 0 if Block 00h is not already locked and to bit 1 if Block 01h is not already locked.  

4. LOCK_CCFILE

 

content is only readable through reading the Block Security Status of blocks 00h and 001h  

(see

)  

5. Write

 

access if DSFID is not locked  

6. Write

 

access if AFI is not locked.  

2

2

7.  

8.  

Write access with I C Write Password command, only after presenting a correct I C password.  

2

Read access is granted if I

 

C security session is open.  

9. Write

 

access only if corresponding RF security session is open.  

DS10925

–

Rev 9  

page 18/200  

ST25DV04K ST25DV16K ST25DV64K  

Dynamic configuration  

4.4  

Dynamic configuration  

ST25DV has a set of dynamic registers that allow temporary modification of its behavior or report on its activity.  

Dynamic registers are volatile and not restored to their previous values after POR.  

Some static registers have an image in dynamic registers: dynamic register value is initialized with the static  

register value and may be updated by the application to modify the device behavior temporarily (i.e.: set reset  

of Energy Harvesting). When a valid change occurs in a static register, in RF or I

2

C, the corresponding dynamic  

register is automatically updated.  

Other, dynamic registers, automatically updated, contain indication on ST25DV activity. (i.e.: IT_STS_Dyn gives  

the interruption’s status or MB_CTRL_Dyn gives the fast transfer mode mailbox control).  

In R

F

,

d

ynamic registers can be accessed via dedicated (Fast) Read Dynamic Configuration and (Fast) Write  

Dynamic Configuration commands, with a pointer acting as the register address. No password is needed to  

access dynamic registers.  

In I

2

C, dynamic registers can be accessed with I

2

C read and write commands with device select E2=0. Dynamic  

registers can be read in continuity. Dynamic registers and fast transfer mode mailbox can be read in continuity,  

but not written in continuity. No password is needed to access dynamic registers.  

shows the complete map of dynamic registers, as seen by RF interface  

and by I

2

C interface.  

Table 12.

Dynamic registers memory map  

2

RF access  

Address Type  

Dynamic Registers  

Function  

I C

 

access  

Device  

select  

Name  

Address  

Type  

00h  

RO  

–

GPO control  

ST Reserved  

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

2000h  

2001h  

2002h  

2003h  

2004h  

2005h  

2006h  

2007h  

R/W  

RO  

No access  

02h  

R/W  

Energy Harvesting management & usage status  

RF interface usage management  

R/W  

R/W  

RO  

2

No access  

I C

 

security session status  

Interruptions Status  

RO  

0Dh  

NA  

R/W  

RO  

Fast transfer mode control and status  

length of fast transfer mode message  

R/W  

RO  

DS10925

–

Rev 9  

page 19/200  

ST25DV04K ST25DV16K ST25DV64K  

Fast transfer mode mailbox  

4.5  

Fast transfer mode mailbox  

ST25DVxxx fast transfer mode uses a dedicated mailbox buffer for transferring messages between RF and I

2

C  

worlds. This mailbox contains up to 256 Bytes of data which are filled from the first byte.  

Fast transfer mode mailbox is accessed in bytes from both RF and I

2

C.  

In R

F

,

m

ailbox is read via a dedicated (Fast) Read Message command. Read can start from any address value  

inside the mailbox, between 00h and FFh. Writing in the mailbox is done via the (Fast) Write Message command  

in one shot, always starting at mailbox address 00h. No password is needed to access mailbox from R

F

,

b

ut fast  

transfer mode must be enabled.  

In I

2

C, mailbox read can start from any address value between 2008h and 2107h. Write mailbox MUST start from  

address 2008h to a max of 2107h. No password is needed to access mailbox from I

2

C, but fast transfer mode  

must be enabled.  

shows the map of fast transfer mode mailbox, as seen by RF  

interface and by I

2

C interface.  

Table 13.

Fast transfer mode mailbox memory map  

2

RF access  

Fast transfer mode buffer  

Function  

I C access  

Device  

select  

Address  

Type  

Name  

Address  

Type  

00h  

01h  

…

R/W  

R/W  

…

MB_Dyn Byte 0  

MB_Dyn Byte 1  

…

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

E2 = 0  

2008h  

2009h  

…  

R/W  

R/W  

…  

Fast transfer mode buffer (256-Bytes)  

FEh  

FFh  

R/W  

R/W  

MB_Dyn Byte 254  

MB_Dyn Byte 255  

2106h  

2107h  

R/W  

R/W  

DS10925

–

Rev 9  

page 20/200  

ST25DV04K ST25DV16K ST25DV64K  

ST25DVxxx specific features  

5

ST25DVxxx specific features  

ST25DVxxx offers the following features:  

•

A fast transfer mode (FTM), to achieve a fast link between RF and contact worlds, via a 256 byte buffer  

called Mailbox. This mailbox dynamic buffer of 256 byte can be filled or emptied via either RF or I

2

C.  

•

A GPO pin, which indicates incoming event to the contact side, like RF Field changes, RF activity in  

progress, RF writing completion or Mailbox message availability.  

•

•

An Energy Harvesting element to deliver µW of power when external conditions make it possible.  

RF management, which allows ST25DVxxx to ignore RF requests.  

All these features can be programmed by setting static and/or dynamic registers of the ST25DVxxx. ST25DVxxx  

can be partially customized using configuration registers located in the E

2

system area.  

These registers are:  

•

•

•

•

•

dedicated to Data Memory organization and protection ENDA

i

, I2CSS, RFAiSS, LOCK_CCFILE.  

dedicated to fast transfer mode MB_WDG, MB_MODE  

dedicated to observation, GPO, IT_TIME  

dedicated to RF , RF_MNG

T

,

E

H_MODE  

dedicated the device’s structure LOCK_CFG  

A set of additional registers allows to identify and customize the product (DSFID, AFI, IC_RE

F

,

e

tc.).  

In I²C,  

Read accesses to the static configuration register is always allowed, except for passwords. For dedicated  

registers, write access is granted after prior successful presentation of the I

2

C password. Configuration register  

are located from @00h to 0Fh in the system area (device code 111)  

In RF  

Dedicated commands Read Configuration and Write Configuration must be used to access the static  

configuration registers. Update is only possible when the access right was granted by presenting the RF  

configuration password (RF_PWD_0), and if the system configuration was not previously locked by the I

2

C host  

(LOCK_CFG=1), which acts as security master.  

After any valid write access to the static configuration registers, the new configuration is immediately applied.  

Some of the static registers have a dynamic image (notice _Dyn) preset with the static register value:  

GPO_CTRL_Dyn, EH_CTRL_Dyn, RF_MNGT_Dyn and MB_CTRL_Dyn.  

When it exists, ST25DVxxx uses the dynamic configuration register to manage its processes. A dynamic  

configuration register updated by the application will recover its default static value after a Power On Reset  

(POR).  

Other dynamic registers are dedicated to process monitoring:  

•

•

•

I2C_SSO_Dyn is dedicated to data memory protection  

MB_LEN_Dyn, MB_CTRL_Dyn are dedicated to fast transfer mode  

IT_STS_Dyn is dedicated to interrupt  

In I

2

C, read and write of the Dynamic registers is done using usual I

2

C read & write command at dedicated  

address. (E2 =0 in device select).  

In RF read or write accesses to the Dynamic registers are associated to the dedicated commands, Read Dynamic  

Configuration, Write Dynamic Configuration and Read Message Length.  

DS10925

–

Rev 9  

page 21/200  

ST25DV04K ST25DV16K ST25DV64K  

Fast transfer mode (FTM)  

5.1  

Fast transfer mode (FTM)  

5.1.1  

Fast transfer mode registers  

Static Registers  

Table 14.

MB_MODE access  

RF  

I2C  

Type  

Command  

Type  

Address  

R always, W if RF configuration security  

session is open and configuration not  

locked  

Read Configuration (cmd code A0h) @0Dh  

Write Configuration (cmd code A1h) @0Dh  

R always, W if I2C security  

session is open  

E2=1, 000Dh  

Table 15.

MB_MODE  

Function  

Bit  

b0  

Name  

MB_MODE  

RFU  

Factory Value  

0b  

0: Enabling fast transfer mode is forbidden.  

1: Enabling fast transfer mode is authorized.  

b7-b1  

–

0000000b  

Note:  

Refer to

for the MB_MODE register.  

Table 16.

MB_WDG access  

RF  

I2C  

Command  

Type  

Address  

Type  

R always, W if RF configuration security  

session is open and configuration not  

locked  

Read Configuration (cmd code A0h) @0Eh  

Write Configuration (cmd code A1h) @0Eh  

2

R always, W if I

 

C security  

E2=1, 000Eh  

session is open  

Table 17.

MB_WDG  

Bit  

Name  

MB_WDG  

RFU  

Function  

Factory Value  

111b  

(MB_WDG-1)  

Watch dog duration = 2  

x30ms±6  

b2-b0  

b7-b3  

If MD_WDG = 0, then watchdog duration is infinite  

–

00000b  

Note:  

Refer to

for the MB_WDG register.  

DS10925

–

Rev 9  

page 22/200  

ST25DV04K ST25DV16K ST25DV64K  

Fast transfer mode (FTM)  

Dynamic Registers  

Table 18.

MB_CTRL_Dyn access  

RF  

I2C  

Command  

Read Dynamic Configuration (cmd code ADh) @0Dh  

Fast Read Dynamic Configuration (cmd code CDh) @0Dh

 

b0: R always, W always  

Type  

Address  

Type  

b0: R always, W always  

b7-b1: RO  

E2 = 0, 2006h  

Write Dynamic Configuration (cmd code AEh) @0Dh  

Fast Write Dynamic Configuration (cmd code CEh) @0Dh  

b7-b1: RO  

Table 19.

MB_CTRL_Dyn  

Function  

Bit  

Name  

Factory Value  

0: Disable FTM, FTM mailbox is empty  

1: Enable FTM  

MB_EN

b0  

0b  

2

0: No I

 

C message in FTM mailbox  

b1  

HOST_PUT_MSG  

0b  

2

1: I

 

C has Put a message in FTM mailbox  

0: No RF message in FTM mailbox  

b2  

b3  

RF_PUT_MSG  

RFU  

0b  

0b  

1: RF has Put message in FTM mailbox  

–

2

0: No message missed by I

 

C  

b4  

b5  

b6  

b7  

HOST_MISS_MSG  

RF_MISS_MSG  

0b  

0b  

0b  

0b  

2

1: I C did not read RF message before watchdog time out  

0: No message missed by RF  

1: RF did not read message before watchdog time out  

2

0: No message or message not coming from I

 

C  

HOST_CURRENT_MSG  

RF_CURRENT_MSG  

2

1: Current Message in FTM mailbox comes from I

 

C  

0: No message or message not coming from RF  

1: Current Message in FTM mailbox comes from RF  

1. MB_EN

 

bit is automatically reset to 0 if MB_MODE register is reset to 0.  

Note:  

Refer to

for the MB_CTRL_Dyn register.  

Table 20.

MB_LEN_Dyn access  

RF  

I2C  

Type  

Command  

Type  

Address  

Read Message Length (cmd code ABh)  

RO  

E2 = 0, 2007h  

RO  

Fast Read Message Length (cmd code CBh)  

DS10925

–

Rev 9  

page 23/200  

ST25DV04K ST25DV16K ST25DV64K  

Fast transfer mode (FTM)  

Table 21.

MB_LEN_Dyn  

Function  

Bit  

Name  

Factory Value  

Size in byte, minus 1 byte, of message contained in FTM  

mailbox (automatically set by ST25DVxxx)  

b7-b0  

MB_LEN  

0h  

Note:  

Refer to

for the MB_LEN_Dyn register.  

5.1.2  

Fast transfer mode usage  

ST25DV acts as mailbox between RF (reader, smartphone, …) and an I

2

C host (microcontroller…). Each interface  

can send a message containing up to 256 bytes of data to the other interface through that mailbox.  

To

s

end data from RF reader to I

2

C host, fast transfer mode must be enabled, the mailbox must be free, V

CC  

power must be present, and the RF user must first writes the message containing data in the mailbox.  

I

2

C host is then informed (by interruption on GPO output or polling on MB_CTRL_Dyn register) that a message  

from RF is present in the mailbox.  

Once the complete message has been read by I

2

C, mailbox is considered free again and is available for receiving  

a new message (data is not cleared).  

The RF user is informed that the message has been read by the I

2

C host by polling on MB_CTRL_Dyn register.  

Figure 9.

RF to I

2

C fast transfer mode operation  

ST25DV  

Dynamic registers  

MB_LEN_Dyn  

MB_CRTL_Dyn  

1Mb/s  

26.5kb/s  

RF message  

Fast Transfer Mode mailbox  

(256 Bytes)  

ISO/IEC  

15693 reader  

I2C host  

I2C  

Static registers  

MB_MODE  

MB_WDG  

GPO/RF_PUT_MSG  

To

s

end data from the I

2

C host to the RF reader, fast transfer mode must be enabled, the mailbox must be free,  

V

CC

power must be present, and the I2C host must first write the message containing data in the mailbox.  

The RF user must poll on MB_CTRL_Dyn register to check for the presence of a message from I

2

C in the  

mailbox.  

Once the complete message has been read by RF user, mailbox is considered free again and is available for  

receiving a new message (data is not cleared).  

The I

2

C host is informed that message has been read by RF user through a GPO interruption or by polling on the  

MB_CTRL_Dyn register.  

DS10925

–

Rev 9  

page 24/200  

ST25DV04K ST25DV16K ST25DV64K  

Fast transfer mode (FTM)  

Figure 10.

I

2

C to RF fast transfer mode operation  

ST25DV  

Dynamic registers  

MB_LEN_Dyn  

MB_CRTL_Dyn  

Fast Transfer Mode mailbox  

(256 Bytes)  

ISO/IEC  

15693 reader  

I2C host  

I2C  

Host message  

1Mb/s  

GPO/RF_GET_MSG  

Up to  

53kb/s  

Static registers  

MB_MODE  

MB_WDG  

V

CC

supply source is mandatory to activate this feature.  

No precedence rule is applied: the first request is served first.  

Adding a message is only possible when fast transfer mode is enabled (MB_EN=1) and mailbox is free  

(HOST_PUT_MSG and RF_PUT_MSG cleared, which is the case after POR or after complete reading of I

2

C  

message by R

F

,

a

nd complete reading of RF message by I

2

C).  

A watchdog limits the message availability in time: when a time-out occurs, the mailbox is considered free, and  

the HOST_MISS_MSG or RF_MISS_MSG bits is set into MB_CTRL_Dyn register. The data contained in the  

mailbox is not cleared after a read or after the watchdog has been triggered: message data is still available  

for read and until fast transfer mode is disabled. HOST_CURRENT_MSG and RF_CURRENT_MSG bits are  

indicating the source of the current data.  

The message is stored in a buffer (256 Bytes), and the write operation is done immediately. .  

The data written in user or system memory (EEPROM), either from I

2

C or from R

F

,

t

ransits via the 256-Bytes  

fast transfer mode’s buffer. Consequently fast transfer mode must be deactivated (MB_EN=0) before starting  

Caution:  

any write operation in user or system memory, otherwise command will be NotACK for I

2

C or get an answer 0Fh  

for RF and programming is not done.  

I

2

C access to mailbox  

The access by I

2

C can be done by dedicated address mapping to mailbox (2008h to 2107h) with device identifier  

E2 = 0.  

I

2

C reading operation does not support rollover. Therefore data out is set to FFh when the counter reaches the  

message end.  

The RF_PUT_MSG is cleared after reaching the STOP consecutive to reading the last message byte, and the  

mailbox is considered free (but the message is not cleared and it is still present in the mailbox).  

A I

2

C reading operation will never clear HOST_PUT_MSG, and the message remains available for R

F

.  

An I

2

C read can start at any address inside the mailbox (between address 2008h and 2107h).  

A I

2

C write operation must start from the first mailbox location, at address 2008h. After reaching the Mailbox  

border at address 2107h all bytes are NACK and the command is not executed (rollover feature not supported).  

At the end of a successful I

2

C message write, the message length is automatically set into MB_LEN_Dyn register,  

and HOST_PUT_MSG bit is set into MB_CTRL_Dyn register, and the write access to the mailbox is not possible  

until the mailbox has been released again. MB_LEN_Dyn contains the size of the message in byte, minus 1.  

DS10925

–

Rev 9  

page 25/200  

ST25DV04K ST25DV16K ST25DV64K  

Fast transfer mode (FTM)  

RF access to mailbox  

The RF Control & Access to mailbox is possible using dedicated custom commands:  

•

•

•

•

•

Read Dynamic Configuration and Fast Read Dynamic Configuration to check availability of mailbox.  

Write Dynamic Configuration and Fast Write Dynamic configuration to enable or disable fast transfer mode.  

Read Message Length and Fast Read Message Length to get the length of the contained message,  

Read Message and Fast Read Message to download the content of the mailbox,  

Write Message and Fast Write Message to put a new message in mailbox. (New length is automatically  

updated after completion of a successful Write Message or Fast Write Message command).  

HOST_PUT_MSG is cleared following a valid reading of the last message byte, and mailbox is considered free  

(but message is not cleared and is still present in the mailbox).  

A RF read can start at any address of inside the message, but return an error 0Fh if trying to read after the last  

byte of the message.  

A RF reading operation will never clear RF_PUT_MSG , the message will remain available for I

2

C.  

At the end of a successful RF message write, the message length is automatically set in MB_LEN_Dyn register,  

and RF_PUT_MSG bit is set in MB_CTRL_Dyn register. and write access to the mailbox is not possible until  

mailbox has been freed again.  

The presence of a DC supply is mandatory to get RF access to the mailbox. VCC_ON can be checked reading  

the dynamic register EH_CTRL_Dyn.  

To

g

et more details about sequences to prepare and initiate a Fast Transfer, to detect progress of a fast transfer  

or to control and execute a fast transfer, please refer to AN4910. How to exchange data between wired (I

2

C) and  

wireless world (RF ISO15693) using fast transfer mode supported by ST25DVxxx).  

DS10925

–

Rev 9  

page 26/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

Figure 11.

Fast transfer mode mailbox access management.  

MB_EN=00h or  

VCC OFF  

MB_EN=00h or  

VCC OFF  

FTM disabled  

MB_CTRL_Dyn=00h  

No access  

VCC ON and  

MB_EN=01h  

MB_EN=00h or  

VCC OFF  

I2C read msg  

RF read msg  

FTM enabled  

I2C write msg  

RF write msg  

FTM enabled  

FTM enabled  

Mailbox empty  

MB_CTRL_Dyn=01h  

R/W access  

I2C Message  

MB_CTRL_Dyn=43h  

Read access  

RF Message  

MB_CTRL_Dyn=85h  

Read access  

Mailbox free  

RF read full msg  

msg  

FTM enabled  

Mailbox free  

I2C read full  

MB_CTRL_Dyn=41/81h  

R/W access  

RF read  

MB_CTRL_Dyn  

I2C read  

MB_CTRL_Dyn  

FTM enabled  

Mailbox free  

MB_CTRL_Dyn=61/91h  

R/W access  

Watchdog trig  

Watchdog trig  

Note:  

Assuming MB_MODE=01h  

Assuming no error occurred  

5.2  

GPO  

GPO signal is used to alert the I

2

C host of external RF events or ST25DVxxx processes activity. Several causes  

could be used to request a host interruption. RF user can also directly drive GPO pin level using a dedicated RF  

command.  

5.2.1  

ST25DVxxx interrupt capabilities on RF events  

ST25DVxxx supports multi interruption mode and can report several events occurring through RF interface.  

In this chapter, all drawings are referring to the open drain version of GPO output (ST25DVxxK-IE).  

The reader can retrieve the behaviour of CMOS version (ST25DVxxK-JF) by inverting the GPO curve polarity and  

replace in text “released” or “high-Z” by “pull to ground”.  

Supported RF events is listed hereafter:  

DS10925

–

Rev 9  

page 27/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

RF_USER:  

•

•

GPO output level is controlled by Manage GPO command (set or reset)  

When RF_USER is activated, GPO level is changed after EOF of ST25DV response to a Manage GPO set  

or reset command (see

).  

•

RF_USER is prevalent over all other GPO events when set by Manage GPO command (other interrupts are  

still visible in IT_STS_Dyn status register, but do not change GPO output level).  

Figure 12.

RF_USER chronogram  

1) VCD sends a ManageGPO command with value 00h (set GPO) and ST25DV replies.  

GPO/RF_USER is tied low after ST25DV response.  

ManageGPO  

00h  

command  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

ST25DV  

reply  

GPO/RF_USER (OD)  

2) VCD sends a ManageGPO command with value 01h (reset GPO) and ST25DV replies.  

GPO/RF_USER is set high-Z low after ST25DV response.  

ManageGPO  

01h  

command  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

ST25DV  

reply  

GPO/RF_USER (OD)  

3) VCD sends a ManageGPO command (any value) and ST25DV replies with error.  

GPO/RF_USER remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

ManageGPO  

command  

ST25DV  

reply  

GPO/RF_USER (OD)  

4) VCD sends a ManageGPO command (any value) and ST25DV stays quiet (command not for this  

VICC, or quiet state). GPO/RF_USER remains high-Z.  

S

O

F

E

O

F

ManageGPO  

command  

GPO/RF_USER (OD)  

5) VCD sends any command other than ManageGPO command and ST25DV replies.  

GPO/RF_USER remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t1/Wt  

Any other  

command  

ST25DV  

reply  

GPO/RF_USER (OD)  

DS10925

–

Rev 9  

page 28/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

RF_ACTIVITY

:  

•

•

GPO output level reflects the RF activity.  

When RF_ACTIVITY is activated, a GPO output level change from RF command EOF to ST25DV response  

EO

F

.  

Figure 13.

RF_ACTIVITY chronogram  

1) VCD sends a command and ST25DV replies. GPO/RF_ACTIVITY is released after ST25DV  

response.  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

VCD  

command  

ST25DV  

reply  

GPO/RF_ACTIVITY (OD)  

2) VCD sends a write command and ST25DV replies after write completed. GPO/RF_ACTIVITY is  

released after ST25DV response.  

S

O

F

E

O

F

S

O

F

E

O

F

(m*)W

t  

Write  

command  

ST25DV  

reply  

GPO/RF_ACTIVITY (OD)  

3) VCD sends a write command with option flag set to 1, and ST25DV replies after receiving EO

F

.  

GPO/RF_ACTIVITY is released after ST25DV response.  

E

O

F

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

>(m*)W

t  

Write  

command  

ST25DV  

reply  

GPO/RF_ACTIVITY (OD)  

4) VCD sends an Inventory 16 slots command, and ST25DV replies in its slot. GPO/RF_ACTIVITY is  

released after ST25DV response.  

E

O

F

E

O

F

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

Inventory  

command  

ST25DV  

reply  

Slot 1  

Slot n  

GPO/RF_ACTIVITY (OD)  

5) VCD sends a command and ST25DV stays quiet (Stay Quiet command, command not for this  

VICC, or quiet state). GPO/RF_ACTIVITY remains high-Z.  

S

O

F

E

O

F

VCD  

Command  

GPO/RF_ACTIVITY (OD)  

DS10925

–

Rev 9  

page 29/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

RF_INTERRUP

T

:  

•

•

A pulse is emitted on GPO by Manage GPO command (interrupt).  

When RF_INTERRUPT is activated, a pulse of duration IT_TIME is emitted after EOF of ST25DV response  

to a Manage GPO interrupt command (see

).  

Figure 14.

RF_INTERRUPT chronogram  

1) VCD sends a ManageGPO command with value 80h (GPO emit pulse) and ST25DV replies.  

GPO/RF_INTERRUPT generates a pulse of duration IT_TIME after ST25DV response.  

ManageGPO  

80h  

command  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

ST25DV  

reply  

GPO/RF_INTERRUPT (OD)  

2) VCD sends a ManageGPO command (any value) and ST25DV replies with error.  

GPO/RF_INTERRUPT remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

ST25DV  

reply  

ManageGPO  

command  

GPO/RF_INTERRUPT (OD)  

3) VCD sends a ManageGPO command (any value) and ST25DV stays quiet (command not for this  

VICC, or quiet state). GPO/RF_INTERRUPT remains high-Z.  

S

O

F

E

O

F

ManageGPO  

command  

GPO/RF_INTERRUPT (OD)  

4) VCD sends any command other than ManageGPO command and ST25DV replies.  

GPO/RF_INTERRUPT remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t

1

/W

t  

Any other  

command  

ST25DV  

reply  

GPO/RF_INTERRUPT (OD)  

DS10925

–

Rev 9  

page 30/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

FIELD_CHANGE:  

•

•

A pulse is emitted on GPO to signal a change in RF field state.  

When FIELD_CHANGE is activated, and when RF field appear or disappear, GPO emits a pulse of duration  

IT_TIME.  

•

•

In case of RF field disappear, the pulse is emitted only if V

CC

power supply is present.  

If RF is configured in RF_SLEEP mode, field change are not reported on GPO, even if FIELD_CHANGE  

event is activated, as shown in

.  

Table 22.

FIELD_CHANGE when RF is disabled or in sleep mode  

RF_DISABLE  

RF_SLEEP  

GPO behaviour when FIELD_CHANGE is enabled  

0

1

0

0

1

1

A pulse is emitted on GPO if RF field appears or disappears

X

X

GPO remains High-Z (OD) or tied low (CMOS)  

IT_STS_Dyn register is not updated.  

1. assuming

 

that GPO output is enabled (GPO_EN = 1).  

Figure 15.

FIELD_CHANGE chronogram  

1) RF field appears. GPO/FIELD_CHANGE generates a pulse during IT_TIME.  

RF field  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

First VCD  

command  

ST25DV  

reply  

GPO/FIELD_CHANGE (OD)  

2) RF field disappears and ST25DV is powered through VCC. GPO/FIELD_CHANGE generates a  

pulse during IT_TIME.  

RF field  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

ST25DV  

reply  

VCD  

command  

GPO/FIELD_CHANGE (OD)  

3) RF field disappears and ST25DV is not powered through VCC. GPO/FIELD_CHANGE doesn’t  

generates any pulse.  

RF field  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

ST25DV  

reply  

VCD  

command  

GPO/FIELD_CHANGE (OD)  

DS10925

–

Rev 9  

page 31/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

RF_PUT_MSG:  

•

•

A pulse is emitted on GPO when a message is successfully written by RF in fast transfer mode mailbox.  

When RF_PUT_MSG is activated, a pulse of duration IT_TIME is emitted on GPO at completion of valid  

Write Message or Fast Write Message commands (after EOF of ST25DV response).  

Figure 16.

RF_PUT_MSG chronogram  

1) VCD sends a Write Message or Fast Write Message command and ST25DV replies with no error.  

GPO/RF_PUT_MSG generates a pulse during IT_TIME after ST25DV response.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

ST25DV  

reply  

Write Msg  

command  

GPO/RF_PUT_MSG (OD)  

2) VCD sends a Write Message or Fast Write Message command and ST25DV replies with error.  

GPO/RF_PUT_MSG remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

ST25DV  

reply  

Write Msg  

command  

GPO/RF_PUT_MSG (OD)  

3) VCD sends Write Message or Fast Write Message command and ST25DV stays quiet (command  

not for this VICC, or quiet state). GPO/RF_PUT_MSG stays high-Z.  

S

O

F

E

O

F

Write Msg  

Command  

GPO/RF_PUT_MSG (OD)  

4) VCD sends a any other command than Write Message or Fast Write Message commands and  

ST25DV replies. GPO/RF_PUT_MSG remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

Any other  

command  

ST25DV  

reply  

GPO/RF_PUT_MSG (OD)  

DS10925

–

Rev 9  

page 32/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

RF_GET_MSG:  

•

•

A pulse is emitted on GPO when RF has successfully read a message, up to its last byte, in fast transfer  

mode mailbox.  

When RF_GET_MSG is activated, a pulse of duration IT_TIME is emitted on GPO at completion of valid  

Read Message or Fast Read Message commands (after EOF of ST25DV response), and end of message  

has been reached.  

Figure 17.

RF_GET_MSG chronogram  

1) VCD sends a Read Message or Fast Read Message command and ST25DV replies with no error.  

GPO/RF_GET_MSG generates a pulse during IT_TIME after ST25DV response.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

Read Msg  

command  

ST25DV  

reply  

GPO/RF_GET_MSG (OD)  

2) VCD sends a Read Message or Fast Read Message command and ST25DV replies with error.  

GPO/RF_GET_MSG remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

Read Msg  

command  

ST25DV  

reply  

GPO/RF_GET_MSG (OD)  

3) VCD sends Read Message or Fast Read Message command and ST25DV stays quiet (command  

not for this VICC, or quiet state). GPO/RF_GET_MSG stays high-Z.  

S

O

F

E

O

F

Read Msg  

Command  

GPO/RF_GET_MSG (OD)  

4) VCD sends any other command than Read Message or Fast Read Message commands and  

ST25DV replies. GPO/RF_GET_MSG remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t1  

ST25DV  

reply  

Any other  

command  

GPO/RF_GET_MSG (OD)  

DS10925

–

Rev 9  

page 33/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

RF_WRITE:  

•

•

When RF_WRITE is activated, a pulse of duration IT_TIME is emitted at completion of a valid RF write  

operation in EEPROM (after EOF of ST25DV response).  

Following commands trigger the RF_WRITE interrupt after a valid write operation in EEPROM:  

–

–

–

–

–

–

–

–

–

–

–

–

Write Single Block  

Extended Write Single Block  

Write Multiple Block  

Extended Write Multiple Block  

Lock Block  

Extended Lock Block  

Write AFI  

Lock AFI  

Write DSFID  

Lock DSFID  

Write Configuration  

Write Password  

•

Note that writing in dynamic registers or fast transfer mode mailbox does not trigger RF_WRITE interrupt (no  

write operation in EEPROM).  

Figure 18.

RF_WRITE chronogram  

1) VCD sends a write command and ST25DV replies after write completed. GPO/RF_WRITE  

generates a pulse during IT_TIME after ST25DV response.  

S

O

F

E

O

F

S

O

F

E

O

F

(m*)W

t  

ST25DV  

reply  

Write  

command  

GPO/RF_WRITE (OD)  

2) VCD sends a write command with option flag set to 1, and ST25DV replies after receiving EO

F

.  

GPO/RF_WRITE generates a pulse during IT_TIME after ST25DV response.  

E

O

F

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

>(m*)W

t  

ST25DV  

reply  

Write  

command  

GPO/RF_WRITE (OD)  

3) VCD sends a write command and ST25DV replies with error. GPO/RF_WRITE remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

Write  

command  

ST25DV  

reply  

GPO/RF_WRITE (OD)  

4) VCD sends any other command than a write command. GPO/RF_WRITE remains high-Z.  

S

O

F

E

O

F

S

O

F

E

O

F

t

1  

ST25DV  

reply  

Any other  

command  

GPO/RF_WRITE (OD)  

5) VCD sends any command and ST25DV stays quiet (command not for this VICC, or quiet state).  

RF_ACTIVITY remains high-Z.  

S

O

F

E

O

F

VCD  

Command  

GPO/RF_WRITE (OD)  

DS10925

–

Rev 9  

page 34/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

5.2.2  

GPO and power supply  

When at the same time RF field is present and V

CC

is ON, GPO is acting as configured in GPO, GPO_CTRL_Dyn  

and IT_TIME registers.  

When the RF field disappears, the GPO state is reset and the output level is set to high-Z (open drain) or tied low  

(CMOS). Interruption status in IT_STS_Dyn register is maintained until next I

2

C read or V

CC

power off.  

Table 23.

GPO interrupt capabilities in function of RF field  

RF field on  

RF field off  

GPO state is function of RF events

GPO remains High-Z (OD) or tied low (CMOS)  

1. If

 

pull-up resistor is powered (Open Drain-IE version), and V  

is powered (CMOS –JF version).  

DCG  

When V

CC

is not present, or ST25DVxxx is in low power mode, all events are available on GPO pin, assuming  

pull-up resistor is supplied with correct voltage (Open Drain-IE version) or V

DCG

is powered (CMOS-JF version).  

The host can be waken up using GPO interrupt in any power condition.  

The exception is FIELD_CHANGE when RF field is falling, which can’t be reported on GPO output if V

CC

is off or  

in low power mode (no power supply on ST25DVxxx).  

Table 24.

GPO interrupt capabilities in function of V

CC

power supply  

V

CC  

ON and LPD high

ON and LPD low

V

OFF  

V

GPO events  

CC  

CC  

(low power mode)  

GPO remains High-Z (OD)  

or tied low (CMOS)  

GPO remains High-Z (OD) or tied  

low (CMOS)

FIELD_CHANGE if RF field  

disappears  

Pulse emitted on GPO  

GPO state is function of RF  

events

GPO state is function of  

RF events

GPO state is function of RF events

Any other activated RF event  

1. For

 

STM25DVxxK-JF only.  

2. If

 

pull-up resistor is powered (Open Drain-IE version) and V  

is powered (CMOS-JF version).  

DCG  

DS10925

–

Rev 9  

page 35/200  

ST25DV04K ST25DV16K ST25DV64K  

GPO  

5.2.3  

GPO registers  

Four registers are dedicated to this feature:  

•

•

Two static registers in system configuration  

Two dynamic registers  

Table 25.

GPO access  

RF  

I2C  

Command  

Type  

Address  

Type  

R always, W if RF configuration security  

session is open and configuration not  

locked  

Read Configuration (cmd code A0h) @00h  

Write Configuration (cmd code A1h) @00h  

2

R always, W if I

 

C security  

session is open  

E2=1, 0000h  

Table 26.

GPO  

Function  

Bit  

Name  

Factory Value  

0: disabled  

b0  

RF_USER_EN  

0b  

1: GPO output level is controlled by Manage GPO Command (set/reset)  

0: disabled  

b1  

b2  

b3  

RF_ACTIVITY_EN  

RF_INTERRUPT_EN  

FIELD_CHANGE_EN  

0b  

0b  

1b  

1: GPO output level changes from RF command EOF to response EO

F

.  

0: disabled  

1: GPO output level is controlled by Manage GPO Command (pulse).  

0: disabled  

1: A pulse is emitted on GPO, when RF field appears or disappears.  

0: disabled  

b4  

b5  

RF_PUT_MSG_EN  

RF_GET_MSG_EN  

0b  

0b  

1: A pulse is emitted on GPO at completion of valid RF Write Message  

command.  

0: disabled  

1: A pulse is emitted on GPO at completion of valid RF Read Message  

command if end of message has been reached.  

0: disabled  

b6  

b7  

RF_WRITE_EN  

GPO_EN  

0b  

1b  

1: A pulse is emitted on GPO at completion of valid RF write operation in  

EEPROM.  

0: GPO output is disabled. GPO is High-Z (open drain) or 0 (CMOS)  

1: GPO output is enabled. GPO outputs enabled interrupts.  

Note:  

Refer to

for the GPO register.  

•

•

•

Enables the interruption source, and enable GPO output.  

Several interruption sources can be enabled simultaneously.  

The updated value is valid for the next command (except for the RF_WRITE interrupt, which is valid right  

after EOF of the Write Configuration command if enabled through RF).  

•

•

The GPO_EN bit (b7) allows to disable GPO output (High-Z for open drain version, driven low for CMOS  

version). Interruptions are still reported in IT_STS_Dyn register.  

RF configuration security session (present RF password 0) or I

2

C security session (present I

2

C password)  

must be open in order to write the GPO register.  

DS10925

–

Rev 9  

page 36/200