STMicroelectronics-ST25R3912-AQFT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . 76

ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

. . . . . . . . . . . . . . . . . . . . . . . . 78

Stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

1.3.10 Auxiliary

definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

1.3.11 Receiver

configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.3.12 Receiver

configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.3.13 Receiver

configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

1.3.14 Receiver

configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

1.3.15 Mask

receive timer register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

1.3.16 No-response

timer register 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

1.3.17 No-response

timer register 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

1.3.18 General

purpose and no-response timer control register

. . . . . . . . . . . 86

1.3.19 General

purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.3.20 General

purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

1.3.21 Mask

main interrupt register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1.3.22 Mask

timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1.3.23 Mask

error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . 89

1.3.24 Main

interrupt register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

1.3.25 Timer

and NFC interrupt register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.3.26 Error

and wake-up interrupt register

. . . . . . . . . . . . . . . . . . . . . . . . . . . 91

1.3.27 FIFO

status register 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

1.3.28 FIFO

status register 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

1.3.29 Collision

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

1.3.30 Number

of transmitted bytes register 1

. . . . . . . . . . . . . . . . . . . . . . . . . 93

1.3.31 Number

of transmitted bytes register 2

. . . . . . . . . . . . . . . . . . . . . . . . . 94

1.3.32 NFCIP

Bit Rate Detection Display register

. . . . . . . . . . . . . . . . . . . . . . 94

1.3.33 A/D

converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

1.3.34 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

DS11794 Rev 7

3/130

Contents

ST25R3912

1.3.35 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

1.3.36 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

1.3.37 AM

modulation depth control register

. . . . . . . . . . . . . . . . . . . . . . . . . . 97

1.3.38 AM

modulation depth display register

. . . . . . . . . . . . . . . . . . . . . . . . . . 97

1.3.39 RFO

AM modulated level definition register

. . . . . . . . . . . . . . . . . . . . . 98

1.3.40 RFO

normal level definition register

. . . . . . . . . . . . . . . . . . . . . . . . . . . 98

1.3.41 External

field detector threshold register

. . . . . . . . . . . . . . . . . . . . . . . . 99

1.3.42 Regulator

voltage control register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

1.3.43 Regulator

and timer display register

. . . . . . . . . . . . . . . . . . . . . . . . . . 101

1.3.44 RSSI

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

1.3.45 Gain

reduction state register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

1.3.46 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

1.3.47 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

1.3.48 Auxiliary

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

1.3.49 Wake-up

timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

1.3.50 Amplitude

measurement configuration register

. . . . . . . . . . . . . . . . . . 106

1.3.51 Amplitude

measurement reference register . . . . . . . . . . . . . . . . . . . . . 106

1.3.52 Amplitude

measurement auto-averaging display register

. . . . . . . . . . 107

1.3.53 Amplitude

measurement display register . . . . . . . . . . . . . . . . . . . . . . . 107

1.3.54 Phase

measurement configuration register . . . . . . . . . . . . . . . . . . . . . 108

1.3.55 Phase

measurement reference register

. . . . . . . . . . . . . . . . . . . . . . . 108

1.3.56 Phase

measurement auto-averaging display register

. . . . . . . . . . . . . 109

1.3.57 Phase

measurement display register

. . . . . . . . . . . . . . . . . . . . . . . . . 109

1.3.58 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

1.3.59 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

1.3.60 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

111

1.3.61 Reserved

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

111

1.3.62 IC

Identity register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Electrical characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.1

3.2

3.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Operating conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

DC/AC characteristics for digital inputs and outputs

. . . . . . . . . . . . . . . .117

3.3.1

3.3.2

CMOS inputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

CMOS outputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4/130

DS11794 Rev 7

ST25R3912

Contents

3.4

3.5

Electrical specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Typical operating characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

3.5.1

Thermal resistance and maximum power dissipation

. . . . . . . . . . . . . 120

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.1

4.2

4.3

QFN32 package information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

121

VFQFPN32 package information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

123

WLCSP30 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

125

Ordering information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Revision history

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

DS11794 Rev 7

5/130

List of tables

ST25R3912

List of tables

First and third stage zero setting

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Low pass contro

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver filter selection and gain range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Recommended blocking capacitor values

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Serial data interface (4-wire interface) signal lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SPI operation modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

IRQ output

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Timing parameters of NFC Field ON commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Analog test and observation register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Test access register – Tana signal selection of TO1 and TO2 pins . . . . . . . . . . . . . . . . . . 48

FeliCa™ frame format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Operation mode/bit rate setting for NFCIP-1 passive communication . . . . . . . . . . . . . . . . 55

Operation mode/bit rate setting for NFCIP-1 active communication initiator

. . . . . . . . . . . 57

Setting mod bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

IO Configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Initiator operation modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Target Operation Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Bit rate codin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

ISO14443A modulation pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Minimum TR1 codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Stream Mode Definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Sub-carrier frequency definition for Sub-Carrier and BPSK stream mode . . . . . . . . . . . . . 79

Definition of time period for Stream mode Tx modulator control. . . . . . . . . . . . . . . . . . . . . 79

Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Mask receive timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

No-response timer register 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

No-response timer register 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

General purpose and no-response timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Timer trigger sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

General purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

General purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6/130

DS11794 Rev 7

ST25R3912

List of tables

Mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Main interrupt registe

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

FIFO status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

FIFO status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Collision display registe

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Number of transmitted bytes register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Number of transmitted bytes register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

NFCIP Bit Rate Detection Display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

A/D converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

AM modulation depth control registe

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AM modulation depth display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

RFO AM modulated level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

RFO normal level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Peer detection threshold as seen on RFI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Collision avoidance threshold as seen on RFI1 inpu

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Regulator voltage control registe

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Regulator and timer display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Regulated voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Gain reduction state register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Auxiliary display registe

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Typical wake-up time

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Amplitude measurement configuration register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Amplitude measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Amplitude measurement auto-averaging display register. . . . . . . . . . . . . . . . . . . . . . . . . 107

Amplitude measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Phase measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Phase measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Phase measurement auto-averaging display register

. . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

IC Identity register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

ST25R3912 pin definitions – QFN32, VFQFPN32 and WLCSP packages . . . . . . . . . . . . 114

Electrical parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Temperature ranges and storage conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Operating condition

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS inputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 100.

CMOS outputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

DS11794 Rev 7

7/130

List of tables

ST25R3912

Table 101.

Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 102.

QFN32 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 103.

VFQFPN32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 104.

WLCSP30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 105.

Table 106.

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 107.

Document revision history

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8/130

DS11794 Rev 7

ST25R3912

List of figures

ST25R3912 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Minimum configuration with single sided antenna driving (including EMC filter)

. . . . . . . . 13

Minimum configuration with differential antenna driving (including EMC filter). . . . . . . . . . 14

Receiver block diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Phase detector inputs and output in case of 90º phase shift . . . . . . . . . . . . . . . . . . . . . . . 26

Phase detector inputs and output in case of 135º phase shift . . . . . . . . . . . . . . . . . . . . . . 26

ST25R3912 power supply

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Exchange of signals with microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SPI communication: writing a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 10.

SPI communication: writing multiple bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11.

SPI communication: reading a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12.

SPI communication: loading of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13.

SPI communication: reading of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14.

SPI communication: direct command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 15.

SPI communication: direct command chainin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 16.

SPI general timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17.

SPI read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 18.

Direct command NFC Initial Field ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19.

Direct command NFC Response Field O

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 20.

ISO14443A states for PCD and PICC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21.

Selection of MRT and NRT for a given FDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22.

Flowchart for ISO14443A anticollision with ST25R3912

. . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 23.

Transport frame format according to NFCIP-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 24.

Example of sub-carrier stream mode for scf = 01b and scp = 10b . . . . . . . . . . . . . . . . . . . 66

Figure 25.

Example of Tx in Stream Mode for stx = 000b and OOK modulatio

. . . . . . . . . . . . . . . . .

ST25R3912 QFN32 and VFQFPN32 pinouts

Figure 26.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 27.

ST25R3912 WLCSP top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 28.

TCASE vs. power dissipation for different copper areas at Tamb = 25 °C

. . . . . . . . . . . 120

Figure 29.

RthCA vs. copper area

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 30.

QFN32 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 31.

VFQFPN32 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 32.

Figure 33.

WLCSP30 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 34.

DS11794 Rev 7

9/130

Functional overview

ST25R3912

Functional overview

The ST25R3912 is suitable for a wide range of applications, among them



Gaming

Access control

NFC infrastructure

Ticketing

1.1

Block diagram

The block diagram is shown in

Figure 1

Figure 1. ST25R3912 block diagram

VDD_IO

XTO XTI

VDD

POR

and

bias

XTAL

oscillator

Regulators

Logic

RFO1

RFO2

Transmitter

FIFO

SPI

Phase and

amplitude

detector

A/D

converter

Control

logic

Level

shifters

IRQ

MCU_CLK

SPI

RFI1

RFI2

Receiver

TRIMx

Framing

External

field

detector

oscillator

Wake-up

timer

ST25R3912

MS42439V

1.1.1

Transmitter

The transmitter incorporates drivers that drive external antenna through pins RFO1 and

RFO2. Single sided and differential driving is possible. The transmitter block additionally

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DS11794 Rev 7

ST25R3912

Functional overview

contains a sub-block that modulates transmitted signal (OOK or configurable AM

modulation).

The ST25R3912 transmitter is intended to directly drive antennas (without 50

Ω

cable,

usually antenna is on the same PCB). Operation with 50

Ω

cable is also possible, but in that

case some of the advanced features are not available.

By applying FFh to register 27h, the output drivers are in tristate.

1.1.2

1.1.3

Receiver

The receiver detects transponder modulation superimposed on the 13.56 MHz carrier

signal. The receiver contains two receive chains (one for AM and another for PM

demodulation) composed of a peak detector followed by two gain and filtering stages and a

final digitizer stage. The filter characteristics are adjusted to optimize performance for each

mode and bit rate (sub-carrier frequencies from 212 kHz to 6.8 MHz are supported). The

receiver chain inputs are the RFI1 and RFI2 pins. The receiver chain incorporates several

features that enable reliable operation in challenging phase and noise conditions.

Phase and amplitude detector

The phase detector is observing the phase difference between the transmitter output signals

(RFO1 and RFO2) and the receiver input signals (RFI1 and RFI2). The amplitude detector is

observing the amplitude of the receiver input signals (RFI1 and RFI2) via self-mixing. The

amplitude of the receiver input signals (RFI1 and RFI2) is directly proportional to the

amplitude of the antenna LC tank signal.

The phase detector and the amplitude detector can be used for the following purposes:



PM demodulation, by observing RFI1 and RFI2 phase variation

average phase difference between RFOx pins and RFIx pins is used for inductive

phase wakeup via the MCU



amplitude of signal present on RFI1 and RFI2 pins is used for inductive amplitude

wakeup

1.1.4

1.1.5

A/D converter

The ST25R3912 contains a built in Analog to Digital (A/D) converter. Its input can be

multiplexed from different sources and is used in several applications, such as

measurement of RF amplitude and phase, or calibration of modulation depth. The result of

the A/D conversion is stored in the

and can be read via SPI.

External field detector

The External field detector is a low power blockused in NFC mode to detect the presence of

an external RF field. It supports two different detection thresholds, Peer Detection Threshold

and Collision Avoidance Threshold. The Peer Detection Threshold is used in the NFCIP-1

target mode to detect the presence of an initiator field, and is also used in active

communication initiator mode to detect the activation of the target field. The Collision

Avoidance Threshold is used to detect the presence of an RF field during the NFCIP-1 RF

Collision Avoidance procedure.

DS11794 Rev 7

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Functional overview

ST25R3912

1.1.6

Quartz crystal oscillator

The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. At start-up

the transconductance of the oscillator is increased to achieve a fast start-up. The start-up

time varies with crystal type, temperature and other parameters, hence the oscillator

amplitude is observed and an interrupt is sent when stable oscillator operation is reached.

The oscillator block also provides a clock signal to the external microcontroller (MCU_CLK),

according to the settings in the

Regulator and timer display register

1.1.7

Power supply regulators

Integrated power supply regulators ensure a high power supply rejection ratio for the

complete reader system. If the reader system PSRR has to be improved, the command

Adjust Regulators is sent. As a result of this command, the power supply level of V

measured in maximum load conditions and the regulated voltage reference is set 250 mV

below this measured level to assure a stable regulated supply. The resulting regulated

voltage is stored in the

. It is also possible to define

regulated voltage by writing to the

ecouple any noise

sources from different parts of the IC there are three regulators integrated with separated

external blocking capacitors (the regulated voltage of all of them is the same in 3.3 V supply

mode). One regulator is for the analog blocks, one for the digital blocks, and one for the

antenna drivers.

This block additionally generates a reference voltage for the analog processing



(AGD – analog ground). This voltage also has an associated external buffer capacitor.

1.1.8

1.1.9

1.1.10

POR and bias

This block provides the bias current and the reference voltages to all other blocks. It also

incorporates a power on reset (POR) circuit that provides a reset at power-up and at low

supply voltage levels.

RC oscillator and wake-up timer

The ST25R3912 includes several possibilities of low power detection of card presence

(phase measurement, amplitude measurement). The RC oscillator and the register

configurable wake-up timer are used to schedule the periodic card presence detection.

ISO-14443 and NFCIP-1 framing

This block performs framing for receive and transmit according to the selected ISO mode

and bit rate settings.

In reception it takes the demodulated sub-carrier signal from the receiver. It recognizes the

OF and data bits, performs parity and CRC check, organizes the received data in

bytes and places them in the FIFO.

During transmit, it operates inversely, it takes bytes from the FIFO, generates parity and

CRC bits, adds SOF and EOF and performs final encoding before passing the modulation

signal to the transmitter.

In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal

(the receiver output), is directly sent to the MISO pin, and the signal applied to the MOSI pin

is directly used to modulate the transmitter.

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DS11794 Rev 7

ST25R3912

Functional overview

1.1.11

FIFO

The ST25R3912 contains a 96-byte FIFO. Depending on the mode, it contains either data

that has been received or data to be transmitted.

1.1.12

1.1.13

Control logic

The control logic contains I/O registers that define operation of device.

SPI

A 4-wire serial peripheral interface (SPI) is used for communication between the external

microcontroller and the ST25R3912.

1.2

Application information

The minimum configurations required to operate the ST25R3912 are shown in

Figure 2

and

Figure 3

Figure 2. Minimum configuration with single sided antenna driving (including EMC filter)

1.65 to 5.5 V

2.4 to 5.5 V

VDD_IO

VDD

AGD

/SS

MISO

VSS

MOSI

SCLK

IRQ

MCU

VSP_A

VSN_A

VSP_D

MCU_CLK

XTI

VSN_D

XTO

VSP_RF

Antenna

coil

VSN_RF

RF01

RF02

RFI1

RFI2

ST25R3912

MS42436V2

DS11794 Rev 7

13/130

Functional overview

ST25R3912

Figure 3. Minimum configuration with differential antenna driving (including EMC filter)

1.65 to 5.5 V

2.4 to 5.5 V

VDD_IO

VDD

AGD

/SS

MISO

VSS

MOSI

SCLK

IRQ

MCU

VSP_A

VSN_A

VSP_D

MCU_CLK

XTI

VSN_D

XTO

VSP_RF

Antenna

coil

VSN_RF

RF01

RF02

RFI1

RFI2

ST25R3912

MS42437V2

1.2.1

Operating modes

The ST25R3912 operating mode is defined by the contents of the

Operation control

At power-up all bits of the

are set to 0, the ST25R3912 is in

Power-down mode. In this mode AFE static power consumption is minimized, only the POR

and part of the bias are active, while the regulators are transparent and are not operating.

The SPI is still functional in this mode so all settings of ISO mode definition and

configuration registers can be done.

Control bit en (bit 7 of the

) is controlling the quartz crystal

oscillator and regulators. When this bit is set, the device enters in Ready mode. In this mode

the quartz crystal oscillator and regulators are enabled. An interrupt is sent to inform the

microcontroller when the oscillator frequency is stable.

Enable of receiver and transmitter are separated so it is possible to operate one without

switching on the other (control bits rx_en and tx_en). In some cases this may be useful, if

the reader field has to be maintained and there is no transponder response expected, the

receiver can be switched-off to save current. Another example is the NFCIP-1 active

communication receive mode in which the RF field is generated by the initiator and only the

receiver operates.

Asserting the

bit wu while the other bits are set to 0 puts the

ST25R3912 into the Wake-Up mode that is used to perform low power detection of card

presence. In this mode the low power RC oscillator and register configurable Wake-Up timer

14/130

DS11794 Rev 7

ST25R3912

Functional overview

are used to schedule periodic measurement(s). When a difference of the measured value

vs. the predefined reference is detected an interrupt is sent to wake-up the microcontroller.

1.2.2

Transmitter

The transmitter contains two identical push-pull driver blocks connected to the pins RFO1

and RFO2. These drivers are differentially driving the external antenna LC tank. It is also

possible to operate only one of the two drivers by setting the

level definition register

bit

single to 1. Each driver is composed of eight segments having binary weighted output

resistance. The MSB segment typical ON resistance is 2

Ω

, when all segments are turned

on; the output resistance is typically 1

Ω

. All segments are turned on to define the normal

transmission (non-modulated) level. It is also possible to switch off certain segments when

driving the non-modulated level to reduce the amplitude of the signal on the antenna and/or

to reduce the antenna Q factor without making any hardware changes. The

RFO normal

defines which segments are turned on to define the normal

transmission (non-modulated) level. Default setting is that all segments are turned on.

Using the single driver mode the number of the antenna LC tank components (and therefore

the cost) is halved, but also the output power is reduced. In single mode it is possible to

connect two antenna LC tanks to the two RFO outputs and multiplex between them by

controlling the

bit rfo2.

In order to transmit the data the transmitter output level needs to be modulated. Both AM

and OOK modulation are supported. The type of modulation is defined by setting the bit

tr_am in the

During the OOK modulation (for example ISO14443A) the transmitter drivers stop driving

the carrier frequency. As consequence the amplitude of the antenna LC tank oscillation

decays, the time constant of the decay is defined with the LC tank Q factor. The decay time

in case of OOK modulation can be shortened by asserting the

bit

ook_hr. When this bit is set to logic one the drivers are put in tristate during the OOK

modulation.

AM modulation (for example ISO14443B) is done by increasing the output driver impedance

during the modulation time. This is done by reducing the number of driver segments that are

turned on. The AM modulated level can be automatically adjusted to the target modulation

depth by defining the target modulation depth in the

modulation depth: definition and calibration

and sending the Calibrate Modulation Depth direct command. Refer to

Section 1.2.19: AM

for further details.

Slow transmitter ramping

When the transmitter is enabled it starts to drive the antenna LC tank with full power, the

ramping of the field emitted by antenna is defined by antenna LC tank Q factor.

However there are some reader systems where the reader field has to ramp up with a

longer transition time when it is enabled. The STIF (Syndicat des transports d’Ile de France)

specification requires a transition time from 10% to 90% of field longer than or equal to

s.The ST25R3912 supports that feature. It is realized by collapsing VSP_RF regulated

voltage when transmitter is disabled and ramping it when transmitter is enabled. Typical

transition time is 15

s at 3 V supply and 20

s at 5 V supply.

DS11794 Rev 7

15/130

Functional overview

ST25R3912

Procedure to implement the slow transition:

1. When

transmitter is disabled set

bit slow_up to 1. Keep this

state for at least 2 ms to allow discharge of VSP_R

2. Enable

transmitter, its output will ramp slowly.

3. Before

sending any command set the bit slow_up back to 0.

1.2.3

Receiver

The receiver performs demodulation of the transponder sub-carrier modulation that is

superimposed on the 13.56 MHz carrier frequency. It performs AM and/or PM demodulation,

amplification, band-pass filtering and digitalization of sub-carrier signals. Additionally it

performs RSSI measurement, automatic gain control (AGC) and Squelch.

In typical applications the receiver inputs RFI1 and RFI2 are outputs of capacitor dividers

connected directly to the terminals of the antenna coil. This concept ensures that the two

input signals are in phase with the voltage on the antenna coil. The design of the capacitive

divider must ensure that the RFI1 and RFI2 input signal peak values do not exceed the

supply voltage level.

SP_A

The receiver comprises two complete receive channels, one for the AM demodulation and

another one for the PM demodulation. In case both channels are active the selection of the

channel used for reception framing is done automatically by the receive framing logic. The

receiver is switched on when

bit rx_en is set to one. Additionally

the

Receiver configuration register 1

contains bits rx_chn and rx_man; rx_chn defines whether

both, AM and PM, demodulation channels will be active or only one of them, while bit

rx_man defines the channel selection mode in case both channels are active (automatic or

manual). Operation of the receiver is controlled by four receiver configuration registers.

The operation of the receiver is additionally controlled by the signal rx_on that is set high

when a modulated signal is expected on the receiver input. This signal is used to control

RSSI and AGC and also enables processing of the receiver output by the framing logic.

Signal rx_on is automatically set to high after the Mask Receive Timer expires. Signal rx_on

can also be directly controlled by the controller by sending direct commands Mask Receive

Data and Unmask Receive Data.

Figure 4

details the receiver block diagram.

16/130

DS11794 Rev 7

ST25R3912

Functional overview

Figure 4. Receiver block diagram

rec1<7:6>

Demodulator

Mixer

rec2<6:5>

rec4<7:4>

rec3<7:5>

rec3<4:2>

AGC

Squelch

RSSI

RSSI_AM<3:0>

RF_IN1

RF_IN2

Peak detector

Digital sub-carrier

RX_on

sg_on

rec4<3:0>

AGC

Squelch

RSSI

RSSI_PM<3:0>

Demodulator

Mixer

Digital sub-carrier

rec3<2:0>

rec1<5:3>

Low-pass

Demodulation

stage

AC coupling

High-pass

Digitizing

stage

+ 1

gain stage

+ 2

gain stage

+ 3

gain stage

MS42452V1

Demodulation stage

The first stage performs demodulation of the transponder sub-carrier signal, superimposed

on the HF field carrier. Two different blocks are implemented for AM demodulation:



Peak detector

AM demodulator mixer.

The choice of the used demodulator is made by the

bit

amd_sel.

The peak detector performs AM demodulation using a peak follower. Both the positive and

negative peaks are tracked to suppress any common mode signal. The peak detector is

limited in speed; it can operate for sub-carrier frequencies up to fc / 16 (848 kHz). Its

demodulation gain is G = 0.7. Its input is taken from one demodulator input only (usually

RFI1).

The AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and

RFI2). Its gain is G = 0.55.

PM demodulation is also done by a mixer. The PM demodulator mixer has differential

outputs with 60 mV differential signal for 1% phase change (16.67 mV / °). Its operation is

optimized for sub-carrier frequencies up to fc / 16 (848 kHz).

In case the demodulation is done externally, it is possible to multiplex the LF signals applied

to pins RFI1 and RFI2 directly to the gain and filtering stage by selecting the

configuration register 2

bit lf_en.

Filtering and gain stages

The receiver chain has band pass filtering characteristics. Filtering is optimized to pass



sub-carrier frequencies while rejecting carrier frequency and low frequency noise and DC

DS11794 Rev 7

17/130

Functional overview

ST25R3912

component. Filtering and gain is implemented in three stages, where the first and the last

stage have first order high pass characteristics, and the second stage has second order low

pass characteristic.

Gain and filtering characteristics can be optimized by writing the

Receiver configuration

(filtering), the

(gain in first stage) and the

(gain in second and third stage).

The gain of the first stage is about 20 dB and can be reduced in six 2.5 dB steps. There is

also a special boost mode available, which boosts the maximum gain by additional 5.5 dB.

The first stage gain can only be modified by writing

. The

default setting of this register is the minimum gain. The default first stage zero is set at 60

kHz, it can also be lowered to 40 kHz or to 12 kHz by writing option bits in the

. The control of the first and third stage zeros is done with common

control bits (see

ble 1

Table 1. First and third stage zero setting

rec1<2> h200

rec1<1> h80

rec1<0> z12k

First stage zero

Third stage zero

60 kHz

40 kHz

12 kHz

400 kHz

200 kHz

80 kHz

200 kHz

80 kHz

200 kHz

Others

Not used

The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. The

gain of these two stages is included in the AGC and Squelch loops. It can also be manually

set in

. Sending of direct command Reset Rx Gain is

necessary to reset the AGC, Squelch and RSSI block. Sending this command clears the

current Squelch setting and loads the gain reduction configuration from

configuration register 4

into the internal shadow registers of the AGC and Squelch block.

The second stage has a second order low pass filtering characteristic, the pass band is

adjusted according to the sub-carrier frequency using the bits lp2 to lp0 of the

See

Table 2

for -1 dB cut-off frequency for different settings.

Table 2. Low pass control

rec1<5> lp2

rec1<4> lp1

rec1<3> lp0

-1 dB point

1200 kHz

600 kHz

300 kHz

2 MHz

7 MHz

Others

Not used

18/130

DS11794 Rev 7

ST25R3912

Functional overview

ble 3

provides information on the recommended filter settings. For all supported operation

modes and receive bit rates there is an automatic preset defined, additionally some

alternatives are listed. Automatic preset is done by sending direct command Analog Preset.

There is no automatic preset for Stream and Transparent modes. Since the selection ofthe

filter characteristics also modifies gain, the gain range for different filter settings is also

listed.

Table 3. Receiver filter selection and gain range

Gain (dB)

Comments

Max

all

Min1 Max1

Max23 Min23

Min

all

With

boost

Automatic preset for ISO14443A fc / 128 and NFC

Forum Type 1

000

43.4

44.0

28.0

29.0

26.4

27.5

11.0

12.0

49.8

49.7

Automatic preset for ISO14443B fc / 128

ISO14443 fc / 64

001

000

100

44.3

41.1

32.0

27.0

23.6

17.2

11.7

8.3

49.8 Recommended

for 424/484 kHz sub-carrier

46.8 Alternative

choice for ISO14443 fc / 32 and fc / 16

37.6 Automatic

preset for ISO14443 fc / 32 and fc / 16

25.8

17.0

2.0

Automatic preset FeliCa

™

(fc / 64, fc / 32)

46.8

000

41.1

36.5

25.8

21.5

23.6

24.9

8.3

9.9

Alternative choice for ISO14443 fc / 32 and fc / 16

41.5 Automatic

preset for NFCIP-1 (initiator and target)

Digitizing stage

The digitizing stage produces a digital representation of the sub-carrier signal coming from

the receiver. This digital signal is then processed by the receiver framing logic. The digitizing

stage consists of a window comparator with adjustable digitizing window (five possible

settings, 3 dB steps, adjustment range from ±33 mV to ±120 mV). Adjustment of the

digitizing window is included in the AGC and Squelch loops. In addition, the digitizing

window can also be set manually in the

AGC, Squelch and RSSI

As mentioned above, the second and third gain stage gain and the digitizing stage window

are included in the AGC and Squelch loops. Eleven settings are available. The default state

features minimum digitizer window and maximum gain. The first four steps increase the

digitizer window in 3 dB steps, the next six steps additionally reduce the gain in the second

and third gain stage, again in 3 dB steps. The initial setting with whom Squelch and AGC

start is defined in

Gain reduction state register

. The

displays the actual state of gain that results from Squelch, AGC and initial settings in

Receiver configuration register 2

. During bit anticollision like Type A, the AGC should be

disabled.

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Functional overview

Squelch

ST25R3912

This feature is designed for operation of the receiver in noisy conditions. The noise can

come from tags (caused by the processing of reader commands), or it can come from a

noisy environment. This noise may be misinterpreted as start of transponder response,

resulting in decoding errors.

During execution of the Squelch procedure the output of the digitizing comparator is

observed. In case there are more than two transitions on this output in a 50

s time period,

the receiver gain is reduced by 3 dB, and the output is observed during the next 50

s. This

procedure is repeated until the number of transitions in 50

s is lower or equal to two, or

until the maximum gain reduction is reached. This gain reduction can be cleared sending

the direct command Reset Rx Gain.

There are two possibilities of performing squelch: automatic mode and using the direct

command Squelch.

1. Automatic

mode is enabled in case bit sqm_dyn in the

is set. It is activated automatically 18.88

s after end of Tx and is terminated when the

Mask Receive timer expires. This mode is primarily intended to suppress noise

generated by tag processing during the time when a tag response is not expected

(covered by Mask Receive timer).

2. Command

Squelch is accepted in case it is sent when signal rx_on is low. It can be

used when the time window in which noise is present is known by the controller.

AGC (automatic gain control)

AGC is used to reduce gain to keep the receiver chain out of saturation. With gain properly

adjusted the demodulation process is also less influenced by system noise.

AGC action starts when signal rx_on is asserted high and is reset when it is reset to low. At

the high to low transitions of the rx_on signal the state of the receiver gain is stored in the

Gain reduction state register

. Reading this register at a later stage gives information on the

gain setting used during last reception.

When AGC is switched on the receiver gain is reduced so that the input to the digitizer stage

is not saturated. The AGC system comprises a comparator with a window 3.5 times larger

than that of the digitizing window comparator. When the AGC function is enabled the gain is

reduced until there are no transitions on the output of its window comparator. This

procedure ensures that the input to the digitizing window comparator is less than 3.5 times

larger than its threshold.

AGC operation is controlled by the control bits agc_en, agc_m and agc_fast in the

configuration register 2

. Bit agc_en enables the AGC operation, bit agc_m defines the AGC

mode, and bit agc_alg defines the AGC algorithm.

Two AGC modes are available. The AGC can operate during the complete Rx process (as

long as signal rx_on is high), or it can be enabled only during the first eight sub-carrier

pulses.

Two AGC algorithms are available. The AGC can either start by presetting code 4h (max

digitizer window, max gain) or by resetting the code to 0h (min digitizer window, max gain).

The algorithm with preset code is faster, therefore it is recommended for protocols with short

SOF (like ISO14443A fc / 128).

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Default AGC settings are:



AGC is enabled

AGC operates during complete Rx process

algorithm with preset is used.

RSSI

The receiver also performs the RSSI (received signal strength indicator) measurement for

both channels. The RSSI measurement is started after the rising edge of rx_on. It stays

active as long as signal rx_on is high, it is frozen while rx_on is low. The RSSI is a peak hold

system, and the value can only increase from the initial zero value. Every time the AGC

reduces the gain the RSSI measurement is reset and starts from zero. Result of RSSI

measurements is a 4-bit value that can be observed by reading the

The LSB step is 2.8 dB, and the maximum code is Dh (13d).

Since the RSSI measurement is of peak hold type the RSSI measurement result does not

follow any variations in the signal strength (the highest value will be kept). In order to follow

RSSI variations it is possible to reset the RSSI bits and restart the measurement by sending

the direct command Clear RSSI.

Receiver in NFCIP-1 active communication mode

There are several features built into the receiver to enable reliable reception of active



NFCIP-1 communication. All these settings are automatically preset by sending the direct

command Analog Preset after the NFCIP-1 mode has been configured. In addition to the

filtering options, there are two NFCIP-1 active communication mode specific configuration

bits stored in the

Bit lim enables clipping circuits that are positioned after the first and second gain stages.

The function of the clipping circuits is to limit the signal level for the following filtering stage

(when the NFCIP-1 peer is close the input signal level can be quite high).

Bit rg_nfc forces gain reduction of second and third filtering stage to -6 dB while keeping the

digitizer comparator window at maximum level.

1.2.4

Wake-Up mode

Asserting the

RFO normal level definition

bit wu while the other bits are set to 0 puts the

ST25R3912 in Wake-Up mode, used to perform low power detection of card presence. The

ST25R3912 includes several possibilities of low power detection of a card presence ( phase

measurement, amplitude measurement). An integrated low power 32 kHz RC oscillator and

a register configurable Wake-Up timer are used to schedule periodic detection.

Usually the presence of a card is detected by a so-called polling loop. In this process the

reader field is periodically turned on and the controller checks whether a card is present

using RF commands. This procedure consumes a lot of energy since the reader field has to

be turned on for 5 ms before a command can be issued.

Low power detection of card presence is performed by detecting a change in the reader

environment, produced by a card. When a change is detected, an interrupt is sent to the

controller. As a result, the controller can perform a regular polling loop.

In the Wake-Up mode the ST25R3912 periodically performs the configured reader

environment measurements and sends an IRQ to the controller when a difference to the

configured reference value is detected.

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Functional overview

ST25R3912

Detection of card presence can be done by performing phase and amplitude

measurements.

Presence of a card close to the reader antenna coil produces a change of the antenna LC

tank signal phase and amplitude. The reader field activation time needed to perform the

phase or the amplitude measurement is extremely short (~20

s) compared to the activation

time needed to send a protocol activation command.

Additionally the power level during the measurement can be lower than the power level

during normal operation since the card does not have to be powered to produce a coupling

effect. The emitted power can be reduced by changing the

The registers on locations from 31h to 3Dh are dedicated to Wake-Up timer configuration

and display. The

Wake-up timer control register

is the main Wake-Up mode configuration

selected in this register. Timeouts in the range from 10 to 800 ms are available, 100 ms is

the default value. Any combination of available measurements can be selected (one, two or

all of them).

The next twelve registers (32h to 3Dh) are configuring the three possible detection

measurements and storing the results, four registers are used for each measurement.

An IRQ is sent when the difference between a measured value and the reference value is

larger than the configured threshold value. There are two possible definitions for the

reference value:

1. The

ST25R3912 can calculate the reference based on previous measurements



(auto-averaging)

2. The

controller determines the reference and stores it in a register

The first register in the series of four is the

Amplitude measurement configuration register

The difference to the reference value that triggers the IRQ, the method of reference value

definition and the weight of the last measurement result in case of auto-averaging are

defined in this register. The next register is storing the reference value in case the reference

is defined by the controller. The following two registers are display registers. The first one

stores the auto-averaging reference, and the second one stores the result of the last

measurement.

The Wake-Up mode configuration registers have to be configured before the Wake-Up

mode is entered. Any modification of the Wake-Up mode configuration while it is active may

result in unpredictable behavior.

Auto-averaging

In case of auto-averaging the reference value is recalculated after every measurement as

NewAverage = OldAverage + (MeasuredValue – OldAverage) / Weight

The calculation is done on 13 bits to have sufficient precision.The auto-averaging process is

initialized when the Wake-Up mode is entered for the first time after initialization (at power-

up or after Set Default command). The initial value is taken from the measurement display

registers (for example

Amplitude measurement display register

) until the content of this

Every Measurement Configuration register contains a bit that defines whether the

measurement that causes an interrupt is taken in account for the average value calculation

(for example bit am_aam of the

Amplitude measurement configuration register

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1.2.5

Quartz crystal oscillator

The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. The

operation of quartz crystal oscillator is enabled when the

Section 1.3.24: Main interrupt register

bit en is

set to one. An interrupt is sent to inform the microcontroller when the oscillator frequency is

stable (see

The status of oscillator can be observed by observing the

General purpose and no-response timer control register

bit

osc_ok. This bit is set to ‘1’ when oscillator frequency is stable.

The oscillator is based on an inverter stage supplied by a controlled current source. A

feedback loop is controlling the bias current in order to regulate amplitude on XTI pin to

1 V

nable a fast reader start-up an interrupt is sent when the oscillator amplitude exceeds

750 mV

Division by two ensures that 13.56 MHz signal has a duty cycle of 50%, which is better for

the transmitter performance (no PW distortion). Use of 27.12 MHz crystal is therefore

recommended for better performance.

In case of 13.56 MHz crystal, the bias current of stage that is digitizing oscillator signal is

increased to assure as low PW distortion as possible.

The oscillator output is also used to drive a clock signal output pin MCU_CLK) that can be

used by the external microcontroller. The MCU_CLK pin is configured in the

IO configuration

1.2.6

Timers

The ST25R3912 contains several timers that eliminate the need to run counters in the

controller, thus reducing the effort of the controller code implementation and improve

portability of code to different controllers.

Every timer has one or more associated configuration registers in which the timeout

duration and different operating modes are defined. These configuration registers have to

be set while the corresponding timer is not running. Any modification of timer configuration

while the timer is active may result in unpredictable behavior.

All timers except the Wake-Up timer are stopped by direct command Clear.

Note:

In case bit nrt_emv in the

is set to

one, the No-response timer is not stopped

Mask receive timer and No-response timer

Mask receive timer and No-response timer are both automatically started at the end of

transmission (at the end of EOF).

Mask receive timer

The Mask receive timer is blocking the receiver and reception process in framing logic by

keeping the rx_on signal low after the end of Tx during the time the tag reply is not

expected.

While the Mask Receive timer is running, the Squelch is automatically turned on (if

enabled). Mask Receive timer does not produce an IRQ.

The Mask Receive timer timeout is configured in the

Mask receive timer register

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Functional overview

ST25R3912

In the NFCIP-1 active communication mode the Mask Receive timer is started when the

peer NFC device (a device with whom communication is going on) switches on its field.

The Mask Receive timer has a special use in the low power Initial NFC

rget Mode. After

the initiator field has been detected the controller turns on the oscillator, regulator and

receiver. Mask Receive timer is started by sending direct command Start Mask Receive

Timer. After the Mask Receive Timer expires the receiver output starts to be observed to

detect start of the initiator message. In this mode the Mask Receive timer clock is

additionally divided by eight it (one count is 512/fc) to cover range up to about 9.6 ms.

No-response timer

As its name indicates, this timer is intended to observe whether a tag response is detected

in a configured time started by end of transmission. The I_nre flag in the

Timer and NFC

interrupt register

is signaling interrupt events resulting from this timer timeout.

The No-response timer is configured by writing the two registers

No-response timer register

and

No-response timer register 2

. Operation options of the No-response timer are defined

by setting bits nrt_emv and nrt_step in the

General purpose and no-response timer control

Bit nrt_step configures the time step of the No-response timer. Two steps are available,

64/fc (4.72

s) to cover range up to 309 ms, and 4096/fc, covering the range up to 19.8 s.

Bit nrt_emv controls the timer operation mode:



When this bit is set to 0 (default mode) the IRQ is produced in case the No-response

timer expires before a start of a tag reply is detected and rx_on is forced to low to stop

receiver process. In the opposite case, when start of a tag reply is detected before

timeout, the timer is stopped, and no IRQ is produced.

When this bit is set to 1 the timer unconditionally produces an IRQ when it expires, it is

also not stopped by direct command Clear. This means that IRQ is independent of the

fact whether or not a tag reply was detected. In case at the moment of timeout a tag

reply is being processed no other action is taken, in the opposite case, when no tag

response is being processed additionally the signal rx_on is forced to low to stop

receive process.

The No-response timer can also be started using direct command Start No-Response Timer.

The intention of this command is to extend the No-response timer timeout beyond the range

defined in the No-response timer control registers. In case this command is sent while the

timer is running, it is reset and restarted. In NFCIP-1 active communication mode the No-

response timer cannot be started using the direct command.

In case this timer expires before the peer NFC device (a device with whom communication

is going on) switches on its field an interrupt is sent.

In all modes, where timer is set to nonzero value, it is a must that M_txe is not set and

interrupt I_txe is read via SPI for synchronization between transmitter and timer.

General Purpose timer

The triggering of the General Purpose timer is configured by setting the

General purpose

and no-response timer control register

. It can be used to survey the duration of the reception

process (triggering by start of reception, after SOF) or to time out the PCD to PICC

response time (triggered by end of reception, after EOF). In the NFCIP-1 active

communication mode it is used to timeout the field switching off. In all cases an IRQ is sent

when it expires.

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Functional overview

The General Purpose timer can also be started by sending the direct command Start

General Purpose Timer. In case this command is sent while the timer is running, it is reset

and restarted.

Wake-Up timer

Wake timer is primarily used in the Wake-Up mode (see

Section 1.2.4: Wake-Up mode

Additionally it can be used by sending a direct command Start Wake-Up Timer. This

command is accepted in any operation mode except Wake-Up mode. When this command

is sent the RC oscillator used as clock source for Wake-Up timer is started, timeout is

defined by setting in the

Wake-up timer control register

. When the timer expires, an IRQ with

the I_wt flag in the

Error and wake-up interrupt register

is sent.

Wake-Up timer is useful in the Low Power operation mode, in which other timers cannot be

used (in the Low Power operation mode the crystal oscillator, which is clock source for the

other timers, is not running).

Note:

The tolerance of Wake-Up timer timeout is defined by tolerance of the RC oscillator.

1.2.7

A/D converter

The ST25R3912 contains an 8-bit successive approximation A/D converter, whose inputs

can be multiplexed from different sources to be used in several direct commands and

adjustment procedures. The result of the last A/D conversion is stored in the

A/D converter

output register

The A/D converter has two operating modes, absolute and relative.



In absolute mode the low reference is 0 V and the high reference is 2 V. This means

that A/D converter input range is from 0 to 2

0h code means input is 0 V or lower,

FFh means that input is 2 V – 1 LSB or higher (LSB is 7.8125 mV).



In relative mode low reference is 1/6 of V

and high reference is 5/6 of V

, so

SP_A

the input range is from 1/6 to 5/6 V

SP_A

Relative mode is only used in phase measurement (phase detector output is proportional to

power supply). In all other cases absolute mode is used.

1.2.8

Phase and amplitude detector

This block is used to provide input to A/D converter to perform measurements of amplitude

and phase, expected by direct commands Measure Amplitude and Measure Phase. Several

phase and amplitude measurements are also performed by direct commands Calibrate

Modulation Depth and Calibrate Antenna.

Phase detector

The phase detector is observing phase difference between the transmitter output signals

(RFO1 and RFO2) and the receiver input signals RFI1 and RFI2, which are proportional to

the signal on the antenna LC tank. These signals are first elaborated by digitizing

comparators, then digitized signals are processed by a phase detector with a strong low

pass filter to get average phase difference.

The phase detector output is inversely proportional to the phase difference between the two

inputs. The 90° phase shift results in V

/2 output voltage, in case both inputs are in

SP_A

phase output voltage is V

, in case they are in opposite phase output voltage is 0 V.

SP_A

During execution of direct command Measure Phase this output is multiplexed to A/D

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Functional overview

ST25R3912

converter input (A/D converter is in relative mode during execution of command Measure

Phase). Since the A/D converter range is from 1/6 to 5/6 V

range is from 30º to 150º.

the actual phase detector

SP_A

Figure 5

and

Figure 6

show the two inputs and the output of phase detector, respectively, in

case of 90º and 135º shifts.

Figure 5. Phase detector inputs and output in case of 90º phase shift

SP_A

Input 1

SP_A

Input 2

SP_A

Output

SP_A

MS42426V1

Figure 6. Phase detector inputs and output in case of 135º phase shift

SP_A

Input 1

SP_A

Input 2

SP_A

Output

SP_A

MS42427V1

Amplitude detector

Signals from pins RFI1 and RFI2 are used as inputs to the self-mixing stage. The output of

this stage is a DC voltage proportional to amplitude of signal on pins RFI1 and RFI2. During

execution of direct command Measure Amplitude this output is multiplexed to A/D converter

input.

1.2.9

External field detector

The External Field Detector is used to detect the presence of an external device generating

an RF field. It is automatically switched on in NFCIP-1 active communication modes; it can

also be used in other modes. The External field detector supports two different detection

thresholds, Peer Detection Threshold and Collision Avoidance Threshold. The two

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Functional overview

thresholds can be independently set by writing the

The actual state of the External field detector output can be checked by reading the

. Input to this block is the signal from the RFI1 pin.

Peer detection threshold

This threshold is used to detect the field emitted by peer NFC device with whom NFC

communication is going on (initiator field in case the ST25R3912 is the target and the

opposite, target field in case the ST25R3912 is the initiator). It can be selected in the range

from 75 to 800 mV

. When this threshold is enabled the External Field Detector is in low

power mode. An interrupt is generated when an external field is detected and also when it is

switched off. With such implementation it can also be used to detect the moment when the

external field disappears. This is useful to detect the moment when the peer NFC device (it

can be either an initiator or a target) has stopped emitting an RF field.

The External Field Detector is automatically enabled in the low power Peer Detection mode

when NFCIP-1 mode (initiator or target) is selected in the

Additionally it can be enabled by setting bit en_fd in the

Collision Avoidance threshold

This threshold is used during the RF Collision Avoidance sequence that is executed by

sending NFC Field ON commands (see

NFC Field ON commands

). It can be selected in the

range from 25 to 800 mV

1.2.10

Power supply system

The ST25R3912 (

Figure 7

) features two positive supply pins, VDD and VDD_IO.

VDD is the main power supply pin. It supplies the ST25R3912 blocks through three

regulators (VSP_A, VSP_D and VSP_RF).

range from 2.4 to 5.5 V is supported.

is used to define supply level for digital communication pins (/SS, MISO, MOSI,

DD_IO

SCLK, IRQ, MCU_CLK). Digital communication pins interface with ST25R3912 logic

through level shifters, therefore the internal supply voltage can be either higher or lower

than V

. V

range from 1.65 to 5.5 V is supported.

DD_IO

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Functional overview

ST25R3912

Figure 7. ST25R3912 power supply

VDD

sup3V

1 kΩ

VSP_D

REG

Power-down

support

VSP_A

REG

VSP_RF

REG

VSP_RF

50 Ω

VSP_A

VSP_D

BGR

and

AGC

AGD

RV<3:0>

AUTOREG

reg 2Ah

reg 2Bh

adjust

MS42462V1

Figure 7

shows the building blocks of the ST25R3912 power supply system and the signals

that control it.

The power supply system contains three regulators, a power-down support block, a block

generating analog reference voltage (AGD) and a block performing automatic power supply

adjustment procedure. The three regulators are providing supply to analog blocks (VSP_A),

logic (VSP_D) and transmitter (VSP_RF). The use of VSP_A and VSP_D regulators is

mandatory at 5 V power supply to provide regulated voltage to analog and logic blocks that

only use 3.3 V devices. The use of VSP_A and VSP_D regulators at 3 V supply and

VSP_RF regulator at any supply voltage is recommended to improve system PSRR.

Regulated voltage can be adjusted automatically to have maximum possible regulated

voltage while still having good PSRR. All regulator pins also have corresponding negative

supply pins that are externally connected to ground potential (V

). The reason for

separation is in decoupling of noise induced by voltage drops on the internal power supply

lines.

Figure 2

and

Figure 3

show typical ST25R3912 application schematics with all regulators

used. All regulator pins and AGD voltage are buffered with capacitors. Recommended

blocking capacitor values are detailed in

ble 4

Table 4. Recommended blocking capacitor values

Pins

Recommended capacitors

n parallel with 10 nF

AGD – VSS

VSP_A – VSN_A

VSP_D – VSN_D

2.2

n parallel with 10 nF

2.2

n parallel with 10 nF

VSP_RF – VSN_RF

2.2

n parallel with 10 nF

Regulators have two basic operation modes depending on supply voltage, 3.3 V supply

mode (max 3.6 V) and 5 V supply mode (max 5.5 V). The supply mode is set by writing bit

sup3 V in the

. Default setting is 5 V, hence this bit has to be set to

one after power-up in case of 3.3 V supply.

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In 3.3 V mode all regulators are set to the same regulated voltage in range from 2.4 V to

3.4

hile in 5 V only the V

can be set in range from 3.9 V to 5.1 V, while V

and

SP_RF

SP_A

are fixed to 3.4

SP_D

The regulators are operating when signal en is high (en is configuration bit in

Operation

. When signal en is low the ST25R3912 is in low power mode. In this mode

consumption of the power supply system is also minimized.

VSP_RF regulator

The intention of this regulator is to improve PSRR of the transmitter (the noise of the

transmitter power supply is emitted and fed back to the receiver). The VSP_RF regulator

operation is controlled and observed by writing and reading two regulator registers:



Regulator and timer display register

controls the regulator mode and regulated voltage.

Bit reg_s controls regulator mode. In case it is set to 0 (default state) the regulated

voltage is set using direct command Adjust Regulators. When bit reg_s is asserted to 1

regulated voltage is defined by bits rege_3 to rege_1 of the same register. The

regulated voltage adjustment range depends on the power supply mode. In case of 5 V

supply mode the adjustment range is between 3.9 and 5.1 V in steps of 120 mV, in

case of 3.3 V supply mode the adjustment range is from 2.4 to 3.4 V with steps of 100

. Default regulated voltage is the maximum one (5.1 V and 3.4 V, respectively, in

case of 5 V and 3.3 V supply mode).



is a read only register that displays actual

regulated voltage when regulator is operating. It is especially useful in case of

automatic mode, since the actual regulated voltage, which is the result of direct

command Adjust Regulators, can be observed.

The VSP_RF regulator also includes a current limiter that limits the regulator typically to

current of 200 mA

in normal operation (500 mA in case of short). In case the transmitter

rms

output current higher the 200 mA

is required, VSP_RF regulator cannot be used to

rms

supply the transmitter, VSP_RF has to be externally connected to VDD (connection of

VSP_RF to supply voltage higher than V

is not allowed).

The voltage drop of the transmitter current is the main source of the ST25R3912 power

dissipation. This voltage drop is composed of drop in the transmitter driver and in the drop

on VSP_RF regulator. Due to this it is recommended to set regulated voltage using direct

command Adjust Regulators. It results in good power supply rejection ration with relatively

low dissipated power due to regulator voltage drop.

In Power-down mode the VSP_RF regulator is not operating.

VSP_RF pin is connected to V

through a 1 k

Ω

resistor.

Connection through resistors ensures smooth power-up of the system and a smooth

transition from Power-down mode to other operating modes.

VSP_A and VSP_D regulators

VSP_A and VSP_D regulators are used to supply, respectively, the ST25R3912 analog and

digital blocks. In 3.3 V mode, VSP_A and VSP_D regulator are set to the same regulated

voltage as the VSP_RF regulator, in 5 V mode VSP_A and VSP_D regulated voltage is fixed

to 3.4 V.

The use of VSP_A and VSP_D regulators is obligatory in 5 V mode since analog and digital

blocks supplied with these two pins contain low voltage transistors that support maximum

DS11794 Rev 7

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Functional overview

ST25R3912

supply voltage of 3.6 V. In 3.3 V supply mode the use of regulators is strongly recommended

to improve PSRR of analog processing.

For low cost applications it is possible to disable the VSP_D regulator and to supply digital

blocks through external short between VSP_A and VSP_D (configuration bit vspd_off in the

. In case VSP_D regulator is disabled VSP_D can alternatively be

supplied from VDD (in 3.3 V mode only) if V

is not more than 300 mV lower than V

SP_A

Power-down support block

In the Power-down mode the regulators are disabled to save current. In this mode a low

power Power-down support block that maintains the VSP_D and VSP_A in below 3.6 V is

enabled. Typical regulated voltage in this mode is 3.1 V at 5 V supply and 2.2 V at 3 V

supply. When 3.3 V supply mode is set the Power-down support block is disabled, its output

is connected to VDD through 1 k

Ω

resistor.

Typical consumption of Power-down support block is 600 nA at 5 V supply.

Measurement of supply voltages

Using direct command Measure Power Supply it is possible to measure VDD and regulated

voltages VSP_A, VSP_D, and VSP_R

1.2.11

Communication with an external microcontroller

The ST25R3912 is a slave device and the external microcontroller initiates all

communication. Communication is performed by a 4-wire serial peripheral interface (SPI).

The ST25R3912 sends an interrupt request (pin IRQ) to the microcontroller, which can use

clock signal available on pin MCU_CLK when the oscillator is running.

Serial peripheral interface (SPI)

While signal /SS is high the SPI interface is in reset, while it is low the SPI is enabled. It is

recommended to keep /SS high whenever the SPI is not in use. MOSI is sampled at the

falling edge of SCLK. All communication is done in blocks of 8 bits (bytes). First two bits of

first byte transmitted after high to low transition of /SS define SPI operation mode.

Table 5. Serial data interface (4-wire interface) signal lines

Name

Signal

Signal level

Description

/SS

Digital input

SPI Enable (active low)

Serial data input

MOSI

MISO

SCLK

CMOS

Digital output with tristate

Digital input

Serial data output

Clock for serial communication

MSB bit is always transmitted first (valid for address and data).

Read and Write modes support address auto-incrementing. This means that if some

additional data bytes are sent/read after the address and first data byte, they are written

to/read from addresses incremented by ‘1’.

Figure 8

defines possible modes.

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Figure 8. Exchange of signals with microcontroller

Separate SPI input and

output signals to MCU

Bidirectional data

IO signal to MCU

MOSI

MISO

MOSI

I/O

MISO

MS42438V2

MISO output is usually in tristate, it is only driven when output data is available. Due to this

the MOSI and the MISO can be externally shorted to create a bidirectional signal.

During the time the MISO output is in tristate, it is possible to switch on a 10 k

Ω

pull down by

activating option bits miso_pd1 and miso_pd2 in the

ble 6

provides information on the SPI operation modes. Reading and writing of registers

is possible in any ST25R3912 operation mode. FIFO operations are possible in case en (bit

7 of the

) is set and Xtal oscillator frequency is stable.

Table 6. SPI operation modes

Pattern (communication bits)

Mode

Trailer

Related data

M1 M0 C5 C4 C3 C2 C1 C0

A5 A4 A3

A2 A1

Data byte (or more bytes in case of

auto-incrementing)

FIFO Load

One or more bytes of FIFO data

–

FIFO Read

Direct Command Mode

C5 C4 C3 C2 C1 C0

Writing data to addressable registers (Write mode)

Figure 9

and

Figure 10

show cases of writing a single byte and writing multiple bytes with

auto-incrementing address. After the SPI operation mode bits, the address of register to be

written is provided. Then one or more data bytes are transferred from the SPI, always from

the MSB to the LSB. The data byte is written in register on falling edge of its last clock. In

case the communication is terminated by putting /SS high before a packet of 8 bits (one

byte) is sent, writing of this register is not performed. In case the register on the defined

address does not exist or it is a read only register no write is performed.

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Figure 9. SPI communication: writing a single byte

/SS

Raising

edge

indicates

end of

Write Mode

SCLK

MOSI

Two leading bits

indicate Mode

SCLK rising edge

SCLK falling edge

Data is moved to

address <A5-A0>

Data transferred from MCU

Data is sampled

MS42463V1

Figure 10. SPI communication: writing multiple bytes

/SS

/SS raising edge

indicates end of

Write mode

SCLK

MOSI

A A

A A D D D D D D D D D D D D D D D D D D

1 0

5 4

D D D D D D D D D D

1 0 7 6 5 4 3 2 1 0

0 0

SCLK falling edge

Data moved to

address <A5-A0> + 1

SCLK falling edge

Data moved to

address <A5-A0> + n

Two leading 0s

indicate Write mode

SCLK falling edge

Data moved to

address <A5-A0>

SCLK falling edge

Data moved to

address <A5-A0> + (n-1)

MS42468V1

Reading data from addressable registers (Read mode)

After the SPI operation mode bits the address of register to be read has to be provided from

the MSB to the LSB. Then one or more data bytes are transferred to MISO output, always

from the MSB to the LSB. As in case of the write mode also the read mode supports



auto-incrementing address.

MOSI is sampled at the falling edge of SCLK (like shown in the following diagrams), data to

be read from the ST25R3912 internal register is driven to MISO pin on rising edge of SCLK

and is sampled by the master at the falling edge of SCLK.

In case the register on defined address does not exist all 0 data is sent to MISO.

Figure 11

is an example for reading of single byte.

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Figure 11. SPI communication: reading a single byte

/SS

/SS raising edge

indicates end of

Read mode

SCLK

MOSI

tristate

MISO

SCLK rising edge

Data moved from

Address A5-A0

SCLK falling edge

Data transferred to MCU

Two leading bits

indicate Mode

SCLK rising edge

SCLK falling edge

Data transferred from MCU

Data is sampled

MS42467V1

Loading transmitting data into FIFO

Loading the transmitting data into the FIFO is similar to writing data into an addressable

registers. Difference is that in case of loading more bytes all bytes go to the FIFO. SPI

operation mode bits 10 indicate FIFO operations. In case of loading transmitting data into

FIFO all bits <C5 – C0> are set to 0. Then a bit-stream, the data to be sent (1 to 96 bytes),

can be transferred. In case the command is terminated by putting /SS high before a packet

of 8 bits (one byte) is sent, writing of that particular byte in FIFO is not performed.

Figure 12

shows how to load the Transmitting Data into the FIFO.

Figure 12. SPI communication: loading of FIFO

/SS raising

edge

/SS

indicates

end of

SCLK

FIFO Mode

1 to 96

bytes

MOSI

10 pattern

indicates

FIFO Mode

Start of

paylod data

SCLK rising edge

SCLK falling edge

Data transferred from MCU

Data is sampled

MS42464V1

Reading received data from FIFO

Reading received data from the FIFO is similar to reading data from an addressable

registers. Difference is that in case of reading more bytes they all come from the FIFO. SPI

DS11794 Rev 7

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Functional overview

ST25R3912

operation mode bits 10 indicate FIFO operations. In case of reading the received data from

the FIFO all bits <C5 – C0> are set to 1. On the following SCLK rising edges the data from

FIFO appears as in case of read data from addressable registers. If the command is

terminated by putting /SS high before a packet of 8 bits (one byte) is read, that particular

byte is considered unread and will be the first one read in next FIFO read operation.

Figure 13. SPI communication: reading of FIFO

/SS

/SS raising

edge

indicates

end of

FIFO Mode

SCLK

MOSI

MISO

1 to 96

bytes

tristate

10 pattern

indicates

FIFO Mode

SCLK rising edge

Data moved from FIFO

SCLK rising edge

SCLK falling edge

Data transferred to MCU

Data transferred from MCU

Data is sampled

MS42465V2

Direct Command Mode

Direct Command Mode has no arguments, so a single byte is sent. SPI operation mode bits

11 indicate Direct Command Mode. The following six bits define command code, sent MSB

to LSB. The command is executed on falling edge of last clock (see

Figure 14

While execution of some Direct Commands is immediate, there are others that start a

process of certain duration (calibration, measurement…). During execution of such

commands it is not allowed to start another activity over the SPI interface. After execution of

such a command is terminated an IRQ is sent.

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Figure 14. SPI communication: direct command

/SS

/SS raising edge

indicates start of

command execution

SCLK

MOSI

Two leading 1s

indicate

Command Mode

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

MS42466V1

Direct command chaining

As shown in

Figure 15

, direct commands with immediate execution can be followed by

another SPI mode (Read, Write or FIFO) without deactivating the /SS signal in between.

Figure 15. SPI communication: direct command chaining

/SS

Direct command

Read, Write or FIFO Mode

MS42425V1

SPI timing

Table 7. SPI timing

Min Typ Max

Unit

General timing (V

= V

DD_IO

= V

SP_D

= 3.3

5 °C)

Symbol

Parameter

Comments

SCLK

SCLKL

SCLKH

, use of shorter SCLK

period may lead to incorrect FIFO operation.

SCLK

SCLK period

167

–

SCLKL

SCLKH

SSH

SCLK low

SCLK high

–

SPI reset (/SS high)

100

–

NCSL

NCSH

DIS

/SS falling to SCLK rising

SCLK falling to /SS rising

Data in set-up time

First SCLK pulse

300

Last SCLK pulse

–

DIH

Data in hold time

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Functional overview

ST25R3912

Table 7. SPI timing (continued)

Min Typ Max

Unit

Symbol

Parameter

Comments

Read timing (V

= V

DD_IO

= V

SP_D

= 3.3

, 25 °C, C

LOAD

≤

50 pF)

DOD

Data out delay

–

Data out to high

impedance delay

DOHZ

Figure 16. SPI general timing

/SS

…

NCSL

SCLKH

SCLKL

NCSH

SCLK

MOSI

…

DIS

DIH

DATAI

MISO

/SS

MS42449V1

Figure 17. SPI read timing

…

SCLK

MOSI

…

DATAI

DATAO

MISO

DOD

DOHZ

MS42448V1

Interrupt interface

There are three interrupt registers implemented in the ST25R3912:

Timer and NFC interrupt register

contains information about six interrupt sources, while two bits reference to interrupt

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Functional overview

sources detailed in

and

Error and wake-up interrupt

When an interrupt condition is met the source of interrupt bit is set in the

Main interrupt

and the IRQ pin transitions to high.

Table 8. IRQ output

Name

Signal

Signal level

Description

IRQ

Digital output

CMOS

Interrupt output pin

The microcontroller then reads the

to distinguish between different

interrupt sources. The interrupt registers 0x17, 0x18 and 0x19 are to be read in one attempt.

After a particular Interrupt register is read, its content is reset to 0. Exceptions to this rule are

the bits pointing to auxiliary registers. These bits are only cleared when corresponding

auxiliary register is read. IRQ pin transitions to low after the interrupt bit(s) that caused its

transition to high has (have) been read.

Note:

There may be more than one interrupt bit set in case the microcontroller does not

immediately read the Interrupt registers after the IRQ signal has been set and another event

causing interrupt has occurred. In that case the IRQ pin transitions to low after the last bit

that caused interrupt is read.

If an interrupt from a certain source is not required, it can be disabled by setting

corresponding bit in the Mask Interrupt registers. When masking a given interrupt source the

interrupt is not produced, but the source of interrupt bit is still set in Interrupt registers.

FIFO water level and FIFO status registers

The ST25R3912 contains a 96-byte FIFO. In case of transmitting the Control logic shifts the

data that was previously loaded by the external microcontroller to the Framing block and

further to the transmitter. During reception, the demodulated data is stored in the FIFO and

the external microcontroller can download received data at a later moment.

Transmit and receive capabilities are not limited by the FIFO size due to a FIFO water level

interrupt system. During transmission an interrupt is sent (

IRQ

due to FIFO water level in the

) when the content of data in the FIFO passes from (water level + 1) to

water level and the complete transmit frame has not been loaded in the FIFO yet. The

external microcontroller can now add more data in the FIFO. The same stands for the

reception: when the number of received bytes passes from (water level – 1) to water level an

interrupt is sent to inform the external controller that data has to be downloaded from FIFO

in order not to lose receive data due to FIFO overflow.

During transmission water level IRQ is additionally set in case all transmission bytes have

not been written in FIFO yet and if number of bytes written into FIFO is lower than water

level. In this case an IRQ is sent when number of bytes in FIFO drops below 4.

Note:

FIFO IRQ is not produced while SPI is active in FIFO load or read mode. Due to this the

FIFO loading/reading rate has to be higher than Tx/Rx bit rate, once FIFO loading/reading is

finished the /SS pin has to be pulled to VDD (logic remains in FIFO load/read mode as long

as /SS remains low).

The external controller has to serve the FIFO faster than data is transmitted or received.

Using SCLK frequency that is at least double than the actual receive or transmit bit rate is

recommended.

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Functional overview

ST25R3912

There are two settings of the FIFO water level available for receive and transmit in the

At the beginning of a data reception the FIFO,

and

FIFO status

are cleared automatically.

After data reception is terminated the external microcontroller needs to know how much

data is still stored in the FIFO: This information is available in the

and

that display number of bytes in the FIFO that were not read out.

FIFO

status register 1

can also be read while reception and transmission processes are active to

get info about current number of bytes in FIFO. In that case user has to take in account that

Rx/Tx process is going on and that the number of data bytes in FIFO may have already

changed by the time the reading of register is finished.

The

contains the information on whether the last received byte was

completed or not. An incomplete byte can occur on certain protocols that use frames shorter

than one byte for status information or for example, if the receive data stream breaks in the

middle due to an unexpected card removal. The status of the last received byte and the

number of valid bits received is stored in the bits fifo_ncp, fifo_lb<2:0>, and np_lb. These

bits are cleared when the

is read and must be stored in the MCU if

needed for further processing.

The

additionally contains two bits that indicate that the FIFO was not

correctly served during reception or transmission process (FIFO overflow and FIFO

underflow).

FIFO overflow is set when too much data is written in FIFO. In case this bit is set during

reception the external controller did not react on time on water level IRQ and more than 96

bytes were written in the FIFO. The received data is of course corrupted in such a case.

During transmission this means that controller has written more data than FIFO size. The

data to be transmitted was corrupted.

FIFO underflow is set when data was read from empty FIFO. In case this bit is set during

reception the external controller read more data than was actually received. During

transmission this means that controller has failed to provide the quantity of data defined in

number of transmitted bytes registers on time.

Pin MCU_CLK

Pin MCU_CLK may be used as clock source for the external microcontroller. Depending on

the operation mode either a low frequency clock (32 kHz) from the RC oscillator or the clock

signal derived from crystal oscillator is available on pin MCU_CLK. The MCU_CLK output

pin is controlled by bits out_c1, out_cl0 and lf_clk_off in the

Section 1.2.20: Stream mode and Transparent mode

. Bits

out_cl enable the use of pin MCU_CLK as clock source and define the division for the case

the crystal oscillator is running (13.56 MHz, 6.78 MHz and 3.39 MHz are available). Bit

lf_clk_off controls the use of low frequency clock (32 kHz) in case the crystal oscillator is not

running. By default configuration (defined at power-up) the 3.39 MHz clock is selected and

the low frequency clock is enabled.

In Transparent mode (see

) the use of

MCU_CLK is mandatory since clock that is synchronous to the field carrier frequency is

needed to implement receive and transmit framing in the external controller. The use of

MCU_CLK is recommended also for the case where the internal framing is used. Using

MCU_CLK as the microcontroller clock source generates noise synchronous with the reader

carrier frequency and is therefore filtered out by the receiver, while using some other

incoherent clock source may produce noise that perturbs the reception.

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Use of MCU_CLK is also better for EMC compliance.

1.2.12

Direct commands

Table 9. Direct commands

Interrupt

Operation

after

termination

Command

code (hex)

Command

chaining

Command

Comments

mode

(1)

Puts the ST25R3912 in default

state (same as after power-up)

C2, C3

Set Default

All

Clear

Stops all activities and clears FIFO

Starts a transmit sequence using

automatic CRC generation

Transmit With CRC

en, tx_en

Starts a transmit sequence without

automatic CRC generation

Transmit Without CRC

Transmit REQA

en, tx_en

(2)

Transmits REQA command

(ISO14443A mode only)

Transmits WUPA command

(ISO14443A mode only)

Transmit WUPA

Performs Initial RF Collision

Avoidance and switches on the field

NFC Initial Field ON

Yes

NFC Response Field

Performs Response RF Collision

Avoidance and switches on the field

(2)

Performs Response RF Collision

Avoidance with n=0 and switches

on the field

NFC Response Field

ON with n=0

Yes

(2)

Accepted in NFCIP-1 active

communication bit rate detection

mode

Go to Normal NFC

Mode

–

Presets Rx and Tx configuration

based on state of

Mode definition

and

Bit rate definition

Analog Preset

All

Receive after this command is

ignored

Mask Receive Data

Unmask Receive Data

en, rx_en

Receive data following this

command is normally processed

(this command has priority over

internal Mask Receive timer)

–

Not used

–

Amplitude of signal present on RFI

inputs is measured, result is stored

Measure Amplitude

Performs gain reduction based on

the current noise level

Squelch

en, rx_en

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Functional overview

Command

ST25R3912

Table 9. Direct commands (continued)

Interrupt

after

termination

Command

Operation

mode

(1)

Command

Comments

code (hex)

chaining

Clears the current Squelch setting

and loads the manual gain

reduction from

Reset Rx Gain

(3)

Adjusts supply regulators according

to the current supply voltage level

Adjust Regulators

Starts sequence that activates the

Tx, measures the modulation depth

and adapts it to comply with the

specified modulation depth

Calibrate Modulation

Depth

Measurement of phase difference

between the signal on RFO and RFI

Measure Phase

Clear RSSI

Clears RSSI bits and restarts the

measurement

Amplitude of signal present on RFI

inputs is measured, result is stored

Transparent Mode

Measure Power Supply

–

Yes

Start General Purpose

Timer

All except

Start Wake-Up Timer

–

Start Mask Receive

Timer

See note

(4)

Start No-Response

Timer

en, rx_en

All

Clears all test registers. Must be

sent as chained sequence “FCFA”

Clear

st Registers

st Access

Enable /W to test registers

Reserved for test

Not used

All

–

Other Fx

Other codes

–

1. Defines

the bits of the

that have to be set in order to accept a particular command.

After termination of this command I_cat or I_cac IRQ is sent.

3. This

command is not accepted in case the external definition of the regulated voltage is selected in the

Regulator voltage

(bit reg_s is set to high).

4. Accepted

only in the Initial NFC Active

rget Communication Mode.

Set Default

This direct command puts the ST25R3912 in the same state as power-up initialization. All

registers are initialized to the default state. The only exceptions are for

IO configuration

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and

(not affected by Set

Default command) that are set to default state only at power-up.

Note:

Results of different calibration and adjust commands are also lost.

This direct command is accepted in all operating modes. If this command is sent while en

(bit 7 of the

General purpose and no-response timer control register

) is not set FIFO and FIFO status registers are not

cleared.

Direct command chaining is not allowed since this command clears all registers.

IRQ due to termination of direct command is not produced.

Clear

This direct command stops all current activities (transmission or reception), clears FIFO,

clears FIFO status registers and stops all timers except Wake-up timer. If bit nrt_emv in the

is set to 1, the



No-response timer is not stoppedIf nfc_ar in the

is set to 1, the

internal timer for the Response RF Collision Avoidance is not stopped and the Response RF

Collision Avoidance will take place once this timer epxires. Set nfc_ar to 0 prior to sending

the direct command Clear to stop any Response RF Collision Avoidance activity too. It also

clears collision and interrupt registers. This command has to be sent first in a sequence

preparing a transmission before writing data to be transmitted in FIFO (except in case of

direct commands Transmit REQA and Transmit WUPA).

This command is accepted in case en (bit 7 of the

transmitted bytes register 2

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

Transmit commands

All transmit commands (Transmit With CRC, Transmit Without CRC, Transmit REQA and

Transmit WUPA) are accepted only in case the transmitter is enabled (bit tx_en is set).

Before sending commands Transmit With CRC and Transmit Without CRC direct command

Clear has to be sent, followed by definition of number of transmitted bytes and writing data

to be transmitted in FIFO.

Direct commands Transmit REQA and Transmit WUPA are used to transmit ISO14443A

commands REQA and WUPA respectively. Sending command Clear before these two

commands is not necessary.

The number of valid bits in the last byte must be set to zero (nbtx<2:0> in the

Number of

) prior to executing Transmit REQA or Transmit WUPA.

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

NFC Field ON commands

These commands areis used to perform the RF Collision Avoidance and switch the field on

in case no collision was detected. The Collision Avoidance threshold defined in the

External

field detector threshold register

is used to observe the RF_IN inputs and to determine

whether there is some other device close to the ST25R3912 antenna emitting the

13.56 MHz field. In case collision is not detected the reader field is switched on

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Functional overview

ST25R3912

automatically (bit tx_en in the

Timer and NFC interrupt register

is set) and an IRQ with I_cat flag in

is sent after minimum guard time defined by the NFCIP-1

standard to inform the controller that message transmission using a Transmit command can

be initiated.

If an external field is detected an IRQ with I_cac flag is sent. In such case a transmission

cannot be performed, NFC Field ON command has to be repeated as long as collision is not

detected anymore. Command NFC Initial Field ON performs Initial Collision Avoidance

according to NFCIP-1 standard; number n is defined by bits nfc_n1 and nfc_n0 in

Auxiliary

Command NFC Response Field ON performs Response Collision Avoidance according to

NFCIP-1 standard; number n is defined by bits nfc_n1 and nfc_n0 in

Auxiliary definition

Command NFC Response Field ON with n=0 performs Response Collision Avoidance

where n is 0.

Implemented active delay time is on lower NFCIP-1 specification limit, since the actual

active delay time will also include detection of the field deactivation, controller processing

delay and sending the NFC Field ON command.

This command is accepted in case en (bit 7 of the

) is set and both

Xtal oscillator frequency and amplitude are stable.

Figure 18. Direct command NFC Initial Field ON

RF on

RFW

Start

IDT

n x T

RFW

IRFG

MS42450V1

Figure 19. Direct command NFC Response Field ON

RF on

RFW

Start

ADT

n x T

RFW

ARFG

MS42451V1

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Table 10. Timing parameters of NFC Field ON commands

Symbol

Parameter

Value

Unit

Comments

IDT

RWF

IRFG

ADT

Initial delay time

RF waiting time

Initial guard time

Active delay time

Active guard time

4096

512

NFC Initial Field ON

/fc

–

NFC Initial Field ON

768

1024

NFC Response Field ON

ARFG

Go to Normal NFC Mode

This command is used to transition from NFC target bit rate detection mode to normal

mode. Additionally it copies the content of the

the

and correctly sets the bit tr_am in the

Auxiliary definition

Analog Preset

This command is used to preset receiver and transmitter configuration based on state of

and

Table 21: Operation control register

. In case of Sub-carrier bit stream or

BPSK bit stream mode, this command should not be used. The list of configuration bits that

are preset is given in

ble 11

Table 11. Register preset bits

Bit Bit

name

Function

Address 02h:

rx_chn

one channel enabled

→

NFCIP-1 active communication (both initiator and target)

tx_en

disable TX operation

→

NFCIP-1 active communication (both initiator and target)

Note

: In case of any target mode or NFCIP-1 initiator mode bit

tx_en

is set to 0 to disable transmitter

in case it was enabled. In NFCIP-1 mode the switching on of the transmitter field is controlled by

dedicated commands.

Address 05h:

ble 27: ISO14443A and NFC 106kb/s settings register

Adds SB (F0) and LEN byte during Tx and skip SB (F0) byte during



nfc_f0

→

NFCIP-1 active communication (both initiator and target)

Address 09h:

ble 35: Auxiliary definition register

Tx Modulation type (depends on mode definition and Tx bit rate)

OOK

→

ISO144443A, NFCIP-1 106 kb/s (both initiator and target), NFC Forum

Type 1 Tag

→

ISO144443B, FeliCa

™

, NFCIP-1 212 kb/s and 424 kb/s

tr_am

en_fd

Enables External Field Detector with Peer Detection threshold

All modes except NFCIP-1 active communication

NFCIP-1 active communication (both initiator and target)

Address 0Ah:

Table 36: Receiver configuration register 1

ch_sel

Enables AM channel

→

NFCIP-1 active communication (both initiator and target)

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Functional overview

ST25R3912

Table 11. Register preset bits (continued)

Function

Bit Bit

name

AM demodulator select (depend on Rx bit rate)

amd_sel

Peak detector

→

All Rx bit rates equal or below fc / 16 (848 kb/s)

Mixer

lp2

Low pass control (depends on mode definition and Rx bit rate), see

ble 3:

Receiver filter selection and gain range

lp1

lp0

h200

h80

z12k

First and third stage zero setting (depends on mode definition and Rx bit rate), see

Table 3: Receiver filter selection and gain range

Address 0Ch:

ble 38: Receiver configuration register 3

Clips output of 1

and 2

stage

lim

All modes except NFCIP-1 active communication

NFCIP-1 active communication (both initiator and target)

Forces gain reduction in 2

and 3

gain stage

rg_nfc

All modes except NFCIP-1 active communication

NFCIP-1 active communication (both initiator and target)

Mask Receive Data and Unmask Receive Data

After the direct command Mask Receive Data the signal rx_on that enables the RSSI and

AGC operation of the receiver (see

Section 1.1.2: Receiver

) is forced to low, processing of

the receiver output by the receive data framing block is disabled. This command is useful to

mask receiver and receive framing from processing the data when there is actually no input

and only a noise would be processed (for example in case where a transponder processing

time after receiving a command from the reader is long) Masking of receive is also possible

using Mask Receive timer. Actual masking is a logical or of the two mask receive

processesThe direct command Unmask Receive Data is enabling normal processing of the

received data (signal rx_on is set high to enable the RSSI and AGC operation), the receive

data framing block is enabled. A common use of this command is to enable again the

receiver operation after it was masked by the command Mask Receive Data. If Mask

Receive timer is running while command Unmask Receive Data is received, reception is

enabled, Mask Receive timer is reset.

The commands Mask Receive Data and Unmask Receive Data are only accepted when the

receiver is enabled (bit rx_en is set).

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

Measure Amplitude

This command measures the amplitude on the RFI inputs and stores the result in the

A/D

converter output register

When this command is executed the transmitter and Amplitude Detector are enabled, the

output of the Amplitude Detector is multiplexed to the A/D converter input (the A/D converter

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DS11794 Rev 7

ST25R3912

Functional overview

is in absolute mode). The Amplitude Detector conversion gain is 0.6 V

/ V

. One LSB

INPP

OUT

of the A/D converter output represents 13.02 mV

on the RFI inputs. A 3 V

signal (the

maximum allowed level on each of the two RFI inputs), results in 1.8 V output DC voltage

and will produce a value of 1110 0110b on the A/D converter output.

Duration time: 25

s max.

This command is accepted in case en (bit 7 of the

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is not possible.

IRQ due to termination of direct command is produced after command execution is

terminated.

Squelch

This direct command is intended to avoid demodulation problems of transponders that

produce a lot of noise during data processing. It can also be used in a noisy environment.

The operation of this command is explained in

Squelch

Duration time: 500

s max.

This command is only accepted when the transmitter and the receiver are operating.

Command is actually executed only in case signal rx_on is low.

Direct command chaining is not possible.

IRQ due to termination of direct command is not produced.

Reset Rx Gain

This command initializes the AGC, Squelch and RSSI block. Sending this command stops a

squelch process in case it is going on, clears the current Squelch setting and loads the

manual gain reduction from

This command is accepted in case en (bit 7 of the

Section 1.2.10: Power supply

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

Adjust Regulators

When this command is sent the power supply level of V

is measured in maximum load

conditions and the regulated voltage reference is set 250 mV below this measured level to

ensure maximum possible stable regulated supply (see

system

). The use of this command increases the system PSSR.

At the beginning of execution of the command, both the receiver and transmitter are

switched on to have the maximum current consumption, and the regulators are set to their

maximum regulated voltage (5.1 V in case of 5 V supply and 3.4 V in case of 3.3 V supply).

After 300

s V

is compared to V

, if is not at least 250 mV lower the regulator setting

SP_RF

is reduced by one step (120 mV in case of 5 V supply and 100 mV in case of 3.3 V supply)

and measurement is done after another 300

s. The procedure is repeated until V

SP_RF

drops at least 250 mV below V

, or until the minimum regulated voltage (3.9 V in case of

5 V supply and 2.4 V in case of 3.3 V supply) is reached.

Duration time: 5 ms max.

DS11794 Rev 7

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Functional overview

ST25R3912

This command is accepted if en (bit 7 of the

) is set and Xtal

oscillator frequency is stable.

This command is not accepted when the external definition of the regulated voltage is

selected in the

AM modulation depth control

(bit reg_s is set to H).

Direct command chaining is not possible.

IRQ due to termination of direct command is produced after command execution is

terminated.

Calibrate Modulation Depth

Starts a sequence that activates the transmission, measures the modulation depth and

adapts it to comply with the modulation depth specified in the

. When calibration procedure is finished result is displayed in the same register.

Refer to

Section 1.2.19: AM modulation depth: definition and calibration

for details about

setting the AM modulation depth and running this command.

Duration time: 275

s max.

This command is accepted when en (bit 7 of the

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is not possible.

IRQ due to termination of direct command is produced after command execution is

terminated.

Measure Phase

This command measures the phase difference between the signals on the RFO outputs and

the signals on the RFI inputs and stores the result in the

During execution of the direct command Measure Phase the transmitter and Phase Detector

are enabled, the Phase Detector output is multiplexed on the input of A/ D converter, which

is set in relative mode. Since the A/D converter range is from 1/6 VSP_A to 5/6 VS

the

P_A

actual phase detector range is from 30º to 150º. Values below 30º result in FFh, while

values above 150º result in 00h. One LSB of the A/D conversion output represents 0.13% of

carrier frequency period (0.468°). The result of A/D conversion is in case of 90º phase shift

in the middle of range (1000 0000b or 0111 1111b). A value higher than 1000 0000b means

that phase detector output voltage is higher than V

/2, which corresponds to case with

SP_A

phase shift lower than 90º. In the opposite case, when the phase shift is higher than 90º, the

result of A/D conversion is lower than 0111 1111b. For example, the phase difference of 135º

shown in

Figure 6

results in 0.75 V

, result stored in A/D converter is 31d (1Fh).

SP_A

The phase measurement result can be calculating using the following formulas:



0º

≤ φ ≤

30º: result = 255 (decimal)

30º <

< 150º: angle (in º) = 30 + [(255 – u_angle) / 255) * 120]

150º

≤ φ ≤

180º: result = 0 (decimal)

Duration time: 25

s max.

This command is accepted in case en (bit 7 of the

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is not possible.

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ST25R3912

Functional overview

IRQ due to termination of direct command is produced after command execution is

terminated.

Clear RSSI

The receiver automatically clears the RSSI bits in the

and starts to

measure the RSSI of the received signal when the signal rx_on is asserted. Since the RSSI

bits store peak value (peak-hold type) the variations of the receiver input signal will not be

followed (this may happen in case of long messages or test procedures). The direct

command Clear RSSI clears the RSSI bits in the

, and the RSSI

measurement is restarted (in case, of course, rx_on is still high).

This command is accepted in case en (bit 7 of the

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is possible.

IRQ due to termination of direct command is not produced.

Transparent Mode

Enters in the Transparent mode. The Transparent mode is entered on the rising edge of

signal /SS and is maintained as long as this signal is kept high.

This command is accepted when en (bit 7 of the

) is set and Xtal

oscillator frequency is stable.

Measure Power Supply

This command performs the power supply measurement. Configuration bits mpsv1 and

mpsv0 of the

define which power supply is measured

(VDD,VSP_A, VSP_D and VSP_RF can be measured). Result of measurement is stored in

the

During the measurement the selected supply input is connected to a 1/3 resistive divider,

whose output is multiplexed to A/D converter in absolute mode. Due to division by 3, one

LSB represents 23.438 m

Duration time: 25

s max.

This command is accepted in case en (bit 7 of the

Section 1.2.6: Timers on page 23

) is set and Xtal

oscillator frequency is stable.

Direct command chaining is not possible.

IRQ due to termination of direct command is produced after command execution is

terminated.

1.2.13

1.2.14

Start timers

See

Test access

A direct command

st Access is used to enable RW access of test registers and entry in

different test modes. Pins TO1 and TO2 are used as test pins.

DS11794 Rev 7

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Functional overview

ST25R3912

Test mode entry and access to test registers

st registers are not part of normal SPI register address space. After sending a direct

command

st Access, test registers can be accessed using normal Read/Write register

SPI command. Access to test registers is possible in a chained command sequence where

first command

st Access is sent, followed by read/write access to test registers using auto

increment feature. After SPI interface reset (SS toggle) the content of test registers is kept.

st register are set to default state at power-up and by sending the command Clear

Registers.

Table 12. Analog test and observation register

Test Address 01h: Analog test and observation register – Type: RW

Bit

Name Default

Function

Comments

tana_7

tana_6

tana_5

–

Reserved

–

Not used

tana_3

tana_2

tana_1

tana_0

These test modes are also intended for observation in

normal mode.



Other modes of this register are also available when

See

Table 13

analog test mode is not set.

Table 13. Test access register – Tana signal selection of TO1 and TO2 pins

Tana_

Pin TO1

Pin TO2

Comments

Type

Functionality

Type

Functionality

Analog output of AM

channel (before digitizer)

Digital output of AM

channel (after digitizer)

Normal operation

Analog output of PM

channel (before digitizer)

Digital output of PM

channel (after digitizer)

Analog output of AM

channel (before digitizer)

Analog output of PM

channel (before digitizer)

Digital output of AM

channel (after digitizer)

Digital output of PM

channel (after digitizer)

Normal operation:

Analog signal after first

stage

Analog signal after

second stage

– PM channel if enabled

– AM if PM is not enabled

Channel selection from

logic

Collision Avoidance

detector output

Collision Avoidance

detectors are enabled

Digital TX modulation

signal

Analog part of channel

selection

DO Select

Analog output of AM

channel (before digitizer)

Digital output of AM

channel (after digitizer)

Normal operation

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DS11794 Rev 7

ST25R3912

Functional overview

1.2.15

Power-up sequence

At power-up, the ST25R3912 enters the Power-down mode. The content of all registers is

set to the default state.

1. The

microcontroller, after a power-up, must correctly configure the two IO configuration

registers. The content of these two registers defines operation options related to

hardware (power supply mode, Xtal type, use of MCU_CLK clock, antenna operation

mode).

2. Configure

the regulators. It is recommended to use direct command Adjust Regulators

to improve the system PSRR.

3. When

using the AM modulation (ISO-14443B for example), set the modulation depth in

the

and send the command Calibrate Modulation

Depth.

4. The

device is now ready to operate.

1.2.16

Reader operation

egin with, the operation mode and data rate have to be configured by writing the

Mode

and

. Additionally, the receiver and transmitter

operation options related to operation mode have to be defined. This is done automatically

by sending the direct command Analog Preset. If more options are required apart from

those defined by Analog Preset, then such options must be additionally set by writing the

appropriate registers.

Next, the Ready mode has to be entered by setting the bit en of the

Operation control

. In this mode the oscillator is started and the regulators are enabled. When the

oscillator operation is stable, an interrupt is sent.

Before sending any command to a transponder, the transmitter and receiver have to be

enabled by setting the bits rx_en and tx_en. RFID protocols usually require that the reader

field is turned on for a while before sending the first command (5 ms for ISO14443). General

purpose timer can be used to measure this time interval.

If REQA or WUPA have to be sent, this is simply done by sending the appropriate direct

command, otherwise the following sequence has to be followed:

1. Send

the direct command Clear

2. Define

the number of transmitted bytes in the

Number of transmitted bytes register 2

and

3. Write

the bytes to be transmitted in the FIFO

4. Send

the direct command Transmit With CRC or Transmit Without CRC (whichever is

appropriate)

5. When

all the data is transmitted an interrupt is sent to inform the microcontroller that

the transmission is finished (IRQ due to end of transmission)

After the transmission is executed, the ST25R3912 receiver automatically starts to observe

the RFI inputs to detect a transponder response. The RSSI and AGC (when enabled) start.

The framing block processes the sub-carrier signal from receiver and fills the FIFO with

data. When the reception is finished and all the data is in the FIFO an interrupt is sent to the

microcontroller (IRQ due to end of receive), additionally the

and

FIFO

status register 2

display the number of bytes in the FIFO so that the microcontroller can

proceed with data download.

DS11794 Rev 7

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Functional overview

ST25R3912

In case of an error or bit collision detected during reception, an interrupt with appropriate

flag is sent.

Transmit and Receive when the data packet is longer than FIFO

In case a data packet is longer than FIFO the sequence explained above is modified.

Before transmit the FIFO is filled. During transmit an interrupt is sent when remaining

number of bytes is lower than the water level (IRQ due to FIFO water level). The

microcontroller in turn adds more data in the FIFO. When all the data is transmitted an

interrupt is sent to inform the microcontroller that transmission is finished.

During reception situation is similar. In case the FIFO is loaded with more data than the

receive water level, an interrupt is sent and the microcontroller in turn reads the data from

the FIFO.

When reception is finished an interrupt is sent to the microcontroller (IRQ due to end of

receive), additionally the

and

display the

number of bytes in the FIFO that are still to be read out.

Anticollision – ISO 14443A

Note:

For this section, it is assumed that there is more than one ISO/IEC 14443A PICC in the

reader RF field, and all of them are compatible with ISO/IEC 14443 up to level 4.

This section describes the anticollision procedure of ST25R3912 for ISO14443A tags. After

an ISO14443 type A tag enters in the reader field, the reader has to perform a selection

process that brings it into the PROTOCOL state in which the actual application implemented

in the tag can be executed. This selection process is described in the ISO/IEC 14443-3.

Figure 20

shows the states that a tag and a reader have to pass through to enter the

protocol state.

The selection procedure starts when a PICC enters the reader field and the PCD sends a

REQA (or WUPA) command followed by an anticollision procedure (including SELEC

RATS and PPS).

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DS11794 Rev 7

ST25R3912

Functional overview

Figure 20. ISO14443A states for PCD and PICC

PICC

PCD

Power off

(no field)

Standby

Poll for PICC

with REQA

Idle

(field ON)

Receive ATQA

Ready

Active

Perform bit frame

anticollision loop

Increase

Cascade level

UID not complete

Check SAK

UID complete and PICC

compliant with ISO 14443-4

ISO 14443-4

MS42428V2

Setting up the ST25R3912 for ISO 14443A anticollision

et up the ST25R3912 for the ISO14443A anticollision follow the steps indicated below.

1. The

Initiator operation mode of ST25R3912 must be set up for ISO 14443A in the

(default is already for ISO14443A).

2. The

Tx and Rx bit rates must be set to default (106 kbps) in the

Bit rate definition

3. Set

the antcl bit in the

Mask receive timer register

. This needs to be

set before sending the REQA (or WUPA). As a result, the ST25R3912 does not trigger

a framing error if the collision occurs in the ATQA or during anticollision procedure.

Note:

This bit must be set to one for REQA, WUPA and ANTOCOLLISION commands, for other

commands it has to be zero.

4. Review

and set a value for

lower than the Frame delay

time, as required by the ISO14443A., and set the

No-response timer register 1

and

No-

response timer register 2

according to the requirements. This is typically larger than the

DS11794 Rev 7

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Functional overview

ST25R3912

Note:

ST25R3912

offers the resolution of n / 2 (64 / fc – half steps) compared to n (128 / fc) as

mentioned in ISO 14443A so that the receiver can be unmasked n / 2 steps before the

actual transmission from the PICC.

5. According

to ISO 14443A the FDT must be 1236 / fc if last transmitted bit is 1, or

1172 / fc if last transmitted bit is 0.

Figure 21

shows an example of how MRT and NRT

timers are set for a given FD

Figure 21. Selection of MRT and NRT for a given FDT

FDT

PCD to PICC

PICC to PCD

MRT < FDT – 64/fc

NRE > FDT + 64/fc

MS42443V1

6. The

receiver and transmitter operation options related to operation mode must be

defined. This is done automatically by sending the direct command Analog Preset. If

different options are required apart from those defined by Analog Preset, they must be

additionally set by writing the appropriate registers.

7. Set

rx_en and tx_en in the

. RFID protocols usually require

that the reader field is turned on for a while before sending the first command (5 ms for

ISO14443). General purpose timer can be used to count this time.

8. The

reply from PICC for the REQA, WUPA, and replies within anticollision sequence

before SAK do not contain CRC. In this case the no_CRC_rx bit in the

Auxiliary

must be set to 1 (receive without CRC) before sending these

commands.

REQA and WUPA

Sending these two commands is simple since they are implemented as direct commands

(Transmit REQA and Transmit WUPA). The end of transmission of these commands is

signaled to microcontroller by an interrupt – IRQ due to end of transmission). After the

transmission is executed, the ST25R3912 receiver automatically starts to observe the RFI

inputs to detect a transponder after the expiration of the Mask Receive timer.

As a response to REQA (or WUPA) all the PICC in the field respond simultaneously with an

ATQA. A collision can occur in this state if there are PICC with different UID size or has the

bit frame anticollision bits set differently. Hence it is important to set the antcl bit to 1. If there

is any IRQ (except I_nre) that ST25R3912 signals, the microcontroller must consider as a

valid presence of tag and must proceed with the anticollision procedure.

If more than one PICC is expected in the field, the following algorithm must be used to

select multiple tags:

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DS11794 Rev 7

ST25R3912

Functional overview

1. Send

REQA, if there is any answer continue

2. Perform

anticollision, and select one PICC

3. Send

HLTA to move the selected PICC to the HALT state

4. Go

to step 1, and repeat this procedure until all the PICCs are in HALT state and all the

UIDs have been extracted.

Anticollision procedure

After receiving the ATQA from the tags in the field, the next step is to execute the

anticollision procedure to resolve the IDs of the tags.

The procedure mainly uses the ANTICOLLISION and SELECT commands, which consist

of:



Select code SEL (1 byte)

Number of valid bits NVB (1 byte)

0 to 40 data bits of UID CLn according to the value of NVB

The ANTICOLLISION command uses bit oriented anticollision frame (it does not use CRC).

In this case the transmit needs to be done with direct command Transmit Without CRC and

for the receive, the no_CRC_rx bit in the

must be set to 1. The

final SELECT command and its response SAK contains a CRC, so the transmit needs to be

done with command Transmit With CRC and before sending this command the

configuration bit no_CRC_rx bit in the

must be set back to 0.

If there is more than one PICC in the field, the collision will occur when the tags reply to the

ANTICOLLISION command during anticollision, when the PICCs reply back with their UID.

This collision can occur after a complete byte (Full byte scenario) or it can occur within a

byte (Split byte scenario). The antcl bit in

Section 1.2.16: Reader operation

must be set during this procedure too. As a result, the ST25R3912 does not trigger a

Framing Error. This bit is also responsible for correct timing of anticollision and correct parity

extraction.

Note:

It must only be set before sending an anticollision frame, REQA or WUPA. This bit must not

be used in any other commands.

Figure 22

shows how to implement the anticollision with ST25R3912.

Since SPI is byte oriented, in case of Split byte scenario, the invalid MSB bits must be

ignored when reading out the FIFO for the received data. Similarly, 0s must be

concatenated as MSB bits to complete a byte for the Transmit (which will then be ignored

based on register 0x1E).

DS11794 Rev 7

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Functional overview

ST25R3912

Figure 22. Flowchart for ISO14443A anticollision with ST25R3912

SELn=0x93 for n=1 for 4 bytes UID

Cascade level n (n =1)

SELn=0x95 for n=2 for 7 bytes UID

SELn=0x97 for n=3 for 10 bytes UID

1) Fill FIFO with SELn + NVB (0x20)

2) Set registers:

Number of transmitted bytes register 1 = 0x00

Number of transmitted bytes register 2 = 0x10

1) Send command Transmit without CRC

2) Expected interrupts:

I_txe

I_col (if collision occurs)

I_rxs

I_rxe

FIFO is filled in with PICC response

Read FIFO for the valid data

from the selected PICC

I_col occured?

PICC sends complete UID

Set

– no_CRC_rx = 0

1) Read Collision Display Register to identify the

bit position where the collision occurred

2) Read FIFO for the response from PICC

– antcl = 0

Set

– no_CRC_rx = 1

– antcl = 1

Send SELEC

ill FIFO with

SELn + NVB(0x70) + UID CLn

1) Fill FIFO with part 1 of bit anticollision frame:

SELn + NVB (available from valid tag response) + received

valid data +1 or 0 for the bit where the collision occurred

2) Set registers: mention the number of received

1) Send command Transmit with CRC

full bytes and split bits + 1 in:

Number of transmitted bytes register 1

Number of full bytes

2) Expected nterrupts:

I_txe

I_rxe

Number of transmitted bytes register 2

FIFO is filled in with SAK

FIFO is filled in with PICC response

Enter

Cascade level n+1

End anticollision

with RATS

UID complete?

MS42423V1

™

1.2.17

FeliCa reader

mode

™

The general recommendation from

is valid for FeliCa

reader mode as well. Both 212 and 424 kb/s bit rates are supported, they are same in both

directions (reader to tag and tag to reader). Modulation reader to tag is AM.

™

In FeliCa

mode the FeliCa

frame format (see

Table 14

) is supported.

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DS11794 Rev 7

ST25R3912

Functional overview

Table 14. FeliCa™ frame format

Length

Preamble

Sync

Payload

CRC

48 data bits,

all logical 0

2 bytes

(B2h, 4Dh)

Length byte (value= payload length + 1),

the length range is from 2 to 255

Payload

2 bytes

FeliCa

™

transmission

™

ransmit the FeliCa

frame only the Payload data is put in the FIFO. The number of

Payload bytes is defined in the

transmitted bytes register 2

and

Number of

. Preamble length is defined by bits f_p1 and f_p0 in the

, default value is 48 bits, but other options are

possible.

Transmission is triggered by sending direct command Transmit With CRC. First preamble is

sent, followed by SYNC and Length bytes. Then Payload stored in FIFO is sent,

transmission is terminated by two CRC bytes that are calculated by the ST25R3912. Length

byte is calculated from the number of transmitted bytes. The following equation is used:

length = payload length + 1 = number of transmitted bytes +1

FeliCa

™

reception

After transmission is done the ST25R3912 logic starts to parse the receiver output to detect

™

the Preamble of FeliCa

tag reply.

Once the Preamble (followed by the two SYNC bytes) is detected the Length byte and

Payload data are put in the FIFO. CRC bytes are internally checked.

1.2.18

NFCIP-1 operation

The ST25R3912 supports all NFCIP-1 initiator modes and active communication target

modes. All NFCIP-1 bit rates (106, 212 and 424 kbit/s) are supported.

NFCIP-1 passive communication Initiator

NFCIP-1 passive communication is equivalent to reader (PCD) to tag (PICC)

communication where initiator acts as a reader and target acts as tag. The only difference is

that in case of the NFCIP-1 passive communication the initiator performs Initial RF Collision

Avoidance procedure at the beginning of communication.

ct as NFCIP-1 passive communication initiator configure the ST25R3912 according to

ble 15

Table 15. Operation mode/bit rate setting for NFCIP-1 passive communication

NFCIP-1 bit

rate (kb/s)

Operation

mode setting

Bit rate

for Tx (kb/s)

Bit rate

for Rx (kb/s)

Comments

106

212

424

ISO14443A

FeliCa

™

fc / 128 (~106)

–

fc / 64 (~212)

fc / 32 (~424)

–

In FeliCa Mode data rate is

the same in both directions

DS11794 Rev 7

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Functional overview

ST25R3912

Initial set-up of the

before the start of communication is the same

as in case of reader to tag communication, with the exception that the transmitter is not

enabled by setting the tx_en bit. The direct command NFC Initial Field ON is sent instead.

This command first performs the Initial RF Collision Avoidance with Collision Avoidance

Threshold defined in the

parameters of NFC Field ON commands

. The timing of Collision

Avoidance is according to NFCIP-1 standard (for timing details see

Table 10: Timing

). In case collision is not detected the tx_en bit is

automatically set to switch the transmitter on. After minimum guard time T

is sent to inform controller that the first initiator command can be sent.

the I_cat IRQ

IRFG

From this point on communication is the same as for ISO14443A (for 106 kb/s) or for

™

FeliCa (for

242 and 424 kb/s) reader communication.

In case a presence of external field is detected an I_cac IRQ is sent. In such case a

transmission should not be performed, command NFC Initial Field ON has to be repeated

until collision is not detected anymore.

Initial Collision Avoidance is not limited to modes supported by NFCIP-1. The initial Collision

Avoidance according to procedure described above can be performed before any reader

mode is started to avoid collision with an HF reader or an NFC device operating in proximity.

Support of NFCIP-1 transport frame format

Figure 23

shows the transport frame according to NFCIP-1.

Figure 23. Transport frame format according to NFCIP-1

Transport data field

LEN CMD0

CMD1 Byte

0 Byte

1 Byte

2 … Byte

n E1

106 kbps

Transport data field

LEN CMD0

CMD1 Byte

0 Byte

1 Byte

2 … Byte

n E2

MS51090V1

212 kbps

424 kbps

Transport Frame for bit rate 212 and 424 kb/s has the same format as communication frame

™

used during Initialization and SDD. This format is also used in FeliCa

protocol (see also

Section 1.2.17: FeliCa™ reader mode

). In case of 106 kb/s the SB (Start byte at F0h) and

LEN (length byte) are only used in Transport Frame.

Support of Transport Frame for 106 kb/s NFCIP-1 communication is enabled by setting bit

nfc_f0 in the

Once this bit is set and ISO 14443A mode with bit rate 106 kb/s is configured, the

ST25R3912 behaves as indicated in the next subsections.

Transmission

In order to transmit a Transport Frame only the Transport Data has to be put in FIFO. The

number of Transport Data bytes is defined in the

Number of transmitted bytes register 2

and

. Transmission is triggered by sending direct

command Transmit With CRC. First Start byte with value F0h followed by Length byte are

sent. Then Transport Data stored in FIFO is sent, transmission is terminated by two CRC

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DS11794 Rev 7

ST25R3912

Functional overview

bytes (E1 in

Figure 23

) that are calculated by the ST25R3912. Length byte is calculated

from ‘number of transmitted bytes’. The following equation is used:

length = Transport Data length + 1 = number of transmitted bytes +1

Reception

After transmission is done the ST25R3912 logic starts to parse the receiver output to detect

the start of tag reply.

Once the start of communication sequence is detected the first byte (Start Byte with value

F0h) is checked the Length byte and Transport Data bytes are put in the FIFO. CRC bytes

are internally checked. In case the Start byte is not equal to F0h the following data bytes are

still put in FIFO, additionally a soft framing error IRQ is set to indicate the Start Byte error.

NFCIP-1 Active Communication Initiator

During NFCIP-1 active communication both, initiator and target switch on its field when

transmitting and switch off its field when receiving. In order to operate as NFCIP-1 active

communication initiator the configure the ST25R3912 according to

Table 16

(bit targ in

has to be 0):

Table 16. Operation mode/bit rate setting for NFCIP-1 active communication initiator

NFCIP-1 bit rate

Initiator operation

Bit rate

for Tx (kb/s)

Bit rate

for Rx (kb/s)

Comments

(kb/s)

mode setting

106

212

424

fc / 128 (~106)

fc / 64 (~212)

fc / 32 (~424)

–

Data rate is the same



in both directions



for all NFCIP-1

NFCIP-1 active

communication

communication.

After selecting the NFCIP-1 active communication mode the receiver and transmitter have

to be configured properly. This configuration can be done automatically by sending direct

command Analog Preset (see

Analog Preset

During NFCIP-1 active communication the RF Collision Avoidance and switching on the

field is performed using NFC Field ON commands (see

NFC Field ON commands

), while

the sending of message is performed using Transmit commands as in the case of reader

communication. Alternatively the Response RF Collision Avoidance sequence is started

automatically when the switching off of target field is detected in case the bit nfc_ar in the

is set.

When NFCIP-1 mode is activated the External Field Detector is automatically enabled by

setting bit en_fd in the

. The Peer Detection Threshold is used to

detect target field. During execution of ‘NFC Field ON’ commands, the Collision Avoidance

Threshold is used.

Initial set-up of the

General purpose and no-response timer control

before the start of communication is the same

as in case of reader to tag communication with the exception that the transmitter is not

enabled by setting the tx_en bit. The tx_en bit and therefore switching on of the transmitter

is controlled by NFC Field ON commands. Switching off the field is performed automatically

after a message has been sent. The

is used to define the time during which the field stays switched on after a message

has been transmitted.

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Functional overview

ST25R3912

In order to receive the NFCIP-1 active reply only the AM demodulation channel is used. Due

to this the receiver AM channel has to be enabled. The preset done by Analog Preset

command enables only the AM demodulation channel, while PM channel is disabled to save

current.

In NFCIP-1 active communication the NFCIP-1Transport Frame format (see

Figure 23

) is

always used. Due to this the

bit nfc_f0 is set

by Analog Preset command (see

Support of NFCIP-1 transport frame format

NFCIP-1 active communication sequence when bit nfc_ar in the

set (automatic Response RF Collision Avoidance sequence). During this sequence bits

nfc_n1 and nfc_n0 of the

have to be 0 to produce Response

Collision Avoidance sequence with n=0:

1. The

direct command NFC Initial Field ON is sent. In case no collision was detected

during RF Collision Avoidance the field is switched on and an IRQ with I_cat flag set is

sent to controller after T

IRFG

2. The

message, prepared as in case of reader to tag communication, is transmitted using

Transmit command.

3. After

the message is sent the field is switched off. The time between the end of the

message and switching off the field is defined by the General Purpose timer (the

General Purpose timer IRQ may be masked since controller does not need this

information).

4. After

switching off its field the ST25R3912 starts the No-response timer and observes

the External Field Detector output to detect the switching on of the target field. In case

the target field is not detected before No-response timer timeout, an IRQ due No-

response timer expire is sent.

5. When

rget field is detected an IRQ with I_eon flag set is sent to controller and Mask

Receive timer is started. After the Mask Receive Timer expires the receiver output

starts to be observed to detect start of the target response. The reception process goes

on as in case of reader to tag communication.

6. When

the External Field Detector detects that the target has switched off its field, it

sends an IRQ with I_eof flag set to the controller, and in case bit nfc_ar is set

automatically activates the sequence of direct command NFC Response Field ON. In

case no collision is detected during RF Collision Avoidance the field is switched on and

an IRQ with I_cat flag set is sent to controller after T

ARFG

7. Sequence

loops through point 2. In case the last initiator command is sent in next

sequence (DLS_REQ in case of NFCIP-1 protocol) the bit nfc_ar in the

Mode definition

has to be put to 0 to avoid switching on the initiator field after the target has

switched of its field.

NFCIP-1 active communication target

The target mode is activated by setting bit targ in the

to 1. When

target mode is activated the External Field Detector is automatically enabled by setting bit

en_fd in the

When bit targ is set and all bits of the

are set to 0, the ST25R3912

is in low power Initial NFC

rget Mode.

In this mode the External Field Detector with Peer Detection Threshold is enabled.

There are two different NFC target modes implemented (defined by mode bits of the

Mode

): the bit rate detection mode and normal mode. In the bit rate detection

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Functional overview

mode the framing logic performs automatic detection of the initiator data rate and writes it in

the

. In the normal mode it is supposed that the

data rate defined in the

is used.

After selecting the NFCIP-1 active target mode the receiver and transmitter have to be

configured properly. Configuration is the same as in case of NFCIP-1 active initiator mode.

This configuration can be done automatically by sending direct command Analog Preset

(see Analog Preset).

NFCIP-1 active communication sequence when bit nfc_ar in the

set (automatic Response RF Collision Avoidance sequence). During this sequence bits

nfc_n1 and nfc_n0 of the

have to be 0 to produce Response

Collision Avoidance with n=0.

The following sequence assumes that the ST25R3912 is in the low power Initial NFC

rget

Mode with the bit rate detection mode selected. Bit nfc_ar in the

NFCIP Bit Rate Detection Display

set (automatic Response RF Collision Avoidance sequence). When the initiator field is

detected the following sequence is executed:

1. An

IRQ with I_eon flag set is sent to the controller.

2. The

controller turns on the oscillator, regulator and receiver. Mask Receive timer is

started by sending direct command Start Mask Receive timer Timer. After the Mask

Receive Timer expires the receiver output starts to be observed to detect start of the

initiator message.

3. Once

the start of initiator message is detected, an IRQ due to start of receive is sent,

the framing logic switches on a module that automatically recognizes the bit rate of

signal sent by the initiator. Once the bit rate is recognized an IRQ with I_nfct flag set is

sent and the bit rate is automatically loaded in the

. Detection of bit rate is also a condition that automatic Response RF Collision

Avoidance sequence is enabled). The received message is decoded and put into the

FIFO, IRQ is sent as after any received message.

4. The

controller sends direct command Go to Normal NFC Mode, to copy the content of

the

to the

and to

change the NFCIP-1 target mode to normal (the command Go

ormal Mode and

reading of received data can be chained). Since the Tx modulation type depends on bit

rate, the Tx modulation type also has to be correctly set at this point.

5. When

the External Field Detector detects that the target has switched off its field, it

sends an IRQ with I_eof flag set to the controller, and in case bit nfc_ar is set

automatically activates the sequence of direct command NFC Response Field ON. Bits

nfc_n1 and nfc_n0 of the

are used to define number n of

Response RF Collision Avoidance sequence. In case no collision is detected during RF

Collision Avoidance the field is switched on and an IRQ with I_cat flag set is sent to

controller after T

ARFG

6. The

reply, prepared as in case of reader to tag communication is transmitted using

Transmit command.

7. After

the message is sent the field is switched off. The time between the end of the

message and switching off the field is defined in the General Purpose timer (the

General Purpose timer IRQ may be masked since controller does not need this

information).

From this point on the communication with initiator loops through the following sequence

(during this sequence bits nfc_n1 and nfc_n0 of the

have to be 0

to produce Response RF Collision Avoidance with n=0):

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Functional overview

ST25R3912

1. After

switching off its field the ST25R3912 starts the No-response timer and observes

the External Field Detector output to detect the switching on of the initiator field. In case

the initiator field is not detected before No-response timer timeout, an IRQ due No-

response timer expire is sent.

2. When

initiator field is detected an IRQ with I_eon flag set is sent to controller and Mask

Receive timer is started. After the Mask Receive Timer expires the receiver output

starts to be observed to detect start of the initiator response. The reception process

goes on as in case of reader to tag communication.

3. When

the External Field Detector detects that the target has switched off its field, it

sends an IRQ with I_eof flag set to the controller, and in case bit nfc_ar is set

automatically activates the sequence of direct command NFC Response Field ON. In

case no collision is detected during RF Collision Avoidance the field is switched on and

an IRQ with I_cat flag set is sent to controller after T

ARFG.

4. The

reply that was prepared as in case of reader to tag communication is transmitted

using Transmit command

5. After

the message is sent the field is switched off. The time between the end of the

message and switching off the field is defined in General Purpose timer. In case a new

command from initiator is expected the General Purpose timer IRQ may be masked

since controller does not need this information.

6. If

a new command from Initiator is expected the sequence loops through point

. In

case the target reply was the last in a sequence (DLS_RES in case of NFCIP-1

protocol) a new command from initiator is not expected.



When the field is switched off, a General Purpose timer IRQ is received and the

ST25R3912 is put back in the low power NFC

rget Mode by deactivating the

. NFC mode is changed back to rate detection mode by

writing the

1.2.19

AM modulation depth: definition and calibration

The ST25R3912 transmitter supports OOK and AM modulation.

The choice between OOK and AM modulation is done by writing bit tr_am in the

Auxiliary

. AM modulation is preset by direct command Analog Preset in case the

following protocols are configured:



ISO14443B

™

FeliCa

NFCIP-1 212 and 424 kb/s

The AM modulation depth can be automatically adjusted by setting the

AM modulation

depth control register

and sending the direct command Calibrate Modulation Depth. There is

also an alternative possibility where the command Calibrate Modulation Depth is not used

and the modulated level is defined by writing the Antenna driver

RFO AM modulated level

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Functional overview

AM modulation depth definition using the direct command Calibrate

Modulation Depth

Before sending the direct command Calibrate Modulation Depth the

AM modulation depth

level definition register

has to be configured in the following way:



Bit 7 (am_s) has to be set to 0 to choose definition by the command Calibrate

Modulation Depth



Bits 6 to 1 (mod5 to mod0) define target AM modulation depth

Definition of modulation depth using bits mod5 to mod0

The RFID standard documents usually define the AM modulation level in form of the

modulation index. The modulation index is defined as (a – b) / (a + b), where a and b are,

respectively, the amplitude of the non-modulated carrier and of the modulated carrier.

The modulation index specification is different for different standards. The ISO-14443B

modulation index is typically 10% with allowed range from 8 to 14%, while range from 10 to

30% is defined in the ISO-15693, and 8 to 30% in the FeliCa™ and NFCIP-1 212 kb/s and

424 kb/s.

The bits mod5 to mod0 are used to calculate the amplitude of the modulated level. The



non-modulated level that was before measured by the A/D converter and stored in an 8 bit

binary decimals of this number.

Example

In case of the modulation index 10% the ratio between the non-modulated level (a) and the

modulated level (b) is 1.2222, which, converted to binary and truncated to six decimals is

1.001110. So, in order to define the modulation index 10% the bits mod5 to mod0 have to be

set to 001110.

ble 17

shows the setting of the mod bits and the associated modulation indexes.

Table 17. Setting mod bits

Modulation index (%)

mod5 … mod0

Modulation index (%)

mod5 … mod0

0.0

0.8

1.5

2.3

3.0

3.8

4.5

5.2

5.9

6.6

7.2

7.9

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

20.0

20.5

21.0

21.5

22.0

22.4

22.9

23.4

23.8

24.3

24.7

25.1

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

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Functional overview

ST25R3912

Table 17. Setting mod bits (continued)

Modulation index (%)

mod5 … mod0

Modulation index (%)

mod5 … mod0

8.6

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

25.6

26.0

26.4

26.9

27.3

27.7

28.1

28.5

28.9

29.3

29.7

30.1

30.4

30.8

31.2

31.6

31.9

32.3

32.6

33.0

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

9.2

9.9

10.5

11.1

11.7

12.3

12.9

13.5

14.1

14.7

15.2

15.8

16.3

16.9

17.4

17.9

18.5

19.0

19.5

Execution of direct command Calibrate Modulation Depth

The modulation level is adjusted by increasing the RFO1 and RFO2 driver output

resistance. The RFO drivers are composed of 8 binary weighted segments. Usually all these

segments are turned on to define the normal, non-modulated level, there is also a possibility

to increase the output resistance of the non-modulated state by writing the

RFO normal

Before sending the direct command Calibrate Modulation Depth the oscillator and

regulators have to be turned on. When the direct command Calibrate Modulation Depth is

sent the following procedure is executed:

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1. The

transmitter is turned on, non-modulated level is established.

2. The

amplitude of the non-modulated carrier level established on the inputs RFI1 and

RFI2 is measured by the A/D converter and stored in the

RFO normal level definition

3. Based

on the measurement of the non-modulated level and the target modulated level

defined by the bits mod5 to mod0 the target modulated level is calculated.

4. The

output driver strength is adjusted using a successive approximation algorithm until

the field strength is as close as possible to the calculated target modulated level.

5. The

result of the output driver strength adjustment is copied in the

AM modulation

depth display register

. Content of this register is used to define the AM modulated

level.

Note:

After the calibration procedure is finished, the content of the

must not be changed. Modifications of the content of this register will change the

non-modulated amplitude and therefore the ratio between the modulated and non-

modulated level.

In case the calibration of antenna resonant frequency in used, the command Calibrate

Antenna has to be run before AM modulation depth adjustment.

AM modulation depth definition using the RFO AM modulated level definition

When bit 7 (am_s) of the

is set to 1 the AM modulated

level is controlled by writing the

. If the setting of the

modulated level is already known it is not necessary to run the calibration procedure, the

modulated level can be defined just by writing this register.

It is also possible to implement calibration procedure through an external controller using

the

and the direct command Measure Amplitude. This

procedure has to be used when the target modulation depth is deeper than 33%.

The procedure is the following:

1. Write

the non-modulated level in the

(usually it is

all 0 to have the lower possible output resistance).

2. Switch

on the transmitter.

3. Send

the direct command Measure Amplitude. Read result from the

A/D converter

output register

4. Calculate

the target modulated level from the target modulation index and result of the

previous point.

5. In

the following iterations content of the

is modified,

the command Measure Amplitude executed and the result compared with the target

modulated level as long as the result is not equal (or as close as possible) to the target

modulated level.

6. At

the end the content of the

RFO AM modulated level definition register

that results in the

target modulated level is written in the

while the

is restored with the non-modulated

definition value.

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Functional overview

ST25R3912

1.2.20

Stream mode and Transparent mode

Standard and custom 13.56 MHz RFID reader protocols not supported by the ST25R3912

framing can be implemented using the ST25R3912 AFE and framing implemented in the

external microcontroller.

Transparent mode

After sending the direct command Transparent Mode the external microcontroller directly

controls the transmission modulator and gets the receiver output (control logic becomes

“transparent”).

The Transparent mode is entered on rising edge of signal /SS after sending the command

Transparent Mode and is maintained as long as the signal /SS is kept high. Before sending

the direct command Transparent Mode the transmitter and receiver have to be turned on,

the AFE has to be configured properly.

While the ST25R3912 is in the Transparent mode, the AFE is controlled directly through the

SPI:



Transmitter modulation is controlled by pin MOSI (high is modulator on)

Signal rx_on is controlled by pin SCLK (high enables RSSI and AGC)

Output of receiver AM demodulation chain (digitized sub-carrier signal) is sent to pin

MISO



Output of receiver PM demodulation chain (digitized sub-carrier signal) is sent to pin

IRQ

By controlling the rx_on advanced receiver features like the RSSI and AGC can be used.

The receiver channel selection bits are valid also in Transparent mode, therefore it is

possible to use only one of the two channel outputs. In case single channel is selected it is

always multiplexed to MISO, while IRQ is kept low.

Configuration bits related to the ISO mode, framing and FIFO are meaningless in

Transparent mode, while all other configuration bits are respected.

Use of Transparent mode to implement active Peer to Peer (NFC)

communication

The framing implemented in the ST25R3912 supports all active modes according to the

NFCIP-1 specification (ISO/IEC 18092:2004). In case any amendments to this specification

or some custom active NFC communication need to be implemented Transparent mode can

be used.

There is no special NFC active communication transparent mode, controlling of the Tx

modulation and the Rx is done as described above. The difference comparing to the reader

transparent mode is that the emission of the carrier field has to be enabled only during Tx.

This is done by writing the

before and after Tx. Since with every

SPI command the Transparent mode is lost it has to be re-entered.

In order to receive the reply in active NFC communication mode only the AM demodulation

channel is used. Due to this the receiver AM channel has to be enabled, while PM can be

disabled.

Implementing active communication requires detection of external field. Setting the bit en_fd

in the

enables the External Field Detector with Peer Detection

Threshold. When bit en_fd is selected and the ST25R3912 is in Transparent mode, the

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External Field Detector output is multiplexed to pin IRQ. This enables detection of external

target/initiator field and performing RF Collision Avoidance.

In case timing of the NFC Field ON command is correct for the NFC active protocol being

implemented, these commands can be used in combination with the Transparent mode.

These commands are used to perform the RF Collision Avoidance, switching on the field

and timing out the minimum time from switching on the field to start of transmitting the

message. After getting the interrupt, the controller generates the message in the

Transparent mode.

When bit en_fd is set and all bits of the

are set to 0 the

ST25R3912 is in the low power NFC

rget Mode (same as in case of setting of targ bit,

(see NFCIP-1 Active Communication

rget). In this mode initiator field is detected.

After getting an IRQ with I_eon flag set, the controller turns on the oscillator, regulator and

receiver and performs reception in the Transparent mode.

MIFARE™ Classic compatibility

For communication with MIFARE™ Classic compliant devices the bit6 and bit7 from the

ST25R3912 can be used to send and receive MIFARE™ Classic compliant or custom

frames.

Stream mode

Stream mode can be used to implement protocols, where the low level framing needed for

ISO14443 receive coding can be used and decoded information can be put in FIFO. The

main advantage of this mode over the Transparent mode is that timing is generated in the

ST25R3912 therefore the external controller does not have to operate in real time. The

stream mode is selected in the

Stream mode definition register

, the operating options are defined in

the

Two different modes are supported for tag to reader communication (Sub-carrier and BPSK

Stream Modes). General rule for Stream mode is that the first bit sent/received is put on the

LSB position of the FIFO byte.

After selecting the stream mode the receiver and transmitter have to be configured properly

(Analog Preset direct command doesn’t apply for stream mode).

Sub-Carrier Stream Mode

This mode supports protocols where during the tag to reader communication the time

periods with sub-carrier signal are interchanged with time periods without modulation (like in

the ISO14443A 106 kbit/s mode). In this mode the sub-carrier frequency and number of

sub-carrier frequency periods in one reporting period is defined. Sub-carrier frequencies in

the range from fc / 64 (212 kHz) to fc / 16 (848 kHz) are supported.

Supported number of sub-carrier frequency periods in one reporting period range from two

to eight.

Start of receive interrupt is sent and the first data bit is put in FIFO after the first reporting

time period with sub-carrier is detected. One bit of FIFO data gives information about status

of input signal during one reporting period. Logic 1 means that the sub-carrier was detected

during reporting period, while 0 means that no modulation was detected during reporting

period. End of receive is reported when no sub-carrier signal in more than eight reporting

periods have been detected.

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Functional overview

ST25R3912

Figure 24

shows an example for setting scf = 01b and scp = 10b. With this setting the



sub-carrier frequency is set to fc / 32 (424 kHz) and the reporting period to four sub-carrier

periods (128 / fc ~106

s).

Figure 24. Example of sub-carrier stream mode for scf = 01b and scp = 10b

Data in

FIFO

Input

signal

fc/32

fc/128

MS42420V1

BPSK Stream Mode

This mode supports protocols where during the tag to reader communication BPSK code is

used (like in the ISO14443B mode).

In this mode the sub-carrier frequency and number of sub-carrier frequency periods in one

reporting period is defined. Sub-carrier frequency fc / 16 (848 kHz) is supported. Supported

number of sub-carrier frequency periods in one reporting period range from one to eight.

Start of receive interrupt is sent and the first data bit is put in FIFO after the first reporting

time period with sub-carrier is detected. Logic 0 is used for the initially detected phase, while

logic 1 indicates inverted phase comparing to the initial phase.

End of receive is reported when the first reporting period without sub-carrier is detected.

Reader to Tag Communication in Stream Mode

Reader to tag communication control is the same for both stream modes. Reader to tag

coding is defined by data put in FIFO. The stx bits of

Stream mode definition register

define

the Tx time period during which one bit of FIFO data define the status of transmitter. In case

the data bit is set to logic 0 there is no modulation, in case it is logic 1 the transmitted carrier

signal is modulated according to current modulation type setting (AM or OOK).

Transmission in stream mode is started by sending direct commands Transmit Without CRC

or Transmit With CRC.

Figure 25

shows an example for setting stx = 000b. With this setting the Tx time period is

defined to 128/fc (~9,44

s).

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Figure 25. Example of Tx in Stream Mode for stx = 000b and OOK modulation

Data in

FIFO

Input

signal

fc/128

MS42421V1

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ST25R3912

1.3

Registers

The 6-bit register addresses below are defined in hexadecimal notation. The possible

addresses range from 00h to 3Fh.

There are two types of registers implemented, namely configuration and display registers.

The configuration registers are used to configure the ST25R3912. They can be read and

written (RW) through the SPI. The display registers are read only (R); they contain

information about the ST25R3912 internal state.

Registers are set to their default state at power-up and after sending direct command Set

Default. The exceptions are

IO Configuration register 1

and

IO Configuration register 1

. These registers are related to the hardware configuration and are

reset to their default state only at power-up.

Table 18. Registers map

Address

Main function

Content

Comment

Type

(hex)

Set to default state

only at power-up

IO configuration

Set to default state

only at power-up

Operatio

ontrol

and

Mode definition

ISO14443A and NFC 106kb/s settings

–

–

ISO14443B settings register 1

Stream mode definition register

Receiver configuration register 1

–

Configuration

Receiver configuration register 2

Mask receive timer register

No-response timer register 1

No-response timer register 2

Timer definition

General purpose and no-response timer

General purpose timer register 1

–

General purpose timer register 2

–

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Table 18. Registers map (continued)

Content

Address

(hex)

Main function

Comment

Type

Mask timer and NFC interrupt register

–

Mask error and wake-up interrupt register

Mask timer and NFC interrupt register

Interrupt and

associated

reporting

Error and wake-up interrupt register

Collision display register

Number of transmitted bytes register 2

Definition of

transmitted bytes

NFCIP bit rate

detection display

–

A/D converter

output

AM modulation depth display register

RFO AM modulated level definition register

–

AM modulation

depth and

Antenna driver

External field

detector

–

threshold

Regulator and timer display register

–

Regulator

Gain reduction state register

Receiver State

display

–

Reserved

Auxiliary display

Wake-up timer control register

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112

ST25R3912

Table 18. Registers map (continued)

Content

Address

(hex)

Main function

Comment

Type

–

Amplitude measurement configuration

Wake-Up

Amplitude measurement reference register

Amplitude measurement auto-averaging

Amplitude measurement display register

Phase measurement configuration register

Phase measurement reference register

–

Phase measurement auto-averaging

Phase measurement display register

–

–

Reserved

IC Identity

–

IC Identity register

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1.3.1

IO configuration register 1

Address: 00h

Type: RW

(1)

Table 19. IO Configuration register 1

Bit

Name

Default

Function

Comments

Choose between single and

differential antenna driving

single

1: Only one RFO driver will be used

Choose which output driver and

which input will be used in case of

single driving

0: RFO1, RFI1

1: RFO2, RFI2

rfo2

0: 64

1: 80

fifo_lr

fifo_lt

osc

FIFO water level for receive

FIFO water level for transmit

Selector for crystal oscillator

0: 32

1: 16

0: 13.56 MHz Xtal

1: 27.12 MHz Xtal

out_cl1

out_cl0 MCU_CLK

Selection of clock frequency on

MCU_CLK output in case Xtal

6.78 MHz

oscillator is running. In case of “11”

out_cl1

out_cl0

3.39 MHz

MCU_CLK output is permanently

low.

13.56 MHz

disabled

By default the 32 kHz LF clock is

present on MCU_CLK output when

Xtal oscillator is not running and the

MCU_CLK output is not disabled.

lf_clk_off

1: No LF clock on MCU_CLK

1. Default

setting takes place at power-up only.

DS11794 Rev 7

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112

ST25R3912

1.3.2

IO configuration register 2

Address: 01h

Type: RW

(1)

Table 20. IO configuration register 2

Function

Bit

Name

Default

Comments

0: 5 V supply

5 V supply, range: 4.1 V to 5.5 V

3.3 V supply, range: 2.4 V to 3.6 V

sup3 V

1: 3.3 V supply

Used for low cost applications. When this

bit is set:

– At 3 V or 5 V supply VSP_D and VSP_A

shall be shorted externally

vspd_off

1: Disable VSP_D regulator

– For 3.3 V applications VSP_D can

alternatively be supplied from V

in case

SP_A

is not more than 300 mV lower

then V

–

Not used

–

1: Pull-down on MISO, when /SS is low

and MISO is not driven by the

ST25R3912

miso_pd2

–

miso_pd1

io_18

1: Pull-down on MISO when /SS is high

–

1: Increase MISO driving level in case

of 1.8 V V

DD_IO

–

Not used

–

slow_up

1: Slow ramp at Tx on

≥

10 µs, 10% to 90%, for B

1. Default

setting takes place at power-up only.

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DS11794 Rev 7

ST25R3912

1.3.3

Operation control register

Address: 02h

Type: RW

(1)

Table 21. Operation control register

Function

Bit

Name

Default

Comments

1: Enables oscillator and regulator

(Ready mode)

–

rx_en

1: Enables Rx operation

0: Both, AM and PM, channels

enabled

1: One channel enabled

In case only one Rx channel is enabled,

selection is done by the

Receiver configuration

bit ch_sel

rx_chn

In case both Rx channels are enabled, it

chooses the method of channel selection,

manual selection is done by the

bit ch_sel

0: Automatic channel selection

1: Manual channel selection

rx_man

This bit is automatically set by NFC Field ON

commands and reset in NFC active

communication modes after transmission is

finished

tx_en

1: Enables Tx operation

According to settings in

Wake-up timer control

1: Enables Wake-up mode

Not used

–

1. Default

setting takes place at power-up only.

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ST25R3912

1.3.4

Mode definition register

Address: 03h

Type: RW

(1)

Table 22. Mode definition register

Function

Bit

Name

Default

Comments

0: Initiator

rget

targ

–

om3

om2

om1

om0

–

Selection of operation mode

Refer to

Table 23

and

Table 24

Different for initiator and target modes

–

Not used

–

1: Automatic start Response RF

Collision Avoidance sequence

Automatically starts the Response RF Collision

Avoidance if an external field off is detected

nfc_ar

1. Default

setting takes place at power-up and after Set Default command.

(1)

Table 23. Initiator operation modes

om1 om0

om3

om2

Comments

NFCIP-1 active communication

ISO14443A

ISO14443B

FeliCa

™

NFC Forum Type 1

g (

paz)

Sub-carrier stream mode

BPSK stream mode

Not used

Other combinations

1. If

a non supported operation mode is selected the Tx/Rx operation is disabled.

(1)

Table 24. Target Operation Modes

om3

om2

om1

om0

Comments

NFCIP-1 active communication,

bit rate detection mode

NFCIP-1 active communication,

normal mode

Other combinations

Not used

1. If

a non supported operation mode is selected the Tx/Rx operation is disabled.

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DS11794 Rev 7

ST25R3912

1.3.5

Bit rate definition register

Address: 04h

Type: RW

(1)(2)

Table 25. Bit rate definition register

Function

Bit

Name

Default

Comments

tx_rate3

tx_rate2

tx_rate1

tx_rate0

rx_rate3

rx_rate2

rx_rate1

rx_rate0

Selects bit rate for Tx

Refer to

Table 26

Selects bit rate for Rx in case selected protocol

allows different bit rates for Rx and Tx

1. Default

setting takes place at power-up and after Set Default command.

2. Automatically

loaded by direct command Go to Normal NFC Mode.

(1)

Table 26. Bit rate coding

Bit rate (kbit/s)

rate3

rate2

rate1

rate0

Comments

fc / 128 (~106)

fc / 64 (~212)

fc / 32 (~424)

fc / 16 (~848)

–

Other combinations

Not used

1. If

a non supported bit rate is selected the Tx/Rx operation is disabled.

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ST25R3912

1.3.6

ISO14443A and NFC 106kb/s settings register

Address: 05h

Type: RW

(1)

Table 27. ISO14443A and NFC 106kb/s settings register

Bit

Name

Default

Function

Comments

1: No parity bit is generated

during Tx

Data stream is taken from FIFO, transmit has to

be done using command Transmit Without CRC.

no_tx_par

(2)

When set to 1 received bit stream is put in the

FIFO, no parity and CRC detection is done, must

be set to 0 when not in ISO14443A mode.

1: Receive without parity and

CRC

no_rx_par

(2)

nfc_f0

1: Support of NFCIP-1 Transport

Add SB (F0) and LEN bytes during Tx and skip

Frame format

SB (F0) byte during Rx.

p_len3

p_len2

p_len1

p_len0

Modulation pulse width, defined in number of

13.56 MHz clock periods.

Refer to

Table 28

Must be set to 1 when ISO14443A bit oriented

anticollision frame is sent.

antcl

1: ISO14443 anticollision frame

1. Default

setting takes place at power-up and after Set Default command.

2. no_tx_par

and no_rx_par are used to send and receive custom frames like Mifare™ Classic frames.

Table 28. ISO14443A modulation pulse width

Pulse width in number of 1/fc for different bit rates

p_len3

p_len2

p_len1

p_len0

fc / 128

fc / 64

fc / 32

fc / 16

–

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DS11794 Rev 7

ST25R3912

Table 28. ISO14443A modulation pulse width (continued)

Pulse width in number of 1/fc for different bit rates

p_len3

p_len2

p_len1

p_len0

fc / 128

fc / 64

fc / 32

fc / 16

–

1.3.7

ISO14443B settings register 1

Address: 06h

Type: RW

(1)

Table 29. ISO14443B settings register 1

Function

Bit

Name Default

Comments

egt2

egt1

egt0

Number of etu

egt2

egt1

egt0

EGT defined in number of etu

0: 10 etu



1: 11 etu

sof_0

sof_1

eof

umber of etu with logic 0 (10 or 11)

umber of etu with logic 1 (2 or 3)

umber of etu with logic 0 (10 or 11)

0: 2 etu



1: 3 etu

0: 10 etu



1: 11 etu

0: SO

nd EOF defined by sof_0, sof_1,

and eof bit



1: SOF 10.5, 2.5, EOF: 10.5

Sets SOF and EOF settings in middle of

specification

half

0: Start/stop bit must be present for Rx



1: Start/stop bit omission for Rx

SOF= fixed to 10 low – 2 high, EOF not

defined, put in FIFO last full byte

(2)

rx_st_om

1. Default

setting takes place at power-up and after Set Default command.

2. Start/stop

bit omission for Tx can be implemented by using Stream mode.

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ST25R3912

1.3.8

ISO14443B and FeliCa settings register

Address: 07h

Type: RW

(1)

Table 30. ISO14443B and FeliCa settings register

Bit

Name

Default

Function

Comments

tr1_1

tr1_0

Refer to

Table 31

–

According to ISO14443-3 chapter 7.10.3.3

Support of B’

no_sof

no_eof

eof_12

1: No SOF PICC to PCD

1: No EOF PICC to PCD

According to ISO14443-3 chapter 7.10.3.3

Support of B

(2)

0: PICC EOF 10 to 11 etu

1: PICC EOF 10 to 12 etu

1: Increased tolerance of phase

change detection

phc_th

f_p1

–

00: 48

01: 64

10: 80

11: 96

FeliCa preamble length (valid also for NFCIP-1

active communication bit rates 242 and 484 kb/s)

f_p0

1. Default

setting takes place at power-up and after Set Default command.

2. Detection

of EOF requires larger tolerance range for bit rates with only one sub-carrier frequency period per bit (fc / 16 and

higher). Due to this it is not possible to distinguish between EOF with 11 and 12 etu and setting this bit has no impact on

EOF detection.

Table 31. Minimum TR1 codings

Minimum TR1 for a PICC to PCD Bit Rate

tr1_1

tr1_0

fc / 128

>fc / 128

80 / fs

64 / fs

80 / fs

32 / fs

Not used

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DS11794 Rev 7

ST25R3912

1.3.9

Stream mode definition register

Address: 08h

Type: RW

(1)

Table 32. Stream Mode Definition register

Bit

Name Default

Function

Comments

–

scf1

scf0

Sub-carrier frequency definition for Sub-

carrier and BPSK stream mode

Refer to

Table 33

scp1

scp0 Number

of pulses

scp1

1 (BPSK only)

Number of sub-carrier pulses in report period

for Sub-carrier and BPSK stream mode

scp0

stx2

stx1

stx0

Definition of time period for Tx modulator

control (for Sub-carrier and BPSK stream

mode)

Refer to

Table 34

1. Default

setting takes place at power-up and after Set Default command.

Table 33. Sub-carrier frequency definition for Sub-Carrier and BPSK stream mode

scf1

scf0

Sub-Carrier Mode

BPSK Mode

fc / 64 (212 kHz)

fc / 32 (424 kHz)

fc / 16 (848 kHz)

Not used

fc / 16 (848 kHz)

Not used

Table 34. Definition of time period for Stream mode Tx modulator control

stx2

stx1

stx0

Time period

fc / 128 (106 kHz)

fc / 64 (212 kHz)

fc / 32 (424 kHz)

fc / 16 (848 kHz)

Not used

DS11794 Rev 7

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1.3.10

Auxiliary definition register

Address: 09h

Type: RW

(1)

Table 35. Auxiliary definition register

Bit

Name

Default

Function

Comments

Valid for all protocols, for ISO14443A REQA,

WUPA and anticollision receive without CRC is

done automatically

(2)

no_crc_rx

1: Receive without CRC

1: Make CRC check, but put

CRC bytes in FIFO and add

them to number of receive bytes

crc_2_fifo

tr_am

Needed for EMV compliance

Set automatically by command Analog Preset,

can be modified by register write, has to be

defined for transparent and bit stream mode Tx

0: OOK



1: AM

External Field Detector with Peer Detection

threshold is activated.

1: Enable External Field

Detector

en_fd

Preset for NFCIP-1 active communication mode.

1: Put RFO driver in tristate

during OOK modulation

Valid for all protocols using OOK modulation

(also in transparent mode)

ook_hr

1: BPSK fc / 32: more tolerant

BPSK decoder for bit rate fc / 32,

ISO14443A fc / 128, NFCIP-1 fc

/ 128: more tolerant processing

of first byte

rx_tol

–

nfc_n1

nfc_n0

Value of n for direct commands NFC Initial Field

ON and NFC Response Field ON (0 … 3)

–

1. Default

setting takes place at power-up and after Set Default command.

2. Receive

without CRC is done automatically when REQA and WUPA commands are sent using direct commands Transmit

REQA and Transmit WUPA, respectively, and in case anticollision is performed setting bit antcl.

80/130

DS11794 Rev 7

ST25R3912

1.3.11

Receiver configuration register 1

Address: 0Ah

Type: RW

(1)

Table 36. Receiver configuration register 1

Bit

Name

Default

Function

Comments

If only one Rx channel is enabled in the

and no-response timer control

it defines which

channel is enabled.

0: Enable AM channel

1: Enable PM channel

ch_sel

If both channels are enabled and manual

channel selection is active, it defines which

channel is used for receive framing.

0: Peak detector

1: Mixer

AM demodulator type select



amd_sel

lp2

lp1

Low pass control (see

ble 2

)

lp0

For automatic and other recommended filter

settings, refer to

ble 3

h200

h80

z12k

First and third stage zero setting

(see

Table 1

)

1. Default

setting takes place at power-up and after Set Default command.

DS11794 Rev 7

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ST25R3912

1.3.12

Receiver configuration register 2

Address: 0Bh

Type: RW

(1)

Table 37. Receiver configuration register 2

Function

Bit

Name

Default

Comments

rx_lp

1: Low power receiver operation

0: Differential LF operation

–

lf_op

–

1: LF input split (RFI1 to AM

channel, RFI2 to PM channel)

lf_en

1: LF signal on receiver input

1: AGC is enabled

–

agc_en

0: AGC operates on first eight

sub-carrier pulses

agc_m

–

1: AGC operates during

complete receive period

Algorithm with preset is recommended for

protocols with short SOF (like ISO14443A fc /

128)

0: Algorithm with preset is used

1: Algorithm with reset is used

agc_alg

1: Automatic squelch activation

Squelch is started 18.88 µs after end of Tx, and

sqm_dyn

pmix_cl

after end of Tx

stopped when Mask Receive Timer expires

0: RFO

PM demodulator mixer clock source, in single

mode internal signal is always used

1: Internal signal

1. Default

setting takes place at power-up and after Set Default command.

82/130

DS11794 Rev 7

ST25R3912

1.3.13

Receiver configuration register 3

Address: 0Ch (1

stage gain settings)

Type: RW

(1)

Table 38. Receiver configuration register 3

Function

Bit

Name

Default

Comments

rg1_am2

rg1_am1

rg1_am0

rg1_pm2

rg1_pm1

rg1_pm0

0: Full gain

Gain reduction/boost in first gain

stage of AM channel.

1-6: Gain reduction 2.5 dB per step (15 dB total)

7: Boost +5.5 dB

0: Full gain

Gain reduction/boost in first gain

stage of PM channel.

1-6: Gain reduction 2.5 dB per step (15 dB total)

7: Boost +5.5 dB

1: Clip output of 1

and 2

stage

Signal clipped to 0.6 V, preset for NFCIP-1 active

communication mode

lim

1: Forces gain reduction in 2

and 3

gain stage to -6 dB and

maximum comparator window

Preset for NFCIP-1 active communication mode.

After clearing this bit, receiver must be restarted.

rg_nfc

1. Default

setting takes place at power-up and after Set Default command.

1.3.14

Receiver configuration register 4

Address: 0Dh (2

and 3

stage gain settings)

Type: RW

(1)(2)

Table 39. Receiver configuration register 4

Bit

Name

Default

Function

Comments

rg2_am3

rg2_am2

rg2_am1

rg2_am0

rg2_pm3

rg2_pm2

rg2_pm1

rg2_pm0

Only values from 0h to Ah are used:

– settings 1h to 4h reduce gain by increasing the

digitizer window in 3dB steps

AM channel: Gain reduction in

second and third stage and

digitizer

– values from 5h to Ah additionally reduce the

gain in 2

and 3

gain stage, always in 3 dB

steps.

Only values from 0h to Ah are used:

– settings 1h to 4h reduce gain by increasing the

digitizer window in 3dB steps

PM channel: Gain reduction in

second and third stage and

digitizer

– values from 5h to Ah additionally reduce the

gain in 2

and 3

gain stage, always in 3 dB

steps.

1. Default

setting takes place at power-up and after Set Default command.

2. Sending

of direct command Reset Rx Gain is necessary to load the value of this register into AGC, Squelch, and RSSI

block.

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ST25R3912

1.3.15

Mask receive timer register

Address: 0Eh

Type: RW

(1)(2)

Table 40. Mask receive timer register

Function

Bit

Name

Default

Comments

mrt7

mrt6

mrt5

mrt4

mrt3

mrt2

mrt1

mrt0

Defined in steps of 64/fc (4.72

µs).

Defines time after end of Tx during which

receiver output is masked (ignored).

Range from 256/fc (~18.88 µs)

to 16320/fc (~1.2 ms)

For the case of ISO14443A 106 kbit/s the Mask

Receive timer is defined according to PCD to

PICC frame delay time definition, where bits

mrt<7:0> define the number of n/2 steps.

Timeout = mrt<7:0> * 64/fc

Timeout (0

≤

mrt<7:0>

≤

4) = 4 *

64/fc (18.88 µs)

Minimum mask receive time of 18.88 µs covers

the transients in receiver after end of

transmission.

In NFCIP-1 bit rate detection

mode one step is 512/fc

(37.78 µs)

1. Default

setting takes place at power-up and after Set Default command.

2. In

NFCIP-1 bit rate detection mode, the clock of the Mask Receive timer is additionally divided by eight (one count is 512/fc)

to cover range up to ~9.6 ms.

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DS11794 Rev 7

ST25R3912

1.3.16

No-response timer register 1

Address: 0Fh

Type: RW

(1)

Table 41. No-response timer register 1

Bit

Name

Default

Function

Comments

nrt15

nrt14

nrt13

nrt12

nrt11

nrt10

nrt9

Defines timeout after end of Tx. In case this

timeout expires without detecting a response a

No-response interrupt is sent.

No-response timer definition



MSB bits

In NFC mode the No-response timer is started

only when external field is detected. In the

NFCIP-1 active communication mode the



No-Response timer is automatically started when

the transmitter is turned off after the message has

been sent.

Defined in steps of 64/fc (4.72 µs).



Range from 0 to 309 ms

If bit nrt_step in

General purpose

is set the step is changed

to 4096/fc

All 0: No-response timer is not started.

No-response timer is reset and restarted with

Start No-Response Timer direct command.

nrt8

1. Default

setting takes place at power-up and after Set Default command.

1.3.17

No-response timer register 2

Address: 10h

Type: RW

(1)

Table 42. No-response timer register 2

Bit

Name

Default

Function

Comments

nrt7

nrt6

nrt5

nrt4

nrt3

nrt2

nrt1

nrt0

No-response timer definition

LSB bits

–

1. Default

setting takes place at power-up and after Set Default command.

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ST25R3912

1.3.18

General purpose and no-response timer control register

Address: 11h

Type: RW

(1)

Table 43. General purpose and no-response timer control register

Bit

Name

Default

Function

Comments

gptc2

–

Defines the timer trigger source.



Refer to

Table 44

gptc1

gptc0

–

nrt_emv

1: EMV mode of No-response timer

0: 64/fc

nrt_step

Selects the No-response timer step.

1: 4096/fc

1. Default

setting takes place at power-up and after Set Default command.

Table 44. Timer trigger sources

gptc2

gptc1

gptc0

Trigger source

No trigger source, start only with direct command Start

General Purpose Timer.

End of Rx (after EOF)

Start of Rx

End of Tx in NFC mode, when General Purpose Timer

expires the field is switched off

Not used

86/130

DS11794 Rev 7

ST25R3912

1.3.19

General purpose timer register 1

Address: 12h

Type: RW

(1)

Table 45. General purpose timer register 1

Function

Bit

Name

Default

Comments

gpt15

gpt14

gpt13

gpt12

gpt11

gpt10

gpt9

–

General purpose timeout

definition MSB bits

–

Defined in steps of 8/fc (590 ns)

Range from 590 ns to 38,7 ms

gpt8

1. Default

setting takes place at power-up and after Set Default command.

1.3.20

General purpose timer register 2

Address: 13h

Type: RW

(1)

Table 46. General purpose timer register 2

Function

Bit

Name

Default

Comments

gpt7

gpt6

gpt5

gpt4

gpt3

gpt2

gpt1

gpt0

–

General purpose timeout

definition LSB bits

–

Defined in steps of 8/fc (590 ns)

Range from 590 ns to 38,7 ms

1. Default

setting takes place at power-up and after Set Default command.

DS11794 Rev 7

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112

ST25R3912

1.3.21

Mask main interrupt register

Address: 14h

Type: RW

(1)

Table 47. Mask main interrupt register

Function

Bit

Name

Default

Comments

M_osc

M_wl

M_rxs

M_rxe

M_txe

M_col

–

1: Mask IRQ when oscillator frequency is stable

1: Mask IRQ due to FIFO water level

1: Mask IRQ due to start of receive

1: Mask IRQ due to end of receive

1: Mask IRQ due to end of transmission

1: Mask IRQ due to bit collision

–

Not used

–

1. Default

setting takes place at power-up and after Set Default command.

1.3.22

Mask timer and NFC interrupt register

Address: 15h

Type: RW

(1)

Table 48. Mask timer and NFC interrupt register

Default Function

Bit

Name

Comments

M_dct

M_nre

M_gpe

1: Mask IRQ due to termination of direct command

1: Mask IRQ due to No-response timer expire

1: Mask IRQ due to general purpose timer expire

–

1: Mask IRQ due to detection of external field higher

than

rget activation level

M_eon

M_eof

–

1: Mask IRQ due to detection of external field drop

below

rget activation level

1: Mask IRQ due to detection of collision during RF

Collision Avoidance

M_cac

M_cat

M_nfct

–

1: Mask IRQ after minimum guard time expire

1: Mask IRQ when in target mode the initiator bit

rate was recognized

1. Default

setting takes place at power-up and after Set Default command.

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DS11794 Rev 7

ST25R3912

1.3.23

Mask error and wake-up interrupt register

Address: 16h

Type: RW

(1)

Table 49. Mask error and wake-up interrupt register

Bit

Name

Default

Function

1: Mask IRQ due to CRC error

Comments

M_crc

M_par

–

1: Mask IRQ due to parity error

M_err2

M_err1

M_wt

1: Mask IRQ due to soft framing error

1: Mask IRQ due to hard framing error

1: Mask IRQ due to wake-up timer interrupt

1: Mask Wake-up IRQ due to amplitude measurement

1: Mask Wake-up IRQ due to phase measurement.

M_wam

M_wph

M_wcap

1: Mask Wake-up IRQ due to capacitance measurement

1. Default

setting takes place at power-up and after Set Default command.

1.3.24

Main interrupt register

Address: 17h

Type: R

(1)(2)

Table 50. Main interrupt register

Function

Bit Name

Default

Comments

Set after oscillator is started by setting

Operation

Timer and NFC interrupt register

bit en.

I_osc

–

IRQ when oscillator frequency is stable

Set during receive, informing that FIFO is almost

full and has to be read out.

I_wl

–

IRQ due to FIFO water level

Set during transmit, informing that FIFO is almost

empty and that additional data has to be sent.

I_rxs

I_rxe

I_txe

I_col

I_tim

I_err

–

IRQ due to start of receive

IRQ due to end of receive

–

IRQ due to end of transmission

IRQ due to bit collision

–

IRQ due to timer or NFC event

IRQ due to error and wake-up timer

Details in

Details in

Error and wake-up interrupt register

1. At

power-up and after Set Default command content of this register is set to 0.

2. After

the register has been read, its content is set to 0, except for bits 1 and 0, which are set to 0 after corresponding

interrupt register is read.

DS11794 Rev 7

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112

ST25R3912

1.3.25

Timer and NFC interrupt register

Address: 18h

Type: R

(1)(2)

Table 51. Timer and NFC interrupt register

Function

Bit

Name

Default

Comments

IRQ due to termination of direct

command

I_dct

–

IRQ due to No-Response Timer

expire

I_nre

I_gpe

–

IRQ due to general purpose

timer expire

IRQ due to detection of external

field higher than

rget

activation level

I_eon

–

IRQ due to detection of external

field drop below

rget activation

level

I_eof

I_cac

–

IRQ due to detection of collision

An external field was detected during RF

during RF Collision Avoidance

Collision Avoidance

An external field was not detected during RF

Collision Avoidance, field was switched on, IRQ

is sent after minimum guard time according to

NFCIP-1

IRQ after minimum guard time

expire

I_cat

–

IRQ when in target mode the

initiator bit rate was recognized

I_nfct

–

1. At

power-up and after Set Default command content of this register is set to 0.

2. After

Main interrupt register has been read, its content is set to 0.

90/130

DS11794 Rev 7

ST25R3912

1.3.26

Error and wake-up interrupt register

Address: 19h

Type: R

(1)(2)

Table 52. Error and wake-up interrupt register

Default Function

Comments

Bit

Name

I_crc

I_par

–

CRC error

Parity error

–

Framing error which does not result in corrupted

Rx data

I_err2

I_err1

–

Soft framing error

Hard framing error

Framing error which results in corrupted Rx data

Timeout after execution of Start Wake-Up Timer

command

I_wt

–

Wake-up timer interrupt

In case option with IRQ at every timeout is

selected

Wake-up interrupt due to

amplitude measurement

Result of amplitude measurement was

∆

larger than reference

I_wam

I_wph

l_wcap

–

Wake-up interrupt due to phase

Result of phase measurement was

∆

pm larger

measurement.

than reference

Wake-up interrupt due to

capacitance measurement

Result of capacitance measurement was

∆

larger than reference

1. At

power-up and after Set Default command content of this register is set to 0.

2. After

Main interrupt register has been read, its content is set to 0.

DS11794 Rev 7

91/130

112

ST25R3912

1.3.27

FIFO status register 1

Address: 1Ah

Type: R

(1)

Table 53. FIFO status register 1

Bit

Name

Default

Function

Comments

–

fifo_b6

fifo_b5

fifo_b4

fifo_b3

fifo_b2

fifo_b1

fifo_b0

Valid range is from 0 (000 0000b) to 96



Number of bytes (binary coded)

in the FIFO which were not read

out

(110 0000b)

1. At

power-up and after Set Default command content of this register is set to 0.

1.3.28

FIFO status register 2

Address: 1Bh

Type: R

(1)(2)(3)

Table 54. FIFO status register 2

Bit

Name

Default

Function

Comments

–

Set when more bytes then actual content of FIFO

were read

fifo_unf

fifo_ovr

fifo_ncp

–

1: FIFO underflow

1: FIFO overflow

–

1: Last FIFO byte is not

complete

fifo_lb<2:0> and np_lb indicate the number of

valid bits received in the incomplete byte

fifo_lb2

fifo_lb1

fifo_lb0

–

Number of bits in the last FIFO

byte if it was not complete

(fifo_ncp=1)

The received bits are stored in the LSB part of

the last byte in the FIFO

1: Parity bit is missing in last

byte

np_lb

–

This is a framing error

1. At

power-up and after Set Default command content of this register is set to 0.

2. If

FIFO is empty, the value of

(0x1Ah) is 0x00, register bits fifo_ncp, fifo_lb2, fifo_lb1 and fifo_lb0 in

e cleared.

3. Correct

procedure for FIFO read is to read both

and

in MCU because bits fifo_nc

, and then read FIFO.

Second register values need to be saved

p, fifo_lb<2:0>, and np_lb ar

e cleared automatically

at readout.

92/130

DS11794 Rev 7

ST25R3912

1.3.29

Collision display register

Address: 1Ch

Type: R

(1)

Table 55. Collision display register

Bit

Name

Default

Function

Comments

c_byte3

c_byte2

c_byte1

c_byte0

c_bit2

–

Number of full bytes before the

bit collision happened.

The

Collision display register

range covers

ISO14443A anticollision command. In case

collision (or framing error that is interpreted as

collision) happens in a longer message, the

Collision display register

is not set.

Number of bits before the

collision in the byte where the

collision happened

c_bit1

c_bit0

This is an error, reported in case it is the first

collision detected

c_pb

–

1: Collision in parity bit

1. At

power-up and after Set Default command content of this register is set to 0.

1.3.30

Number of transmitted bytes register 1

Address: 1Dh

Type: RW

(1)

Table 56. Number of transmitted bytes register 1

Bit

Name

Default

Function

Comments

ntx12

ntx11

ntx10

ntx9

Number of full bytes to be

transmitted in one command,

MSB bits

Maximum supported number of bytes is 8191

ntx8

ntx7

ntx6

ntx5

1. Default

setting takes place at power-up and after Set Default command.

DS11794 Rev 7

93/130

112

ST25R3912

1.3.31

Number of transmitted bytes register 2

Address: 1Eh

Type: RW

(1)(2)

Table 57. Number of transmitted bytes register 2

Bit

Name

Default

Function

Comments

ntx4

ntx3

Number of full bytes to be

transmitted in one command,

MSB bits

ntx2

Maximum supported number of bytes is 8191

Applicable for ISO14443A:

ntx1

ntx0

nbtx2

nbtx1

Number of bits in the split byte

Bit oriented anticollision frame in case last byte is

split byte

000 means that there is no split

byte (all bytes all complete)

nbtx0

Tx is done without parity bit generation

1. Default

setting takes place at power-up and after Set Default command.

2. If

anctl bit is set while card is in idle state and nbtx is not 000, then i_par will be triggered during WUPA direct command is

issued.

1.3.32

NFCIP Bit Rate Detection Display register

Address: 1Fh

Type: R

(1)

Table 58. NFCIP Bit Rate Detection Display register

Bit

Name

Default

Function

Comments

nfc_rate3

–

This register stores result of automatic bit rate

detection in the NFCIP-1 active communication

bit rate detection mode

nfc_rate2

Refer to

ble 26

nfc_rate1

nfc_rate0

–

Not used

–

1. At

power-up and after Set Default command content of this register is set to 0.

94/130

DS11794 Rev 7

ST25R3912

1.3.33

A/D converter output register

Address: 20h

Type: R

(1)

Table 59. A/D converter output register

Function

Bit

Name

Default

Comments

ad7

ad6

ad5

ad4

ad3

ad2

ad1

ad0

–

Displays result of last A/D

conversion.

–

1. At

power-up and after Set Default command, see

ble 9

, content of this register is set to 0.

1.3.34

Reserved register

Address: 21h

Type: R

Table 60. Reserved register

Function

Bit

Name

Default

Comments

–

DS11794 Rev 7

95/130

112

ST25R3912

1.3.35

Reserved register

Address: 22h

Type: RW

Table 61. Reserved register

Function

Bit

Name

Default

Comments

–

1.3.36

Reserved register

Address: 23h

Type: R

Table 62. Reserved register

Function

Bit

Name

Default

Comments

–

96/130

DS11794 Rev 7

ST25R3912

1.3.37

AM modulation depth control register

Address: 24h

Type: RW

(1)

Table 63. AM modulation depth control register

Default Function

Bit

Name

Comments

0: AM modulated level is defined

by bits mod5 to mod0. Level is

adjusted automatically by

Calibrate Modulation Depth

command, see

Table 9

am_s

–

1: AM modulated level is defined

by bits dram7 to dram0.

mod5

mod4

mod3

mod2

mod1

mod0

–

MSB

–

See

Section 1.2.19: AM modulation depth:

definition and calibration

for details about AM

modulation level definition.

–

LSB

–

1. Default

setting takes place at power-up and after Set Default command.

1.3.38

AM modulation depth display register

Address: 25h

Type: R

(1)

Table 64. AM modulation depth display register

Bit

Name

Default

Function

Comments

md_7

md_6

md_5

md_4

md_3

md_2

md_1

md_0

–

MSB

–

Displays result of Calibrate Modulation Depth

command. Antenna drivers are composed of 8

binary weighted segments. Bit md_x set to one

indicates that this particular segment will be

disabled during AM modulated state.

In case of error all 1 value is set.

LSB

1. At

power-up and after Set Default command content of this register is set to 0.

DS11794 Rev 7

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112

ST25R3912

1.3.39

RFO AM modulated level definition register

Address: 26h

Type: RW

(1)

Table 65. RFO AM modulated level definition register

Bit

Name

Default

Function

Comments

dram7

dram6

dram5

dram4

dram3

dram2

dram1

dram0

2 Ohm

4 Ohm

8 Ohm

Antenna drivers are composed of eight binary

weighted segments. Setting a bit dram to 1 will

disable corresponding segment during AM

modulated state in case am_s bit is set to 1.

16 Ohm

32 Ohm

64 Ohm

128 Ohm

256 Ohm

1. Default

setting takes place at power-up and after Set Default command.

1.3.40

RFO normal level definition register

Address: 27h

Type: RW

(1)

Table 66. RFO normal level definition register

Function

Bit

Name

Default

Comments

droff7

droff6

droff5

droff4

droff3

droff2

droff1

droff0

2 Ohm

4 Ohm

Antenna drivers are composed of eight binary

weighted segments. Setting a bit droff to 1 will

disable corresponding segment during normal

non-modulated operation.



The TX drivers are made up of 8 segments,

binary weighted from 2 to 256 Ohm (nominal).



As an example, setting this register to 0xC0

disables the 2 Ohm and 4 Ohm segments.

8 Ohm

16 Ohm

32 Ohm

64 Ohm

128 Ohm

256 Ohm

1. Default

setting takes place at power-up and after Set Default command.

Applying value FFh to the register 27h will put the drivers in tristate.

98/130

DS11794 Rev 7

ST25R3912

1.3.41

External field detector threshold register

Address: 29h

Type: RW

(1)

Table 67. External field detector threshold register

Bit

Name

Default

Function

Comments

–

Not used

–

trg_l2

trg_l1

trg_l0

rfe_t3

rfe_t2

rfe_t1

rfe_t0

Peer detection threshold.



Refer to

ble 68

–

Collision avoidance threshold.



Refer to

ble 69

1. Default

setting takes place at power-up and after Set Default command.

Table 68. Peer detection threshold as seen on RFI1 input

Target peer detection

trg_I2

trg_I1

trg_I0

threshold voltage (mV

on RFI1)

105

150

205

290

400

560

800

Table 69. Collision avoidance threshold as seen on RFI1 input

Typical Collision Avoidance

rfe_3

rfe_2

rfe_1

rfe_0

threshold voltage (mV

on RFI1)

105

150

205

290

400

560

DS11794 Rev 7

99/130

112

ST25R3912

Table 69. Collision avoidance threshold as seen on RFI1 input (continued)

Typical Collision Avoidance

rfe_3

rfe_2

rfe_1

rfe_0

threshold voltage (mV

on RFI1)

800

125

175

250

1.3.42

Regulator voltage control register

Address: 2Ah

Type: RW

(1)

Table 70. Regulator voltage control register

Bit

Name

Default

Function

Comments

0: Regulated voltages are defined by

result of Adjust Regulators command

reg_s

Defines mode of regulator voltage setting.

1: Regulated voltages are defined by

rege_x bits written in this register

rege_3

rege _2

rege _1

rege _0

External definition of regulated voltage.



Refer to

ble 72

for definition.



In 5 V mode V

SP_D

and V

SP_A

regulators are set to 3.4 V

–

00: V

mpsv1

01: V

SP_A

10: V

SP_D

11: V

SP_RF

Defines source of direct command Measure

Power Supply.

mpsv0

–

1. Default

setting takes place at power-up and after Set Default command.

100/130

DS11794 Rev 7

ST25R3912

1.3.43

Regulator and timer display register

Address: 2Bh

Type: R

(1)

Table 71. Regulator and timer display register

Function Comments

Bit

Name

Default

reg_3

reg_2

reg_1

reg_0

–

Actual regulated voltage setting.



Refer to

ble 72

for definition.

–

1: General purpose timer is

running

gpt_on

–

nrt_on

mrt_on

–

1: No-response timer is running

1: Mask receive timer is running

1. 1.

At power-up and after Set Default command regulated voltage is set to maximum 3.4V.

Table 72. Regulated voltages

reg_3

reg_2

reg_1

reg_0

Typical regulated voltage (V)

rege_3

rege_2

rege_1

rege_0

5 V mode

3.3 V mode

5.1

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

2.4

4.98

4.86

4.74

4.62

4.50

4.38

4.26

4.14

4.02

3.90

Other combinations

Not used

DS11794 Rev 7

101/130

112

ST25R3912

1.3.44

RSSI display register

Address: 2Ch

Type: R

(1)(2)

Table 73. RSSI display register

Bit

Name

Default

Function

Comments

rssi_am_3

rssi_am_2

rssi_am_1

rssi_am_0

rssi_pm_3

rssi_pm_2

rssi_pm_1

rssi_pm_0

–

Stores peak value of AM channel RSSI

measurement. Automatically cleared at

beginning of transponder message and with

Clear RSSI command.

AM channel RSSI peak value.

Refer to

ble 74

for definition.

Stores peak value of PM channel RSSI

measurement. Automatically cleared at

beginning of transponder message and with

Clear RSSI command.

PM channel RSSI peak value.

Refer to

ble 74

for definition.

1. At

power-up and after Set Default command content of this register is set to 0.

2. Bit

0x30[7] indicates which RSSI value is use in the logic for internal use.

Table 74. RSSI

rssi_3

rssi_2

rssi_1

rssi_0

Typical signal on RFI1 (mV

rms

)

≤

>20

>27

>37

>52

>72

>99

>136

>190

>262

>357

>500

>686

>950

>1150

102/130

DS11794 Rev 7

ST25R3912

1.3.45

Gain reduction state register

Address: 2Dh

Type: R

(1)

Table 75. Gain reduction state register

Function

Bit

Name

Default

Comments

gs_am_3

gs_am_2

gs_am_1

gs_am_0

gs_pm_3

gs_pm_2

gs_pm_1

gs_pm_0

–

MSB

Actual gain reduction of second stage of AM

channel (including register gain reduction,

squelch and AGC)

–

LSB

MSB

–

Actual gain reduction of second stage of PM

channel (including register gain reduction,

squelch and AGC)

–

LSB

1. At

power-up and after Set Default command content of this register is set to 0.

1.3.46

Reserved register

Address: 2Eh

Type: R

Table 76. Reserved register

Function

Bit

Name

Default

Comments

–

DS11794 Rev 7

103/130

112

ST25R3912

1.3.47

Reserved register

Address: 2Fh

Type: R

Table 77. Reserved register

Function

Bit

Name

Default

Comments

–

1.3.48

Auxiliary display register

Address: 30h

Type: R

(1)

Table 78. Auxiliary display register

Function

Bit

Name

Default

Comments

Currently selected channel

0: AM

1: PM

a_cha

–

efd_o

tx_on

–

1: External field detected

1: Transmission is active

External Field Detector output

–

Indication that Xtal oscillator is active and

its output is stable

osc_ok

–

1: Xtal oscillation is stable

rx_on

rx_act

–

1: Receive coder is enabled

–

1: Receive coder is receiving a message

1: External Field Detector is active



in peer detection mode

nfc_t

–

1: External Field Detector is active



in RF Collision Avoidance mode

en_ac

1. At

power-up and after Set Default command content of this register is set to 0.

104/130

DS11794 Rev 7

ST25R3912

1.3.49

Wake-up timer control register

Address: 31h

Type: RW

(1)

Table 79. Wake-up timer control register

Function

Bit

Name

Default

Comments

0: 100 ms

1: 10 ms

wur

Wake-up timer range

wut2

wut1

wut0

wto

Refer to

ble 80

Wake-up timer timeout value

1: IRQ at every timeout

–

1: At timeout perform amplitude

measurement

wam

IRQ if difference larger than

∆

1: At timeout perform phase

measurement

wph

IRQ if difference larger than

∆

RFU

–

1. Default

setting takes place at power-up and after Set Default command.

Table 80. Typical wake-up time

wut2

wut1

wut0

100 ms range (wur=0)

10 ms range (wur=1)

100 ms

200 ms

300 ms

400 ms

500 ms

600 ms

700 ms

800 ms

10 ms

20 ms

30 ms

40 ms

50 ms

60 ms

70 ms

80 ms

DS11794 Rev 7

105/130

112

ST25R3912

1.3.50

Amplitude measurement configuration register

Address: 32h

Type: RW

(1)

Table 81. Amplitude measurement configuration register

Bit

Name

Default

Function

Comments

am_d3

am_d2

am_d1

am_d0

Definition of

∆

am (difference to

reference that triggers interrupt)

–

Include/exclude the measurement that causes

IRQ (having difference >

∆

am to reference) in

auto-averaging

0: Exclude the IRQ measurement

1: Include the IRQ measurement

am_aam

00: 4

am_aew1

am_aew2

01: 8

Define weight of last measurement result for

auto-averaging

10: 16

11: 32

0: Use

Amplitude measurement

reference register

Select reference value for amplitude

measurement Wake-Up mode

am_ae

1: Use amplitude measurement

auto-averaging as reference

1. Default

setting takes place at power-up and after Set Default command.

1.3.51

Amplitude measurement reference register

Address: 33h

Type: RW

(1)

Table 82. Amplitude measurement reference register

Bit

Name

Default

Function

Comments

am_ref7

am_ref6

am_ref5

am_ref4

am_ref3

am_ref2

am_ref1

am_ref0

–

1. Default

setting takes place at power-up and after Set Default command.

106/130

DS11794 Rev 7

ST25R3912

1.3.52

Amplitude measurement auto-averaging display register

Address: 34h

Type: R

(1)

Table 83. Amplitude measurement auto-averaging display register

Bit

Name

Default

Function

Comments

amd_aad7

amd_aad6

amd_aad5

amd_aad4

amd_aad3

amd_aad2

amd_aad1

amd_aad0

–

1. At

power-up and after Set Default command content of this register is set to 0.

1.3.53

Amplitude measurement display register

Address: 35h

Type: R

(1)

Table 84. Amplitude measurement display register

Bit

Name

Default

Function

Comments

am_amd7

am_amd6

am_amd5

am_amd4

am_amd3

am_amd2

am_amd1

am_amd0

–

1. At

power-up and after Set Default command content of this register is set to 0.

DS11794 Rev 7

107/130

112

ST25R3912

1.3.54

Phase measurement configuration register

Address: 36h

Type: RW

(1)

Table 85. Phase measurement configuration register

Bit

Name

Default

Function

Comments

pm_d3

pm_d2

pm_d1

pm_d0

Definition of

∆

pm (difference to

reference that triggers interrupt)

–

Include/exclude the measurement that causes

IRQ (having difference >

∆

pm to reference) in

auto-averaging

0: Exclude the IRQ measurement

1: Include the IRQ measurement

pm_aam

00: 4

pm_aew1

pm_aew0

01: 8

Define weight of last measurement result for

auto-averaging

10: 16

11: 32

0: Use

Phase measurement

reference register



1: Use phase measurement



auto-averaging as reference

Select reference value for phase measurement

Wake-Up mode

pm_ae

1. Default

setting takes place at power-up and after Set Default command.

1.3.55

Phase measurement reference register

Address: 37h

Type: RW

(1)

Table 86. Phase measurement reference register

Bit

Name

Default

Function

Comments

pm_ref7

pm_ref6

pm_ref5

pm_ref4

pm_ref3

pm_ref2

pm_ref1

pm_ref0

–

1. Default

setting takes place at power-up and after Set Default command.

108/130

DS11794 Rev 7

ST25R3912

1.3.56

Phase measurement auto-averaging display register

Address: 38h

Type: R

(1)

Table 87. Phase measurement auto-averaging display register

Bit

Name

Default

Function

Comments

pm_aad7

pm_aad6

pm_aad5

pm_aad4

pm_aad3

pm_aad2

pm_aad1

pm_aad0

–

1. At

power-up and after Set Default command content of this register is set to 0.

1.3.57

Phase measurement display register

Address: 39h

Type: R

(1)

Table 88. Phase measurement display register

Default Function

Bit

Name

Comments

pm_amd7

pm_amd6

pm_amd5

pm_amd4

pm_amd3

pm_amd2

pm_amd1

pm_amd0

–

1. At

power-up and after Set Default command content of this register is set to 0.

DS11794 Rev 7

109/130

112

ST25R3912

1.3.58

Reserved register

Address: 3Ah

Type: R

Table 89. Reserved register

Function

Bit

Name

Default

Comments

–

1.3.59

Reserved register

Address: 3Bh

Type: R

Table 90. Reserved register

Function

Bit

Name

Default

Comments

–

110/130

DS11794 Rev 7

ST25R3912

1.3.60

Reserved register

Address: 3Ch

Type: R

Table 91. Reserved register

Function

Bit

Name

Default

Comments

–

1.3.61

Reserved register

Address: 3Dh

Type: R

Table 92. Reserved register

Function

Bit

Name

Default

Comments

–

DS11794 Rev 7

111/130

112

ST25R3912

1.3.62

IC Identity register

Address: 3Fh

Type: R

Table 93. IC Identity register

Function

Bit

Name

Default

Comments

ic_type4

ic_type3

ic_type2

ic_type1

ic_type0

ic_rev2

–

Code for ST25R3912: 00001

5-bit IC type code

010: silicon r3.1

011: silicon r3.3

100: silicon r4.0

101: silicon r4.1

ic_rev1

3-bit IC revision code

ic_rev0

–

112/130

DS11794 Rev 7

ST25R3912

Pinouts and pin description

The ST25R3912 pin and pad assignments are described in

Figure 26

and

Figure 27

Figure 26. ST25R3912 QFN32 and VFQFPN32 pinouts

3 1

3 0

2 9

2 8

2 7

VDD_IO

TO2

AGD

RFI2

RFI1

VSS

VSP_D

XTO

QFN32 / VFQFPN32

XTI

VSN_D

VSP_A

VDD

1 1

1 2

1 3

1 4

1 5

1 6

MS42461V3

1. The

above figure shows the package top view.

Figure 27. ST25R3912 WLCSP top view

TO1

AGD

VSN_A MCU_CLK

/SS

TO2

RFI2

RFI1

VSN_A

SCLK VDD_IO

B4 B5

XTO

VSS

MOSI

VSP_D VSN_D VSP_A

XTI

IRQ

MISO

RFO2

RFO1 VSP_RF

D4 D5

VDD

VSN_RF VSN_RF

RFO2

RFO1 VSP_RF

E4 E5

VDD

MS42441V1

DS11794 Rev 7

113/130

115

Pinouts and pin description

ST25R3912

Table 94. ST25R3912 pin definitions – QFN32, VFQFPN32 and WLCSP packages

Pin number

Pin name

Pin type

Description

QFN32

VFQFPN32

WLCSP

VDD_IO

TO2

Supply pad

Positive supply for peripheral communication

st output 2

VSP_D

XTO

Analog output

Digital supply regulator output

Xtal oscillator output

Analog input /

Xtal oscillator input

Digital input

XTI

VSN_D

VSP_A

VDD

Supply pad

Digital ground

Analog output

Analog supply regulator output

D6, E6

D5, E5

D4, E4

D3, E3

E1, E2

Supply pad

Analog output

Supply pad

External positive supply

VSP_RF

RFO1

RFO2

VSN_RF

Supply regulator output for antenna drivers

Antenna driver output

Ground of antenna drivers

Analog I/O

Supply pad

Pads not connected

VSS

Ground, die substrate potential

RFI1

RFI2

AGD

TO1

Analog input

Receiver input

Analog I/O

Analog reference voltage

Analog input

st output 1

A3, B3

VSN_A

IRQ

Supply pad

Analog ground

Interrupt request output

Microcontroller clock output

Digital output

MCU_CLK

Digital output /

tristate

MISO

Serial Peripheral Interface data output

114/130

DS11794 Rev 7

ST25R3912

Pinouts and pin description

Table 94. ST25R3912 pin definitions – QFN32, VFQFPN32 and WLCSP packages

Pin number

Pin name

Pin type

Description

QFN32

VFQFPN32

WLCSP

MOSI

SCLK

Serial Peripheral Interface data input

Serial Peripheral Interface clock

Digital input

Serial Peripheral Interface enable



(active low)

/SS

Ground, die substrate potential,



connected to V

on PCB

VSS

Exposed pad

DS11794 Rev 7

115/130

115

Electrical characteristics

ST25R3912

Electrical characteristics

3.1

Absolute maximum ratings

Stresses beyond those listed in

ble 95

ble 96

and

Table 97

may cause permanent

damage to the device. These are stress ratings only.

Functional operation of the device at these or any other conditions beyond those indicated

Section 3.2

is not guaranteed. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 95. Electrical parameters

Symbol

DD_IO

DC_IO supply voltage

Parameter

Min

Max

Unit

Comments

DC supply voltage

-0.5

6.0

–

Input pin voltage for peripheral

communication pins

-0.5

6.5

–

INA

scr

Input pin voltage for analog pins

Input current (latch-up immunity)

Drive capability of output driver

-0.5

-100

6.0

100

250

–

Norm: JEDEC 78

–

outmax

Table 96. Electrostatic discharge

Symbol

Parameter

Min

Max

Unit

Comments

ESD

Electrostatic discharge

±2

Standard JS-001-2014 (human body model)

Table 97. Temperature ranges and storage conditions

Symbol

Parameter

Min

Max

Unit

Comments

strg

Storage temperature

-55

125

°C

–

The reflow peak soldering temperature (body

temperature) is specified according to

IPC/JEDEC J-STD-020 “Moisture/Reflow

Sensitivity Classification for Non-hermetic

Solid State Surface Mount Devices”.



The lead finish for Pb-free leaded packages

is matte tin (100% Sn).

body

Package body temperature

–

260

°C

Relative humidity



non-condensing

MSL

–

QFN32 only.

WLCSP only.

Moisture sensitivity level

116/130

DS11794 Rev 7

ST25R3912

Electrical characteristics

3.2

Operating conditions

All limits are guaranteed. The parameters with Min and Max values are guaranteed with

production tests or SQC (Statistical Quality Control) methods.

All defined tolerances for external components in this specification need to be assured over

the whole operating conditions range and over lifetime.

Table 98. Operating conditions

Symbol

Parameter

Min

Max

Unit

Comments

Positive supply voltage

2.4

5.5

If power supply is lower than 2.6

SSR

cannot be improved using internal regulators

(minimum regulated voltage is 2.4 V).

Peripheral communication

supply voltage

DD_IO

1.65

5.5

Negative supply voltage

Junction temperature

–

JUN

-40

125

°C

Minimum RFI input signal definition is meant for

NFC receive mode.



In HF reader mode and NFC transmit mode the

RFI_A

RFO

RFI input amplitude

Driver current

0.150

recommended signal level is 2.5 V

250

–

3.3

DC/AC characteristics for digital inputs and outputs

3.3.1

CMOS inputs

Valid for input pins SS, MOSI, and SCLK.

Table 99. CMOS inputs

Symbol

Parameter

Min

Max

Unit

High level input voltage

Low level input voltage

Input leakage current

0.7 * V

DD_IO

0.3 * V

DD_IO

-1

LEAK

µA

3.3.2

CMOS outputs

Valid for output pins MISO, IRQ and MCU_CLK, io_18 = 0 (

Table 100. CMOS outputs

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High level output

voltage

SOURCE/SINK

= 1 mA,



measured at V

DDIO

= 2.4 V

0.9 * V

DD_IO

–

DD_IO

SOURCE/SINK

= 0.5 mA,



measured at V

DDIO

= 1.65 V

Low level output

voltage

–

0.1 * V

DD_IO

Capacitive load

–

DS11794 Rev 7

117/130

120

Electrical characteristics

ST25R3912

Table 100. CMOS outputs (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output resistance

–

250

550

Ω

Pull-down can be enabled while

Pull-down resistance



MISO output is in tristate.



Ω

pin MISO

The activation is controlled by

3.4

Electrical specifications

= 3.3

emperature 25 °C unless noted otherwise.

3.3 V supply mode, regulated voltages set to 3.4 V, 27.12 MHz Xtal connected to XTO and

XTI.

Table 101. Electrical specifications

Symbol

Parameter

Min Typ Max

Unit

Comments

02hset to 00h register 03h set to 08h, other

registers in default state.

Supply current in

Power-down mode

–

0.7

3.5

µA

02hset to 00h register 03h set to 80h (enable NFC

rget mode), other registers in default state.

Supply current in initial

NFC

rget mode

NFCT

02h set to 04h (enable Wake-up mode), register

03hset to 08h, register 31h set to 08h (100 ms

timeout, IRQ at every timeout), other registers in

default state.

Supply current in Wake-

up mode

–

3.6

5.4

µA

mA VSP_D),

to 08h, other registers in default state, short

VSP_A and VSP_D.

Supply current in Ready

mode

7.5

(3 V supply mode, disable VSP_D), register 02h

set to E8h (one channel Rx, enable Tx), register

mA 03h

set to 08h, register 0Bh set to 00h, register

27h set to FFh (all RFO segments disabled), other

registers in default state, short VSP_A and

VSP_D.

Supply current,



all active

–

8.7 12.5

(3 V supply mode, disable VSP_D), register 02h

set to E8h (one channel Rx, enable Tx), register

mA 03h

set to 08, register 0Bh set to 80 (low power

mode), register 27h set to FFh (all RFO segments

disabled), other registers in default state, short

VSP_A and VSP_D.

Supply current,



all active,



low power receiver

6.8

mode

118/130

DS11794 Rev 7

ST25R3912

Symbol

Electrical characteristics

Comments

Table 101. Electrical specifications (continued)

Min Typ Max

Unit

Parameter

RFO

= 10 mA

The following measurement procedure, which

cancels resistance of measurement setup, is

used:

– all driver segments are switched on, resistance

is measured

RFO1 and RFO2 driver

output resistance

RFO

0.25 0.6

1.8

Ω

– all driver segments except the MSB segment

are switched on, resistance is measured

– difference between the two measurements is

the resistance of MSB segment

– resistance of MSB segment multiplied by two is

the value of R

RFO

Using a load impedance lower than the minimum

value can result in permanent damage to the

device.

Load impedance across



RFO1 and RFO2

load

Ω

SUB

= 848 kHz, AM channel with peak detector

input stage selected.

RFI

RFI input sensitivity

RFI input resistance

–

0.5

–

rms

Ω

–

POR

Power on Reset voltage

1.31 1.5 1.75

VSP_D), register 02h set to 80h, register 03h set

to 08h, other registers in default state, short

VSP_A and VSP_D.

AGD

AGD voltage

1.4

1.5

1.6

Manual regulator mode, regulated voltage set to

3.0

, measured on pin VSP_RF: register 00h set

to 0Fh, register 01h set to 80h (3 V supply mode),

Tx), register 2Ah set to D8h.

REG

Regulated voltage

2.80 3.0 3.32

13.56 MHz or 27.12 MHz crystal



ESR

MAX

= 150

Ω

max, load capacitance according

to crystal specification, IRQ is issued once the

oscillator frequency is stable. This parameter

changes with ESRMAX parameter.

Oscillator



OSC

0.65 0.7

start-up time

DS11794 Rev 7

119/130

120

Electrical characteristics

ST25R3912

3.5

Typical operating characteristics

3.5.1

Thermal resistance and maximum power dissipation

Figure 28. T

vs. power dissipation for different copper areas at T

= 25 °C

amb

CASE

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ꢈꢁ

ꢇꢁ

ꢆꢁ

ꢅꢁ

ꢄꢁ

ꢃꢁ

ꢂꢁ

ꢀꢁ

ꢁ[ꢁPP

ꢉꢁ[ꢉꢁPP

ꢀꢁ[ꢀꢁPP

ꢂꢁ[ꢂꢁPP

ꢃꢁ[ꢃꢁPP

ꢄꢁ[ꢄꢁPP

ꢅꢁ[ꢅꢁPP

ꢆꢁ[ꢆꢁPP

ꢁ

ꢁꢍꢄ

ꢉ

ꢉꢍꢄ

ꢀ

ꢀꢍꢄ

3RZHUꢊGLVVLSDWLRQꢊꢋ:ꢌ

06Yꢃꢀꢀꢁꢈ9ꢀ

Figure 29. R

vs. copper area

thCA

ꢉꢁꢁ

ꢈꢁ

ꢇꢁ

ꢆꢁ

ꢅꢁ

ꢄꢁ

ꢃꢁ

ꢂꢁ

ꢀꢁ

ꢉꢁ

ꢁ

ꢉꢁ

ꢀꢁ

ꢂꢁ

ꢃꢁ

ꢄꢁ

ꢅꢁ

$UHDꢊꢋFP

ꢀ

ꢌ

06Yꢃꢀꢀꢉꢁ9ꢀ

120/130

DS11794 Rev 7

ST25R3912

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages,

depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at

www.st.com

ECOPACK is

an ST trademark.

4.1

QFN32 package information

The ST25R3912 is available in a 32-pin QFN (5 mm x 5 mm) package (see

Figure 30

Dimensions are detailed in

ble 102

Figure 30. QFN32 outline

1. Dimensioning

and tolerances conform to ASME Y14.5M-1994.

2. Co-planarity

applies to the exposed heat slug as well as to the terminal.

3. Radius

on terminal is optional.

4. N

is the total number of terminals.

5. This

drawing is subject to change without notice.

DS11794 Rev 7

121/130

126

Package information

ST25R3912

Max.

(1)

Table 102. QFN32 dimensions

Symbol

Min.

Typ.

(as specified in

Figure 30

)

0.80

0.90

0.02

0.65

0.20

0.40

–

1.00

0.05

–

1.00

–

0.35

0º

0.45

14º

0.18

0.25

0.30

–

5.00 (with BSC)

–

5.00 (with BSC)

–

0.50 (with BSC)

–

aaa

bbb

ccc

ddd

eee

fff

3.40

3.50

3.60

3.40

3.50

3.60

–

4.75 (with BSC)

–

4.75 (with BSC)

0.15

0.10

0.05

0.08

0.10

(2)

1. All

dimensions are in mm. All angles are in degrees.

tal

number of terminals.

122/130

DS11794 Rev 7

ST25R3912

Package information

4.2

VFQFPN32 package information

VFQFPN32 is a 32-pin, 5×5 mm, 0.5 mm pitch, very thin fine pitch quad flat no lead

package.

Figure 31. VFQFPN32 outline

Pin #1 ID

Chamfer 0.35

32x

bbb M C A B

BOTTOM VIEW

TOP VIEW

SIDE VIEW

Detail A

ccc C

^{T
e
rm
L
inal length}

32x

eee C

rminal thickness

0.05 Ref.

SLP1 PLATED AREA

Detail A

SIDE VIEW

B04R_ME_V1

1. Drawing

is not to scale.

2. Coplanarity

applies to the exposed pad as well as the terminal.

Table 103. VFQFPN32 mechanical data

millimeters

inches

(1)

Typ

Symbol

Min

Typ

Max

Min

Max

0.800

0.900

–

1.000

0.050

0.0315

0.0354

–

0.0394

0.0020

0.200

0.400

0.250

5.000

3.500

5.000

3.500

0.500

0.350

0.100

0.0079

0.0157

0.0098

0.1969

0.1378

0.1969

0.1378

0.0197

0.0138

0.0039

0.300

0.180

0.500

0.300

0.0118

0.0071

0.0197

0.0118

3.400

3.600

0.1339

0.1417

bbb

–

DS11794 Rev 7

123/130

126

Package information

ST25R3912

Table 103. VFQFPN32 mechanical data (continued)

millimeters

Typ

inches

(1)

Symbol

Min

Max

Min

Typ

Max

ccc

–

0.100

0.080

–

0.0039

0.0031

–

eee

1. Values

in inches are converted from mm and rounded to 4 decimal digits.

Figure 32. VFQFPN32 recommended footprint

3.50

0.80

0.25

0.50

3.50

B04R_FP_V1

1. Dimensions

are expressed in millimeters.

124/130

DS11794 Rev 7

ST25R3912

Package information

4.3

WLCSP30 package information

WLCSP30 is a 30-ball, 3.065 x 2.865 mm, 0.5 mm pitch wafer level chip scale package.

Figure 33. WLCSP30 outline

bbb

A1 Orientation

reference

A1 ball

location

DETAIL A

aaa

(4X)

p view

Wafer back side

Bottom view

Bump side

Side view

DETAIL A

Rotated by 90 °C

BUMP

eee

b(36x)

ccc

X Y

ddd

Seating plane

WLCSP30_B028_ME_V1

Table 104. WLCSP30 mechanical data

millimeters

inches

(1)

Symbol

Min

Typ

Max

Min

Typ

Max

0.620

0.650

0.232

0.393

0.025

0.329

3.065

2.865

0.5

0.680

0.0244

0.0256

0.0091

0.0155

0.0010

0.0130

0.1207

0.1128

0.0197

0.0984

0.0268

–

3.015

3.115

0.1187

0.1226

2.815

2.915

0.1108

0.1148

–

2.5

DS11794 Rev 7

125/130

126

Package information

ST25R3912

Table 104. WLCSP30 mechanical data (continued)

millimeters

Typ

inches

(1)

Symbol

Min

Max

Min

Typ

Max

–

0.0787

0.0111

0.0170

1.1811

0.0039

0.0020

–

0.2825

0.4325

aaa

bbb

ccc

ddd

eee

0.10

0.05

1. Values

in inches are converted from mm and rounded to 4 decimal digits.

Figure 34. WLCSP30 recommended footprint

Dpad

Dsm

WLCSP30_B028_FP_V1

1. Dimensions

are expressed in millimeters.

Table 105. WLCSP30 recommended PCB

Recommended values

Dimension

Pitch

Dpad

Dsm

0.5 mm

0.314 mm

0.359 mm typ. (depends on the solder-mask registration tolerance)

Stencil opening

Stencil thickness

0.329 mm

0.100 mm

126/130

DS11794 Rev 7

ST25R3912

Ordering information

Table 106. Ordering information scheme

ST25 R

Example:

12 –

A QF

Device type

ST25 = NFC/RFID tags and readers

Product type

R = Reader

Frequency range

39 = HF products

Product feature

12 = High performance HF reader / NFC initiator for

payment applications with 1W output power

Temperature range

A = -40 °C to 125 °C

Package/Packaging

QW = 32-pin VFQFPN (5 mm x 5 mm) with wettable flanks

Tape and Reel

T = 4000 pcs/reel

Note:

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are

not yet qualified and therefore not approved for use in production. ST is not responsible for

any consequences resulting from such use. In no event will ST be liable for the customer

using any of these engineering samples in production. ST’s Quality department must be

contacted prior to any decision to use these engineering samples to run a qualification

activity.

DS11794 Rev 7

127/130

129

Revision history

ST25R3912

Revision history

Table 107. Document revision history

Changes

Date

Revision

13-Oct-2016

Initial release.

Updated document title,

Section 1: Functional overview

and

Description

Updated

Section 1.1.1: Transmitter

Section 1.1.2: Receiver

Section 1.1.3: Phase and amplitude detector

Section 1.1.5: External field detector

Section 1.1.6: Quartz crystal

oscillator

Section 1.1.7: Power supply regulators

Section 1.1.8: POR

and bias

Section 1.1.9: RC oscillator and wake-up timer

Section 1.2.2:

Transmitter

Demodulation stage

Filtering and gain stages

Digitizing

stage

Squelch

Receiver in NFCIP-1 active communication mode

Section 1.2.4: Wake-Up mode

Auto-averaging

Section 1.2.7: A/D

converter

Section 1.2.11: Communication with an external

microcontroller

and

Section 4.1: QFN32 package information

Added

Section 1.2.12: Direct commands

Updated

ble 11: Register preset bits

ble 18: Registers map

ble 19: IO Configuration register 1

Table 22: Mode definition register

ble 29: ISO14443B settings register 1

ble 35: Auxiliary definition

Table 37: Receiver configuration register 2

Table 38: Receiver

configuration register 3

ble 43: General purpose and no-response

timer control register

Table 47: Mask main interrupt register

Table 48:

Mask timer and NFC interrupt register

ble 49: Mask error and wake-

up interrupt register

Table 52: Error and wake-up interrupt register

ble 54: FIFO status register 2

Table 55: Collision display register

ble 57: Number of transmitted bytes register 2

Table 60: Antenna

Calibration Control Register

ble 65: RFO AM modulated level

ble 66: RFO normal level definition register

ble 67: External field detector threshold register

Table 70: Regulator

voltage control register

Table 71: Regulator and timer display register

ble 73: RSSI display register

Table 78: Auxiliary display register

ble 81: Amplitude measurement configuration register

ble 85:

Phase measurement configuration register

Table 93: IC Identity register

ble 96: Electrostatic discharge

ble 101: Electrical specifications

and

ble 106: Ordering information scheme

05-Jan-2017

Removed footnote from

ble 31: Minimum TR1 codings

Updated figures

Section 1.2.11: Communication with an

external microcontroller

Figure 24: Connection of tuning capacitors to

the antenna LC tank

and

Figure 26: ST25R3912 QFN32 and VFQFPN32

pinouts

12-May-2017

Updated

Figure 34: WLCSP package outline

128/130

DS11794 Rev 7

ST25R3912

Revision history

Table 107. Document revision history (continued)

Revision Changes

Updated

FIFO water level and FIFO status registers

and

Description

Date

Updated

Clear

and

Test

mode entry and access to test registers

Updated

ble 6: SPI operation modes

Table 17: Setting mod bits

ble 54: FIFO status register 2

and its footnotes,

Table 74: RSSI

ble 93: IC Identity register

ble 97: Temperature ranges and storage

conditions

and

Table 101: Electrical specifications

27-Jul-2017

Updated

Section 4.3: WLCSP30 package information

Updated title of

Section 5: Ordering information

and

Note:

Updated

ble 2: Low pass control

Table 6: SPI operation modes

ble 9: Direct commands

and

Table 27: ISO14443A and NFC 106kb/s

settings register

12-Mar-2018

01-Aug-2018

Updated

Example

and

Section 1.3.62: IC Identity register

Updated

Figure 23: Transport frame format according to NFCIP-1

and image caption on cover page.

Updated

Figure 26: ST25R3912 QFN32 and VFQFPN32 pinouts

TCASE vs. power dissipation for different copper areas at Tamb = 25 °C

Figure 28:

and

Figure 29: RthCA vs. copper area

Replaced former

Figure 24: FeliCa™ frame format

with

Table 14:

FeliCa™ frame format

Updated

ble 94: ST25R3912 pin definitions – QFN32, VFQFPN32 and

WLCSP packages

and

Table 106: Ordering information scheme

Added

Section 4.2: VFQFPN32 package information

Document scope limited to ST25R3912.

Updated

Section 1.1.3: Phase and amplitude

Description

detector

Demodulation stage

Section 1.2.15: Power-up sequence

Sub-

Carrier Stream Mode

BPSK Stream Mode

Section 1.3.34: Antenna

Calibration Control register

Section 1.3.35: Antenna Calibration Target

Section 1.3.36: Reserved register

and

Section 5: Ordering

information

Updated

Figure 2: Minimum configuration with single sided antenna

driving (including EMC filter)

Figure 3: Minimum configuration with

differential antenna driving (including EMC filter)

Figure 20: ISO14443A

states for PCD and PICC

and

Figure 26: ST25R3912 QFN32 and

08-Feb-2021

VFQFPN32 pinouts