STMicroelectronics-STA8089FGBD

Part #	STMicroelectronics-STA8089FGBD
Download	STMicroelectronics-STA8089FGBD

STA8089FG

Fully integrated GPS/Galileo/GLONASS/BeiDou/QZSS receiver

with embedded RF and in-package Flash

Datasheet

–

production data



2 Controller Area Network (CAN)



2 channels ADC (10 bits)



Operating condition:

– Main

voltage regulator (V

): 1.8 V ± 5%

INL

– Backup

voltage (V

): 1.6 V to 4.3 V

VFQFPN56

INB

(7 x 7 x 1.0 mm)

– Digital

voltage (V

): 1.0 V to 1.32 V

– RF

core voltage (V

): 1.2 V ± 10%

– IO

Ring Voltage (V

3.3 V ± 10%

): 1.8 V ± 5% or

ddIO



Package:

– VFQFPN56

(7 x 7 x 1.0 mm) 0.4 mm pitch

Features



Ambient temperature range: -40/+85°C



STMicroelectronics positioning

receiver with

48 tracking channels and 2 fast acquisition

channels supporting GPS, Galileo, GLONASS,

BeiDou and QZSS systems

Description

STA8089FG belongs to

seo III family products.

The device is a single die standalone positioning

receiver IC working on multiple constellations

(GPS/Galileo/GLONASS/BeiDou/QZSS).



ST-DRAW (Dead Reckoning Automotive Way)

supported (STA8089FGBD only)



Pin to pin compatible with STA8088FG

The device is backward compatible with

STA8088F

his enables fast customer

application migration.



Single die standalone receiver embedding RF

Front-End and low noise amplifier



-162 dBm indoor sensitivity (tracking mode)

The device is offered with a complete GNSS

firmware which performs all GNSS operations

including tracking, acquisition, navigation and

data output with no need of external memories.



Fast TTFF < 1 s in Hot start and 30 s in Cold

Start



High performance ARM946 MCU (up to

196 MHz)

STA8089FGBD can run also TESEO-DRAW the

STMicroelectronics dead reckoning firmware.



256 Kbyte embedded SRAM



In-package SQI Flash Memory (16 Mbits)



Real Time Clock (RTC) circuit



32-bit Watch-dog timer



3 UARTs



1 I

C master interface



1 Synchronous Serial Port (SSP, Motorola-SPI

supported)



USB2.0 full speed (12 MHz) with integrated

physical layer transceiver

July 2017

DocID027175 Rev 8

1/34

This is information on a product in full production.

www.st.com

Contents

STA8089FG

Contents

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VFQFPN56 pin configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power supply pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main function pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

st/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Communication interface pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF front-end pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+) processor

. . . . . .

MCU Subsystem

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1

AHB slaves

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4

APB peripherals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SSP .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

UART .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

GPIO .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADC .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

RTC .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Minimum and maximum values

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2/34

DocID027175 Rev 8

STA8089FG

Contents

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended DC operating conditions

. . . . . . . . . . . . . . . . . . . . . . . . .

DC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF electrical specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Oscillator electrical specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

OSCI oscillator specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1

5.2

ECOPACK

packages .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VFQFPN56 7 x 7 mm package information

. . . . . . . . . . . . . . . . . . . . . . .

Ordering information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision history

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DocID027175 Rev 8

3/34

List of tables

STA8089FG

List of tables

Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Main function pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test/emulated dedicated pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Communication interface pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RF front-end pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TCM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Frequency limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power consumption

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Recommended DC operating conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

LDO1 DC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LDO2 DC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Low voltage detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I/O buffers DC characteristic

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.0 V I/O buffers DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

RFACHAIN – GALGPS filter and VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

RFCHAIN – GLONASS/BeiDou filter and VGA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Synthesize

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Crystal recommended specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Oscillator amplifier specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Characteristics of external slow clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SARADC specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Flash specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VFQFPN56 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Document revision history

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4/34

DocID027175 Rev 8

STA8089FG

List of figures

STA8089FG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VFQFPN56 connection diagram (with CAN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VFQFPN56 connection diagram (no CAN

)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

32.768 kHz crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SARADC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

VFQFPN56 7 x 7 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DocID027175 Rev 8

5/34

Overview

STA8089FG

Overview

STA8089FG is one of the part number of

seo III STA8089x series.

The device is a highly integrated single-chip standalone GNSS receiver designed for

positioning system applications. STA8089FG embeds the new STMicroelectronics GNSS

positioning engine capable of receiving signals from multiple satellite navigation systems,

including the US GPS, European Galileo, Russia’s GLONASS, Chinese BeiDou and

Japan’s QZSS.

STA8089FGBD can be offered also bundled with STMicroelectronics dead reckoning

firmware called TESEO-DRAW.

The STA8089FG ability of tracking simultaneously the signals from multiple satellites

regardless of their constellation, make this chip capable of delivering exceptional accuracy

in urban canyons and in the environments where buildings and other obstructions make

satellite visibility challenging.

The STA8089FG is backward compatible with STA8088F

nabling fast customer

application migration. The STA8089FG combines a high performance ARM946

microprocessor with I/O capabilities and enhanced peripherals. It supports USB2.0 standard

at full speed (12 Mbps) with on-chip PH

The chip embeds backup logic with real time clock. The device is offered with a complete

firmware performing all positioning operations including acquisition, tracking, navigation and

data output with no need of external memories.

The device powered with 1.8V enables the on-chip voltage regulators to internally supply

the RF front-end, core logic and the backup logic. The device can be directly powered with

1.2 V bypassing the embedded voltage regulators which will be put in power down mode.

I/O lines are compatible with 1.8 V and 3.3 V. The STA8089F

sing STMicroelectronics

CMOSRF

chnology, is housed in a VFQFPN-56 (7 x 7 x 1.0 mm) package with stacked 16

Mbit Flash memory.

6/34

DocID027175 Rev 8

STA8089FG

Pin description

2.1

Block diagram

Figure 1. STA8089FG system block diagram

*ꢄ5)ꢃ,3

*ꢀ%%ꢂꢃ&RUUHODWRU (QJLQH

$FT

ꢄꢅꢂ7UN

**ꢂ,)

$’&

/1$

5$0V

&KDQQHOV

26&,

3//

&/2&.B*(1

6HFWLRQ

$3%

%ULGJH

ꢁꢂ)DVWꢂ$FT

&KDQQHO

*&ꢂ,)

$’&

6HFWLRQ

63,ꢂ,)

$+%

5LQJ

26&,

)/$6+

ꢇꢅꢈ0Eꢉ

$3%

%ULGJHꢃ

,2V

8$57ꢀ

5[ꢈ7[

8$57ꢋ

5[ꢈ7[

8$57ꢁ

5[ꢈ7[

663

$’&

&$1ꢋ

$3%ꢀ

&$1ꢁ

64,

7HVWꢃ

FRQWUROOHU

$3%

%ULGJHꢀ

:’

*3,2

078

()7

,ꢀ&

-7$*

86%ꢂ

9,&

308

%.B’RPDLQ

+,*+ꢂ63((‘ꢂ’ꢈ7&0

ꢁꢀꢅ.%

35&&

%.5$0ꢂꢃꢀ.%

%./’2

/’2ꢁ

/’2ꢅ

,ꢈ&DFKH

,62

ꢁꢇ.%

&(//

$3%

%ULGJHꢁ

$50ꢂꢆꢄꢇ

‘ꢈ&DFKH

ꢅ.%

26&,ꢀꢁ

57&

%DQGJDSꢆꢃ%LDVꢆꢃ2VFLOODWRUꢆꢃ/9’Vꢃ

+,*+ꢂ63((‘ꢂ,ꢈ7&0

ꢁꢇ.%

(“1(ꢀꢁꢂꢀꢀꢃꢀꢄꢀꢂ$’5

DocID027175 Rev 8

7/34

Pin description

STA8089FG

2.2

VFQFPN56 pin configuration

Figure 2. VFQFPN56 connection diagram (with CAN)

ꢄꢃ

ꢄꢄ

ꢄꢌ

ꢄꢇ

ꢄꢊ

ꢄꢅ

ꢄꢆ

ꢌꢋ

ꢌꢁ

ꢌꢀ

ꢌꢃ

ꢌꢄ

ꢌꢌ

ꢌꢇ

ꢁ

ꢀ

ꢄꢀ

ꢄꢁ

ꢄꢋ

ꢃꢆ

ꢃꢅ

ꢃꢊ

ꢃꢇ

ꢃꢌ

ꢃꢄ

ꢃꢃ

ꢃꢀ

ꢃꢁ

ꢃꢋ

ꢀꢆ

$”/ꢀ@59

41*@%*

41*@$-,

41*@$4/

6″35ꢂ@59

6″35ꢂ@39

6″35ꢅ@59

6″35ꢅ@39

(1*0ꢀ

5.4

ꢃ

5345O

ꢄ

ꢌ

51@*’@1

51@*’@/

ꢇ

ꢊ

ꢅ

7$$@3′

-/”@*/

(/%@-/”

ꢆ

7%%@42*

“%$@*/ꢅ

“%$@*/ꢀ

7*/-ꢀ

ꢁꢋ

ꢁꢁ

ꢁꢀ

ꢁꢃ

ꢁꢄ

70-ꢅ

7*/-ꢅ

70-ꢀ

7*/#

ꢀꢅ

ꢀꢊ

ꢀꢇ

ꢀꢌ

ꢀꢄ

ꢀꢃ

ꢀꢀ

ꢀꢁ

ꢀꢋ

ꢁꢆ

ꢁꢅ

ꢁꢊ

ꢁꢇ

ꢁꢌ

(“1(ꢀꢁꢂꢀꢀꢃꢂꢇꢃꢅ$’5

8/34

DocID027175 Rev 8

STA8089FG

Pin description

Figure 3. VFQFPN56 connection diagram (no CAN)

ꢄꢃ

ꢄꢄ

ꢄꢌ

ꢄꢇ

ꢄꢊ

ꢄꢅ

ꢄꢆ

ꢌꢋ

ꢌꢁ

ꢌꢀ

ꢌꢃ

ꢌꢄ

ꢌꢌ

ꢌꢇ

ꢁ

ꢀ

ꢄꢀ

ꢄꢁ

ꢄꢋ

ꢃꢆ

ꢃꢅ

ꢃꢊ

ꢃꢇ

ꢃꢌ

ꢃꢄ

ꢃꢃ

ꢃꢀ

ꢃꢁ

ꢃꢋ

ꢀꢆ

*ꢅ$@$-,

5.4

41*@%*

41*@$-,

41*@$4/

6″35ꢂ@59

6″35ꢂ@39

6″35ꢅ@59

6″35ꢅ@39

(1*0ꢀ

ꢃ

5345O

ꢄ

ꢌ

51@*’@1

51@*’@/

ꢇ

ꢊ

ꢅ

7$$@3′

-/”@*/

(/%@-/”

ꢆ

7%%@42*

“%$@*/ꢅ

“%$@*/ꢀ

7*/-ꢀ

ꢁꢋ

ꢁꢁ

ꢁꢀ

ꢁꢃ

ꢁꢄ

70-ꢅ

7*/-ꢅ

70-ꢀ

7*/#

ꢀꢅ

ꢀꢊ

ꢀꢇ

ꢀꢌ

ꢀꢄ

ꢀꢃ

ꢀꢀ

ꢀꢁ

ꢀꢋ

ꢁꢆ

ꢁꢅ

ꢁꢊ

ꢁꢇ

ꢁꢌ

(“1(ꢅꢀꢂꢀꢀꢃꢂꢈꢀꢂ$’5

2.3

Power supply pins

Table 1. Power supply pins

Description

Symbol

I/O voltage

I/O

STA8089FG

VCC_CHAIN

VCC_PLL

VCC_RF

VDD_SQI

VDDD

1.2 V

1.8 V

1.1 V

PWR Analog

supply voltage for RF chain (1.2 V)

PWR Analog

supply voltage for PLL RF (1.2 V)

PWR Analog

supply voltage for RF (1.2 V)

PWR Digital

supply voltage for SQI

PWR Digital

supply voltage

22,47

VDDIO_R1 1.8

V or 3.3 V

PWR Digital

supply voltage for I/O ring 1 (1.8 V or 3.3 V)

VDDIO_R2

3.3 V

PWR Digital

supply voltage for I/O ring 2 (3.3 V)

DocID027175 Rev 8

9/34

Pin description

STA8089FG

Table 1. Power supply pins (continued)

Symbol

I/O voltage

I/O

Description

VINB

VINL1

VINL2

VOB

1.6 V – 4.3 V

PWR Backup

LDO input supply voltage (1.6 V to 4.3 V)

1.8 V

PWR LDO1

and ADC input supply voltage

1.6 V – 4.3 V

PWR LDO2

input supply voltage (1.6 V to 4.3 V)

1.0 V

1.1 V

1.2 V

GND

PWR LDO

backup output voltage (1.0 V)

PWR LDO1

output voltage (1.1

, it can be also configured to 1.2 V)

PWR LDO2

output voltage (1.2 V)

GND Ground

VOL1

VOL2

GND

GND_LNA

GND Ground

2.4

Main function pins

Table 2. Main function pins

I/O Description

Symbol

I/O voltage

STA8089FG

ADC_IN1

ADC_IN2

1.4 V – 0

V typ range

1.4 V – 0 V typ range

ADC Analog input [1]

ADC Analog input [2]

Reset Input with Schmitt-Trigger characteristics and

noise filter.

RSTn

1.0 V

Input of the 32 KHz oscillator amplifier circuit and

input of the internal real time clock circuit.

RTC_XTI

1.0 V (max)

RTC_XTO

1.0 V (max)

1.0 V

Output of the oscillator amplifier circuit.

STDBY_OUT

When low, indicates the chip is in Standby mode

When low, the chip is forced in Standby Mode – All

pins in high impedance except the ones powered by

Backup supply

STDBYn

1.0 V

WAKEUP

WAKEUP from STANDBY mode

2.5

Test/emulated dedicated pins

Table 3. Test/emulated dedicated pins

Symbol

I/O voltage

I/O

Description

STA8089FG

TCK

TDI

VDDIO_R2

JTAG Test Clock

JTAG Test Data In

JTAG Test Data Out

TDO

TMS

TRSTn

JTAG Test Mode Select

JTAG Test Circuit Reset

10/34

DocID027175 Rev 8

STA8089FG

Symbol

Pin description

STA8089FG

Table 3. Test/emulated dedicated pins (continued)

I/O voltage

I/O

Description

Diff.

st Point for IF – Neg.

Diff.

st Point for IF – Pos.

TP_IF_N

TP_IF_P

1.2 V

2.6

Communication interface pins

Table 4. Communication interface pins

Alternative

function

Symbol

I/O voltage

I/O

Function

Description

STA8089FG

AF0

(default)

CAN0_RX

(1)

CAN0 receive data input

AF1

AF2

AF3

UART0_RX

SENSE

UART0 Rx data

CAN0_RX

(1)

VDDIO_R2

External temperature capture

port

I/O

I2C_SD

I2C serial data

AF0

(default)

CAN0_TX

(1)

CAN0 transmit data output

CAN0_TX

(1)

VDDIO_R2

CAN1_RX

(1)

VDDIO_R2

CAN1_TX

(1)

VDDIO_R2

AF1

AF2

AF3

AF0

AF1

UART0_TX

GPIO7

UART0 Tx data

I/O

General purpose I/O #7

I2C clock

I2C_CLK

I2C_SD

GPIO9

I/O

I2C serial data

General purpose I/O #9

AF2

(default)

CAN1_RX

(1)

CAN1 receive data input

I/O

AF3

AF0

AF1

SPI_CSN

I2C_CLK

GPIO8

SPI chip select active low

I2C clock

I/O

General purpose I/O #8

AF2

(default)

CAN1_TX

(1)

CAN1 transmit data output

AF3

SPI_CLK

SPI clock

AF0

(default)

I/O

AF1

AF2

AF3

GPIO25

SQI_CLK

Reserved

General purpose I/O #25

SQI Flash clock

—

SPI_CLK

VDDIO_R1

DocID027175 Rev 8

11/34

Pin description

STA8089FG

Table 4. Communication interface pins (continued)

Alternative

Symbol

I/O voltage

I/O

Function

Description

function

AF0

(default)

SPI chip select active low /

IO_Power Sel Ring 1

SPI_CSN

I/O

AF1

AF2

AF3

GPIO24

SQI_CEN

Reserved

General purpose I/O #24

SQI Flash chip enable

—

SPI_CSN

VDDIO_R1

AF0

(default)

SPI_DI

SENSE

SPI serial data input / BOOT2

External temperature capture

port

I/O

AF1

SPI_DI

I/O

AF2

AF3

SQI_SIO0/SI SQI

Flash data IO 0 / ser. I

Reserved

SPI_DO

GPIO27

—

AF0

(default)

SPI serial data output

General purpose I/O #27

I/O

AF1

AF2

AF3

SPI_DO

SQI_SIO1/SO SQI

Flash data IO 1 / ser. O

Reserved

—

AF0

(default)

UART0_RX

UART0 Rx data

AF1

AF2

SPI_DO

SPI serial data output

SQI Flash data IO 2

UART0_RX VDDIO_R1

I/O

SQI_SIO2

Extended Function Timer – Input

Capture_A

AF3

Timer_ICAPA

UART0_TX

AF0

(default)

UART0 Tx data / BOOT1

AF1

AF2

SPI_DI

SPI serial data input

SQI Flash data IO 3

UART0_TX VDDIO_R1

I/O

SQI_SIO3

Extended Function Timer –

Output Compare A

AF3

Timer_OCMPA

UART2_RX

AF0

(default)

UART2 Rx data

I/O

AF1

AF2

AF3

GPIO28

I2C_SD

General purpose I/O #28

UART2_RX VDDIO_R1

I2C serial data

—

Reserved

AF0

(default)

UART2_TX

UART2 Tx data / BOOT0

I/O

AF1

AF2

AF3

GPIO29

I2C_CLK

Reserved

General purpose I/O #29

UART2_TX VDDIO_R1

I2C clock

—

I/O

12/34

DocID027175 Rev 8

STA8089FG

Symbol

Pin description

STA8089FG

Table 4. Communication interface pins (continued)

Alternative

I/O voltage

I/O

Function

Description

function

USB

AF0

USB_DM

USB D- signal

UART1 Rx data

AF1

(default)

UART1_RX

USB_DM

VDDIO_R2

AF2

AF3

AF0

CAN1_RX

(1)

CAN1 receive data input

I/O

I2C_SD

I2C serial data

USB D+ signal

USB

USB_DP

AF1

(default)

UART1_TX

UART1 Tx data

USB_DP

VDDIO_R2

AF2

AF3

CAN1_TX

(1)

CAN1 transmit data output

I2C_CLK I2C

clock

1. Only

for STA8089FGB and STA8089FGBD.

2.7

General purpose pins

Table 5. General purpose pins

Alternative

Function

function

Symbol

I/O voltage

I/O

Description

STA8089FG

General purpose I/O #1 /

BOOT3

I/O

AF0 (default)

GPIO1

I/O

AF1

AF2

Reserved

PPS_OUT

—

GPIO1

VDDIO_R1

Pulse per second output

External temperature

capture port

I/O

AF3

SENSE

2.8

RF front-end pins

Table 6. RF front-end pins

Symbol

I/O voltage

I/O

Description

Low Noise Amplifier Input

STA8089FG

LNA_IN

XTAL_IN

1.2 V

Input Side of Crystal Oscillator or TCXO Input

Output Side of Crystal Oscillator

XTAL_OUT

DocID027175 Rev 8

13/34

General description

STA8089FG

General description

3.1

RF front end

The RF front-end is able to down-convert both the GPS-Galileo signal from 1575.42 MHz to

4.092 MHz (4 Fo, being F0 = 1.023 MHz), the GLONASS signal from 1601.718 MHz to

8.57 MHz and the BeiDou signal from 1561.098 MHz to 10.23 MHz.

It embeds high performance LNA minimizing external component count and two LDOs to

supply the internal core facilitating requirements for external power supply. A three bits ADC

converts the IF signals to sign (SIGN) and magnitude (MAG0 and MAG1). They can be

sampled or not by SPI. The magnitude bits are internally integrated in order to control the

variable gain amplifiers. The VGA gain can be also set by the SPI interface.

The RF tuner accepts a wide range of reference clocks (10 to 52 MHz) and can generate

64 Fo sampling clock for the baseband and 192 Fo clock for MCU subsystem.

3.2

GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+)

processor

STA8089FG integrates G3BB+ proprietary I

hich is the ST last generation high-

sensitivity Baseband processor fully compliant with GPS, Galileo, GLONASS and BeiDou

systems.

The baseband receives, from the embedded RF Front-End, two separate IF signals coded

in sign-magnitude digital format on 3 bits and the related clocks. The Galileo/GPS

(GALGPS) and GLONASS/BeiDou (GNSCOM) signals at the base band inputs are

centered on 4.092 MHz, 8.57 MHz and 10.23 MHz.

The baseband processes the two IF signals performing data codification, sample rate

conversion and final frequency conversion to zero IF before acquisition and tracking

correlations.

The baseband processor has the capability of acquiring and tracking the Galileo, GPS,

GLONASS and BeiDou signals in a simultaneous or single way, or a combination of three,

being GLONASS and BeiDou mutually exclusive. The number of tracking channels to be

used is programmable; the not used tracking channels can be powered down.

A complete multi-OS software library is provided by ST to handle GPS processing,

managing satellite acquisition, tracking, pseudo-range calculation and positioning,

generating the output in the standard NMEA message format or in a ST binary format. The

library includes support of ST self-trained assisted GPS (ST-AGPS), a complete and

scalable solution for assisting GPS start-up with autonomous and server-based ephemeris

prediction and extension.

3.3

MCU Subsystem

The implemented sub-system includes an AHB Lite bus matrix.

An ARM946 core is embedded in the sub-system and masters the AHB bus. The totally

available TCM SRAM is 256 KB. The amount of memory on ITCM and DTCM can be

14/34

DocID027175 Rev 8

STA8089FG

General description

configured by the ARM946 (see

Table 7: TCM Configuration

). ITCM can be configured as Ni

x 16 KB; DTCM can be configured as 128 + Nd x 16 KB, where Ni + Nd = 8, Ni



Table 7. TCM Configuration

TCMcfg [2]

TCMcfg [1]

TCMcfg [0]

ITCM

DTCM

16 KB

32 KB

48 KB

64 KB

80 KB

96 KB

112 KB

128 KB

240 KB

224 KB

208 KB

192 KB

176 KB

160 KB

144 KB

128 KB

3.3.1

AHB slaves



G3 APB port that allows to interface with the G3BB acquisition memory and control

registers.



512 Kbytes ROM

Vectored Interrupt Controller (VIC).

SQI flash memory controller

3 x ARM946 APB peripheral bus (APB1, APB2, APB3).

Vectored Interrupt Controller (VIC)

This Vectored Interrupt Controller (VIC) allows the operative system interrupt handler to

quickly dispatch interrupt service routines in response to peripheral interrupts. It provides a

software interface to the interrupt system. There are up to 64 interrupt lines. The VIC uses a

bit position for each different interrupt source.

The software can control each request line to generate software interrupts. Each interrupt

line can be independently enabled and configured to trigger a non-vectored Normal Interrupt

Request (IRQ) or Fast Interrupt Request (FIQ) to the ARM946 CPU. Sixteen interrupt lines

can also be selected to trigger a vectored IRQ.

The VIC has two operation modes: the user mode and the privilege mode, in order to have

the possibility to set (or not) one level of protection during execution.

FS USB device controller

Full speed USB device with transceiver. It is an AHB slave. When active requires a 48 MHz

clock XTAL_IN.

DocID027175 Rev 8

15/34

General description

STA8089FG

3.4

APB peripherals

3.4.1

CAN

(a)

The 2 CAN

cores perform communication according to the CAN protocol version 2.0 part

A and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the

physical layer, additional transceiver hardware is required.

CAN consists of the CAN core, message RAM, message handler, control registers and

module. For communication on a CAN network, individual message objects are configured.

The message objects and identifier masks for acceptance filtering of received messages are

stored in the message RAM. All functions concerning the handling of messages are

implemented in the message handler. These functions include acceptance filtering, the

transfer of messages between the CAN core and the message RAM, and the handling of

transmission requests as well as the generation of the module interrupt.

The register set of the CAN can be accessed directly by the CPU through the module

interface. These registers are used to control/configure the CAN core and the message

handler and to access the message RAM.

CAN features



Supports CAN protocol version 2.0 part A and B

Bit rates up to 1 MBit/s

Each message object has its own identifier mask

Maskable interrupt

Disabled automatic re-transmission mode for time triggered CAN applications

Programmable loop-back mode for self-test operation

Two 16-bit module interfaces to the AMBA APB bus from ARM

3.4.2

SSP

The SSP is a master interface for synchronous serial communication with peripheral

devices that have Motorola SPI.

The SSP performs serial-to-parallel conversion on data received from a peripheral device

on SPI_DI pin, and parallel-to-serial conversion on data written by CPU for transmission on

SPI_DO pin. The transmit and receive paths are buffered with internal FIFO memories

allowing up to 32 x 32-bit values to be stored independently in both transmit and receive

modes. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one

to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO.

The SSP includes a programmable bit rate clock divider and prescaler to generate the serial

output clock SSPCLK from the on-chip clock. One combined interrupt is delivered, which is

asserted from several internal maskable events.

a. Only

for STA8089FGB and STA8089FGBD(see

Figure 7: Ordering information scheme

16/34

DocID027175 Rev 8

STA8089FG

General description

SSP features

The SSP has the following features:



Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep

transmit FIFO

Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location

deep receive FIFO

Programmable data frame size from 4 to 32 bits,

Programmable clock bit rate and prescaler

Programmable clock phase and polarity in SPI mode

3.4.3

UART

The UARTx (x = 0|1|2) performs serial-to-parallel conversion on data asynchronously

received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on

data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are

buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64

data byte with 4-bit status (break, frame, parity, and overrun) for receive.

UART features

The UARTx (x = 0|1|2) are Universal Asynchronous Receiver/Transmitter that support much

of the functionality of the industry-standard 16C650 UAR

he main features are:



Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz),

or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate

generator



5, 6, 7 or 8 bits of data

Even, odd, stick or no-parity bit generation and detection

1 or 2 stop bit generation

Support of software flow control using programmable Xon/Xoff characters

False start bit detection

Line break generation and detection

Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO

Programmable FIFO disabling for 1-byte depth data path

These UAR

ary from industry-standard 16C650 on some minor points which are:



Receive FIFO trigger levels

The internal register map address space, and the bit function of each register differ

The deltas of the modem status signals are not available

1.5 stop bits is not supported

Independent receive clock feature is not supported

3.4.4

Flash

The STA8089FG integrates 16Mbits of Flash Memory. This eliminates the need external

Flash simplifying the routing associated to integrate a GPS receiver into a customer board.

DocID027175 Rev 8

17/34

General description

STA8089FG

3.4.5

MTU

The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit

Free-Running decrementing Counters (FRCs). The FRCs have their own clock input,

allowing the counters to run from a much slower clock than the system clock.

The FRC is the part of the timer that performs the counting. There are four instantiations of

the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit

counter in the FRC is split up into two 16-bit counters.

3.4.6

WDT

Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog

clock is used to generate a regular interrupt (WDOGINT), depending on a programmed

value.

The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt

remains unserviced for the entire programmed period. You can enable or disable the

watchdog unit as required.

Note:

Watchdog is stalled when the ARM processor is in Debug mode.

3.4.7

GPIO

The GPIO block provides twelve (12) programmable inputs or outputs. Each input or output

can be controlled in two modes:



software mode through an APB bus interface

alternate mode, where GPIO becomes a peripheral input or output line

Any GPIO input can be independently enabled or disabled (masked) for interrupt

generation. User can select for each GPIO which edge (rising, falling, both) will trigger an

interrupt.

3.4.8

3.4.9

ADC

10 bit SAR ADC operating at 1.8 V analog supply. It can convert up to 2 single ended

channels with analog input multiplexer at 500KSPS

RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 32 Kbyte

SRAM and supplied with a dedicated voltage regulator.

The RTC provides a high resolution clock which can be used for GPS. It keeps the time

when the system is inactive and can be used to wake the system up when a programmed

alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the

32.768 kHz crystal and a secured time update.

18/34

DocID027175 Rev 8

STA8089FG

General description

RTC features



47-bit counter clocked by 32.768 kHz clock

32-bit for the integer part (seconds) and 15-bit for the fractional part

The integer part and the fractional part are readable independently

The counter, once enabled, can be stopped

Integer part load register (32-bit)

Fractional part load register (15-bit)

Load bit to transfer the content of the entire load register (integer+fractional part) to the

47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the

MCU that the RTC has been updated.

DocID027175 Rev 8

19/34

Electrical characteristics

STA8089FG

Electrical characteristics

4.1

Parameter conditions

Unless otherwise specified, all voltages are referred to GND.

4.2

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

= 25°C.

4.3

4.4

4.5

Typical values

Unless otherwise specified, typical data are based on T

= 25°C, V

They are given only as design guidelines and are not tested.

= 1.8 V, V

= 1.20 V.

ddio

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Absolute maximum ratings

This product contains devices to protect the inputs against damage due to high static

voltages, however it is advisable to take normal precautions to avoid application of any

voltage higher than the specified maximum rated voltages.

ble 8

lists the absolute maximum rating for STA8089FG.

Table 8. Voltage characteristics

Symbol

Parameter

Min.

Max.

Unit

CC_CHAIN

Analog supply voltage for RF chain (1.2 V)

CC_PLL

Analog supply voltage for PLL RF (1.2 V)

-0.3

1.32

1.95

3.63

4.8

CC_RF

DDD

Analog supply voltage for RF (1.2 V)

Power supply pins for the core logic

DD_SQI

Digital supply voltage for SQI

DDIO_R1

Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V)

DDIO_R2

Digital supply voltage for I/O ring 2 (3.3 V)

INB

INL1

INL2

Backup LDO input supply voltage (1.6 V to 4.3 V)

LDO1 input supply voltage (1.8 V)

1.98

4.8

LDO2 input supply voltage (1.6 V to 4.3 V)

20/34

DocID027175 Rev 8

STA8089FG

Electrical characteristics

Table 8. Voltage characteristics (continued)

Symbol

Parameter

Min.

Max.

Unit

ESD-HBM

Electrostatic discharge, human body model

(1)

ESD-CDM

Electrostatic discharge, charge device model

(2)

-2

-250

250

1. Pins

sustaining only ±500 V are: 12, 13, 21, 27, 28, 29, 30 and 31

2. Pin

9 (LNA_IN) sustains only ±100 V.

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Table 9. Thermal characteristics

Symbol

Parameter

Min.

Max.

Unit

oper

Operative ambient temperature

Operative junction temperature

Storage temperature

-40

-55

°C

125

150

24.4

°C

j-amb

Thermal resistance junction to ambient

(1)

°C/W

1. According

to JEDEC specification on a 2 layers board.

Table 10. Frequency limits

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

CLK

AHB

Operating ARM9 CPU frequency

AHB frequency

—

196

MHz

_{DDD
= 1.2 V;}

= 85

(1)

1. Not

tested in production.

Table 11. Power consumption

Symbol

Parameter

Test condition

Min.

Typ. Max.

Unit

G2 = GPS/Galileo;

amb

= 25 °C;

—

INL2

= 1.8 V

G2 + GLONASS;

RFIP power (total V

INL2

)

amb

= 25 °C;

INL2

= 1.8 V

G2 + COMPASS;

_{amb
= 25 °C;}

INL2

= 1.8 V

ARM

= 196 MHz;

AHB

= 49 MHz;

Switchable area power;

(total V

INL1

(1)

MVR

amb

= 25 °C;

—

)

INL1

= .8 V; UART active;

other peripherals inactive

DocID027175 Rev 8

21/34

Electrical characteristics

Symbol

STA8089FG

Table 11. Power consumption (continued)

Parameter Test

condition Min.

ARM

= 196 MHz;

Typ. Max.

Unit

Always ON area power

(total V

INB

(1)

LPVR

AHB

= 49 MHz;

—

)

amb

= 25 °C; V

INB

= 3.3 V

_{ARM
= 196 MHz;}

AHB

= 49 MHz;

amb

= 25 °C;

INL1

= 1.8 V; UART

active; other peripherals

inactive

IO rings power (total

DDIO_R1

+ V

DDIO_R2

(1)

—

)

Standby mode supply

current

DStandby

—

µA

RTC

running = 32.768 KHz;

amb

= 25 °C; V

INB

= 1.8 V

Deep standby mode

supply current

(2)

DDeepStandby

1. Not

tested in production.

2. STDBY_OUT

pin not supported in deep standby.

4.6

Recommended DC operating conditions

ble 12

lists the functional recommended operating DC parameters for STA8089FG.

Table 12. Recommended DC operating conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

CC_CHAIN

Analog supply voltage for RF chain (1.2 V)

CC_PLL

Analog supply voltage for PLL RF (1.2 V)

CC_RF

Analog supply voltage for RF (1.2 V)

DD_SQI

Flash power supply

1.08

1.71

1.00

1.71

3.00

1.20

1.80

1.10

1.80

3.30

1.32

1.89

1.32

1.89

3.60

DDD

Power supply pins for the core logic

Digital supply voltage for I/O ring 1 (1.8 V)

Digital supply voltage for I/O ring 1 (3.3 V)

DDIO_R1

DDIO_R2

Digital supply voltage for I/O ring 2 (3.3 V)

Backup LDO input supply voltage (1.6 V to

4.3 V)

INB

1.60

4.30

INL1

INL2

LDO1 input supply voltage (1.8 V)

LDO2 input supply voltage (1.6 V to 4.3 V)

Operating case temperature

1.71

1.60

-40

1.89

4.30

°C

22/34

DocID027175 Rev 8

STA8089FG

Electrical characteristics

4.7

DC characteristics

ble 13

specifies the LDO1 voltage regulator characteristics.

Table 13. LDO1 DC characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

1.71 V

≤

INL1

≤

1.89 V;

OL1

≤

70 mA

Output voltage (1.2V)

1.08

1.20

1.32

OL1

1.71 V

≤

INL1

≤

1.89 V;

OL1

≤

70 mA

Output voltage (1.1V)

Output current

1.10

—

1.2

OL1

ble 14

specifies the LDO2 voltage regulator characteristics.

Table 14. LDO2 DC characteristics

Symbol

Parameter

Output voltage

Output current

Test condition

Min.

Typ.

Max.

Unit

1.6 V

≤

INL2

≤

4.3 V;

OL2

≤

30 mA

OL2

1.08

1.20

—

1.32

ble 15

specifies the low voltage detection thresholds.

Table 15. Low voltage detection thresholds

Parameter

Min.

Typ.

Max.

Unit

Upper voltage threshold

—

1.680

1.650

0.995

0.935

1.142

1.076

1.048

0.986

—

Input LVD always on

(1)

Lower voltage threshold

Upper voltage threshold

Output LVD always

on VR

(1)

Lower voltage threshold

Upper voltage threshold @ V

OL1

= 1.2 V

Lower voltage threshold @ V

OL1

= 1.2 V

Upper voltage threshold @ V

OL1

= 1.1 V

Lower voltage threshold @ V

OL1

= 1.1 V

Output LVD main

(1)

1. Not

tested in production.

ble 16

lists the DC characteristics for all the IO digital buffers except for the following input

buffers: STBYn (24), STDBY_OUT (23), WAKEUP (26) and RSTn (25).

Table 16. I/O buffers DC characteristics

Test

Symbol

Parameter

Min.

Typ.

Max.

Unit

conditions

DDIO

= 1.8 V

DDIO

= 3.3V

-0.3

—

0.3 * V

DDIO

0.8

(1)

Logical input low level voltage

DocID027175 Rev 8

23/34

Electrical characteristics

Symbol

STA8089FG

Table 16. I/O buffers DC characteristics (continued)

Test

Parameter

Min.

Typ.

Max.

Unit

conditions

DDIO

= 1.8 V

DDIO

= 3.3V

–

0.7 * V

DDIO

—

DDIO

+ 0.3

DDIO

+ 0.3

Logical input high level

voltage

(1)

2.0

(2)

HYST

Schmitt-trigger hysteresis

Low level output voltage

DDIO

= 1.8 V

0.4

DDIO

= 3.3V

_{DDIO
= 1.8 V}

_{DDIO
= 3.3V}

DDIO

– 0.4

DDIO

– 0.4

High level output voltage

1. Excludes

oscillator inputs RTC_XTI and XTAL_IN. Refer to oscillator electrical specifications.

2. Apply

to all digital inputs unless specified otherwise.

ble 17

lists the DC characteristics for the 1.0 V IO digital buffers input buffers: STBYn

(24), STDBY_OUT (23), WAKEUP (26) and RSTn (25).

Table 17. 1.0 V I/O buffers DC characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Logical input low level voltage

= 1.0 V

Logical input high level voltage

= 1.0 V

-0.3

—

0.35 * V

+ 0.3

0.2

0.65 * V

Low level output voltage

High level output voltage

= 1.0 V

– 0.2

4.8

AC characteristics

4.8.1

RF electrical specifications

Table 18. RFACHAIN – GALGPS filter and VGA

Symbol

Parameter

Test conditions

GPS band

Min

Typ

Max

Unit

S11

(1)

Input return loss

—

-8

PLL in default condition with

26Mhz as reference

IF frequency

Noise figure

—

4.045

(1)

MHz

NF overall chain with AGC set

at 0 dB

VGA at min gain

VGA at max gain

—

Conversion gain from

RF input to ADC input

119

RF-IF-VGA input

compression point

1dB

IRR

VGA min

—

-80

dBm

Image rejection ratio

24/34

DocID027175 Rev 8

STA8089FG

Electrical characteristics

Table 18. RFACHAIN – GALGPS filter and VGA (continued)

Symbol

Parameter

Test conditions

GPS mode

Min

Typ

Max

Unit

GPS

GAL

—

2.4

4.8

MHz

-3dB IF bandwidth

Galileo mode

Alias frequency

rejection

F = 60 MHz

(fs = 65.474 MHz)

ATT

—

gGPS

gGAL

GPS mode

—

200

(1)

IF filter group delay

variation

Galileo mode

1. Not

tested in production.

Table 19. RFCHAIN – GLONASS/BeiDou filter and VGA

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

GLONASS band

BeiDou band

-10

-7

S11

(1)

Input return loss

IF frequency for

GLONASS

PLL in default condition

with 26 Mhz as

reference

—

8.519

10.277

(1)

IFGNS/BDU

MHz

IF frequency for BeiDou

Noise figure

NF overall chain with

AGC set at 0 dB

VGA at min gain

VGA at max gain

—

Conversion gain from

RF input to ADC input

118

RF-IF-VGA input

compression point

1dB

IRR

VGA min

—

-80

dBm

Image rejection ratio

—

GNS/BDU

-3dB IF bandwidth

MHz

F = 53 MHz

(fs = 65.474 MHz)

ATT

Alias frequency rejection

—

IF filter group delay

variation

gGNS/BDU

(1)

1. Not

tested in production.

Table 20. Synthesizer

Symbol

Parameter

Min.

Typ.

Max.

Unit

TCXO_XTAL

DIV

Input frequency for xtal amplifier

(1)

Reference divider range

Loop divider range

MHz

DIV

2047

LO operating frequency

3142.656

MHz

1. That

amplifier can be used also as a TCXO input buffer.

DocID027175 Rev 8

25/34

Electrical characteristics

STA8089FG

4.8.2

Oscillator electrical specifications

This device contains two oscillators:



a 32.768 kHz oscillator/buffer for RTC circuit.

an OSCI oscillator/buffer in the RF Front-End

When used in oscillator mode, each oscillator requires a specific crystal, with parameters

that must be as close as possible to the following recommended values. When used in input

buffer mode, an external clock source must be applied.

32.768 kHz OSCI32 oscillator specifications

The 32.768 kHz OSCI32 oscillator is connected between RTC_XTI (oscillator amplifier

input) and RTC_XTO (oscillator amplifier output). It also requires two external capacitors of

(b)

18 pF

, as shown on

Figure 4

OSCI32 is disabled by default and must be enabled by setting bit28-OSCI_EN of

PRCC_BACKUP_REG0 to have 32.768KHz oscillation when an XTAL pi-network is

connected to RTC_XTI/RTC_XTO pins.

The recommended oscillator specifications are shown in

Table 21

Table 21. Crystal recommended specifications

Symbol

Parameter

Crystal frequency

(1)

Min.

Typ.

Max.

Unit

SXTAL

ESR

—

32.768

—

kHz

Motion inductance

(1)

Motional capacitance

(1)

Shunt capacitance

(1)

5.0

1.3

—

Ω

Resonance resistance

(1)

External load capacitance

(1)

1. Not

tested in production.

The oscillator amplifier specifications are shown in the following table:

Table 22. Oscillator amplifier specifications

Symbol

Parameter

Min.

Typ.

Max. Unit

Startup time

(1)

Drive level

(1)

—

0.3

—

0.6

<0.1

—

µW

RLC

Required load capacitance

(1)

—

12.5

33.6

Startup transconductance

22.5

—

µA/V

1. Not

tested in production.

b. Using

crystal with recommended characteristics as per

Table 21

26/34

DocID027175 Rev 8

STA8089FG

Electrical characteristics

Figure 4. 32.768 kHz crystal connection

Device

RCT_XTO

CL = 18 pF

RTC_XTII

CL = 18 pF

32.768 kHz

Crystal

rive the 32.768 kHz crystal pins from an external clock source:



Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This

disables the internal inverter, thus reducing the power consumption to minimum.



Drive the RTC_XTI pin with a square signal or a sine wave.

Table 23. Characteristics of external slow clock input

Symbol

_JIT
(cc)

JIT

(per)

Parameter

Cycle-to-cycle jitter

Min.

Typ.

Max.

Unit

-70

-500

—

Period jitter

Variation

500

ppm

DUTY

Duty cycle

4.8.3

4.8.4

OSCI oscillator specifications

The supported values of the embedded BOOT ROM are 16.368 MHz, 24.00 MHz,

26.00 MHz and 48.00 MHz.

The default values supported by the GNSS binary image is 26MHz and 48MHz, to enable

USB peripheral the 48 MHz is mandatory.

ADC specifications

This section gives the AC specification of the 10 bit Successive Approximation Register

ADC embedded in STA8089FG device. It is controlled by the ARM9 MCU through a

wrapper and an APB bridge as depicted in

Figure 5

and it has a maximum conversion rate

of 1MSPS with 8 muxed analog input channels capability. An internal voltage reference is

used and analog/digital power supplies connections are implemented inside the device

without any needs of dedicated external pins.

DocID027175 Rev 8

27/34

Electrical characteristics

STA8089FG

Figure 5. SARADC connections

GND

VINL1

VDD12_MVR

SARADC

AIN0

ADC_IN1

AIN1

REF

ADC_IN2

REFP

REFN

APB

Bridge2

D[9:0]

AIN7

ADC_IN8

ADC WRAPPER

Table 24. SARADC specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

ADCIN

ADC_IN input range

ADCCR

Conversion range

GND

-0.3

GND

1.35

—

INL1

+0.3

REF

1.45

REF

Voltage reference

1.4

7.0

Input capacitance

(1)

5.5

8.5

Input mux resistance (total

1.5

2.0

2.5



equivalent sampling resistance)

(2)

CLK



CLK

SUP

Clock frequency

Clock duty cycle

Start up time

(1)(3)

Conversion time

Sampling time

2.5

—

MHz

—

µs

cycles

LSB

INL

< +/- 2

Performance

DNL

1. Not

tested in production.

2. Pad

input capacitance included.

3. From

EN=1.

28/34

DocID027175 Rev 8

STA8089FG

Electrical characteristics

4.8.5

Flash specifications

This section gives the AC specification of the embedded Flash in STA8089FG device.

Table 25. Flash specifications

Symbol

Parameter

Test conditions

Min. Typ. Max.

Unit

Serial clock frequency

Sector erase cycle time

Block erase cycle time

Chip erase time

QPI mode – 4 read instructions

—

MHz

500

200

2000 ms

Size = 16 Mb

Page program cycle time

0.9

DocID027175 Rev 8

29/34

Package and packing information

STA8089FG

Package and packing information

5.1

ECOPACK

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages,

depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at:

www.st.com

ECOPACK is

an ST trademark.

5.2

VFQFPN56 7 x 7 mm package information

Table 26. VFQFPN56 package dimensions

Symbol

Min.

Typ.

Max

Common dimensions

0.80

0.85

0.01

0.90

0.05

0.70

0.60

0.65

0.20 REF

0.20

0.15

5.0

0.25

5.2

7.00 BSC

6.75 BSC

5.1

7.00 BSC

6.75 BSC

5.1

5.0

5.2

0.40 BSC



0°

12°

0.30

0.40

0.50

0.24

0.30

0.13

0.42

0.40

0.17

0.60

0.65

0.23

30/34

DocID027175 Rev 8

STA8089FG

Package and packing information

Figure 6. VFQFPN56 7 x 7 mm package dimension

(“1($’5ꢂꢂꢉꢊꢈ

DocID027175 Rev 8

31/34

Ordering information

STA8089FG

Ordering information

Figure 7. Ordering information scheme

Example code:

STA8089FG

Family identifier

Packing

Qualified Grade/CAN Bus

TR =

pe and Reel



<blank> = Tray



D =

GNSS + DRAW



<blank> = GNSS only



B = Industrial Grade (with CAN)



<blank> = Industrial Grade (no CAN)



SAL with Stacked Flash

32/34

DocID027175 Rev 8

STA8089FG

Revision history

Table 27. Document revision history

Changes

Date

Revision

21-Nov-2014

Initial release.

Updated

Features

and

Description

Updated

Chapter 1: Overview

Updated

ble 5: General purpose pins

Updated

Section 3.4.3: UART

15-Apr-2015

Updated

Section 4.7: DC characteristics

Section 4.8: AC

characteristics

and

Section 4.8.3: OSCI oscillator specifications

Table 1: Power supply pins

– VDDD, VOL1: updated description

Table 13: LDO1 DC characteristics

– V

OL1

: set min and max values as TBD, removed condition for Output

voltage at 1.0 V

30-Jun-2015

Table 14: LDO2 DC characteristics

– V

OL2

: set min and max values as TBD

Table 15: Low voltage detection thresholds

– Output LVD main VR: removed condition for Output voltage at 1.0 V

Table 8: Voltage characteristics

24-Nov-2015

25-Nov-2015

– V

ESD-HBM

, V

ESD-CDM

: updated values

Updated package data

Updated

Features

list and

Description

Updated

Overview

Updated

ble 4: Communication interface pins

– Note 1

01-Jun-2016

Updated

Section 3.4.1: CAN

– Note a

Updated

Section Figure 7.: Ordering information scheme

Updated:

–

ble 9: Thermal characteristics on page 21

j-amb

value);

–

ble 11: Power consumption

: removed I

DSLEEP

and added I

DStandby

and I

DDeepStandby

parameters;

29-May-2017

27-Jul-2017

–

ble 13: LDO1 DC characteristics

added Min and Max values of

OL1

parameter;

–

ble 14: LDO2 DC characteristics

added Min and Max values of

OL2

parameter.

Updated:

–

ble 11: Power consumption

: added in I

DDeepStandby

max value.

DocID027175 Rev 8

33/34

STA8089FG

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or

the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of S

ll other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

34/34

DocID027175 Rev 8

STMicroelectronics-STA8089FGBD

Related Posts

CUI-CPE-171

DB-Unlimited-TP243408-1

DB-Unlimited-TE054003-2