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STMicroelectronics-STA8090EXGATR

Part #STMicroelectronics-STA8090EXGATR
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STMicroelectronics-STA8090EXGATR
STA8090EXGA  
Automotive GPS/Galileo/GLONASS/BeiDou/QZSS receiver with  
high performance processing capability  
Datasheet
–
production data  
8 channels ADC (10 bits)  
1 Secure-Digital Multimedia Memory Card  
Interfaces (SDMMC)  
TFBGA169  
1 Multichannel Serial Port (MSP)  
Power Management Unit (PMU) embedding  
switching regulator  
Operating condition:  
Features  
– Main
 
voltage regulator (V
 
): 1.6 V to  
INL  
4.3 V  
AEC-Q100 qualified  
– Backup
 
voltage (V
 
): 1.6 V to 4.3 V  
INB  
STMicroelectronics positioning receiver with 48  
tracking channels and 2 fast acquisition  
channels supporting GPS, Galileo, GLONASS,  
BeiDou and QZSS systems  
– Digital
 
voltage (V
 
): 1.1 V to 1.32 V  
DD  
– RF
 
core voltage (V
 
): 1.2 V ± 10%  
CC  
– IO
 
Ring Voltage (V  
3.3 V ± 10%  
): 1.8 V ± 5% or  
ddIO  
ST-DRAW (ST Dead Reckoning Automotive  
Way) supported (STA8090EXGAD only)  
Package:  
– TFBGA169
 
9 x 9 x 1.2 mm 0.65 pitch  
Single die standalone receiver embedding RF  
Front-End and low noise amplifier  
Operating temperature range: -40/ +85 °C  
-162 dBm indoor sensitivity (tracking mode)  
Description  
Fast TTFF < 1 s in Hot start and 30 s in Cold  
Start  
STA8090EXGA belongs to
T
e
seo III family  
products.  
High performance ARM946 MCU (up to  
196 MHz)  
STA8090EXGA is a highly integrated System-On-  
Chip GNSS receiver designed for high-flexible  
and cost effective solution addressing, trackers,  
hand-held, in-dash navigation and
T
e
lematics  
applications.  
256 Kbyte embedded SRAM  
FSMC external memory interface (NOR and  
SRAM)  
External SQI Flash interface  
8 free running timers/ counters (32 bit)  
Real Time Clock (RTC) circuit  
32-bit Watch-dog timer  
STA8090EXGA embeds the new ST GNSS  
positioning engine capable of receiving signals  
from multiple satellite navigation systems,  
including GPS, Galileo, GLONASS, BeiDou  
QZSS.  
3 UARTs  
2
1 I
 
C master interface  
The STA8090EXGA combines a high  
performance ARM946 microprocessor with I/O  
capabilities and enhanced peripherals. It embeds  
innovative power management unit for power  
consumption optimization.  
1 Synchronous Serial Port (SSP, Motorola-SPI  
supported)  
USB2.0 full speed (12 MHz) with integrated  
physical layer transceiver  
STA8090EXGAD can run also TESEO-DRAW the  
STMicroelectronics dead reckoning firmware.  
2 Controller Area Network (CAN)  
June 2020  
DS11733 Rev 3  
1/42  
This is information on a product in full production.  

www.st.com  

STA8090EXGA  
Table 1. Device summary  
Package  
Root Part Number  
Packaging  
STA8090EXGA  
TFBGA169 9 x 9 mm  
T
a
pe and Reel  
2/42  
DS11733 Rev 3  
 

STA8090EXGA  
Contents  
Contents  

1

2

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  

Pin description

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  

2.1  

2.2  

2.3  

2.4  

2.5  

2.6  

2.7  

2.8  

2.9  

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
 
8  

TFBG_A169 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

Power supply pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

10  

Main function pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  

T

e

st / emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  

FSMC external memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

12  

SQI pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

14  

Communication interface pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

15  

Multimedia card pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

18  

2.10 General

 

purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

19  

2.11 RF

 

front-end pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

20  

3

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  

3.1  

3.2  

3.3  

RF front end

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

21  

GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+) processor

 

. . . . . .

 

21  

MCU Subsystem

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

21  

3.3.1  

AHB slaves

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  

3.4  

APB peripherals

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

23  

3.4.1  

3.4.2  

3.4.3  

3.4.4  

3.4.5  

3.4.6  

3.4.7  

3.4.8  

3.4.9  

CAN .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  

EFT .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  

SSP .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  

I2C .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  

SDMMC .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  

MTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  

WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  

GPIO .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  

3.4.10 ADC

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  

3.4.11 RTC

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  

3.4.12 MSP

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  

DS11733 Rev 3  
3/42  
4

Contents  
STA8090EXGA  

4

Electrical characteristics

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  

4.1  

4.2  

4.3  

4.4  

4.5  

4.6  

4.7  

4.8  

Parameter conditions

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

28  

Minimum and maximum values

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

28  

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

28  

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

28  

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

28  

Recommended DC operating conditions

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

30  

DC characteristics

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

31  

AC characteristics

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

33  

4.8.1  

4.8.2  

4.8.3  

4.8.4  

RF electrical specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  

Oscillator electrical specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  

OSCI oscillator specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  

ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  

5

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  

5.1  

5.2  

ECOPACK packages

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

38  

TFBGA169 9 x 9 x 1.2 mm package information

 

. . . . . . . . . . . . . . . . . . .

 

38  

6

7

Ordering information

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  

Revision history

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  

4/42  
DS11733 Rev 3  

STA8090EXGA  
List of tables  
List of tables  

Table 1.  

Table 2.  

Table 3.  

Table 4.  

Table 5.  

Table 6.  

Table 7.  

Table 8.  

Device summar

y

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  

TFBGA169 ball out Automotive Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  

Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  

Main function pin

s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1  

Test/emulated dedicated pin

s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1  

FSMC external memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  

SQI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  

Communication interface pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  

Multimedia card pin

s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

8  

General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  

RF front-end pins

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  

TCM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  

Frequency limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  

Power consumption

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  

Recommended DC operating conditions

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  

SMPS DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  

LDO1 DC characteristics

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  

LDO2 DC characteristics

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  

Low voltage detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  

I/O buffers DC characteristic

s

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

2  

1.0 V I/O buffers DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  

RFCHAIN – GALGPS filter and VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  

RFCHAIN – GLONASS/BeiDou filter and VGA

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  

Synthesize

r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

4  

Crystal recommended specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  

Oscillator amplifier specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  

Characteristics of external slow clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  

SARADC specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  

TFBGA169 9 x 9 x 1.2 mm mechanical data

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  

Document revision history

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  

Table 9.  

Table 10.  

Table 11.  

Table 12.  

Table 13.  

Table 14.  

Table 15.  

Table 16.  

Table 17.  

Table 18.  

Table 19.  

Table 20.  

Table 21.  

Table 22.  

Table 23.  

Table 24.  

Table 25.  

Table 26.  

Table 27.  

Table 28.  

Table 29.  

Table 30.  

Table 31.  

Table 32.  

DS11733 Rev 3  
5/42  
5

List of figures  
STA8090EXGA  
List of figures  

Figure 1.  

Figure 2.  

Figure 3.  

Figure 4.  

Figure 5.  

STA8090EXGA system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  

32.768 kHz crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  

SARADC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  

TFBGA169 9 x 9 x 1.2 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  

6/42  
DS11733 Rev 3  

STA8090EXGA  
Overview  
1
Overview  
STA8090EXGA is one of the part number of
T
e
seo III STA8090x series.  
STA8090EXGA is a highly integrated System-On-Chip GNSS receiver designed for high-  
flexible and cost effective solution addressing hand-held, in-dash navigation and
T
e
lematics  
applications.  
STA8090EXGA embeds the new ST GNSS positioning engine capable of receiving signals  
from multiple satellite navigation systems, including the US GPS, European Galileo,  
Russia’s GLONASS, Chinese BeiDou and Japan’s QZSS.  
The STA8090EXGA ability of tracking simultaneously the signals from multiple satellites  
regardless of their constellation, make this chip capable of delivering exceptional accuracy  
in urban canyons and in the environments where buildings and other obstructions make  
satellite visibility challenging.  
STA8090EXGAD can be offered also bundled with STMicroelectronics dead reckoning  
firmware called TESEO-DRAW; TESEO-DRAW firmware is a multi-sensors data fusion hub  
for
T
e
seo family IC’s.  
STA8090EXGA embeds innovative power management unit with switching regulator for  
power consumption optimization.  
The extended voltage supply range from 1.6 V to 4.3
V
,
t
he 1.8 V and 3.3 V I/O compliance  
support make the STA8090EXGA the suitable solution for different user applications.  
The STA8090EXGA combines a high performance ARM946 microprocessor with I/O  
capabilities and enhanced peripherals. It embeds FSMC for interfacing external memories  
(NOR and SRAM).  
It supports USB2.0 standard at full speed (12 Mbps) with on-chip PH
Y
.  
The chip embeds backup logic with real time clock.  
The STA8090EXGA, using STMicroelectronics CMOSRF
T
e
chnology, is housed in a  
FBGA169 (9 x 9 x 1.2 mm) 0.65mm pitch package.  
STA8090EXGA is compliant with ST Automotive Grade qualification which includes in  
addition to AEC-Q100 requirements a set of production flow methodologies targeting zero  
defect per million.  
The device, fulfilling the high quality and service level requirements of the automotive  
market, is the ideal solution for in-dash navigation and OEM telematics applications.  
DS11733 Rev 3  
7/42  
41  

Pin description  
STA8090EXGA  
2
Pin description  
2.1  
Block diagram  
Figure 1. STA8090EXGA system block diagram  
G4RF IP  
Antenna  
Sensing  
G3BB+ Correlator Engine  
ADC  
GG  
LNA  
Section  
Acq  
RAMs  
48 Trk  
OSCI  
PLL  
GG IF  
Channels  
CLOCK_GEN  
APB  
Bridge  
1 Fast Acq  
Channel  
ADC  
GC  
RF  
Section  
GC IF  
SPI IF  
AHB  
Ring  
OSCI  
SQI  
IF  
APB  
Bridge3  
FSMC  
IF  
IOs  
UART2  
UART0  
Full  
UART1  
Rx-Tx  
SDMMC  
I2S  
SSP  
CAN1  
GPIO  
CAN0  
APB2  
Rx-Tx  
Test  
controller  
BOOT  
ROM  
APB  
Bridge2  
EFT  
WD  
MTU  
I2C  
ADC  
JTAG  
USB  
IF  
VIC  
PMU  
BK_Domain  
HIGH SPEED D-TCM  
128KB  
PRCC  
BKRAM 32KB  
BKLDO  
LDO2  
LDO1  
SMPS  
I-Cache  
ISO  
16KB  
CELL  
APB  
Bridge1  
ARM 946  
D-Cache  
8KB  
OSCI32  
RTC  
Bandgap, Bias, Oscillator, LVDs  
HIGH SPEED I-TCM  
16KB  
GADG3006161214MAG  
8/42  
DS11733 Rev 3  

2.2  
TFBG_A169 ball out  
Table 2. TFBGA169 ball out Automotive Grade  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
FMSC_  
DATA8  
FMSC_  
DATA5  
FMSC_  
DATA3  
FMSC_  
DATA1  
UART0_  
DSR  
VINM  
VINM  
UART0_CTS  
VINL1  
VOL1  
GND  
VINB  
VOB  
A
B
C
D
A
B
C
D
E
F
FMSC_  
DATA13  
FMSC_  
DATA11  
FMSC_  
DATA9  
FMSC_  
DATA0  
VLX  
GND  
VOM  
VLX  
UART0_RX UART0_RTS  
SPI_DO  
ADC_IN5  
ADC_IN8  
GPIO0  
SPI_DI  
ADC_IN6  
VDD_ADC  
RTC_XTI  
WAKEUP1  
SPI_CLK  
ADC_IN2  
ADC_IN3  
RTC_XTO  
WAKEUP0  
SPI_CSN  
ADC_IN1  
ADC_IN7  
CAN0_RX  
CAN0_TX  
GND  
FMSC_  
DATA12  
FMSC_  
DATA4  
FMSC_  
DATA6  
UART0_  
DCD  
GND  
UART0_TX  
UART2_TX  
UART2_RX  
GND  
ADC_IN4  
Reserved  
I2C_SD  
FMSC_  
DATA15  
FMSC_  
DATA2  
FMSC_  
DATA7  
UART0_  
DTR  

GND  

FMSC_  
DATA10  
FMSC_  
DATA14  
VDDIO_  
FSMC  
VDD_ANA  
GND  
GND  
FMSC_CS1  
FMSC_CS0  
VDDIO_R1  
GND  
GPIO1  
VDDD  
E
F
FMSC_  
BLN1  
FMSC_  
BLN0  
FMSC_  
WEN  
GND  
GND  
GND  
I2C_CLK  
SQI_SIO2  
SQI_CEN  
VCC_PLL  
XTAL_OUT  
FMSC_  
ADD16  
VDD_  
SQI  
SQI_  
SIO0/SI  
SQI_  
SIO1/SO  
FMSC_ADV FMSC_CLK FMSC_CS2  
FMSC_  
GND  
GND  
VDDD  
RSTn  
G
H
J
G
H
J
FMSC_  
ADD13  
(1)  
FMSC_WTN  
NC  
TDO  
VDDD  
VDDD  
VDDD  
STDBYn  
GPIO11  
GPIO13  
GPIO10  
GND_LNA  
VCC_RF  
9
PMU_CFG  
SQI_SIO3  
GPIO3  
GND  
SQI_CLK  
GPIO2  
OUTEN  
FMSC_  
ADD14  
FMSC_  
ADD10  
FMSC_  
ADD3  
FMSC_  
ADD15  
STDBY_  
OUT  
(1)  
(1)  
(2)  
TDI  
TCK  
TRSTn  
GPIO19  
MMC_D3  
GPIO12  
TP_IF_P  
TP_IF_N  
8
FMSC_  
ADD11  
FMSC_  
ADD9  
FMSC_  
ADD5  
FMSC_  
ADD6  
FMSC_  
ADD12  
(1)  
TMS  
MMC_D1  
MMC_CLK  
MMC_D2  
MMC_CMD  
7
GND  
GND  
XTAL_IN  
K
L
K
L
FMSC_  
ADD7  
FMSC_  
ADD21  
FMSC_  
ADD1  
FMSC_  
ADD8  
FMSC_  
ADD17  
ANT_  
SENSE2  
VCC_  
CHAIN  
USB_DP  
USB_DM  
GND  
GND  
FMSC_  
ADD0  
FMSC_  
ADD2  
FMSC_  
ADD4  
FMSC_  
ADD20  
FMSC_  
ADD22  
ANT_  
SENSE1  
GND_LNA  
LNA_IN  
10  
GND_LNA  
VOL2  
GND  
VINL2  
12  
M
N
M
N
FMSC_  
ADD19  
FMSC_  
ADD18  
FMSC_  
ADD23  
VDDIO_R2  
MMC_D0  
GND  
1
2
3
4
5
6
11  
13  
1. NC
 
for STA8090EXGAJ and STA8090EXGAJD  
2. GND
 
for STA8090EXGAJ and STA8090EXGAJD  
 

Pin description  
STA8090EXGA  
STA8090EXGA  
2.3  
Power supply pins  
Table 3. Power supply pins  
Symbol  
I/O
voltage  
I/O  
Description  
VCC_CHAIN  
VCC_PLL  
VCC_RF  
1.2 V  
1.2 V  
1.2 V  
1.8 V  
PWR Analog
 
supply voltage for RF chain (1.2 V)  
PWR Analog
 
supply voltage for PLL RF (1.2 V)  
PWR Analog
 
supply voltage for RF (1.2 V)  
PWR Digital
 
supply voltage for ADC (1.8 V)  
L13  
J13  
N9  
VDD_ADC  
VDD_SQI  
D10  
G10  
1.8 V or 3.3 V
 
PWR Digital
 
supply voltage for SQI  
1.2 V
 
PWR Digital
 
supply voltage  
F8, G8, H6, H7,  
H8  
VDDD  
VDDIO_FSMC 1.8
 
V or 3.3 V
 
PWR Digital
 
supply voltage for I/O ring FSMC (1.8 V or 3.3V)  
E7  
E6  
VDDIO_R1  
VDDIO_R2  
VINB  
1.8 V or 3.3 V
 
PWR Digital
 
supply voltage for I/O ring 1 (1.8 V or 3.3V)  
3.3 V
 
PWR Digital
 
supply voltage for I/O ring 2 (3.3 V)  
N2  
1.6 V – 4.3 V
 
PWR Backup
 
LDO input supply voltage (1.6 V to 4.3 V)  
1.6 V – 4.3 V
 
PWR LDO1
 
input supply voltage (1.6 V to 4.3 V)  
1.6 V – 4.3 V
 
PWR LDO2
 
input supply voltage (1.6 V to 4.3 V)  
1.6 V – 4.3 V
 
PWR SMPS
 
coil input supply (1.6 V to 4.3 V)  
1.6 V – 4.3 V
 
PWR SMPS
 
input supply (1.6 V to 4.3 V)  
A12  
A9  
VINL1  
VINL2  
N12  
A1, A2  
E1  
VINM  
VDD_ANA  
VLX  
0 V – 4.3 V  
1.0 V  
PWR SMPS
 
coil output  
B1, B2  
A13  
VOB  
PWR LDO
 
backup output voltage (1.0 V)  
LDO1 output voltage:  
VOL1  
VOL2  
VOM  
1.2 V or 1.8 V
 
PWR PMU_CFG
 
= high -> 1.2 V  
PMU_CFG = low -> 1.8 V  
A10  
N11  
D1  
1.2 V  
PWR LDO2
 
output voltage (1.2 V)  
SMPS output voltage  
1.2 V or 1.8 V
 
PWR PMU_CFG
 
= high -> 1.8 V  
PMU_CFG = low -> 1.2 V  
A11, B13, C1, C2,  
D5, D8, E2, F1,  
F6, F7, F9, G5,  
G6, G7, K10,  
K11, L10, L11,  
M12, N1, N13  
GND  
GND  
GND  
GND Ground  
GND Ground  
GND_LNA  
M9, M10, M11  
10/42  
DS11733 Rev 3  

STA8090EXGA  
Pin description  
2.4  
Main function pins  
Table 4. Main function pins  
STA8090EXG  
A
Symbol  
I/O
voltage  
I/O Description  
ADC_IN1  
ADC_IN2  
ADC_IN3  
ADC_IN4  
ADC_IN5  
ADC_IN6  
ADC_IN7  
ADC_IN8  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
1.4 V – 0 V typ range  
I
I
I
I
I
I
I
I
ADC Analog input [1]  
ADC Analog input [2]  
ADC Analog input [3]  
ADC Analog input [4]  
ADC Analog input [5]  
ADC Analog input [6]  
ADC Analog input [7]  
ADC Analog input [8]  
C12  
C11  
D11  
C13  
C9  
C10  
D12  
D9  
Power management unit config pin  
High -> VOL1 = 1.1
V
,
V
OM = 1.8 V  
Low -> VOL1 = 1.8
V
,
V
OM = 1.1 V  
PMU_CFG  
1.0 V  
I
H10  
Reset Input with Schmitt-Trigger characteristics and  
noise filter.  
RSTn  
1.0 V  
I
I
G9  
Input of the 32 KHz oscillator amplifier circuit and  
input of the internal real time clock circuit.  
RTC_XTI  
1.0 V (max)  
E10  
RTC_XTO  
1.0 V (max)  
1.0 V  
O
O
Output of the oscillator amplifier circuit.  
E11  
J10  
STDBY_OUT  
When low, indicates the chip is in Standby mode  
When low, the chip is forced in Standby Mode – All  
pins in high impedance except the ones powered by  
Backup supply  
STDBYn  
1.0 V  
I
H9  
WAKEUP0  
WAKEUP1  
1.0 V  
1.0 V  
I
I
WAKEUP from STANDBY mode  
WAKEUP from STANDBY mode  
F11  
F10  
2.5  
Test / emulated dedicated pins  
Table 5. Test/emulated dedicated pins  
Symbol  
I/O
voltage  
I/O  
Description  
STA8090EXGA  
TCK

(1)  

TDI

(1)  

VDDIO_R2  
VDDIO_R2  
VDDIO_R2  
VDDIO_R2  
VDDIO_R2  
1.2 V  
I
I
JTAG
T
e
st Clock  
J6  
J5  
JTAG
T
e
st Data In  
JTAG
T
e
st Data Out  
TDO

(1)  

O
I
H5  
K6  
J7  
TMS

(1)  

JTAG
T
e
st Mode Select  
JTAG Test Circuit Reset  
Diff.
T
e
st Point for IF — Neg.  
Diff.
T
e
st Point for IF — Pos.  
TRSTn

(1)  

TP_IF_N  
TP_IF_P  
I
O
O
N8  
M8  
1.2 V  
1. Not
 
available for STA8090EXGAJ and STA8090EXGAJD  
DS11733 Rev 3  
11/42  
41  
 

Pin description  
STA8090EXGA  
2.6  
FSMC external memory interface pins  
Table 6. FSMC external memory interface pins  
Alternative  
function  
Symbol  
I/O
voltage  
I/O  
Function  
Description  
O
I/O  
O
AF0 (default)
 
FSMC_ADD0 FSMC
 
EMI address bus  
AF1, AF2,  
FSMC_ADD0 VDDIO_FSMC  
FSMC_ADD1 VDDIO_FSMC  
FSMC_ADD2 VDDIO_FSMC  
FSMC_ADD3 VDDIO_FSMC  
FSMC_ADD4 VDDIO_FSMC  
FSMC_ADD5 VDDIO_FSMC  
FSMC_ADD6 VDDIO_FSMC  
FSMC_ADD7 VDDIO_FSMC  
FSMC_ADD8 VDDIO_FSMC  
FSMC_ADD9 VDDIO_FSMC  
FSMC_ADD10 VDDIO_FSMC  
M2  
L4  
M3  
J3  
GPIO32  
General purpose I/O #32  
AF3  
AF0 (default)
 
FSMC_ADD1 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO33  
General purpose I/O #33  
AF3  
AF0 (default)
 
FSMC_ADD2 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO34  
General purpose I/O #34  
AF3  
AF0 (default)
 
FSMC_ADD3 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO35  
General purpose I/O #35  
AF3  
AF0 (default)
 
FSMC_ADD4 FSMC
 
EMI address bus  
M4  
K3  
K4  
L2  
L5  
K2  
J2  
AF1, AF2,  
I/O  
O
GPIO36  
General purpose I/O #36  
AF3  
AF0 (default)
 
FSMC_ADD5 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO37  
General purpose I/O #37  
AF3  
AF0 (default)
 
FSMC_ADD6 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO38  
General purpose I/O #38  
AF3  
AF0 (default)
 
FSMC_ADD7 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO39  
General purpose I/O #39  
AF3  
AF0 (default)
 
FSMC_ADD8 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO40  
General purpose I/O #40  
AF3  
AF0 (default)
 
FSMC_ADD9 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO41  
General purpose I/O #41  
AF3  
AF0 (default)
 
FSMC_ADD10 FSMC
 
EMI address
 
bus  
AF1, AF2,  
I/O  
GPIO42  
General purpose I/O #42  
AF3  
12/42  
DS11733 Rev 3  

STA8090EXGA  
Pin description  
Table 6. FSMC external memory interface pins (continued)  
Alternative  
Symbol  
I/O
voltage  
I/O  
Function  
Description  
function  
O
I/O  
O
AF0 (default)
 
FSMC_ADD11 FSMC
 
EMI address bus  
AF1, AF2,  
FSMC_ADD11 VDDIO_FSMC  
FSMC ADD12
 
VDDIO_FSMC  
FSMC_ADD13 VDDIO_FSMC  
FSMC_ADD14 VDDIO_FSMC  
FSMC_ADD15 VDDIO_FSMC  
K1  
K5  
GPIO43  
General purpose I/O #43  
AF3  
AF0 (default)
 
FSMC ADD12
 
FSMC EMI address bus  
AF1, AF2,  
I/O  
O
GPIO44  
General purpose I/O #44  
AF3  
AF0 (default)
 
FSMC_ADD13 FSMC
 
EMI address bus.  
H1  
J1  
J4  
AF1, AF2,  
I/O  
O
GPIO45  
General purpose I/O #45  
AF3  
AF0 (default)
 
FSMC_ADD14 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
O
GPIO46  
General purpose I/O #46  
AF3  
AF0 (default)
 
FSMC_ADD15 FSMC
 
EMI address bus  
AF1, AF2,  
I/O  
GPIO47  
General purpose I/O #47  
AF3  
—
—
—
—
—
—
—
—
—
—
—
—
FSMC_ADD16 VDDIO_FSMC  
FSMC_ADD17 VDDIO_FSMC  
FSMC_ADD18 VDDIO_FSMC  
FSMC_ADD19 VDDIO_FSMC  
FSMC_ADD20 VDDIO_FSMC  
FSMC_ADD21 VDDIO_FSMC  
FSMC_ADD22 VDDIO_FSMC  
FSMC_ADD23 VDDIO_FSMC  
FSMC_ADV VDDIO_FSMC  
FSMC_BLN0 VDDIO_FSMC  
FSMC_BLN1 VDDIO_FSMC  
O
O
O
O
O
O
O
O
O
O
O
O
FSMC_ADD16 FSMC
 
EMI address bus  
FSMC_ADD17 FSMC
 
EMI address bus  
FSMC_ADD18 FSMC
 
EMI address bus  
FSMC_ADD19 FSMC
 
EMI address bus  
FSMC_ADD20 FSMC
 
EMI address bus  
FSMC_ADD21 FSMC
 
EMI address bus  
FSMC_ADD22 FSMC
 
EMI address bus  
FSMC_ADD23 FSMC
 
EMI address bus  
G1  
L6  
N4  
N3  
M5  
L3  
M6  
N5  
G2  
F4  
F2  
G3  
FSMC_ADV  
FSMC EMI Address Valid  
FSMC_BLN0 FSMC
 
EMI Byte Lane  
FSMC_BLN1 FSMC
 
EMI Byte Lane  
FSMC_CLK  
FSMC_CS0  
VDDIO_FSMC  
VDDIO_FSMC  
FSMC_CLK  
FSMC_CS0  
FSMC EMI Clk  
FSMC EMI Chip Select for External  
Memory Bank 0  
O
O
—
—
F3  
E3  
FSMC EMI Chip Select for External  
Memory Bank 1  
FSMC_CS1  
FSMC_CS2  
VDDIO_FSMC  
VDDIO_FSMC  
FSMC_CS1  
FSMC_CS2  
FSMC EMI Chip Select for External  
Memory Bank 2 / IO_Power Sel  
Ring FSMC  
O
—
—
G4  
B6  
FSMC_DATA0 VDDIO_FSMC
 
I/O  
FSMC_DATA0 FSMC
 
EMI data bus  
DS11733 Rev 3  
13/42  
41  

Pin description  
STA8090EXGA  
Table 6. FSMC external memory interface pins (continued)  
Alternative  
Symbol  
I/O
voltage  
I/O  
Function  
Description  
function  
FSMC_DATA1 VDDIO_FSMC
 
I/O  
FSMC_DATA2 VDDIO_FSMC
 
I/O  
FSMC_DATA3 VDDIO_FSMC
 
I/O  
FSMC_DATA4 VDDIO_FSMC
 
I/O  
FSMC_DATA5 VDDIO_FSMC
 
I/O  
FSMC_DATA6 VDDIO_FSMC
 
I/O  
FSMC_DATA7 VDDIO_FSMC
 
I/O  
FSMC_DATA8 VDDIO_FSMC
 
I/O  
FSMC_DATA9 VDDIO_FSMC
 
I/O  
FSMC_DATA10 VDDIO_FSMC
 
I/O  
FSMC_DATA11 VDDIO_FSMC
 
I/O  
FSMC_DATA12 VDDIO_FSMC
 
I/O  
FSMC_DATA13 VDDIO_FSMC
 
I/O  
FSMC_DATA14 VDDIO_FSMC
 
I/O  
FSMC_DATA15 VDDIO_FSMC
 
I/O  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FSMC_DATA1 FSMC
 
EMI data bus  
FSMC_DATA2 FSMC
 
EMI data bus  
FSMC_DATA3 FSMC
 
EMI data bus  
FSMC_DATA4 FSMC
 
EMI data bus  
FSMC_DATA5 FSMC
 
EMI data bus  
FSMC_DATA6 FSMC
 
EMI data bus  
FSMC_DATA7 FSMC
 
EMI data bus  
FSMC_DATA8 FSMC
 
EMI data bus  
FSMC_DATA9 FSMC
 
EMI data bus  
FSMC_DATA10 FSMC
 
EMI data bus  
FSMC_DATA11 FSMC
 
EMI data bus  
FSMC_DATA12 FSMC
 
EMI data bus  
FSMC_DATA13 FSMC
 
EMI data bus  
FSMC_DATA14 FSMC
 
EMI data bus  
FSMC_DATA15 FSMC
 
EMI data bus  
A6  
D3  
A5  
C4  
A4  
C5  
D4  
A3  
B5  
E4  
B4  
C3  
B3  
E5  
D2  
FSMC_OUTEN VDDIO_FSMC  
FSMC_WEN VDDIO_FSMC  
FSMC_WTN VDDIO_FSMC  
O
O
I
FSMC_OUTEN FSMC
 
EMI Output Enable  
FSMC_WEN FSMC
 
EMI Write Enable  
H2  
F5  
H3  
FSMC_WTN  
FSMC EMI Wait (SNOR, CRAM)  
2.7  
SQI pins  
Table 7. SQI pins  
Symbol  
I/O
voltage  
I/O  
Description  
STA8090EXGA  
SQI_CEN  
SQI_CLK  
VDD_SQI  
VDD_SQI  
VDD_SQI  
VDD_SQI  
VDD_SQI  
VDD_SQI  
O
SQI Flash chip enable / IO_Power Sel Ring SQI  
SQI Flash clock  
H13  
H12  
G11  
G12  
G13  
H11  
O
SQI_SIO0/SI  
SQI_SIO1/SO  
SQI_SIO2  
I/O  
I/O  
I/O  
I/O  
SQI Flash data IO 0 / ser. I  
SQI Flash data IO 1 / ser. O  
SQI Flash data IO 2  
SQI_SIO3  
SQI Flash data IO 3  
14/42  
DS11733 Rev 3  

STA8090EXGA  
Pin description  
2.8  
Communication interface pins  
Table 8. Communication interface pins  
Alternative  
Function  
function  
Symbol  
I/O
voltage
I/O  
Description  
I
AF0 (default)  
AF1  
CAN0_RX  
UART0_RX  
T
s
ense  
CAN0 receive data input  
UART0_Rx data  
I
VDDIO_R2  
I/O  
CAN0_RX  
CAN0_TX  
I2C_CLK  
I2C_SD  
E12  
AF2  
External temperature capture port  
I2C serial data  
I/O  
O
AF3  
I2C_SD  
AF0 (default)  
AF1  
CAN0_TX  
UART0_TX  
GPIO7  
CAN0 transmit data output  
UART0 Tx data  
O
VDDIO_R2  
I/O  
F12  
F13  
E13  
B11  
AF2  
General purpose I/O #7  
I2C clock  
O
O
AF3  
I2C_CLK  
I2C_CLK  
GPIO8  
AF0 (default)  
AF1  
I2C clock  
I/O  
VDDIO_R2  
O
General purpose I/O #8  
CAN1 transmit data output  
SPI clock  
AF2  
CAN1_TX  
SPI_CLK  
I2C_SD  
O
AF3  
I/O AF0
 
(default)  
I2C serial data  
I/O  
I
AF1  
AF2  
GPIO9  
General purpose I/O #9  
CAN1 receive data input  
SPI chip select active low  
SPI clock  
VDDIO_R2  
VDDIO_R1  
CAN1_RX  
SPI_CSN  
SPI_CLK  
GPIO25  
I/O  
O
AF3  
AF0 (default)  
AF1  
I/O  
O
General purpose I/O #25  
SQI Flash clock  
SPI_CLK  
AF2  
SQI_CLK  
MMC_CLK  
O
AF3  
Multimedia Clock line  
SPI chip select active low / IO_Power  
Sel Ring 1  
O
AF0 (default)  
SPI_CSN  
I/O  
I/O  
I/O  
I
AF1  
AF2  
GPIO24  
SQI_CEN  
MMC_CMD  
SPI_DI  
General purpose I/O #24  
SPI_CSN  
SPI_DI  
VDDIO_R1  
VDDIO_R1  
B12  
B10  
SQI Flash chip enable  
AF3  
Multimedia card command line  
SPI serial data input / BOOT2  
External temperature capture port  
AF0 (default)  
AF1  
I/O  
I/O  
I/O  
T
s
ense  
AF2  
SQI_SIO1/SO SQI
 
Flash data IO 1 / ser. 0  
MMC_D0 Multimedia
 
card data 0  
AF3  
DS11733 Rev 3  
15/42  
41  

Pin description  
STA8090EXGA  
Table 8. Communication interface pins (continued)  
Alternative  
Symbol  
I/O
voltage
I/O  
Function  
Description  
function  
O
I/O  
I/O  
I/O  
I
AF0 (default)  
AF1  
SPI_DO  
GPIO27  
SPI serial data output  
General purpose I/O #27  
SPI_DO  
VDDIO_R1  
B9  
A8  
C6  
AF2  
SQI_SIO0/SI SQI
 
Flash data IO 0 / ser. 1  
MMC_D1 Multimedia
 
card data 1  
UART0_CTS UART0
 
clear to send  
AF3  
AF0 (default)  
AF1  
I/O  
O
GPIO15  
General purpose I/O #15  
MSP serial clock output  
GNSS clock out  
UART0_CTS VDDIO_R1  
UART0_DCD VDDIO_R1  
AF2  
i2s_out_sclk  
Clock GNSS  
O
AF3  
I
AF0 (default)
 
UART0_DCD UART0
 
data carrier detect  
I/O  
O
AF1  
AF2  
AF3  
GPIO17  
i2s_out_sdata MSP
 
serial data output  
Clock GNSS
 
GNSS clock out  
General purpose I/O #17  
O
I
AF0 (default)
 
UART0_DSR UART0
 
data set ready  
I/O  
O
AF1  
AF2  
GPIO16  
General purpose I/O #16  
MSP left/right clock output  
UART0_DSR VDDIO_R1  
UART0_DTR VDDIO_R1  
UART0_RTS VDDIO_R1  
A7  
i2s_out_lrclk  
GLONASS and BeiDou 3-bit coding  
output (Sign)  
O
AF3  
Sign GC  
O
AF0 (default)  
AF1  
UART0_DTR UART0
 
data terminal read  
I/O  
GPIO18  
General purpose I/O #18  
Extended Function Timer – Input  
Capture A  
D6  
I
AF2  
AF3  
Timer_ICAPA  
GPS and Galileo 3-bit coding Output  
(MAG1)  
O
Mag_1 GG  
O
I/O  
O
AF0 (default)  
AF1  
UART0_RTS UART0
 
request to send  
GPIO14  
General purpose I/O #14  
TCXO out clock  
B8  
B7  
AF2  
TCXO_OUT  
GPS and Galileo 3-bit coding output  
(Sign)  
O
AF3  
Sign GG  
I
AF0 (default)  
AF1  
UART0_RX  
SPI_DO  
UART0 Rx data  
O
SPI serial data output  
SQI Flash data IO 2  
UART0_RX  
VDDIO_R1  
I/O  
AF2  
SQI_SIO2  
Extended Function Timer – Input  
Capture A  
I
AF3  
Timer_ICAPA  
16/42  
DS11733 Rev 3  

STA8090EXGA  
Pin description  
Table 8. Communication interface pins (continued)  
Alternative  
Symbol  
I/O
voltage
I/O  
Function  
Description  
function  
O
I
AF0 (default)  
AF1  
UART0_TX  
SPI_DI  
UART0 Tx data / BOOT1  
SPI serial data input  
SQI Flash data IO 3  
UART0_TX  
VDDIO_R1  
C7  
I/O  
AF2  
SQI_SIO3  
Extended Function Timer – Output  
Compare A  
O
AF3  
Timer_OCMPA  
I
I/O  
I/O  
I/O  
O
AF0 (default)  
AF1  
UART2_RX  
GPIO28  
UART2 Rx data  
General purpose I/O #28  
I2C serial data  
UART2_RX  
UART2_TX  
USB_DM  
VDDIO_R1  
VDDIO_R1  
VDDIO_R2  
VDDIO_R2  
C8  
D7  
M1  
L1  
AF2  
I2C_SD  
AF3  
MMC_D2  
UART2_TX  
GPIO29  
Multimedia card data 2  
UART2 Tx data / BOOT0  
General purpose I/O #29  
I2C clock  
AF0 (default)  
AF1  
I/O  
O
AF2  
I2C_CLK  
MMC_D3  
USB_DM  
UART1_RX  
CAN1_RX  
I2C_SD  
I/O  
USB  
I
AF3  
Multimedia card data 2  
USB D- signal  
AF0  
AF1 (default)  
AF2  
UART1 Rx data  
I
CAN1 receive data input  
I2C serial data  
I/O  
USB  
O
AF3  
AF0  
USB_DP  
UART1_TX  
CAN1_TX  
I2C_CLK  
USB D+ signal  
AF1 (default)  
AF2  
UART1 Tx data  
USB_DP  
O
CAN1 transmit data output  
I2C clock  
O
AF3  
DS11733 Rev 3  
17/42  
41  

Pin description  
STA8090EXGA  
2.9  
Multimedia card pins  
Table 9. Multimedia card pins  
I/O  
voltage  
Alternative  
function  
Symbol  
I/O  
Function  
Description  
O
O
AF0 (default)  
AF1  
MMC_CLK  
Multimedia Clock line  
MSP left/right clock output  
i2s_out_lrclk  
MMC_CLK VDDIO_R2  
MMC_CMD VDDIO_R2  
L7  
Extended Function Timer – Input  
Capture A  
I
AF2  
AF3  
Timer_ICAPA  
I/O  
GPIO4  
General purpose I/O #4  
I/O AF0
 
(default)  
MMC_CMD  
Multimedia card command line  
O
O
AF1  
AF2  
AF3  
i2s_out_sdata MSP
 
serial data output  
N7  
N6  
CAN0_TX

(1)  

CAN0 transmit data output  
General purpose I/O #5  
Multimedia card data 0  
MSP serial clock output  
I2C serial data  
I/O  
GPIO5  
I/O AF0
 
(default)  
MMC_D0  
i2s_out_sclk  
I2C_SD  
O
AF1  
AF2  
AF3  
MMC_D0  
MMC_D1  
VDDIO_R2  
VDDIO_R2  
I/O  
I/O  
GPIO20  
General purpose I/O #20  
Multimedia card data 1  
MSP serial data input  
I/O AF0
 
(default)  
MMC_D1  
i2s_in_sdata  
I
AF1  
AF2  
AF3  
K7  
GLONASS and BeiDou 3-bit coding  
output (Sign)  
O
Sign GC  
I/O  
GPIO21  
MMC_D2  
Reserved  
CAN0_RX

(1)  

T
s
ense  
General purpose I/O #21  
Multimedia card data 2  
Reserved  
I/O AF0
 
(default)  
I/O  
I
AF1  
AF2  
AF3  
MMC_D2  
MMC_D3  
VDDIO_R2  
VDDIO_R2  
M7  
K8  
CAN0 receive data input  
External temperature capture port  
Multimedia card data 3  
Reserved  
I/O  
I/O AF0
 
(default)  
MMC_D3  
Reserved  
Sign GG  
GPIO23  
I/O  
O
AF1  
AF2  
AF3  
GPS 3-bit coding output (Sign)  
General purpose I/O #23  
I/O  
1. Only
 
for STA8090EXGAA and STA8090EXGAB.  
18/42  
DS11733 Rev 3  

STA8090EXGA  
Pin description  
2.10  
General purpose pins  
Table 10. General purpose pins  
Alternative  
Function  
function  
Symbol I/O
 
voltage
I/O  
Description  
I/O  
I
AF0 (default)  
AF1  
GPIO0  
General purpose I/O #0  
Pulse per second input  
PPS_IN  
Extended Function Timer – Output  
Compare B  
GPIO0  
GPIO1  
GPIO2  
VDDIO_R1  
VDDIO_R1  
VDDIO_R2  
E9  
E8  
O
O
AF2  
AF3  
Timer_OCMPB  
GLONASS and BeiDou 3-bit coding  
Output (MAG0)  
Mag_0 GC  
GPIO1  
I/O  
I
AF0 (default)  
AF1  
General purpose I/O #1 / BOOT3  
i2s_in_sdata MSP
 
serial data input  
O
AF2  
PPS_OUT  
T
s
ense  
Pulse per second output  
External temperature capture port  
General purpose I/O #2  
Reserved  
I/O  
I/O  
I
AF3  
AF0 (default)  
AF1  
GPIO2  
Reserved  
Extended Function Timer – Input  
Capture B  
J12  
I
AF2  
AF3  
Timer_ICAPB  
Mag_1 GC  
GLONASS and BeiDou 3-bit coding  
Output (MAG1)  
O
I/O  
I
AF0 (default)  
AF1  
GPIO3  
General purpose I/O #3  
Reserved  
Reserved  
Extended Function Timer – Output  
Compare A  
GPIO3  
VDDIO_R2  
J11  
O
O
I/O  
I
AF2  
AF3  
Timer_OCMPA  
Mag_0 GG  
GPS and Galileo 3-bit coding Output  
(MAG0)  
AF0 (default),  
AF1  
GPIO10  
General purpose I/O #10  
Extended Function Timer – Input  
Capture A  
GPIO10 VDDIO_R2  
AF2  
AF3  
Timer_ICAPA  
Timer_OCMPB  
GPIO11  
L9  
Extended Function Timer – Output  
Compare B  
O
I/O  
O
I
AF0 (default),  
AF1  
General purpose I/O #11  
Extended Function Timer – Output  
Compare A  
GPIO11  
VDDIO_R2  
AF2  
AF3  
Timer_OCMPA  
Timer_ICAPB  
J9  
Extended Function Timer – Input  
Capture B  
DS11733 Rev 3  
19/42  
41  

Pin description  
STA8090EXGA  
Table 10. General purpose pins (continued)  
Alternative  
Symbol I/O
 
voltage
I/O  
Function  
Description  
function  
AF0 (default),  
AF1, AF2, AF3  
GPIO12 VDDIO_R2  
GPIO13 VDDIO_R2  
GPIO19 VDDIO_R2  
I/O  
I/O  
I/O  
GPIO12  
GPIO13  
GPIO19  
General purpose I/O #12  
General purpose I/O #13  
General purpose I/O #19  
L8  
K9  
J8  
AF0 (default),  
AF1, AF2, AF3  
AF0 (default),  
AF1, AF2, AF3  
2.11  
RF front-end pins  
Table 11. RF front-end pins  
Symbol  
I/O
voltage  
I/O  
Description  
STA8090EXGA  
ANT_SENSE1  
ANT_SENSE2  
LNA_IN  
3.3 V  
3.3 V  
1.2 V  
1.2 V  
1.2 V  
I
I
Antenna sensing input 1  
M13  
L12  
N10  
K12  
K13  
Antenna sensing input 2  
I
Low Noise Amplifier Input  
XTAL_IN  
I
Input Side of Crystal Oscillator or TCXO Input  
Output Side of Crystal Oscillator  
XTAL_OUT  
O
20/42  
DS11733 Rev 3  

STA8090EXGA  
General description  
3
General description  
3.1  
RF front end  
The RF front-end is able to down-convert both the GPS-Galileo signal from 1575.42 MHz to  
4.092 MHz (4 Fo, being F0 = 1.023 MHz), the GLONASS signal from 1601.718 MHz to  
8.57 MHz and the BeiDou signal from 1561.098 MHz to 10.23 MHz.  
It embeds high performance LNA minimizing external component count and a LDO to  
supply the internal core facilitating requirements for external power supply. A three bits ADC  
converts the IF signals to sign (SIGN) and magnitude (MAG0 and MAG1). They can be  
sampled or not by SPI. The magnitude bits are internally integrated in order to control the  
variable gain amplifiers. The VGA gain can be also set by the SPI interface.  
The RF tuner accepts a wide range of reference clocks (10 to 52 MHz) and can generate  
64 Fo sampling clock for the baseband and 192 Fo clock for MCU subsystem.  
3.2  
GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+)  
processor  
STA8090EXGA integrates G3BB+ proprietary I
P
,
w
hich is the ST last generation high-  
sensitivity Baseband processor fully compliant with GPS, Galileo, GLONASS and BeiDou  
systems.  
The baseband receives, from the embedded RF Front-End, two separate IF signals coded  
in sign-magnitude digital format on 3 bits and the related clocks. The Galileo/GPS  
(GALGPS) and GLONASS/BeiDou (GNSCOM) signals at the base band inputs are  
centered on 4.092 MHz, 8.57 MHz and 10.23 MHz.  
The baseband processes the two IF signals performing data codification, sample rate  
conversion and final frequency conversion to zero IF before acquisition and tracking  
correlations.  
The baseband processor has the capability of acquire and track the Galileo, GPS,  
GLONASS and BeiDou signals in a simultaneous or single way, or a combination of three,  
being GLONASS and BeiDou mutually exclusive. The number of tracking channels to be  
used is programmable; the not used tracking channels can be powered down.  
A complete multi-OS software library is provided by ST to handle GPS processing,  
managing satellite acquisition, tracking, pseudo-range calculation and positioning,  
generating the output in the standard NMEA message format or in a ST binary format. The  
library includes support of ST self-trained assisted GPS (ST-AGPS), a complete and  
scalable solution for assisting GPS start-up with autonomous and server-based ephemeris  
prediction and extension.  
3.3  
MCU Subsystem  
The implemented sub-system includes an AHB Lite bus matrix.  
An ARM946 core is embedded in the sub-system and masters the AHB bus. The totally  
available TCM SRAM is 256 KB. The amount of memory on ITCM and DTCM can be  
DS11733 Rev 3  
21/42  
41  

General description  
STA8090EXGA  
configured by the ARM946 (see

Table 12: TCM Configuration

). ITCM can be configured as  
Ni x 16 KB; DTCM can be configured as 128 + Nd x 16 KB, where Ni + Nd = 8, Ni
1.  
Table 12. TCM Configuration  
TCMcfg [2]  
TCMcfg [1]  
TCMcfg [0]  
ITCM  
DTCM  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16 KB  
32 KB  
48 KB  
64 KB  
80 KB  
96 KB  
112 KB  
128 KB  
240 KB  
224 KB  
208 KB  
192 KB  
176 KB  
160 KB  
144 KB  
128 KB  
3.3.1  
AHB slaves  
G3 APB port that allows to interface with the G3BB acquisition memory and control  
registers.  
512 Kbytes ROM  
Vectored Interrupt Controller (VIC).  
FSMC external memory interface  
SQI flash memory controller  
3 x ARM946 APB peripheral bus (APB1, APB2, APB3).  
Vectored Interrupt Controller (VIC)  
This Vectored Interrupt Controller (VIC) allows the operative system interrupt handler to  
quickly dispatch interrupt service routines in response to peripheral interrupts. It provides a  
software interface to the interrupt system. There are up to 64 interrupt lines. The VIC uses a  
bit position for each different interrupt source.  
The software can control each request line to generate software interrupts. Each interrupt  
line can be independently enabled and configured to trigger a non-vectored Normal Interrupt  
Request (IRQ) or Fast Interrupt Request (FIQ) to the ARM946 CPU. Sixteen interrupt lines  
can also be selected to trigger a vectored IRQ.  
The VIC has two operation modes: the user mode and the privilege mode, in order to have  
the possibility to set (or not) one level of protection during execution.  
FS USB device controller  
Full speed USB device with transceiver. It is an AHB slave. When active requires a 48 MHz  
clock XTAL_IN.  
FSMC external memory interface  
16-bit non-muxed memory interface for burst NOR Flash, SRAM and NAND.  
22/42  
DS11733 Rev 3  
 

STA8090EXGA  
General description  
SQI Flash interface  
STA8090EXGA includes a high-performance interface to Serial Quad Interface (SQI) NOR  
Flash chips, to support a low-cost simple implementation.  
3.4  
APB peripherals  
3.4.1  
CAN  
The 2 CAN cores perform communication according to the CAN protocol version 2.0 part A  
and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the  
physical layer, additional transceiver hardware is required.  
CAN consists of the CAN core, message RAM, message handler, control registers and  
module. For communication on a CAN network, individual message objects are configured.  
The message objects and identifier masks for acceptance filtering of received messages are  
stored in the message RAM. All functions concerning the handling of messages are  
implemented in the message handler. These functions include acceptance filtering, the  
transfer of messages between the CAN core and the message RAM, and the handling of  
transmission requests as well as the generation of the module interrupt.  
The register set of the CAN can be accessed directly by the CPU through the module  
interface. These registers are used to control/configure the CAN core and the message  
handler and to access the message RAM.  
CAN features  
Supports CAN protocol version 2.0 part A and B  
32 messages objects  
Each message object has its own identifier mask  
Maskable interrupt  
Disabled automatic re-transmission mode for time triggered CAN applications  
Programmable loop-back mode for self-test operation  
Two 16-bit module interfaces to the AMBA APB bus from ARM  
3.4.2  
EFT  
The Extended Function Timer (EFT) consists of a 16-bit counter driven by a programmable  
prescaler.  
It may be used for a variety of purposes, including pulse length measurement of up to two  
input signals (input capture), generation of up to two output waveforms (output compare)  
and one PWM generation. Pulse lengths and waveform periods can be modulated from a  
very wide range using the timer prescaler.  
DS11733 Rev 3  
23/42  
41  

General description  
STA8090EXGA  
EFT features  
Programmable prescaler: f  
value +1.  
divided from 1 to 256, prescaler register (0 to 255)  
APB  
Overflow status flag and maskable interrupts.  
Output compare functions with:  
–
–
–
–
2 dedicated 16-bit registers  
2 dedicated programmable signals  
2 dedicated status flags  
2 dedicated interrupt flags  
Input capture functions with:  
–
–
–
–
2 dedicated 16-bit registers  
2 dedicated active edge selection signals  
2 dedicated status flags  
2 dedicated interrupt flags  
Pulse Width Modulation mode (PWM).  
One Pulse Mode (OPM).  
PWM input mode.  
Timer global interrupt (5 internally ORed)  
–
–
–
–
–
ICIA: timer input capture A interrupt  
ICIB: timer input capture B interrupt  
OCIA: timer output compare A interrupt  
OCIB: timer output compare B interrupt  
TOI: timer overflow interrupt  
3.4.3  
SSP  
The SSP is a master interface for synchronous serial communication with peripheral  
devices that have Motorola SPI.  
The SSP performs serial-to-parallel conversion on data received from a peripheral device  
on SPI_DI pin, and parallel-to-serial conversion on data written by CPU for transmission on  
SPI_DO pin. The transmit and receive paths are buffered with internal FIFO memories  
allowing up to 32 x 32-bit values to be stored independently in both transmit and receive  
modes. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one  
to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO.  
The SSP includes a programmable bit rate clock divider and prescaler to generate the serial  
output clock SSPCLK from the on-chip clock. One combined interrupt is delivered, which is  
asserted from several internal maskable events.  
24/42  
DS11733 Rev 3  

STA8090EXGA  
General description  
SSP features  
The SSP has the following features:  
Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep  
transmit FIFO  
Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location  
deep receive FIFO  
Programmable data frame size from 4 to 32 bits  
Programmable clock bit rate and prescaler  
Programmable clock phase and polarity in SPI mode  
3.4.4  
UART  
The UARTx (x = 0|1|2) performs serial-to-parallel conversion on data asynchronously  
received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on  
data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are  
buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64  
data byte with 4-bit status (break, frame, parity, and overrun) for receive.  
UART features  
The UARTx (x = 0|1|2) are Universal Asynchronous Receiver/Transmitter that support much  
of the functionality of the industry-standard 16C650 UAR
T
.
T
he main features are:  
Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz),  
or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate  
generator  
5, 6, 7 or 8 bits of data  
Even, odd, stick or no-parity bit generation and detection  
1 or 2 stop bit generation  
Support of the modem control functions CTS, RTS, DCD, DSR, RTS, DTS and RI  
(UART0 only)  
Support of software flow control using programmable Xon/Xoff characters  
False start bit detection  
Line break generation and detection  
Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO  
Programmable FIFO disabling for 1-byte depth data path  
These UAR
T
s
v
ary from industry-standard 16C650 on some minor points which are:  
Receive FIFO trigger levels  
The internal register map address space, and the bit function of each register differ  
The deltas of the modem status signals are not available  
1.5 stop bits is not supported  
Independent receive clock feature is not supported  
3.4.5  
I2C  
STA8090EXGA includes an I2C interface configurable as master or slave.  
DS11733 Rev 3  
25/42  
41  

General description  
STA8090EXGA  
3.4.6  
3.4.7  
SDMMC  
STA8090EXGA features an SD/MMC host.  
MTU  
The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit  
Free-Running decrementing Counters (FRCs). The FRCs have their own clock input,  
allowing the counters to run from a much slower clock than the system clock.  
The FRC is the part of the timer that performs the counting. There are four instantiations of  
the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit  
counter in the FRC is split up into two 16-bit counters.  
3.4.8  
WDT  
Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog  
clock is used to generate a regular interrupt (WDOGINT), depending on a programmed  
value.  
The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt  
remains unserviced for the entire programmed period. You can enable or disable the  
watchdog unit as required.  
Note:  
Watchdog is stalled when the ARM processor is in Debug mode.  
3.4.9  
GPIO  
The GPIO block provides thirty-seven (37) programmable inputs or outputs. Each input or  
output can be controlled in two modes:  
software mode through an APB bus interface  
alternate mode, where GPIO becomes a peripheral input or output line  
Any GPIO input can be independently enabled or disabled (masked) for interrupt  
generation. User can select for each GPIO which edge (rising, falling, both) will trigger an  
interrupt.  
3.4.10  
3.4.11  
ADC  
10 bit SAR ADC operating at 1.8 V analog supply. It can convert up to 8 single ended  
channels with analog input multiplexer at 500KSPS  
RTC  
This is an always-on power domain dedicated to RTC logic (backup system) with 32 Kbyte  
SRAM and supplied with a dedicated voltage regulator.  
The RTC provides a high resolution clock which can be used for GPS. It keeps the time  
when the system is inactive and can be used to wake the system up when a programmed  
alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the  
32.768 kHz crystal and a secured time update.  
26/42  
DS11733 Rev 3  

STA8090EXGA  
General description  
RTC features  
47-bit counter clocked by 32.768 kHz clock  
32-bit for the integer part (seconds) and 15-bit for the fractional part  
The integer part and the fractional part are readable independently  
The counter, once enabled, can be stopped  
Integer part load register (32-bit)  
Fractional part load register (15-bit)  
Load bit to transfer the content of the entire load register (integer+fractional part) to the  
47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the  
MCU that the RTC has been updated.  
3.4.12  
MSP  
The STA8090EXGA provides one MSP transmitter block.  
Element (data) size from 8 to 32 bits, LSB or MSB first  
Programmable frequency shift clock for data transfer  
Direct interface to:  
–
–
–
industry-standard codecs and serially connected A/D and D/A devices  
IIS compliant devices  
SPI compliant devices  
Transmit first-in, first-out memory buffers (FIFOs), 32 bit wide, 8 locations deep  
DS11733 Rev 3  
27/42  
41  

Electrical characteristics  
STA8090EXGA  
4
Electrical characteristics  
4.1  
Parameter conditions  
Unless otherwise specified, all voltages are referred to GND.  
4.2  
Minimum and maximum values  
Unless otherwise specified the minimum and maximum values are guaranteed in the worst  
conditions of ambient temperature, supply voltage and frequencies by tests in production on  
100%.  
STA8090EXGA parts are tested at t=-40
°
C and T=85
°
C  
4.3  
4.4  
4.5  
Typical values  
Unless otherwise specified, typical data are based on T
 
= 25°C, V  
They are given only as design guidelines and are not tested.  
= 1.8
V
, V
 
=
1
.20
V
.  
dd  
A
ddio  
Typical curves  
Unless otherwise specified, all typical curves are given only as design guidelines and are  
not tested.  
Absolute maximum ratings  
This product contains devices to protect the inputs against damage due to high static  
voltages, however it is advisable to take normal precautions to avoid application of any  
voltage higher than the specified maximum rated voltages.  

T

a

ble 13

lists the absolute maximum rating for STA8090EXG.  
Table 13. Voltage characteristics  
Symbol  
Parameter  
Min.  
Max.  
Unit  
V

CC_CHAIN

Analog supply voltage for RF chain (1.2 V)  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
1.32  
1.32  
1.32  
1.98  
3.63  
1.32  
3.63  
3.63  
3.63  
V
V
V
V
V
V
V
V
V
V

CC_PLL  

V

CC_RF  

V

DD_ADC  

V

DD_SQI  

V

DDD  

Analog supply voltage for PLL RF (1.2 V)  
Analog supply voltage for RF (1.2 V)  
Digital supply voltage for ADC (1.8 V)  
Digital supply voltage for SQI  
Power supply pins for the core logic.  
V

DDIO_FSMC

Digital supply voltage for FSMC I/O ring (1.8 V or 3.3 V  
V

DDIO_R1  

V

DDIO_R2  

Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V)  
Digital supply voltage for I/O ring 2 (3.3 V)  
28/42  
DS11733 Rev 3  
 

STA8090EXGA  
Electrical characteristics  
Table 13. Voltage characteristics (continued)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
V

INB  

V

INL1  

Backup LDO input supply voltage (1.6 V to 4.3 V)  
LDO1 input supply voltage (1.6 V to 4.3 V)  
LDO2 input supply voltage (1.6 V to 4.3 V)  
SMPS coil input supply (1.6 V to 4.3 V)  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-2  
4.8  
4.8  
4.8  
4.8  
4.8  
2
V
V
V

INL2  

V
V

INM  

V
V

DD_ANA  

SMPS input supply (1.6 V to 4.3 V)  
V
V

ESD-HBM  

V

ESD-CDM  

Electrostatic discharge, human body model

(1)  

Electrostatic discharge, charge device model

(2)  

kV  
V
-250  
250  
1. Balls
 
sustaining only ±500 V are: A1, A2, A9, A10, A11, A12, A13, B1, B2, B13, C1, C2, D1, E1, E2, E10,  
E11, F1, N11, N12, N13.  
2. Ball
 
N10 (LNA_IN) sustains only ±100 V.  
Note:  
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent  
damage to the device. This is a stress rating only and functional operation of the device at  
these or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to absolute maximum rating conditions for extended  
periods may affect device reliability.  
Table 14. Thermal characteristics  
Symbol  
Parameter  
Min.  
Max.  
Unit  
T

oper  

T

j  

Operative temperature range  
Operative junction temperature  
Storage temperature  
-40  
-40  
-55  
—
85  
125  
150  
41  
°C  
°C  
T

st  

°C  
R

j-amb

Thermal resistance junction to ambient

(1)  

°C/W  
1. According
 
to JEDEC specification on a 2 layers board.  
Table 15. Frequency limits  
Symbol  
Parameter  
Test condition  
Min.  
Typ.  
Max.  
Unit  
F

CLK  

F

AHB  

Operating ARM9 CPU frequency  
AHB frequency  
—
—
—
—
196  
49  
MHz  
MHz  
V

DDD

= 1.2 V;  
T

C

= 85
°
C

(1)  

1. Not
 
tested in production.  
DS11733 Rev 3  
29/42  
41  

Electrical characteristics  
Symbol  
STA8090EXGA  
Table 16. Power consumption  
Parameter Test
 
condition  
G2 = GPS/Galileo;  
Min. Typ. Max.
 
Unit  
—
—
—
25  
35  
35  
—
—
—
mW  
mW  
mW  
T

amb

= 25 °C; V

INL2

= 1.8 V  
G2 + GLONASS;  
T

amb

= 25 °C; V

INL2

= 1.8 V  
P

RF  

RFIP power (total V

INL2

)  
G2 + BeiDou; T

amb

= 25 °C;  
V

INL2

= 1.8 V  
f

ARM

= 196 MHz;  
Switchable area power;
 
f

AHB

= 49 MHz
;
T

amb

= 25 °C;  
(1)  
P

MVR  

—
—
—
90  
1
—
—
—
mW  
mW  
mW  
(total V

INL1  

)
V

INL1

= 1.8 V; UART active;  
other peripherals inactive  
f

ARM

= 196 MHz;  
f

AHB

= 49 MHz
;
T

amb

= 25 °C;  
V

INB

= 3.3 V  
Always ON area power  
(total V

INB  

(1)  

P

LPVR  

)
f

ARM

= 196 MHz;  
IO rings power (total  
V

DDIO_R1

+ V

DDIO_R2  

f

AHB

= 49 MHz
;
T

amb

= 25 °C;  
V

INL1

= 1.8 V; UART active;  
other peripherals inactive  

(1)  

P

IO  

4
)
StandBy mode supply  
current  
I

DStandby  

—
—
29  
7
—
—
µA  
µA  
RTC running = 32.768 KHz;  
T

amb

= 25 °C; V

INB

= 1.8 V  
Deep StandBy mode  
supply current

(2)  

I

DDeepStandby  

1. Not
 
tested in production.  
2. STDBY_OUT
 
pin not supported in deep standby.  
4.6  
Recommended DC operating conditions  

T

a

ble 17

lists the functional recommended operating DC parameters for STA8090EXG.  
Table 17. Recommended DC operating conditions  
Symbol  
Parameter  
Min.  
Typ. Max.
 
Unit  
V

CC_CHAIN

Analog supply voltage for RF chain (1.2 V)  
1.08  
1.08  
1.08  
1.71  
1.71  
3.00  
1.00  
1.71  
3.00  
1.20  
1.20  
1.20  
1.80  
1.80  
3.30  
1.10  
1.80  
3.30  
1.32  
1.32  
1.32  
1.89  
1.89  
3.60  
1.32  
1.89  
3.60  
V
V
V
V
V
V
V
V
V
V

CC_PLL  

V

CC_RF  

Analog supply voltage for PLL RF (1.2 V)  
Analog supply voltage for RF (1.2 V)  
V

DD_ADC  

Digital supply voltage for ADC (1.8 V)  
Digital supply voltage for SQI I/O ring (1.8 V)  
Digital supply voltage for SQI I/O ring (3.3 V)  
Power supply pins for the core logic.  
V

DD_SQI  

V

DDD  

Digital supply voltage for FSMC I/O ring (1.8 V)  
Digital supply voltage for FSMC I/O ring (3.3 V)  
V

DDIO_FSMC  

30/42  
DS11733 Rev 3  
 
 
 

STA8090EXGA  
Electrical characteristics  
Table 17. Recommended DC operating conditions (continued)  
Symbol  
V

DDIO_R1  

Parameter  
Min.  
Typ. Max.
 
Unit  
Digital supply voltage for I/O ring 1 (1.8 V)  
Digital supply voltage for I/O ring 1 (3.3 V)  
1.71  
3.00  
3.00  
1.60  
1.60  
2.10  
1.60  
1.60  
2.10  
1.60  
-40  
1.80  
3.30  
3.30  
—
1.89  
3.60  
3.60  
4.30  
4.30  
4.30  
4.30  
4.30  
4.30  
4.30  
85  
V
V
V
V
V
V
V
V
V
V
°C  
V

DDIO_R2

Digital supply voltage for I/O ring 2 (3.3 V)  
V

INB  

V

INL1  

V

INL2  

V

INM  

Backup LDO input supply voltage (1.6 V to 4.3 V)  
LDO1 input supply voltage to generate 1.2 V  
LDO1 input supply voltage to generate 1.8 V  
LDO2 input supply voltage to generate 1.2 V  
SMPS coil input supply voltage to generate 1.2 V  
SMPS coil input supply voltage to generate 1.8 V  
SMPS input supply (1.6 V to 4.3 V)  
—
—
—
—
—
V

DD_ANA  

T

C  

—
Operating temperature range  
—
4.7  
DC characteristics  

T

a

ble 18

specifies the SMPS voltage regulator characteristics.  
Table 18. SMPS DC characteristics  
Symbol  
Parameter  
Test condition  
Min.  
Typ.  
Max.  
Unit  
1.6 V ≤ V

INM

≤ 4.3 V;  
I

OM

≤ 100 mA  
Output voltage (1.2 V)  
1.1  
1.20  
1.32  
V
V

OM  

2.1 V ≤ V

INM

≤ 4.3 V;  
I

OM

≤ 100 mA  
Output voltage (1.8 V)  
Output current  
1.71  
0
1.80  
—
1.89  
100  
V
I

OM  

mA  

T

a

ble 19

specifies the LDO1 voltage regulator characteristics.  
Table 19. LDO1 DC characteristics  
Symbol  
Parameter  
Test condition  
Min.  
Typ.  
Max.  
Unit  
1.6 V ≤ V

INL1

≤ 4.3 V;  
I

OL1

≤ 70 mA  
Output voltage (1.2V)  
1.1  
1.20  
1.32  
V
V

OL1  

2.1 V ≤ V

INL1

≤ 4.3 V;  
I

OL1

≤ 70 mA  
Output voltage (1.8V)  
Output current  
1.71  
0
1.80  
—
1.89  
70  
V
I

OL1  

mA  
DS11733 Rev 3  
31/42  
41  
 
 

Electrical characteristics  
STA8090EXGA  

T

a

ble 20

specifies the LDO2 voltage regulator characteristics.  
Table 20. LDO2 DC characteristics  
Test condition
 
Min.  
V

OL2

Output voltage
 
1.6 V ≤ V

INL2

≤ 4.3 V; I

OL2

≤ 30 mA  
I

OL2

Output current  
Symbol  
Parameter  
Typ.  
Max. Unit  
1.08  
0
1.20  
—
1.32  
30  
V
—
mA  

T

a

ble 21

specifies the low voltage detection thresholds  
Table 21. Low voltage detection thresholds  
Parameter  
Min.  
Typ. Max.
 
Unit  
Upper voltage threshold  
—
—
—
—
—
—
—
—
—
—
1.680  
1.650  
0.995  
0.935  
1.142  
1.076  
1.048  
0.986  
1.645  
1.626  
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
V
V
V
Input LVD always on  
and main VRs

(1)  

Lower voltage threshold  
Upper voltage threshold  
Output LVD always  
on VR

(1)  

Lower voltage threshold  
Upper voltage threshold @ V

OL1/M

= 1.2 V  
Lower voltage threshold @ V

OL1/M

= 1.2 V  
Upper voltage threshold @ V

OL1/M

= 1.1 V  
Lower voltage threshold @ V

OL1/M

= 1.1 V  
Upper voltage threshold @ V

OL1/M

= 1.8 V  
Lower voltage threshold @ V

OL1/M

= 1.8 V  
Output LVD main VR  
(1.1 V)

(1)  

Output LVD main VR  
(1.8 V)

(1)  

1. Not
 
tested in production.  

T

a

ble 22

lists the DC characteristics for all the IO digital buffers except for the following input  
buffers: STBYn (H9), STDBY_OUT (J10), WAKEUP0 (F11), WAKEUP1 (F10),  
PMU_CFG (H10) and RSTn (G9).  
Table 22. I/O buffers DC characteristics  
Symbol  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
V

DDIO

= 1.8 V  
V

DDIO

= 3.3V  
V

DDIO

= 1.8 V  
V

DDIO

= 3.3V  
–
-0.3  
-0.3  
—
—
—
—
—
—
—
—
—
0.3 * V

DDIO  

V
V
Logical input low level  
voltage  
(1)  
V

IL  

0.8  
0.7 * V

DDIO  

2.0  
V

DDIO

+ 0.3  
V
Logical input high level  
voltage  
(1)  
V

IH  

V

DDIO

+ 0.3  
V
(2)  
V

HYST  

Schmitt-trigger hysteresis  
Low level output voltage  
50  
—
0.4  
0.4  
—
mV  
V
V

DDIO

= 1.8 V  
—
V

OL  

V

DDIO

= 3.3V  
V

DDIO

= 1.8 V  
V

DDIO

= 3.3V  
—
V
V

DDIO

– 0.4  
V

DDIO

– 0.4  
V
V

OH  

High level output voltage  
—
V
1. Excludes
 
oscillator inputs RTC_XTI and XTAL_IN. Refer to oscillator electrical specifications.  
2. Apply
 
to all digital inputs unless specified otherwise.  
32/42  
DS11733 Rev 3  
 
 
 
 

STA8090EXGA  
Electrical characteristics  

T

a

ble 23

lists the DC characteristics for the 1.0 V IO digital buffers input buffers:  
STBYn (H9), STDBY_OUT (J10), WAKEUP0 (F11), WAKEUP1 (F10), PMU_CFG (H10)  
and RSTn (G9).  
Table 23. 1.0 V I/O buffers DC characteristics  
Symbol  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
V

IL  

V

IH  

Logical input low level voltage
 
V

OB

= 1.0 V  
Logical input high level voltage
 
V

OB

= 1.0 V  
-0.3  
0.65 * V

OB  

—
—
—
—
—
0.35 * V

OB  

V

OB

+ 0.3  
0.2  
V
V
V
V
V

OL  

V

OH  

Low level output voltage  
High level output voltage  
V

OB

= 1.0 V  
V

OB

= 1.0 V  
V

OB

– 0.2  
—
4.8  
AC characteristics  
4.8.1  
RF electrical specifications  
Table 24. RFCHAIN – GALGPS filter and VGA  
Symbol  
Parameter  
Test conditions  
GPS band  
Min  
Typ  
Max  
Unit  
S11

(1)  

Input return loss  
—
-8  
—
dB  
PLL in default condition with  
26Mhz as reference  
f

IF  

IF frequency  
Noise figure  
—
—
4.045  
2

(1)  

—
—
MHz  
dB  
NF overall chain with AGC  
set at 0 dB  
NF  
VGA at max gain  
VGA at min gain  
—
—
119  
62  
—
—
dB  
dB  
Conversion gain from  
RF input to ADC input  
C

G  

RF-IF-VGA input  
compression point  
IP

1dB  

VGA min  
—
-70  
—
dBm  
IRR  
Image rejection ratio  
—
—
—
20  
2.4  
4.8  
—
—
—
dB  
BW

GPS  

BW

GAL  

GPS mode  
MHz  
MHz  
-3dB IF bandwidth  
Galileo mode  
Alias frequency  
rejection  
F = 60 MHz  
(fs = 65.474 MHz)  
ATT  
—
30

(1)  

—
dB  
T

gGPS  

T

gGAL  

GPS mode  
—
—
—
—
200

(1)  

30

(1)  

ns  
ns  
IF filter group delay  
variation  
Galileo mode  
1. Not
 
tested in production.  
DS11733 Rev 3  
33/42  
41  
 
 

Electrical characteristics  
STA8090EXGA  
Table 25. RFCHAIN – GLONASS/BeiDou filter and VGA  
Symbol  
Parameter  
Test conditions  
Min  
Typ  
Max  
Unit  
GLONASS band  
BeiDou band  
—
—
-8  
-8  
—
—
S11

(1)  

Input return loss  
dB  
IF frequency for  
GLONASS  
PLL in default condition  
with 26 Mhz as  
reference  
—
—
—
8.519  
10.277  
2

(1)  

—
—
—
f

IFGNS/BDU  

MHz  
dB  
IF frequency for BeiDou  
Noise figure  
NF overall chain with  
AGC set at 0 dB  
NF  
VGA at max gain  
VGA at min gain  
—
—
118  
61  
—
—
dB  
dB  
Conversion gain from  
RF input to ADC input  
C

G  

RF-IF-VGA input  
compression point  
IP

1dB  

IRR  
VGA min  
—
-80  
—
dBm  
Image rejection ratio  
—
—
30  
10  
—
—
dB  
BW

GNS/BDU

-3dB IF bandwidth  
MHz  
F = 53 MHz  
(fs = 65.474 MHz)  
ATT  
Alias frequency rejection  
—
—
30

(1)  

—
dB  
ns  
IF filter group delay  
variation  
T

gGNS/BDU  

—
20

(1)  

1. Not
 
tested in production.  
Table 26. Synthesizer  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
F

TCXO_XTAL  

R

DIV  

Input frequency for xtal amplifier

(1)  

Reference divider range  
Loop divider range  
10  
1
—
—
—
55  
63  
MHz  
—
N

DIV  

56  
—
2047  
—
—
F

LO  

LO operating frequency  
3142.656  
MHz  
1. That
 
amplifier can be used also like TCXO input buffer  
4.8.2  
Oscillator electrical specifications  
This device contains two oscillators:  
a 32.768 kHz oscillator/buffer for RTC circuit.  
an OSCI oscillator/buffer in the RF Front-End  
When used in oscillator mode, each oscillator requires a specific crystal, with parameters  
that must be as close as possible to the following recommended values. When used in input  
buffer mode, an external clock source must be applied.  
34/42  
DS11733 Rev 3  
 
 

STA8090EXGA  
Electrical characteristics  
32.768 kHz OSCI32 oscillator specifications  
The 32.768 kHz OSCI32 oscillator is connected between RTC_XTI (oscillator amplifier  
input) and RTC_XTO (oscillator amplifier output). It also requires two external capacitors of  
(a)  
18 pF
 
, as shown on

Figure 2

.  
OSCI32 is disabled by default and must be enabled by setting bit28-OSCI_EN of  
PRCC_BACKUP_REG0 to have 32.768KHz oscillation when an XTAL pi-network is  
connected to RTC_XTI/RTC_XTO pins.  
The recommended oscillator specifications are shown in

Table 27

:  
Table 27. Crystal recommended specifications  
Symbol  
Parameter  
Crystal frequency

(1)  

Min.  
Typ.  
Max.  
Unit  
F

SXTAL  

LM

SXTAL  

CM

SXTAL  

CO

SXTAL  

ESR  
—
—
—
—
—
—
32.768  
5
—
—
—
—
80  
—
kHz  
kH  
fF  
Motion inductance

(1)  

Motional capacitance

(1)  

Shunt capacitance

(1)  

5.0  
1.3  
—
pF  
kΩ  
pF  
Resonance resistance

(1)  

External load capacitance

(1)  

CL  
18  
1. Not
 
tested in production.  
The oscillator amplifier specifications are shown in following table:  
Table 28. Oscillator amplifier specifications  
Symbol  
Parameter  
Min.  
Typ.  
Max. Unit  
T

S  

DL  
Startup time

(1)  

Drive level

(1)  

—
—
0.3  
—
0.6  
<0.1  
—
s
µW  
pF  
RLC  
GM  
Required load capacitance

(1)  

—
12.5  
33.6  
Startup transconductance  
22.5  
—
µA/V  
1. Not
 
tested in production.  
a. Using
 
crystal with recommended characteristics as per

Table 27

.  
DS11733 Rev 3  
35/42  
41  
 
 

Electrical characteristics  
STA8090EXGA  
Figure 2. 32.768 kHz crystal connection  
Device  
RCT_XTO  
CL = 18 pF  
RTC_XTII  
CL = 18 pF  
32.768 kHz  
Crystal  
To
d
rive the 32.768 kHz crystal pins from an external clock source:  
Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This  
disables the internal inverter, thus reducing the power consumption to minimum.  
Drive the RTC_XTI pin with a square signal or a sine wave.  
Table 29. Characteristics of external slow clock input  
Symbol  

JIT

(cc)  
T

JIT

(per)  
Parameter  
Cycle-to-cycle jitter  
Min.  
Typ.  
Max.  
Unit  
T
-70  
-70  
-500  
45  
—
—
—
—
70  
70  
ps  
ps  
Period jitter  
Variation  
500  
55  
ppm  
%
T

DUTY  

Duty cycle  
4.8.3  
4.8.4  
OSCI oscillator specifications  
The supported values of the embedded BOOT ROM are 16.368 MHz, 24.00 MHz,  
26.00 MHz and 48.00 MHz.  
The default values supported by the GNSS binary image are 26 MHz and 48 MHz, to enable  
USB peripheral the 48 MHz is mandatory.  
ADC specifications  
This section gives the AC specification of the 10 bit Successive Approximation Register  
ADC embedded in STA8090EXGA device. It is controlled by the ARM9 MCU through a  
wrapper and an APB bridge as depicted in

Figure 3

and it has a maximum conversion rate  
of 1MSPS with 8 muxed analog input channels capability. An internal voltage reference is  
used and analog/digital power supplies connections are implemented inside the device  
without any needs of dedicated external pins.  
36/42  
DS11733 Rev 3  

STA8090EXGA  
Electrical characteristics  
Figure 3. SARADC connections  
GND  
VINL1  
VDD12_MVR  
SARADC  
AIN0  
ADC_IN1  
ADC_IN2  
AIN1  
V
REF  
REFP  
REFN  
APB  
Bridge2  
D[9:0]  
AIN7  
ADC_IN8  
ADC WRAPPER  
Table 30. SARADC specifications  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
V

ADCIN

ADC_IN input range  
V

ADCCR

Conversion range  
V

GND

-0.3  
V

GND  

1.35  
—
—
V

DD_ADC

+0.3  
V

REF  

V
V
V

REF  

C

IN  

Voltage reference  
1.4  
7.0  
1.45  
V
Input capacitance

(1)  

5.5  
8.5  
pF  
Input mux resistance (total equivalent  
sampling resistance)

(2)  

R

IN  

1.5  
2.0  
2.5  
k
  
F

CLK  

CLK  

T

SUP  

T

C  

Clock frequency  
Clock duty cycle  
Start up time

(1)(3)  

Conversion time  
Sampling time  
2.5  
45  
—
—
—
—
—
15  
55  
20  
—
MHz  
%
50  
—
14  
3
µs  
cycles  
cycles  
LSB  
LSB  
T

S  

INL  
—
—
< ±2  
< ±2  
Performance  
DNL  
1. Not
 
tested in production.  
2. Pad
 
input capacitance included.  
3. From
 
EN = 1.  
DS11733 Rev 3  
37/42  
41  

Package and packing information  
STA8090EXGA  
5
Package and packing information  
5.1  
ECOPACK packages  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECOPACK packages, depending on their level of environmental compliance. ECOPACK  
specifications, grade definitions and product status are available at:

www.st.com

.  
ECOPACK is an ST trademark.  
5.2  
TFBGA169 9 x 9 x 1.2 mm package information  
Table 31. TFBGA169 9 x 9 x 1.2 mm mechanical data  
Dimensions (mm)  
Ref. dim  
Min.  
Typ.  
Max.  
A

(1)  

A1

(2)  

A2  
1.20  
0.21  
0.20  
0.585  
0.35  
9.00  
7.80  
9.00  
7.80  
0.65  
0.60  
A4  
b

(3)  

0.30  
8.85  
0.40  
9.15  
D
D1  
E
9.85  
9.15  
E1  
e
Z
ddd  
eee

(4)  

fff

(5)  

0.08  
0.15  
0.05  
1. TFBGA
 
stands for Thin profile Fine Pitch Ball Grid Array.  
– The total profile height (Dim A) is measured from the seating plane to the top of the component  
– The maximum total package height is calculated by the following methodology:  
A Max = A1 Typ + A2 Typ + A4 Typ +
(A1

2

+ A2

2

+ A4

2

tolerance values)  
– Thin profile: 1.00 mm < A
1.20 mm / Fine pitch: e < 1.00 mm pitch.  
2. –
 
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized  
markings, or other feature of package body or integral heatslug.  
– A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1  
corner. Exact shape of each corner is optional.  
3. The
 
typical ball diameter before mounting is 0.35 mm.  
4. The
 
tolerance of position that controls the location of the pattern of balls with respect to datums A and B.  
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true  
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball  
must lie within this tolerance zone.  
38/42  
DS11733 Rev 3  

STA8090EXGA  
Package and packing information  
5. The
 
tolerance of position that controls the location of the balls within the matrix with respect to each  
other.For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true  
position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.  
Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each  
ball must lie simultaneously in both tolerance zones.  
Figure 4. TFBGA169 9 x 9 x 1.2 mm package dimension  
1. –
 
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized  
markings, or other feature of package body or integral heatslug.  
– A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1  
corner. Exact shape of each corner is optional.  
DS11733 Rev 3  
39/42  
41  

Ordering information  
STA8090EXGA  
6
Ordering information  
Figure 5. Ordering information scheme  
Example code:  
STA8090EXGA  
J
D
TR  
Family identifier  
JTAG Support  
DRAW Support  
Packing  
TR =
T
a
pe and Reel  
<blank> = Tray  
D= GNSS+DRAW  
<blank> : GNSS Only)  
J = JTAG Disabled  
<blank> JTAG Enabled  
Automotive SoC family  
40/42  
DS11733 Rev 3  

STA8090EXGA  
Revision history  
7
Revision history  
Table 32. Document revision history  
Changes  
Date  
Revision  
07-Jul-2016  
1
Initial release.  
Updated:  
–

Table 16 on page 30

: removed the I

DSLEEP

parameter and added  

I

DStandby

and I

DDeepStandby

parameters;  
–

Table 24 on page 33

: the Typ. value of the C

G

and IP

1dB  

parameters, and add note (1) to t

he Typ. value of ATT parameter;  
11-May-2017  
04-Jun-2020  
2
3
–

Table 25 on page 34

: the Typ. values of the S11 and IRR  
parameters and add note (1) to teh Typ. value of ATT parameter;  
–

Table 26 on page 34

: the Max. value of the F

TCXO_XTAL

parameter.  
Minor text changes.  
DS11733 Rev 3  
41/42  
41  

STA8090EXGA  
IMPORTANT NOTICE – PLEASE READ CAREFULLY  
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and  
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on  
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order  
acknowledgement.  
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or  
the design of Purchasers’ products.  
No license, express or implied, to any intellectual property right is granted by ST herein.  
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
ST and the ST logo are trademarks of S
T
.
F
or additional information about ST trademarks, please refer to

www.st.com/trademarks

.
All other  
product or service names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2020 STMicroelectronics – All rights reserved  
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DS11733 Rev 3  

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