STMicroelectronics-STA8090FGBD

Part #	STMicroelectronics-STA8090FGBD
Download	STMicroelectronics-STA8090FGBD

STA8090FG

Fully integrated GPS/Galileo/GLONASS/BeiDou/QZSS receiver

with embedded RF and in-package Flash

Datasheet

–

production data



1 Secure-Digital Multimedia Memory Card

Interfaces (SDMMC)



1 Multichannel Serial Port (MSP)



Power Management Unit (PMU) embedding

switching regulator



Operating condition:

– Main

voltage regulator (V

): 1.6V to 4.3V

INL

– Backup

voltage (V

): 1.6V to 4.3V

INB

TFBGA99 (5 x 6 x 1.2 mm)

– Digital

voltage (V

): 1.0 V to 1.32 V

GAPG1812131450CFT

– RF

core voltage (V

): 1.2 V ± 10%

– IO

Ring Voltage (V

3.3 V ± 10%

): 1.8 V ± 5% or

ddIO

Features



Package:



STMicroelectronics positioning receiver with 48

tracking channels and 2 fast acquisition

channels supporting GPS, Galileo, GLONASS,

BeiDou and QZSS systems

– TFBGA99

(5 x 6 x 1.2 mm) 0.5 mm pitch



Operating temperature range: -40/+85°C



Single die standalone receiver embedding RF

Description

Front-End and low noise amplifier

STA8090FG belongs to

seo III family products.

STA8090FG is a single die standalone positioning

receiver IC working on multiple constellations

(GPS/Galileo/GLONASS/BeiDou/QZSS).



-162 dBm indoor sensitivity (tracking mode)



Fast TTFF < 1 s in Hot start and 30 s in Cold

Start



High performance ARM946 MCU (up to

STA8090FG, thanks to the ARM9 and wide IOs

availability, can be used as microcontroller with

GNSS capability, allowing a very compact design

offering 256 kByte of internal RAM and 16 Mbits

or 32 Mbits of internal Flash.

196 MHz)



256 Kbyte embedded SRAM



In-Package SQI Flash Memory (16 or 32 Mbits)



Real Time Clock (RTC) circuit



32-bit Watch-dog timer

The minimal BOM makes STA8090FG the ideal

solution for cost competitive and small footprint

products such as OBD dongle, insurance boxes,

trackers, telematics, portable, hands-held

portable and sports accessories.



3 UARTs



1 I

C master interface



1 Synchronous Serial Port (SSP, Motorola-SPI

supported)

STA8090FGBD can also run TESEO-DRAW the

STMicroelectronics dead reckoning firmware.



USB2.0 full speed (12 MHz) with integrated

physical layer transceiver



2 Controller Area Network (CAN)



2 channels ADC (10 bits)

June 2020

DS10719 Rev 6

This is information on a product in full production.

www.st.com

STA8090FG

Table 1. Device summary

Package

Root Part Number

Packaging

STA8090FG

TFBGA99 5x 6mm

pe and Reel

DS10719 Rev 6

STA8090FG

Contents

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TFBGA99 pin configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power supply pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main function pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

st/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Communication interface pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multimedia card pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF Front-end pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+) processor

. . . . . .

MCU Subsystem

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1

AHB slaves

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4

APB peripherals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SSP .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SDMMC .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

GPIO .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ADC .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.10 RTC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.11 MSP

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Electrical characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

Parameter conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS10719 Rev 6

Contents

STA8090FG

Minimum and maximum values

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended DC operating conditions

. . . . . . . . . . . . . . . . . . . . . . . . .

DC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RF electrical specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Oscillator electrical specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

OSCI oscillator specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Flash specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1

5.2

ECOPACK packages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TFBGA99 5 x 6 x 1.2 mm package information

. . . . . . . . . . . . . . . . . . . .

Ordering information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DS10719 Rev 6

STA8090FG

List of tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

TFBGA99 connection diagram (with CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TFBGA99 connection diagram (no CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Main function pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test/emulated dedicated pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Communication interface pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Multimedia card pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

RF Front-end pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Frequency limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power consumption

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Recommended DC operating conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SMPS DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LDO1 DC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

LDO2 DC characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Low voltage detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I/O buffers DC characteristic

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.0 V I/O buffers DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

RFACHAIN – GALGPS filter and VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

RFCHAIN – GLONASS/BeiDou filter and VGA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Synthesize

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Crystal recommended specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Oscillator amplifier specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Characteristics of external slow clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SARADC specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Flash specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TFBGA99 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Document revision history

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DS10719 Rev 6

STA8090FG

Overview

STA8090FG is one of the part number of

seo III STA8090x series.

STA8090FG is a highly integrated single-chip standalone GNSS receiver designed for

positioning system applications.

STA8090FG embeds the new ST GNSS positioning engine capable of receiving signals

from multiple satellite navigation systems, including the US GPS, European Galileo,

Russia’s GLONASS, Chinese BeiDou and Japan’s QZSS.

The STA8090FG ability of tracking simultaneously the signals from multiple satellites

regardless of their constellation, makes this chip capable of delivering exceptional accuracy

in urban canyons and in the environments where buildings and other obstructions make

satellite visibility challenging.

STA8090FG embeds innovative power management with switching regulator for power

consumption optimization.

The extended voltage supply ranges from 1.6 V to 4.3 V, the 1.8 V and 3.3 V I/O compliance

support makes the STA8090FG the suitable solution for different user applications.

The STA8090FG combines a high performance ARM946 microprocessor with I/O

capabilities and enhanced peripherals. It supports USB2.0 standard at full speed (12 Mbps)

with on-chip PH

The chip embeds backup logic with real time clock.

STA8090FG can host customer code on top of STMicroelectronics GNSS library.

Customers can develop on

seoIII their application code by using a software development

kit based on different real time operating systems.

STA8090FGBD can be offered also bundled with STMicroelectronics dead reckoning

firmware called TESEO-DRAW; TESEO-DRAW firmware is a multi-sensors data fusion hub

for

seo family IC’s.

The STA8090FG, using STMicroelectronics CMOSRF

chnology, is housed in a

TFBGA99 (5 x 6 x 1.2 mm) package with stacked 16 Mbit or 32 Mbit Flash memory.

DS10719 Rev 6

Pin description

STA8090FG

Pin description

2.1

Block diagram

Figure 1. STA8090FG system block diagram

G4RF IP

Antenna

Sensing

G3BB+ Correlator Engine

Acq

48 Trk

Channels

GG IF

ADC

LNA

Section

RAMs

CLOCK_GEN

OSCI

PLL

APB

Bridge

1 Fast Acq

Channel

GC IF

ADC

Section

SPI IF

AHB

Ring

OSCI

FLASH

(16Mb or 32Mb)

APB

Bridge3

IOs

UART2

UART0

Full

UART1

Rx-Tx

SDMMC

MSP

SSP

CAN0

APB2

CAN1

GPIO

Rx-Tx

SQI

Test

controller

APB

Bridge2

MTU

EFT

I2C

ADC

JTAG

USB

VIC

PMU

BK_Domain

HIGH SPEED D-TCM

128KB

PRCC

BKRAM 32KB

BKLDO

LDO2

LDO1

SMPS

I-Cache

ISO

16KB

CELL

APB

Bridge1

ARM 946

D-Cache

8KB

OSCI32

RTC

Bandgap, Bias, Oscillator, LVDs

HIGH SPEED I-TCM

16KB

GAPG1701141303CFT

DS10719 Rev 6

STA8090FG

Pin description

2.2

TFBGA99 pin configuration

Table 2. TFBGA99 connection diagram (with CAN)

VINM

VLX

VINM

VLX

GND

TDO

TDI

SPI_CLK SPI_CSN

VINL1

VOL1

GND

VINB

VOB

UART0_

CTS

UART2_

SPI_DI

GPIO1

VDD_SQI

ADC_IN2

GPIO0

GND

VDDIO_

UART2_

UART0_

RTS

VDD_

ADC

GND

SPI_DO

Reserved

RTC_XTO

UART0_

DTR

VOM

TMS

DSR

GND

UART0_

TRSTn

UART0_

VDD_ANA

GND

VDDD

GND

ADC_IN1 WAKEUP0 RTC_XTI

DCD

VDDD

GND

WAKEUP1 STDBYn

RSTn

STDBY_

OUT

PMU_

CFG

XTAL_

OUT

USB_DP

TCK

GND

MMC_

CLK

USB_DM GPIO10 MMC_D3

TP_IF_N

TP_IF_P

GND

VCC_PLL XTAL_IN

MMC_

CMD

ANT_

SENSE2

VCC_

CHAIN

CAN0_TX GPIO11 MMC_D2

VDDIO_

ANT_

SENSE1

CAN0_RX

GPIO2

MMC_D1 GND_LNA

GND_LNA GND_LNA

GND

I2C_SD I2C_CLK MMC_D0 VCC_RF

LNA_IN

VOL2

VINL2

GND

DS10719 Rev 6

Pin description

STA8090FG

Table 3. TFBGA99 connection diagram (no CAN)

VINM

VLX

VINM

VLX

SPI_CLK SPI_CSN

VINL1

VOL1

GND

VINB

GPIO0

VOB

UART0_

UART0_ UART2_

CTS RX

SPI_DI

GPIO1

VDD_SQI

ADC_IN2

GND

VDDIO_

UART2_ UART0_

VDD_

ADC

GND

TDO

SPI_DO

Reserved

RTC_XTO

RTS

UART0_

DTR

VOM

TMS

DSR

GND

UART0_

TRSTn

UART0_

VDD_ANA

GND

VDDD

GND

ADC_IN1 WAKEUP0 RTC_XTI

DCD

TDI

VDDD

GND

WAKEUP1 STDBYn

RSTn

STDBY_

OUT

PMU_

CFG

XTAL_

OUT

USB_DP

USB_DM

TCK

GND

MMC_

CLK

GPIO10

GPIO11

MMC_D3

MMC_D2

GPIO2

TP_IF_N

TP_IF_P

GND

VOL2

VCC_PLL XTAL_IN

UART0_

MMC_

CMD

ANT_

SENSE2

VCC_

CHAIN

GND

UART0_

VDDIO_

ANT_

SENSE1

MMC_D1

GND

GND_LNA

VINL2

GND

I2C_SD

I2C_CLK MMC_D0 VCC_RF

LNA_IN

GND

2.3

Power supply pins

Table 4. Power supply pins

Description

Symbol

I/O

voltage

I/O

STA8090FG

VCC_CHAIN

VCC_PLL

VCC_RF

VDD_ADC

VDD_SQI

VDDD

1.2 V

1.8 V

1.1 V

PWR Analog

supply voltage for RF chain (1.2V)

PWR Analog

supply voltage for PLL RF (1.2V)

PWR Analog

supply voltage for RF (1.2V)

PWR Digital

supply voltage for ADC (1.8V)

PWR Digital

supply voltage for SQI

PWR Digital

supply voltage

E5, F3, F4, G3

VDDIO_R1 1.8

V or 3.3 V

PWR Digital

supply voltage for I/O ring 1 (1.8 V or 3.3 V)

VDDIO_R2

VINB

3.3V

PWR Digital

supply voltage for I/O ring 2 (3.3 V)

1.6 V – 4.3 V

PWR Backup

LDO input supply voltage (1.6 V to 4.3 V)

1.6 V – 4.3 V

PWR LDO1

input supply voltage (1.6 V to 4.3 V)

1.6 V – 4.3 V

PWR LDO2

input supply voltage (1.6 V to 4.3 V)

VINL1

VINL2

10/41

DS10719 Rev 6

STA8090FG

Symbol

Pin description

STA8090FG

Table 4. Power supply pins (continued)

I/O Description

I/O

voltage

VINM

VDD_ANA

VLX

1.6 V – 4.3 V

PWR SMPS

coil input supply (1.6 V to 4.3 V)

1.6 V – 4.3 V

PWR SMPS

input supply (1.6 V to 4.3 V)

A1, A2

0 V – 4.3 V

1.0V

PWR SMPS

coil output

B1, B2

VOB

PWR LDO

backup output voltage (1.0 V)

LDO1 output voltage:

PMU_CFG = high -> 1.1 V (it can be also configured to

1.2 V)

VOL1

VOL2

VOM

1.1 V or 1.8 V

PWR

PMU_CFG = low -> 1.8 V

1.2 V

PWR LDO2

output voltage (1.2 V)

SMPS output voltage

PMU_CFG = high -> 1.8 V

1.1 V or 1.8 V

PWR

PMU_CFG = low -> 1.1 V (it can be also configured to

1.2 V)

A7, B9, C1,

C2, D2, D6,

D8, F1, F5, F6,

G4, G5, G6,

H6, H7, J6, J7,

K8, L1, L9

GND

GND Ground

GND_LNA

GND Ground

K5, K6, K7

2.4

Main function pins

Table 5. Main function pins

Description

Symbol

I/O

voltage

I/O

STA8090FG

1.4 V – 0 V typ

range

ADC_IN1

ADC Analog input [1]

ADC Analog input [2]

1.4 V – 0 V typ

range

ADC_IN2

Power management unit config pin

High -> VOL1 = 1.1

OM = 1.8 V

Low -> VOL1 = 1.8

, VOM = 1.1 V

PMU_CFG

1.0 V

Reset Input with Schmitt-Trigger characteristics and noise

filter.

RSTn

1.0 V

Input of the 32 KHz oscillator amplifier circuit and input of

the internal real time clock circuit.

RTC_XTI

1.0 V (max)

RTC_XTO

1.0 V (max)

1.0 V

Output of the oscillator amplifier circuit.

STDBY_OUT

When low, indicates the chip is in Standby mode

When low, the chip is forced in Standby Mode – All pins in

high impedance except the ones powered by Backup

supply

STDBYn

1.0 V

DS10719 Rev 6

/41

Pin description

Symbol

STA8090FG

Table 5. Main function pins (continued)

I/O

voltage

I/O

Description

WAKEUP0

WAKEUP1

1.0 V

WAKEUP from STANDBY mode

2.5

Test/emulated dedicated pins

Table 6. Test/emulated dedicated pins

Symbol

I/O

voltage

I/O

Description

STA8090FG

TCK

TDI

VDDIO_R2

1.2 V

JTAG Test Clock

JTAG Test Data In

TDO

JTAG Test Data Out

TMS

JTAG Test Mode Select

JTAG Test Circuit Reset

Diff.

st Point for IF – Negative

Diff.

st Point for IF – Positive

TRSTn

TP_IF_N

TP_IF_P

1.2 V

2.6

Communication interface pins

Table 7. Communication interface pins

Alternative

I/O

voltage

Symbol

I/O

Function

Description

STA8090FG

function

AF0

(default)

CAN0_RX

(1)

CAN0 receive data input

AF1

AF2

AF3

UART0_RX

ense

UART0 Rx data

CAN0_RX

(1)

VDDIO_R2

External temperature capture

port

I/O

I2C_SD

I2C serial data

AF0

(default)

CAN0_TX

(1)

CAN0 transmit data output

CAN0_TX

(1)

VDDIO_R2

I/O

AF1

AF2

AF3

UART0_TX

GPIO7

UART0 Tx data

General purpose I/O #7

I2C clock

I2C_CLK

AF0

(default)

I2C_CLK

GPIO8

I2C clock

I/O

AF1

AF2

AF3

General purpose I/O #8

I2C_CLK

VDDIO_R2

CAN1_TX

(1)

CAN1 transmit data output

SPI_CLK

SPI clock

/41

DS10719 Rev 6

STA8090FG

Symbol

Pin description

STA8090FG

Table 7. Communication interface pins (continued)

Alternative

I/O

voltage

I/O

Function

Description

function

AF0

(default)

I/O

I2C_SD

GPIO9

I2C serial data

General purpose I/O #9

I/O

AF1

AF2

AF3

I2C_SD

VDDIO_R2

VDDIO_R1

CAN1_RX

(1)

CAN1 receive data input

SPI_CSN

SPI_CLK

SPI chip select active low

SPI clock

AF0

(default)

I/O

AF1

AF2

AF3

GPIO25

SQI_CLK

MMC_CLK

General purpose I/O #25

SQI Flash clock

SPI_CLK

SPI_CSN

Multimedia Clock line

AF0

(default)

SPI chip select active low /

IO_Power Sel Ring 1

SPI_CSN

I/O

AF1

AF2

AF3

GPIO24

SQI_CEN

MMC_CMD

General purpose I/O #24

SQI Flash chip enable

I/O

Multimedia card command line

AF0

(default)

SPI_DI

ense

SPI serial data input / BOOT2

External temperature capture

port

I/O

AF1

SPI_DI

VDDIO_R1

I/O

AF2

AF3

SQI_SIO1/SO SQI

Flash data IO 1 / ser. output

MMC_D0

SPI_DO

GPIO27

Multimedia card data 0

SPI serial data output

General purpose I/O #27

AF0

(default)

I/O

AF1

AF2

AF3

SPI_DO

SQI_SIO0/SI SQI

Flash data IO 0 / ser. input

MMC_D1 Multimedia

card data 1

AF0

(default)

UART0_CTS UART0

clear to send

GPIO15 General

purpose I/O #15

I/O

AF1

AF2

AF3

UART0_CTS VDDIO_R1

UART0_DCD VDDIO_R1

i2s_out_sclk MSP

serial clock output

Clock GNSS

GNSS clock out

AF0

(default)

UART0_DCD UART0

data carrier detect

I/O

AF1

AF2

AF3

GPIO17

General purpose I/O #17

i2s_out_sdata MSP

serial data output

Clock GNSS

GNSS clock out

DS10719 Rev 6

/41

Pin description

Symbol

STA8090FG

Table 7. Communication interface pins (continued)

Alternative

I/O

voltage

I/O

Function

Description

function

AF0

(default)

UART0_DSR UART0

data set ready

GPIO16 General

purpose I/O #16

I/O

AF1

AF2

UART0_DSR VDDIO_R1

i2s_out_lrclk MSP

left/right clock output

GLONASS and BeiDou 3-bit

Sign GC

AF3

coding output (Sign)

AF0

(default)

I/O

UART0_DTR UART0

data terminal read

AF1

AF2

GPIO18

General purpose I/O #18

UART0_DTR VDDIO_R1

Extended function timer – input

capture A

Timer_ICAPA

GPS and Galileo 3-bit coding

Output (MAG1)

AF3

Mag_1 GG

AF0

(default)

UART0_RTS UART0

request to send

I/O

AF1

AF2

GPIO14

General purpose I/O #14

UART0_RTS VDDIO_R1

TCXO_OUT TCXO

out clock

GPS and Galileo 3-bit coding

output (Sign)

AF3

Sign GG

AF0

(default)

UART0_RX

UART0 Rx data

AF1

AF2

SPI_DO

SPI serial data output

SQI Flash data IO 2

UART0_RX VDDIO_R1

I/O

SQI_SIO2

Extended Function Timer – Input

Capture A

AF3

Timer_ICAPA

UART0_TX

AF0

(default)

UART0 Tx data / BOOT1

AF1

AF2

SPI_DI

Serial data input

UART0_TX VDDIO_R1

I/O

SQI_SIO3

SQI Flash data IO 3

Extended Function Timer –

Output Compare A

AF3

Timer_OCMPA

UART2_RX

AF0

(default)

UART 2 Rx data

I/O

AF1

AF2

AF3

GPIO28

I2C_SD

General purpose I/O #28

I2C serial data

UART2_RX VDDIO_R1

MMC_D2

Multimedia card data 2

/41

DS10719 Rev 6

STA8090FG

Symbol

Pin description

STA8090FG

Table 7. Communication interface pins (continued)

Alternative

I/O

voltage

I/O

Function

Description

function

AF0

(default)

UART2_TX

UART 2 Tx data / BOOT0

I/O

AF1

AF2

AF3

AF0

GPIO29

I2C_CLK

MMC_D3

USB_DM

General purpose I/O #29

I2C clock

UART2_TX VDDIO_R1

I/O

USB

Multimedia card data 2

USB D- signal

AF1

(default)

UART1_RX

UART1 Rx data

USB_DM

USB_DP

VDDIO_R2

AF2

AF3

AF0

CAN1_RX

(1)

CAN1 receive data input

I/O

I2C_SD

I2C serial data

USB D+ signal

USB

USB_DP

AF1

(default)

UART1_TX

UART1 Tx data

AF2

AF3

CAN1_TX

(1)

CAN1 transmit data output

I2C_CLK I2C

clock

1. Only

for STA8090FGB and STA8090FGBD.

2.7

Multimedia card pins

Table 8. Multimedia card pins

Alternative

Function

function

Symbol

I/O

voltage

I/O

Description

STA8090FG

AF0

(default)

MMC_CLK

Multimedia Clock line

AF1

i2s_out_lrclk MSP

left/right clock output

MMC_CLK VDDIO_R2

Extended Function Timer –

Timer_ICAPA

AF2

AF3

Input Capture A

I/O

GPIO4

General purpose I/O #4

Multimedia card command line

AF0

(default)

MMC_CMD

AF1

AF2

AF3

i2s_out_sdata MSP

serial data output

MMC_CMD VDDIO_R2

CAN0_TX

(1)

CAN0 transmit data output

General purpose I/O #5

I/O

GPIO5

DS10719 Rev 6

/41

Pin description

STA8090FG

Table 8. Multimedia card pins (continued)

Alternative

Symbol

I/O

voltage

I/O

Function

Description

function

AF0

(default)

I/O

MMC_D0

Multimedia card data 0

AF1

AF2

AF3

i2s_out_sclk

I2C_SD

MSP serial clock output

I2C serial data

MMC_D0

VDDIO_R2

I/O

GPIO20

General purpose I/O #20

AF0

(default)

I/O

MMC_D1

Multimedia card data 1

AF1

AF2

AF3

i2s_in_sdata MSP

serial data input

MMC_D1

GLONASS and BeiDou 3-bit

Sign GC

coding output (Sign)

I/O

GPIO21

MMC_D2

Reserved

General purpose I/O #21

Multimedia card data 2

Reserved

AF0

(default)

I/O

AF1

AF2

MMC_D2

MMC_D3

VDDIO_R2

CAN0_RX

(1)

CAN0 receive data input

External temperature capture

I/O

AF3

ense

port

AF0

(default)

MMC_D3

Multimedia card data 2

I/O

AF1

AF2

AF3

Reserved

Sign GG

GPIO23

Reserved

GPS 3-bit coding output (Sign)

General purpose I/O #23

I/O

1. Only

for STA8090FGB.

2.8

General purpose pins

Table 9. General purpose pins

I/O

voltage

Alternative

function

Symbol

I/O

Function

Description

STA8090FG

I/O AF0

(default)

GPIO0

General purpose I/O #0

Pulse per second input

AF1

AF2

PPS_IN

Extended Function Timer – Output

Compare B

GPIO0 VDDIO_R1

Timer_OCMPB

Mag_0 GC

GLONASS and BeiDou 3-bit coding

Output (MAG0)

AF3

/41

DS10719 Rev 6

STA8090FG

Symbol

Pin description

Table 9. General purpose pins (continued)

Alternative

I/O

voltage

I/O

Function

Description

STA8090FG

function

I/O AF0

(default)

GPIO1

General purpose I/O #1 / BOOT3

AF1

AF2

AF3

i2s_in_sdata MSP

serial data input

GPIO1 VDDIO_R1

PPS_OUT

ense

Pulse per second output

External temperature capture port

General purpose I/O #2

Reserved

I/O

I/O AF0

(default)

GPIO2

I/O

AF1

AF2

Reserved

Extended Function Timer – Input

Capture B

GPIO2 VDDIO_R2

Timer_ICAPB

Mag_1 GC

GLONASS and BeiDou 3-bit coding

Output (MAG1)

AF3

AF0

(default),

AF1

I/O

GPIO10

General purpose I/O #10

GPIO10 VDDIO_R2

Extended Function Timer – Input

Capture A

AF2

AF3

Timer_ICAPA

Extended Function Timer – Output

Compare B

Timer_OCMPB

AF0

(default),

AF1

I/O

GPIO11

General purpose I/O #11

GPIO11 VDDIO_R2

Extended Function Timer – Output

Compare A

AF2

AF3

Timer_OCMPA

Timer_ICAPB

Extended Function Timer – Input

Capture B

2.9

RF Front-end pins

Table 10. RF Front-end pins

Symbol

I/O

voltage

I/O

Description

STA8090FG

ANT_SENSE1

ANT_SENSE2

LNA_IN

3.3 V

1.2 V

Antenna sensing input 1

Antenna sensing input 2

Low Noise Amplifier Input

XTAL_IN

Input Side of Crystal Oscillator or TCXO Input

Output Side of Crystal Oscillator

XTAL_OUT

DS10719 Rev 6

/41

General description

STA8090FG

General description

3.1

RF front end

The RF front-end is able to down-convert both the GPS-Galileo signal from 1575.42 MHz to

4.092 MHz (4 Fo, being F0 = 1.023 MHz), the GLONASS signal from 1601.718 MHz to

8.57 MHz and the BeiDou signal from 1561.098 MHz to 10.23 MHz.

It embeds high performance LNA minimizing external component count and two LDOs to

supply the internal core facilitating requirements for external power supply. A three bits ADC

converts the IF signals to sign (SIGN) and magnitude (MAG0 and MAG1). They can be

sampled or not by SPI. The magnitude bits are internally integrated in order to control the

variable gain amplifiers. The VGA gain can be also set by the SPI interface.

The RF tuner accepts a wide range of reference clocks (10 to 52 MHz) and can generate

64 Fo sampling clock for the baseband and 192 Fo clock for MCU subsystem.

3.2

GPS/Galileo/GLONASS/BeiDou Base Band (G3BB+)

processor

STA8090FG integrates G3BB+ proprietary I

hich is the ST last generation high-

sensitivity Baseband processor fully compliant with GPS, Galileo, GLONASS and BeiDou

systems.

The baseband receives, from the embedded RF Front-End, two separate IF signals coded

in sign-magnitude digital format on 3 bits and the related clocks. The Galileo/GPS

(GALGPS) and GLONASS/BeiDou (GNSCOM) signals at the base band inputs are

centered on 4.092 MHz, 8.57 MHz and 10.23 MHz.

The baseband processes the two IF signals performing data codification, sample rate

conversion and final frequency conversion to zero IF before acquisition and tracking

correlations.

The baseband processor has the capability of acquiring and tracking the Galileo, GPS,

GLONASS and BeiDou signals in a simultaneous or single way, or a combination of three,

being GLONASS and BeiDou mutually exclusive. The number of tracking channels to be

used is programmable; the unused tracking channels can be powered down.

A complete multi-OS software library is provided by ST to handle GPS processing,

managing satellite acquisition, tracking, pseudo-range calculation and positioning,

generating the output in the standard NMEA message format or in a ST binary format. The

library includes support of ST self-trained assisted GPS (ST-AGPS), a complete and

scalable solution for assisting GPS start-up with autonomous and server-based ephemeris

prediction and extension.

3.3

MCU Subsystem

The implemented sub-system includes an AHB Lite bus matrix.

An ARM946 core is embedded in the sub-system and masters the AHB bus. The totally

available TCM SRAM is 256 KB. The amount of memory on ITCM and DTCM can be

/41

DS10719 Rev 6

STA8090FG

General description

configured by the ARM946 (see

Table 11: TCM Configuration

). ITCM can be configured as

Ni x 16 KB; DTCM can be configured as 128 + Nd x 16 KB, where Ni + Nd = 8, Ni



Table 11. TCM Configuration

TCMcfg [2]

TCMcfg [1]

TCMcfg [0]

ITCM

DTCM

16 KB

32 KB

48 KB

64 KB

80 KB

96 KB

112 KB

128 KB

240 KB

224 KB

208 KB

192 KB

176 KB

160 KB

144 KB

128 KB

3.3.1

AHB slaves



G3 APB port that allows to interface with the G3BB acquisition memory and control

registers.



512 Kbytes ROM

Vectored Interrupt Controller (VIC).

SQI flash memory controller

3 x ARM946 APB peripheral bus (APB1, APB2, APB3).

Vectored Interrupt Controller (VIC)

This Vectored Interrupt Controller (VIC) allows the operative system interrupt handler to

quickly dispatch interrupt service routines in response to peripheral interrupts. It provides a

software interface to the interrupt system. There are up to 64 interrupt lines. The VIC uses a

bit position for each different interrupt source.

The software can control each request line to generate software interrupts. Each interrupt

line can be independently enabled and configured to trigger a non-vectored Normal Interrupt

Request (IRQ) or Fast Interrupt Request (FIQ) to the ARM946 CPU. Sixteen interrupt lines

can also be selected to trigger a vectored IRQ.

The VIC has two operation modes: the user mode and the privilege mode, in order to have

the possibility to set (or not) one level of protection during execution.

FS USB device controller

Full speed USB device with transceiver.



It is an AHB slave. When active it requires a 48 MHz clock XTAL_IN.

DS10719 Rev 6

/41

General description

STA8090FG

3.4

APB peripherals

3.4.1

CAN

(a)

The 2 CAN

cores perform communication according to the CAN protocol version 2.0 part

A and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the

physical layer, additional transceiver hardware is required.

CAN consists of the CAN core, message RAM, message handler, control registers and

module. For communication on a CAN network, individual message objects are configured.

The message objects and identifier masks for acceptance filtering of received messages are

stored in the message RAM. All functions concerning the handling of messages are

implemented in the message handler. These functions include acceptance filtering, the

transfer of messages between the CAN core and the message RAM, and the handling of

transmission requests as well as the generation of the module interrupt.

The register set of the CAN can be accessed directly by the CPU through the module

interface. These registers are used to control/configure the CAN core and the message

handler and to access the message RAM.

CAN features



Supports CAN protocol version 2.0 part A and B

32 messages objects

Each message object has its own identifier mask

Maskable interrupt

Disabled automatic re-transmission mode for time triggered CAN applications

Programmable loop-back mode for self-test operation

Two 16-bit module interfaces to the AMBA APB bus from ARM

3.4.2

SSP

The SSP is a master interface for synchronous serial communication with peripheral

devices that have Motorola SPI.

The SSP performs serial-to-parallel conversion on data received from a peripheral device

on SPI_DI pin, and parallel-to-serial conversion on data written by CPU for transmission on

SPI_DO pin. The transmit and receive paths are buffered with internal FIFO memories

allowing up to 32 x 32-bit values to be stored independently in both transmit and receive

modes. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one

to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO.

The SSP includes a programmable bit rate clock divider and prescaler to generate the serial

output clock SSPCLK from the on-chip clock. One combined interrupt is delivered, which is

asserted from several internal maskable events.

a. STA8090FGB

and STA8090FGBD only (see

Figure 5: Ordering information scheme

/41

DS10719 Rev 6

STA8090FG

General description

SSP features

The SSP has the following features:



Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep

transmit FIFO

Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location

deep receive FIFO

Programmable data frame size from 4 to 32 bits

Programmable clock bit rate and prescaler

Programmable clock phase and polarity in SPI mode

3.4.3

UART

The UARTx (x = 0|1|2) performs serial-to-parallel conversion on data asynchronously

received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on

data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are

buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64

data byte with 4-bit status (break, frame, parity, and overrun) for receive.

UART features

The UARTx (x = 0|1|2) are Universal Asynchronous Receiver/Transmitter that support much

of the functionality of the industry-standard 16C650 UAR

he main features are:



Programmable baud rates up to UARTCLK / 16 (1.5 Mbps with UARTCLK at 24 MHz),

or up to UARTCLK / 8 (3.0 Mbps with UARTCLK at 24 MHz), with fractional baud-rate

generator



5, 6, 7 or 8 bits of data

Even, odd, stick or no-parity bit generation and detection

1 or 2 stop bit generation

Support of the modem control functions CTS, RTS, plus DCD, DSR, RTS, DTS and RI

(UART0 only)



Support of software flow control using programmable Xon/Xoff characters

False start bit detection

Line break generation and detection

Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO

Programmable FIFO disabling for 1-byte depth data path

These UAR

ary from industry-standard 16C650 on some minor points which are:



Receive FIFO trigger levels

The internal register map address space, and the bit function of each register differ

The deltas of the modem status signals are not available

1.5 stop bits is not supported

Independent receive clock feature is not supported

DS10719 Rev 6

/41

General description

STA8090FG

3.4.4

Flash

The STA8090FG integrates 16 Mbits or 32 Mbits of Flash Memory. This eliminates the need

of the external Flash simplifying the routing associated to integrate a GPS receiver into a

customer board.

3.4.5

3.4.6

SDMMC

STA8090FG features an SD/MMC host.

MTU

The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit

Free-Running decrementing Counters (FRCs). The FRCs have their own clock input,

allowing the counters to run from a much slower clock than the system clock.

The FRC is the part of the timer that performs the counting. There are four instantiations of

the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit

counter in the FRC is split up into two 16-bit counters.

3.4.7

WDT

Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog

clock is used to generate a regular interrupt (WDOGINT), depending on a programmed

value.

The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt

remains unserviced for the entire programmed period. You can enable or disable the

watchdog unit as required.

Note:

Watchdog is stalled when the ARM processor is in Debug mode.

3.4.8

GPIO

The GPIO block provides twenty-one (21) programmable inputs or outputs. Each input or

output can be controlled in two modes:



software mode through an APB bus interface

alternate mode, where GPIO becomes a peripheral input or output line

Any GPIO input can be independently enabled or disabled (masked) for interrupt

generation. User can select for each GPIO which edge (rising, falling, both) will trigger an

interrupt.

3.4.9

ADC

10 bit SAR ADC operating at 1.8 V analog supply. It can convert up to 2 single ended

channels with analog input multiplexer at 500KSPS

3.4.10

RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 32 Kbyte

SRAM and supplied with a dedicated voltage regulator.

The RTC provides a high resolution clock which can be used for GPS. It keeps the time

when the system is inactive and can be used to wake the system up when a programmed

/41

DS10719 Rev 6

STA8090FG

General description

alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the

32.768 kHz crystal and a secured time update.

RTC features



47-bit counter clocked by 32.768 kHz clock

32-bit for the integer part (seconds) and 15-bit for the fractional part

The integer part and the fractional part are readable independently

The counter, once enabled, can be stopped

Integer part load register (32-bit)

Fractional part load register (15-bit)

Load bit to transfer the content of the entire load register (integer+fractional part) to the

47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the

MCU that the RTC has been updated.

3.4.11

MSP

The STA8090FG provides one MSP transmitter block.



Element (data) size from 8 to 32 bits, LSB or MSB first

Programmable frequency shift clock for data transfer

Direct interface to:

–

Industry-standard codecs and serially connected A/D and D/A devices

IIS compliant devices

SPI compliant devices



Transmit first-in, first-out memory buffers (FIFOs), 32 bits wide, 8 locations deep

DS10719 Rev 6

/41

Electrical characteristics

STA8090FG

Electrical characteristics

4.1

Parameter conditions

Unless otherwise specified, all voltages are referred to GND.

4.2

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

= 25°C.

4.3

4.4

4.5

Typical values

Unless otherwise specified, typical data are based on T

= 25°C, V

They are given only as design guidelines and are not tested.

= 1.8

, V

.20

ddio

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Absolute maximum ratings

This product contains devices to protect the inputs against damage due to high static

voltages, however it is advisable to take normal precautions to avoid application of any

voltage higher than the specified maximum rated voltages.

ble 12

lists the absolute maximum rating for STA8090FG.

Table 12. Voltage characteristics

Symbol

Parameter

Min.

Max.

Unit

CC_CHAIN

Analog supply voltage for RF chain (1.2 V)

CC_PLL

Analog supply voltage for PLL RF (1.2 V)

-0.3

1.32

1.98

1.95

1.32

3.63

4.8

CC_RF

Analog supply voltage for RF (1.2 V)

DD_ADC

Digital supply voltage for ADC (1.8 V)

DD_SQI

Digital supply voltage for SQI

DDD

Power supply pins for the core logic.

DDIO_R1

Digital supply voltage for I/O ring 1 (1.8 V or 3.3 V)

DDIO_R2

Digital supply voltage for I/O ring 2 (3.3 V)

INB

Backup LDO input supply voltage (1.6 V to 4.3 V)

LDO1 input supply voltage (1.6 V to 4.3 V)

INL1

4.8

/41

DS10719 Rev 6

STA8090FG

Electrical characteristics

Table 12. Voltage characteristics (continued)

Symbol

Parameter

Min.

Max.

Unit

INL2

INM

LDO2 input supply voltage (1.6 V to 4.3 V)

SMPS coil input supply (1.6 V to 4.3 V)

-0.3

-2

4.8

DD_ANA

SMPS input supply (1.6 V to 4.3 V)

ESD-HBM

Electrostatic discharge, human body model

(1)

ESD-CDM

Electrostatic discharge, charge device model

(2)

-250

250

1. Balls

sustaining only ±500 V are: A1, A2, A5, A6, A7, A8, A9, B1, B2, B9, C1, C2, D1, D2, D9, E1, E9, F1,

L7 and L8.

2. Ball

L6 (LNA_IN) sustains only ±150

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Table 13. Thermal characteristics

Symbol

Parameter

Min.

Max.

Unit

oper

Operative temperature range

Operative junction temperature

Storage temperature

-40

-55

125

150

°C

j-amb

Thermal resistance junction to ambient

(1)

°C/W

1. According

to JEDEC specification on a 2 layers board.

Table 14. Frequency limits

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

CLK

AHB

Operating ARM9 CPU frequency

AHB frequency

—

196

MHz

_{DDD
= 1.2 V;}

= 85

(1)

1. Not

tested in production.

DS10719 Rev 6

/41

Electrical characteristics

Symbol

STA8090FG

Table 15. Power consumption

Parameter

Test condition

Min.

Typ. Max.

Unit

G2 = GPS/Galileo;

amb

= 25 °C;

INL2

= 1.8 V

—

G2 + GLONASS;

_{amb
= 25 °C;}

—

RFIP power (total V

INL2

)

INL2

= 1.8 V

G2 + COMPASS;

Beidou2



amb

= 25 °C;

INL2

= 1.8 V

_{ARM
= 196 MHz;}

AHB

= 49 MHz;

amb

= 25 °C;

INL1

= 1.8 V; UART

active; other peripherals

inactive

Switchable area power;

(total V

INL1

(1)

MVR

—

)

ARM

= 196 MHz;

AHB

= 49 MHz;

amb

= 25 °C; V

INB

= 3.3 V

Always ON area power

(total V

INB

(1)

LPVR

)

_{ARM
= 196 MHz;}

AHB

= 49 MHz;

amb

= 25 °C;

INL1

= 1.8 V; UART

active; other peripherals

inactive

IO rings power (total

DDIO_R1

+ V

DDIO_R2

(1)

)

Standby mode supply

current

DStandby

—

µA

RTC

running = 32.768 KHz;

amb

= 25 °C; V

INB

= 1.8 V

Deep standby mode

supply current

(2)

DDeepStandby

1. Not

tested in production.

2. STDBY_OUT

pin not supported in deep standby.

4.6

Recommended DC operating conditions

ble 16

lists the functional recommended operating DC parameters for STA8090FG.

Table 16. Recommended DC operating conditions

Symbol

Parameter

Min.

Typ. Max.

Unit

CC_CHAIN

Analog supply voltage for RF chain (1.2 V)

CC_PLL

Analog supply voltage for PLL RF (1.2 V)

CC_RF

Analog supply voltage for RF (1.2 V)

DD_ADC

Digital supply voltage for ADC (1.8 V)

DD_SQI

Flash power supply.

1.08

1.71

1.20

1.80

1.32

1.89

/41

DS10719 Rev 6

STA8090FG

Electrical characteristics

Table 16. Recommended DC operating conditions (continued)

Symbol

Parameter

Min.

Typ. Max.

Unit

DDD

Power supply pins for the core logic.

1.00

1.71

3.00

1.60

1.10

1.80

3.30

1.32

1.89

3.60

4.30

Digital supply voltage for I/O ring 1 (1.8 V)

Digital supply voltage for I/O ring 1 (3.3 V)

DDIO_R1

DDIO_R2

Digital supply voltage for I/O ring 2 (3.3 V)

INB

INL1

INL2

Backup LDO input supply voltage (1.6 V to 4.3 V)

LDO1 input supply voltage to generate 1.1 V and 1.2 V

1.60

LDO1 input supply voltage to generate 1.8 V

LDO2 input supply voltage to generate 1.2 V

2.10

1.60

SMPS coil input supply voltage to generate 1.1 V and

1.2 V

1.60

4.30

INM

SMPS coil input supply voltage to generate 1.8 V

2.10

1.60

-40

4.30

DD_ANA

SMPS input supply (1.6 V to 4.3 V)

Operating temperature range

°C

4.7

DC characteristics

ble 17

specifies the SMPS voltage regulator characteristics.

Table 17. SMPS DC characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

1.6 V ≤ V

INM

≤ 4.3 V;

≤ 100 mA

Output voltage (1.2 V)

1.08

1.0

1.20

1.10

1.32

1.21

1.6 V ≤ V

INM

≤ 4.3 V;

≤ 100 mA

Output voltage (1.1 V)

2.1 V ≤ V

INM

≤ 4.3 V;

≤ 100 mA

Output voltage (1.8 V)

Output current

1.71

1.80

—

1.89

100

ble 18

specifies the LDO1 voltage regulator characteristics.

DS10719 Rev 6

/41

Electrical characteristics

Symbol

STA8090FG

Table 18. LDO1 DC characteristics

Parameter

Test condition

Min.

Typ.

Max.

Unit

1.6 V ≤ V

INL1

≤ 4.3 V;

OL1

≤ 70 mA

Output voltage (1.2V)

Output voltage (1.1V)

1.08

1.20

1.32

1.6 V ≤ V

INL1

≤ 4.3 V;

OL1

≤ 70 mA

OL1

1.10

1.21

2.1 V ≤ V

INL1

≤ 4.3 V;

OL1

≤ 70 mA

Output voltage (1.8V)

Output current

1.71

1.80

—

1.89

OL1

ble 19

specifies the LDO2 voltage regulator characteristics.

Table 19. LDO2 DC characteristics

Symbol

Parameter

Output voltage

Output current

Test condition

Min.

Typ.

Max.

Unit

1.6 V ≤ V

INL2

≤ 4.3 V;

_{OL2
≤ 30 mA}

OL2

1.08

1.20

—

1.32

ble 20

specifies the low voltage detection thresholds

Table 20. Low voltage detection thresholds

Parameter

Min.

Typ.

Max.

Unit

Upper voltage threshold

—

1.680

1.650

0.995

0.935

1.142

1.076

1.048

0.986

1.645

1.626

—

Input LVD always

on and main VRs

(1)

Lower voltage threshold

Upper voltage threshold

Output LVD always

on VR

(1)

Lower voltage threshold

Upper voltage threshold @ V

OL1/M

= 1.2 V

Lower voltage threshold @ V

OL1/M

= 1.2 V

Upper voltage threshold @ V

OL1/M

= 1.1 V

Lower voltage threshold @ V

OL1/M

= 1.1 V

Upper voltage threshold @ V

OL1/M

= 1.8 V

Lower voltage threshold @ V

OL1/M

= 1.8 V

Output LVD main

(1)

Output LVD main

(1)

1. Not

tested in production.

ble 21

lists the DC characteristics for all the IO digital buffers expect for the following input

buffers: STBYn (F8), STDBY_OUT (G7), WAKEUP0 (E8), WAKEUP1 (F7), PMU_CFG (G8)

and RSTn (F9).

/41

DS10719 Rev 6

STA8090FG

Electrical characteristics

Table 21. I/O buffers DC characteristics

Test

conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

_{DDIO
= 1.8 V}

-0.3

—

0.3 * V

DDIO

0.8

(1)

Logical input low level voltage

DDIO

= 3.3V

DDIO

= 1.8 V

DDIO

= 3.3V

–

0.7 * V

DDIO

2.0

DDIO

+ 0.3

DDIO

+ 0.3

Logical input high level

voltage

(1)

(2)

HYST

Schmitt-trigger hysteresis

Low level output voltage

DDIO

= 1.8 V

0.4

DDIO

= 3.3V

_{DDIO
= 1.8 V}

_{DDIO
= 3.3V}

DDIO

– 0.4

DDIO

– 0.4

High level output voltage

1. Excludes

oscillator inputs RTC_XTI and XTAL_IN. Refer to oscillator electrical specifications.

2. Apply

to all digital inputs unless specified otherwise.

ble 22

lists the DC characteristics for the 1.0 V IO digital buffers input buffers: STBYn

(F8), STDBY_OUT (G7), WAKEUP0 (E8), WAKEUP1 (F7), PMU_CFG (G8) and RSTn (F9).

Table 22. 1.0 V I/O buffers DC characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Logical input low level voltage

= 1.0 V

Logical input high level voltage

= 1.0 V

-0.3

—

0.35 * V

+ 0.3

0.2

0.65 * V

Low level output voltage

High level output voltage

= 1.0 V

– 0.2

4.8

AC characteristics

4.8.1

RF electrical specifications

Table 23. RFACHAIN – GALGPS filter and VGA

Symbol

Parameter

Test conditions

GPS band

Min

Typ

Max

Unit

S11

(1)

Input return loss

—

-8

PLL in default condition with

26Mhz as reference

IF frequency

Noise figure

—

4.045

(1)

MHz

NF overall chain with AGC set

at 0 dB

VGA at max gain

VGA at min gain

—

119

Conversion gain from

RF input to ADC input

DS10719 Rev 6

/41

Electrical characteristics

Symbol

STA8090FG

Table 23. RFACHAIN – GALGPS filter and VGA (continued)

Parameter

Test conditions

Min

Typ

Max

Unit

RF-IF-VGA input

compression point

1dB

VGA min

—

-80

dBm

IRR

Image rejection ratio

—

2.4

4.8

GPS

GAL

GPS mode

MHz

-3dB IF bandwidth

Galileo mode

Alias frequency

rejection

F = 60 MHz

(fs = 65.474 MHz)

ATT

—

gGPS

gGAL

GPS mode

—

200

(1)

IF filter group delay

variation

Galileo mode

1. Not

tested in production.

/41

DS10719 Rev 6

STA8090FG

Electrical characteristics

Table 24. RFCHAIN – GLONASS/BeiDou filter and VGA

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

GLONASS band

BeiDou band

-10

-7

S11

(1)

Input return loss

IF frequency for

GLONASS

PLL in default condition

with 26 Mhz as

reference

—

8.519

10.277

(1)

IFGNS/BDU

MHz

IF frequency for BeiDou

Noise figure

NF overall chain with

AGC set at 0 dB

VGA at max gain

VGA at min gain

—

118

Conversion gain from

RF input to ADC input

RF-IF-VGA input

compression point

1dB

IRR

VGA min

—

-80

dBm

Image rejection ratio

—

GNS/BDU

-3dB IF bandwidth

MHz

F = 53 MHz

(fs = 65.474 MHz)

ATT

Alias frequency rejection

—

IF filter group delay

variation

gGNS/BDU

(1)

1. Not

tested in production.

Table 25. Synthesizer

Symbol

Parameter

Min.

Typ.

Max.

Unit

TCXO_XTAL

DIV

Input frequency for xtal amplifier

(1)

Reference divider range

Loop divider range

MHz

DIV

2047

LO operating frequency

3142.656

MHz

1. That

amplifier can be used as a TCXO input buffer.

DS10719 Rev 6

/41

Electrical characteristics

STA8090FG

4.8.2

Oscillator electrical specifications

This device contains two oscillators:



a 32.768 kHz oscillator/buffer for RTC circuit.

an OSCI oscillator/buffer in the RF Front-End

When used in oscillator mode, each oscillator requires a specific crystal, with parameters

that must be as close as possible to the following recommended values. When used in input

buffer mode, an external clock source must be applied.

32.768 kHz OSCI32 oscillator specifications

The 32.768 kHz OSCI32 oscillator is connected between RTC_XTI (oscillator amplifier

input) and RTC_XTO (oscillator amplifier output). It also requires two external capacitors of

(b)

18 pF

, as shown on

Figure 2

OSCI32 is disabled by default and must be enabled by setting bit28-OSCI_EN of

PRCC_BACKUP_REG0 to have 32.768KHz oscillation when an XTAL pi-network is

connected to RTC_XTI/RTC_XTO pins.

The recommended oscillator specifications are shown in

Table 26

Table 26. Crystal recommended specifications

Symbol

Parameter

Crystal frequency

(1)

Min.

Typ.

Max.

Unit

SXTAL

ESR

—

32.768

—

kHz

Motion inductance

(1)

Motional capacitance

(1)

Shunt capacitance

(1)

5.0

1.3

—

kΩ

Resonance resistance

(1)

External load capacitance

(1)

1. Not

tested in production.

The oscillator amplifier specifications are shown in the following table:

Table 27. Oscillator amplifier specifications

Symbol

Parameter

Min.

Typ.

Max. Unit

Startup time

(1)

Drive level

(1)

—

0.3

—

0.6

<0.1

—

µW

RLC

Required load capacitance

(1)

—

12.5

33.6

Startup transconductance

22.5

—

µA/V

1. Not

tested in production.

b. Using

crystal with recommended characteristics as per

Table 26

/41

DS10719 Rev 6

STA8090FG

Electrical characteristics

Figure 2. 32.768 kHz crystal connection

Device

RCT_XTO

CL = 18 pF

RTC_XTII

CL = 18 pF

32.768 kHz

Crystal

rive the 32.768 kHz crystal pins from an external clock source:



Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This

disables the internal inverter, thus reducing the power consumption to minimum.



Drive the RTC_XTI pin with a square signal or a sine wave.

Table 28. Characteristics of external slow clock input

Symbol

_JIT
(cc)

JIT

(per)

Parameter

Cycle-to-cycle jitter

Min.

Typ.

Max.

Unit

-70

-500

—

Period jitter

Variation

500

ppm

DUTY

Duty cycle

4.8.3

4.8.4

OSCI oscillator specifications

The supported values of the embedded BOOT ROM are 16.368 MHz, 24.00 MHz,

26.00 MHz and 48.00 MHz.

The default values supported by the GNSS binary image is 26 MHz and 48 MHz, to enable

USB peripheral the 48 MHz is mandatory.

ADC specifications

This section gives the AC specification of the 10 bit Successive Approximation Register

ADC embedded in STA8090FG device. It is controlled by the ARM9 MCU through a

wrapper and an APB bridge as depicted in

Figure 3

and it has a maximum conversion rate

of 1MSPS with 8 muxed analog input channels capability. An internal voltage reference is

used and analog/digital power supplies connections are implemented inside the device

without any needs of dedicated external pins.

DS10719 Rev 6

/41

Electrical characteristics

STA8090FG

Figure 3. SARADC connections

GND

VINL1

VDD12_MVR

SARADC

AIN0

ADC_IN1

AIN1

REF

ADC_IN2

REFP

REFN

APB

Bridge2

D[9:0]

AIN7

ADC_IN8

ADC WRAPPER

Table 29. SARADC specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

ADCIN

ADC_IN input range

ADCCR

Conversion range

GND

-0.3

GND

1.35

—

INL1

+0.3

REF

1.45

REF

Voltage reference

1.4

7.0

Input capacitance

(1)

5.5

8.5

Input mux resistance (total

1.5

2.0

2.5



equivalent sampling resistance)

(2)

CLK



CLK

SUP

Clock frequency

Clock duty cycle

Start up time

(1)(3)

Conversion time

Sampling time

2.5

—

MHz

—

µs

cycles

LSB

INL

< +/- 2

Performance

DNL

1. Not

tested in production.

2. Pad

input capacitance included.

3. From

EN=1.

/41

DS10719 Rev 6

STA8090FG

Electrical characteristics

4.8.5

Flash specifications

This section gives the AC specification of the embedded Flash in STA8090FG device.

Table 30. Flash specifications

Symbol

Parameter

Test conditions

Min.

Typ.

Max. Unit

QPI mode – 4 read

instructions

Serial clock frequency

—

78 MHz

Size = 16 Mb

Size = 32 Mb

Size = 16 Mb

Size = 32 Mb

Size = 16 Mb

Size = 32 Mb

Size = 16 Mb

Size = 32 Mb

—

200

BE32

Sector erase cycle time

Block erase (32 KB) cycle time

Block erase (64 KB) cycle time

0.25

0.2

0.5

0.35

12.5

Chip erase time

0.008 +

(n x 0.004)

Size = 16 Mb

Size = 32 Mb

—

Page program cycle time

0.008 +

(n x 0.004)

DS10719 Rev 6

/41

Package and packing information

STA8090FG

Package and packing information

5.1

ECOPACK packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at:

www.st.com

ECOPACK is an ST trademark.

5.2

TFBGA99 5 x 6 x 1.2 mm package information

Table 31. TFBGA99 package dimensions

Symbol

Min.

Typ.

Max

1.20

0.15

0.28

0.60

0.35

6.15

0.25

5.85

0.30

6.00

5.00

4.00

0.50

4.85

5.15

ddd

eee

fff

0.08

0.15

0.05

/41

DS10719 Rev 6

STA8090FG

Package and packing information

Figure 4. TFBGA99 5 x 6 x 1.2 mm package dimension

GAPG1701141247CFT

DS10719 Rev 6

/41

Ordering information

STA8090FG

Ordering information

Figure 5. Ordering information scheme

Example code:

STA8090F

Draw

Support

GNSS

Packing

Qualified Grade

/CAN Bus

Family identifier

Flash size

TR =

pe and Reel



<blank> = Tray



D =

GNSS + DRAW



<blank> = GNSS only

B = Industrial Grade (with CAN)



<blank> = Industrial Grade (no CAN)



G = GPS/Galileo/GLONASS/BeiDou/QZSS



4 = 32 Mbit



<blank> = 16 Mbit



seo III with Stacked Flash

/41

DS10719 Rev 6

STA8090FG

Revision history

Table 32. Document revision history

Changes

Date

Revision

21-Nov-2014

Initial release.

Table 6: Test/emulated dedicated pins

– TDI, TMS: updated description

Table 7: Communication interface pins

– SPI_DI: updated description

Table 9: General purpose pins

– GPIO1: updated description

04-Dec-2014

Table 20: Low voltage detection thresholds

– Input LVD always on and main VRs: removed minimum and maximun values

Updated

Features

and

Description

Updated

Chapter 1: Overview

Updated

Figure 1: STA8090FG system block diagram

Table 4: Power supply pins

– VOL1 VOM, VDDD: updated description

Updated

and

Added

and

Table 12: Voltage characteristics

– V

ESD-HBM

, V

ESD-CDM

: updated values

Table 15: Power consumption

– P

: updated typical value for GPS/Galileo

– P

MVR

, P

LPVR

, P

: added note

– I

DSLEEP

: updated value

Table 16: Recommended DC operating conditions

– V

INL1

, V

INL2

, V

INM

: updated parameter

Table 17: SMPS DC characteristics

05-Nov-2015

– V

: set min and max values as TBD, removed condition for Output voltage at 1.0 V

Table 18: LDO1 DC characteristics

– V

OL1

: set min and max values as TBD, removed condition for Output voltage at 1.0 V

Table 19: LDO2 DC characteristics

– V

OL2

: set min and max values as TBD

Table 20: Low voltage detection thresholds

– Output LVD main VR: removed condition for Output voltage at 1.0 V

Table 23: RFACHAIN – GALGPS filter and VGA

– S11: Added note

– C

: updated values

Table 24: RFCHAIN – GLONASS/BeiDou filter and VGA

– S11: Added note

– C

: updated values

Table 27: Oscillator amplifier specifications

– T

: updated minimum value

Updated

Section 4.8.3: OSCI oscillator specifications



Section 4.8.5: Flash specifications

and

Chapter 6: Ordering information

DS10719 Rev 6

/41

Revision history

STA8090FG

Table 32. Document revision history (continued)

Changes

Date

Revision

Added STA8090FGBD option for DRAW support.

Updated

Section 1: Overview

Table 15: Power consumption

– Updated Min., Typ. and Max. values

Table 17: SMPS DC characteristics

– Updated Min., Typ. and Max. values

Table 18: LDO1 DC characteristics

– Updated Min., Typ. and Max. values

Table 19: LDO2 DC characteristics

– Updated Min., Typ. and Max. values

Updated

Figure 5: Ordering information scheme

22-Mar-2017

Updated:

29-May-2017

05-Jun-2020

Table 15: Power consumption

: removed I

DSLEEP

and added I

DStandby

and I

DDeepStandby

parameters.

Minor text changes.

/41

DS10719 Rev 6

STA8090FG

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or

the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of S

or additional information about ST trademarks, please refer to

www.st.com/trademarks

All other

product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DS10719 Rev 6

41/41

STMicroelectronics-STA8090FGBD

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