STMicroelectronics-STB50N65DM6

Part #STMicroelectronics-STB50N65DM6
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STMicroelectronics-STB50N65DM6
STB50N65DM6  
Datasheet  
N-channel 650
V
,
7
4 mΩ typ., 33 A, MDmesh DM6 Power MOSFET in a D²PAK  
package  
Features  
TAB  
V
R
DS(on)  
max.  
I
D
Order code  
DS  
STB50N65DM6  
650 V  
91 mΩ  
33 A  
2
1
3
•
•
•
•
•
•
Fast-recovery body diode  
Lower R

DS(on)

per area vs previous generation  
D²  
PAK  
Low gate charge, input capacitance and resistance  
100% avalanche tested  
D(2, TAB)  
Extremely high dv/dt ruggedness  
Zener-protected  
G(1)  
Applications  
•
Switching applications  
S(3)  
AM01476v1_tab  
Description  
This high-voltage N-channel Power MOSFET is part of the MDmesh DM6 fast-  
recovery diode series. Compared with the previous MDmesh fast generation, DM6  
combines very low recovery charge (Q

rr

), recovery time (t

rr

) and excellent  
improvement in R

DS(on)

per area with one of the most effective switching behaviors  
available in the market for the most demanding high-efficiency bridge topologies and  
ZVS phase-shift converters.  
Product status link  
Product summary  
Order code  
Marking  
STB50N65DM6  
50N65DM6  
D²PAK  
Package  
Packing  
T
a
pe and reel  
DS13187
–
Rev 2
–
July 2020  
For further information contact your local STMicroelectronics sales office.  

STB50N65DM6  
Electrical ratings  
1
Electrical ratings  
Table 1.
Absolute maximum ratings  
Parameter  
Symbol  
Value  
±25  
33  
Unit  
V
V
Gate-source voltage  
GS  
I
Drain current (continuous) at T
 
= 25 °C  
A
D
C
I
Drain current (continuous) at T
 
= 100 °C  
21  
A
D
C
I
Drain current (pulsed)  
120  
250  
100  
1000  
100  
A
DM  
P
T
o
tal power dissipation at T
 
= 25 °C  
W
TOT  
C
dv/dt

di/dt

dv/dt

Peak diode recovery voltage slope  
Peak diode recovery current slope  
MOSFET dv/dt ruggedness  
V/ns  
A/µs  
V/ns  
T
stg  
Storage temperature range  
-55 to 150  
°C  
T
Operating junction temperature range  
J
1. Pulse
 
width limited by safe operating area  
2.  
3.  
I
≤ 33 A, V
 
(peak) < V  
, V
 
= 400V  
(BR)DSS DD  
SD  
DS  
V
≤ 520 V  
DS  
Table 2.
Thermal data  
Symbol  
Parameter  
Value  
0.5  
Unit  
°C/W  
°C/W  
R
thj-case  
Thermal resistance junction-case  
Thermal resistance junction-pcb  
R
30  
thj-pcb  
1. When
 
mounted on an 1-inch² FR-4, 2 Oz copper board.  
Table 3.
Avalanche characteristics  
Symbol  
Parameter  
Avalanche current, repetitive or not repetitive  
(pulse width limited by T  
Value  
Unit  
I
9
A
AR  
)
jmax  
Single pulse avalanche energy  
(starting T
 
= 25 °C, I
 
= I
 
, V
 
= 50 V)  
E
560  
mJ  
AS  
j
D
AR  
DD  
DS13187
–
Rev 2  
page 2/14  
 
 
 
 
 

STB50N65DM6  
Electrical characteristics  
2
Electrical characteristics  
T

C

= 25 °C unless otherwise specified  
Table 4.
On/off-state  
Symbol  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
V
Drain-source breakdown  
voltage  
V
V
= 0
V
, I
 
= 1
m
A  
650  
(BR)DSS  
GS  
D
V
V
T
= 0
V
, V
 
=
6
50 V  
5
µA  
GS  
DS  
I
= 0
V
, V
 
= 650 V  
Zero gate voltage drain current  
DSS  
GS  
DS  
100  
µA  
= 125 °C

C
I
V
V
= 0
V
, V
 
=
±
25 V  
Gate body leakage current  
Gate threshold voltage  
±5  
µA  
V
GSS  
DS  
GS  
V
= V
 
, I
 
= 250 µA  
3.25  
4
4.75  
GS(th)  
DS  
GS  
GS  
D
Static drain-source on-  
resistance  
R
DS(on)  
V
= 10
V
, I
 
=
1
6.5 A  
D
74  
91  
mΩ  
1. Defined
 
by design, not subject to production test.  
Table 5.
Dynamic  
Symbol  
Parameter  
Input capacitance  
Test conditions  
Min.  
Typ.  
2300  
165  
3
Max.  
Unit  
pF  
pF  
pF  
pF  
Ω
C
iss  
–
–
–
–
–
–
C
oss  
V
V
= 100 V, f = 1 MHz, V
 
= 0 V  
Output capacitance  
DS  
GS  
C
Reverse transfer capacitance  
Equivalent output capacitance  
Intrinsic gate resistance  
T
o
tal gate charge  
rss  
= 0 to 520
V
, V
 
= 0 V  
C
oss eq.  
414  
1.7  
DS  
GS  
R
g
f = 1 MHz, I
 
= 0 A  
D
–
–
–
–
–
–
–
–
Q
g
52.5  
14.5  
22.5  
nC  
nC  
nC  
V
V
= 520
V
, I
 
=
3
3 A  
DD  
D
Q
gs  
Gate-source charge  
= 0 to 10 V (see

GS  
Q
Gate-drain charge  
gd  
1.  
C
oss eq  
. is defined as a constant equivalent capacitance giving the same charging time as C  
when VDS increases from 0  
OSS  
to 80% V  
DSS  
Table 6.
Switching times  
Test conditions  
Symbol  
Parameter  
Turn-on delay time  
Min.  
Typ.  
19.2  
12  
Max.  
Unit  
ns  
t
–
–
–
–
–
–
–
–
d(on)  
V
V
= 325
V
, I
 
=
1
6.5 A, R
 
= 4.7 Ω  
D G  
DD  
t
Rise time  
ns  
r
GS  
t
Turn-off delay time  
Fall time  
59.6  
9.6  
ns  
d(off)  
t
ns  
f
DS13187
–
Rev 2  
page 3/14  
 
 

STB50N65DM6  
Electrical characteristics  
Table 7.
Source-drain diode  
Test conditions  
Symbol  
Parameter  
Source-drain current  
Min.  
Typ.  
Max.  
33  
Unit  
A
I
–
–
–
–
–
–
–
–
–
SD  
I
Source-drain current (pulsed)  
Forward on voltage  
120  
1.6  
A
SDM  
V
V
= 0
V
, I
 
=
3
3 A  
SD  
V
GS  
SD  
t
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
130  
0.65  
10  
ns  
µC  
A
rr  
I
= 33 A, di/dt = 100 A/µs,V
 
= 60 V  
DD  
SD  
Q
rr  
I
RRM  
t
226  
2.32  
20.6  
ns  
µC  
A
rr  
I
= 33 A, di/dt = 100 A/µs V
 
= 60
V
,  
DD  
SD  
T =
 
150 °C (see

j
Q
rr  
I
RRM  
1. Pulse
 
width limited by safe operating area  
2. Pulsed:
 
pulse duration = 300 µs, duty cycle 1.5%  
DS13187
–
Rev 2  
page 4/14  
 
 

STB50N65DM6  
Electrical characteristics (curves)  
2.1  
Electrical characteristics (curves)  
Figure 1.
Safe operating area  
Figure 2.
Maximum transient thermal impedance  
Z
GADG261120190945SOA  
GADG211120191320ZTH  
thj-c  
I

D  

(A)  
(°C/W)  
I

DM  

0.3  
0.4  
duty = 0.5  
10

2  

10

1  

10

0  

t

p

=1 µs  
10

-1  

0.2  
t

p

=10 µs  
0.1  
0.5  
R

DS(on)

max.  
t

p

=100 µs  
V

(BR)DSS  

10

-2  

Single pulse  
R
= 0.5°C/W  
thJ-C  
10

-1  

10

-2  

T

C

= 25 °C  
T

J

≤
150 °C  
single pulse  
t

p

=1 ms  
V

DS

(V)  
t

p

=10 ms  
10

2  

10

-3  

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1  

10

-1  

10

0  

10

1  

t

p

(s)  
Figure 3.
Typical output characteristics  
Figure 4.
Typical transfer characteristics  
GADG090720191225OCH  
GADG090720191225TCH  
I

D  

(A)  
I

D  

(A)  
V

GS

= 9, 10 V  
100  
100  
V

GS

= 8 V  
V

DS

= 20 V  
80  
80  
60  
40  
V

GS

= 7 V  
60  
40  
V

GS

= 6 V  
20  
0
20  
0
V

GS

= 5 V  
12  
0
4
8
16  
V

DS

(V)  
4
5
6
7
8
9
V

GS

(V)  
Figure 5.
Typical gate charge characteristics  
Figure 6.
Typical drain-source on-resistance  
GADG090720191225QVG  
V

DD

= 520
V
,
I

D

= 33 A  
GADG090720191226RID  
V

DS  

(V)  
V

GS  

(V)  
R

DS(on)  

(mΩ)  
600  
500  
400  
300  
200  
12  
10  
8
80  
Q

g  

78  
76  
Q

gs  

Q

gd  

V

GS

= 10 V  
6
74  
72  
4
100  
0
2
70  
68  
0
0
10  
20  
30  
40  
50  
60  
Q

g

(nC)  
0
5
10  
15  
20  
25  
30  
I

D

(A)  
DS13187
–
Rev 2  
page 5/14  

STB50N65DM6  
Electrical characteristics (curves)  
Figure 7.
Typical capacitance characteristics  
Figure 8.
Typical output capacitance stored energy  
GADG090720191226CVR  
GADG090720191228EOS  
C
E

OSS  

(pF)  
(µJ)  
24  
10

4  

20  
16  
12  
8
C

ISS  

10

3  

10

2  

f = 1 MHz  
C

OSS  

10

1  

10

0  

C

RSS  

4
0
10

-1  

10

0  

10

1  

10

2  

V

DS

(V)  
0
100 200 300 400 500 600
 
V

DS

(V)  
Figure 9.
Normalized gate threshold vs temperature  
Figure 10.
Normalized on-resistance vs temperature  
GADG090720191229VTH  
GADG090720191229RON  
V

GS(th)  

R

DS(on)  

(norm.)  
(norm.)  
1.1  
2.5  
1.0  
2.0  
A
ID = 250 µ  
V

GS

= 10 V  
0.9  
0.8  
1.5  
1.0  
0.7  
0.6  
0.5  
0.0  
-75  
-25  
25  
75  
125  
T

j

(°C)  
-75  
-25  
25  
75  
125  
T

j

(°C)  
Figure 11.
Normalized breakdown voltage vs temperature  
Figure 12.
Typical reverse diode forward characteristics  
GADG090720191230VTH  
GADG090720191230SDF  
V

(BR)DSS  

V

SD  

(norm.)  
(V)  
1.1  
1.10  
Tj = -50 °C  
I

D

= 1 mA  
1.05  
1.0  
0.9  
Tj = 25°C  
1.00  
0.95  
0.8  
Tj = 150°C  
0.7  
0.90  
0.85  
0.6  
0.5  
-75  
-25  
25  
75  
125  
T

j

(°C)  
0
5
10  
15  
20  
25  
30  
I

SD

(A)  
DS13187
–
Rev 2  
page 6/14  

STB50N65DM6  
Test circuits  
3
Test circuits  
Figure 13.
Test circuit for resistive load switching times  
Figure 14.
Test circuit for gate charge behavior  
V

DD  

RL  
R

L  

2200  
μF  
3.3  
μF  
I

G

= CONST  
2.7 kΩ  
V

DD  

+
D.U.
T
.  
100 Ω  
V

GS  

V

D  

R

G  

pulse width  
+
D.U.
T
.  
V

G  

V

GS  

2200  
μF  
pulse width  
47 kΩ  
1 kΩ  
AM01469v10  
AM01468v1  
Figure 15.
Test circuit for inductive load switching and  
diode recovery times  
Figure 16.
Unclamped inductive load test circuit  
L
A
A
A
D
S
V

D  

100 µH  
D
fast  
G
D.U.
T
.  
B
diode  
2200  
3.3  
µF  
V

DD  

1000  
µF  
B
+
3.3  
µF  
µF  
B
+
V

DD  

25 Ω  
I

D  

G
D.U.
T
.  
R

G  

S
+
_
D.U.
T
.  
V

i  

pulse width  
AM01471v1  
AM01470v1  
Figure 18.
Switching time waveform  
Figure 17.
Unclamped inductive waveform  
t

on  

t

d(on)  

t

off  

t

d(off)  

V
(BR)DSS  
t

r  

t

f  

V
D  
90%  
90%  
I
DM  
V

DS  

10%  
V

GS  

10%  
0
0
I
D  
V
DD  
V
DD  
90%  
AM01472v1  
10%  
AM01473v1  
DS13187
–
Rev 2  
page 7/14  
 
 
 
 

STB50N65DM6  
Package information  
4
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of

packages,  
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product  
status are available at:

. ECOPACK is an ST trademark.  
DS13187
–
Rev 2  
page 8/14  

STB50N65DM6  
D²PAK (TO-263) type A2 package information  
4.1  
D²PAK (TO-263) type A2 package information  
Figure 19.
D²PAK (TO-263) type A2 package outline  
0079457_A2_26  
DS13187
–
Rev 2  
page 9/14  

STB50N65DM6  
D²PAK (TO-263) type A2 package information  
Table 8.
D²PAK (TO-263) type A2 package mechanical data  
mm  
Dim.  
Min.  
4.40  
0.03  
0.70  
1.14  
0.45  
1.23  
8.95  
7.50  
1.10  
10.00  
8.70  
7.30  
Typ.  
Max.  
4.60  
0.23  
0.93  
1.70  
0.60  
1.36  
9.35  
8.00  
1.50  
10.40  
9.10  
7.70  
A
A1  
b
b2  
c
c2  
D
D1  
D2  
E
7.75  
1.30  
E1  
E2  
e
8.90  
7.50  
2.54  
e1  
H
4.88  
15.00  
2.49  
2.29  
1.27  
1.30  
5.28  
15.85  
2.69  
2.79  
1.40  
1.75  
J1  
L
L1  
L2  
R
0.40  
V2  
0°  
8°  
Figure 20.
D²PAK (TO-263) recommended footprint (dimensions are in mm)  
Footprint_26  
DS13187
–
Rev 2  
page 10/14  

STB50N65DM6  
D²PAK packing information  
4.2  
D²PAK packing information  
Figure 21.
D²PAK tape outline  
DS13187
–
Rev 2  
page 11/14  

STB50N65DM6  
D²PAK packing information  
Figure 22.
D²PAK reel outline  
T
40mm min.  
access hole  
at slot location  
B
D
C
N
A
G measured  
at hub  
Tape slot  
in core for  
tape start  
Full radius  
2.5mm min.width  
AM06038v1  
Table 9.
D²PAK tape and reel mechanical data  
Tape  
Reel  
mm  
mm  
Max.  
330  
Dim.  
Dim.  
Min.  
10.5  
15.7  
1.5  
Max.  
Min.  
A0  
B0  
D
10.7  
15.9  
1.6  
A
B
C
D
G
N
T
1.5  
12.8  
20.2  
24.4  
100  
13.2  
26.4  
30.4  
D1  
E
1.59  
1.65  
11.4  
4.8  
1.61  
1.85  
11.6  
5.0  
F
K0  
P0  
P1  
P2  
R
3.9  
4.1  
11.9  
1.9  
12.1  
2.1  
Base quantity  
Bulk quantity  
1000  
1000  
50  
T
0.25  
23.7  
0.35  
24.3  
W
DS13187
–
Rev 2  
page 12/14  

STB50N65DM6  
Revision history  
Table 10.
Document revision history  
Date  
Version  
Changes  
04-Dec-2019  
28-Jul-2020  
1
2
First release.  
DS13187
–
Rev 2  
page 13/14  

STB50N65DM6  
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T
.
F
or additional information about ST trademarks, please refer to

. All other product or service  
names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2020 STMicroelectronics – All rights reserved  
DS13187
–
Rev 2  
page 14/14