STMicroelectronics-STD20NF06LAG
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STD20NF06LAG
Datasheet
Automotive-grade N-channel 60
V
,
3
2 mΩ typ., 24 A, STripFET II
Power MOSFET in a DPAK package
Features
V
R
DS(on)
max.
I
P
TOT
Order code
DS
D
TAB
STD20NF06LAG
60 V
40 mΩ
24 A
60 W
3
2
1
DPAK
•
•
•
•
AEC-Q101 qualified
Exceptional dv/dt capability
100% avalanche tested
Low gate charge
D(2, TAB)
Applications
G(1)
•
Switching applications
Description
S(3)
AM01475v1_noZen
This Power MOSFET has been developed using STMicroelectronics’ unique
STripFET process, which is specifically designed to minimize input capacitance and
gate charge. This renders the device suitable for use as primary switch in advanced
high-efficiency isolated DC-DC converters for telecom and computer applications,
and applications with low gate charge driving requirements.
Product status link
Product summary
Order code
Marking
STD20NF06LAG
D20NF06L
DPAK
Package
Packing
T
a
pe and reel
DS11845
–
Rev 3
–
October 2019
For further information contact your local STMicroelectronics sales office.
STD20NF06LAG
Electrical ratings
1
Electrical ratings
Table 1.
Absolute maximum ratings
Parameter
Symbol
Value
60
Unit
V
V
Drain-source voltage
Gate-source voltage
DS
GS
V
±18
24
V
Drain current (continuous) at T
Drain current (continuous) at T
= 25 °C
case
case
I
A
D
= 100 °C
17
I
Drain current (pulsed)
96
A
W
DM
P
T
o
tal power dissipation at T
= 25 °C
case
60
TOT
Peak diode recovery voltage slope
Single pulse avalanche energy
Storage temperature range
10
V/ns
mJ
E
225
AS
T
stg
-55 to 175
°C
T
Operating junction temperature range
j
1. Pulse
width is limited by safe operating area.
2. ≤
24 A, di/dt ≤ 300 A/ns, V
= 80% V
3. Starting
T =
25°C, I
= 14 A, V
= 60 V.
I
SD
DD
DD
(BR)DSS
j
D
Table 2.
Thermal data
Symbol
Parameter
Value
2.5
Unit
R
thj-case
Thermal resistance junction-case
Thermal resistance junction-pcb
°C/W
R
50
thj-pcb
1. When
mounted on a 1-inch² FR-4, 2 Oz copper board.
DS11845
–
Rev 3
page 2/15
STD20NF06LAG
Electrical characteristics
2
Electrical characteristics
(T
case
= 25 °C unless otherwise specified)
Table 3.
Static
Test conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
V
V
= 0
V
, I
=
2
50 µA
Drain-source breakdown voltage
60
V
(BR)DSS
GS
GS
GS
D
= 0
V
, V
=
6
0 V
1
DS
I
Zero gate voltage drain current
µA
DSS
V
T
= 0
V
, V
=
6
0 V,
DS
10
case
I
V
= 0
V
, V
=
±
18 V
GS
Gate-body leakage current
Gate threshold voltage
±100
2.5
40
nA
V
GSS
DS
DS
GS
GS
V
V
V
V
= V
, I
= 250 µA
1
GS(th)
GS
D
= 10
V
, I
=
1
2 A
32
D
R
DS(on)
Static drain-source on-resistance
mΩ
= 5
V
, I
=
1
2 A
50
D
1. Defined
by design, not subject to production test.
Table 4.
Dynamic
Test conditions
Symbol
Parameter
Min.
Typ.
660
170
70
Max.
Unit
C
iss
Input capacitance
Output capacitance
Reverse transfer capacitance
T
o
tal gate charge
Gate-source charge
Gate-drain charge
–
–
–
–
–
–
–
–
–
–
–
–
C
oss
V
= 25
V
, f = 1
M
Hz, V
= 0 V
GS
pF
DS
C
rss
Q
13
g
V
= 30
V
, I
=
2
0 A, V
= 5 V
DD
D
GS
Q
3.5
8
nC
gs
Q
gd
Table 5.
Switching times
Test conditions
Symbol
Parameter
Min.
Typ.
11
Max.
Unit
t
V
= 30
V
, I
=
1
0 A,
Turn-on delay time
Rise time
–
–
–
–
–
–
d(on)
DD
D
R
G
= 4.7 Ω, V
= 5 V
t
GS
50
r
ns
t
Turn-off delay time
20
d(off)
t
Fall time
–
12
–
f
DS11845
–
Rev 3
page 3/15
STD20NF06LAG
Electrical characteristics
Table 6.
Source-drain diode
Test conditions
Symbol
Parameter
Min.
Typ.
Max.
24
Unit
A
I
Source-drain current
Source-drain current (pulsed)
Forward on voltage
–
–
–
–
–
SD
I
96
A
SDM
V
V
I
= 0
V
, I
=
2
4 A
SD
1.5
V
GS
SD
t
= 20 A, di/dt = 100 A/µs,
= 20
V
, T
=
1
50 °C
Reverse recovery time
Reverse recovery charge
56
ns
nC
rr
SD
V
DD
Q
J
108
rr
I
Reverse recovery current
–
4
A
RRM
1. Pulse
width is limited by safe operating area.
2. Pulse
test: pulse duration = 300 µs, duty cycle 1.5%.
DS11845
–
Rev 3
page 4/15
STD20NF06LAG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Gate charge vs gate-source voltage
Figure 6.
Static drain-source on-resistance
DS11845
–
Rev 3
page 5/15
STD20NF06LAG
Electrical characteristics (curves)
Figure 8.
Normalized gate threshold voltage vs
temperature
Figure 7.
Capacitance variations
Figure 10.
Normalized V
(BR)DSS
vs temperature
Figure 9.
Normalized on-resistance vs temperature
V
G
S
=10 V
I
D
=12 A
DS11845
–
Rev 3
page 6/15
STD20NF06LAG
Test circuits
3
Test circuits
Figure 11.
Test circuit for resistive load switching times
Figure 12.
Test circuit for gate charge behavior
V
DD
12 V
47 kΩ
1 kΩ
100 nF
R
L
2200
μF
3.3
μF
V
DD
+
I
G
= CONST
2.7 kΩ
V
D
R
G
D.U.
T
.
100 Ω
V
GS
pulse width
+
D.U.
T
.
V
GS
V
G
2200
μF
pulse width
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 13.
Test circuit for inductive load switching and
diode recovery times
Figure 14.
Unclamped inductive load test circuit
L
A
A
A
D
S
V
D
100 µH
D
fast
G
D.U.
T
.
B
diode
2200
3.3
µF
+
V
DD
1000
µF
B
µF
3.3
µF
B
+
V
DD
25 Ω
I
D
G
D.U.
T
.
R
G
S
+
_
D.U.
T
.
V
i
pulse width
AM01471v1
AM01470v1
Figure 16.
Switching time waveform
Figure 15.
Unclamped inductive waveform
t
on
t
d(on)
t
off
t
d(off)
V
(BR)DSS
t
r
t
f
V
D
90%
90%
I
DM
V
DS
10%
V
GS
10%
0
0
I
D
V
DD
V
DD
90%
10%
AM01472v1
AM01473v1
DS11845
–
Rev 3
page 7/15
STD20NF06LAG
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
DS11845
–
Rev 3
page 8/15
STD20NF06LAG
DPAK (TO-252) type A package information
4.1
DPAK (TO-252) type A package information
Figure 17.
DPAK (TO-252) type A package outline
0068772_A_26
DS11845
–
Rev 3
page 9/15
STD20NF06LAG
DPAK (TO-252) type A package information
Table 7.
DPAK (TO-252) type A mechanical data
mm
Dim.
Min.
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
4.95
6.40
4.60
2.159
4.445
9.35
1.00
2.60
0.65
0.60
Typ.
Max.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
5.25
6.60
4.80
2.413
4.699
10.10
1.50
3.00
0.95
1.00
A
A1
A2
b
b4
c
c2
D
D1
E
5.10
E1
e
4.70
2.286
4.572
e1
H
L
(L1)
L2
L4
R
2.80
0.80
0.20
V2
0°
8°
DS11845
–
Rev 3
page 10/15
STD20NF06LAG
DPAK (TO-252) type A package information
Figure 18.
DPAK (TO-252) type A recommended footprint (dimensions are in mm)
FP_0068772_26
DS11845
–
Rev 3
page 11/15
STD20NF06LAG
DPAK (TO-252) packing information
4.2
DPAK (TO-252) packing information
Figure 19.
DPAK (TO-252) tape outline
10 pitches cumulative
tolerance on tape +/- 0.2 mm
P0
Top cover
tape
P2
D
T
E
F
W
K0
B1
B0
For machine ref. only
including draft and
A0
D1
P1
radii concentric around B0
U
s
er direction o
f
f
e
ed
R
Bending radius
U
s
er direction o
f
f
e
ed
AM08852v1
DS11845
–
Rev 3
page 12/15
STD20NF06LAG
DPAK (TO-252) packing information
Figure 20.
DPAK (TO-252) reel outline
T
40mm min.
access hole
at slot location
B
D
C
N
A
G measured
at hub
Tape slot
in core for
tape start
Full radius
2.5mm min.width
AM06038v1
Table 8.
DPAK (TO-252) tape and reel mechanical data
Tape
Reel
mm
mm
Dim.
Dim.
Min.
6.8
Max.
7
Min.
Max.
A0
B0
B1
D
A
B
C
D
G
N
T
330
10.4
10.6
12.1
1.6
1.5
12.8
20.2
16.4
50
13.2
18.4
22.4
1.5
1.5
D1
E
1.65
7.4
1.85
7.6
F
K0
P0
P1
P2
R
2.55
3.9
2.75
4.1
Base qty.
Bulk qty.
2500
2500
7.9
8.1
1.9
2.1
40
T
0.25
15.7
0.35
16.3
W
DS11845
–
Rev 3
page 13/15
STD20NF06LAG
Revision history
Table 9.
Document revision history
Date
Revision
Changes
25-Oct-2016
1
First release.
Modified
T
a
ble 2: “Absolute maximum ratings”
,
T
a
ble 5: “Dynamic”
,
Table 6:
“Switching times
” and
T
a
ble 7: “Source-drain diode”
.
20-Mar-2017
01-Oct-2019
2
Modified
Figure 2: “Safe operating area”
and
Figure 10: “Normalized on-
resistance vs temperature”
.
Minor text changes
Updated marking on cover page.
Minor text changes
3
DS11845
–
Rev 3
page 14/15
STD20NF06LAG
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DS11845
–
Rev 3
page 15/15
