STMicroelectronics-STD2LN60K3

Part #STMicroelectronics-STD2LN60K3
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STMicroelectronics-STD2LN60K3
STD2LN60K3, STF2LN60K3,  
STU2LN60K3  
N-channel 600
V
, 4
Ω
typ., 2 A SuperMESH3™ Power MOSFET  
in D
P
A
K, TO-220FP and I
P
A
K packages  
Datasheet — production data  
Features  
TAB  
R

DS(on)  

max  
Order codes  
V

DSS  

I

D  

P

TOT  

3
1
3
2
D
P
A
K  
STD2LN60K3  
STF2LN60K3  
STU2LN60K3  
45 W  
20 W  
45 W  
1
600 V  
< 4.5
Ω  
2 A  
TO-220FP  
T
A
B  
■
100% avalanche tested  
3
■
Extremely high dv/dt capability  
■
Very low intrinsic capacitance  
2
1
IPAK  
■
Improved diode reverse recovery  
characteristics  
■
Zener-protected  
Figure 1.  
Internal schematic diagram  
Applications  
D(2,TAB)  
■
Switching applications  
Description  
These SuperMESH3™ Power MOSFETs are the  
result of improvements applied to  
G(1)  
STMicroelectronics’ SuperMESH™ technolog
y
,  
combined with a new optimized vertical structure.  
These devices boast an extremely low on-  
resistance, superior dynamic performance and  
high avalanche capabilit
y
,
r
endering them suitable  
for the most demanding applications.  
S(3)  
AM01476v1  
Table 1.  
Device summary  
Order codes  
Marking  
Package  
Packaging  
STD2LN60K3  
STF2LN60K3  
STU2LN60K3  
D
P
A
K  
TO-220FP  
I
P
A
K  
T
a
pe and reel  
T
u
be  
2LN60K3  
July 2012  
Doc ID 023500 Rev 1  
1/20  
This is information on a product in full production.  
20  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Electrical ratings  
1
Electrical ratings  
Table 2.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
D
P
A
K TO-220FP
 
IPAK  
V

DS  

V

GS  

I

D  

Drain-source voltage  
600  
30  
V
V
Gate- source voltage  
Drain current (continuous) at T

C

= 25 °C  
Drain current (continuous) at T

C

= 100 °C  
Drain current (pulsed)  
2
1.26  
8
2

(1)  

1.26

(1)  

8

(1)  

2
1.26  
8
A
I

D  

A
(2)  
I

DM  

A
P

TOT  

T
o
tal dissipation at T

C

= 25 °C  
Derating factor  
45  
20  
45  
W
0.36  
0.16  
0.36  
W/°C  
Gate source ESD  
V

ESD(G-S)  

2500  
12  
V
(HBM-C = 100 p
F
, R =
1
.5 k
Ω
)  
dv/dt

(3)

Peak diode recovery voltage slope  
V/ns  
Insulation withstand voltage (RMS) from all three  
leads to external heat sink  
(t = 1 s; T
C
= 25 °C)  
V

ISO  

2500  
V
T

stg  

T

j  

Storage temperature  
-55 to 150  
150  
°C  
°C  
Max. operating junction temperature  
1. Limited
 
by package  
2. Pulse
 
width limited by safe operating area  
3.  
I
≤
2 A, di/dt
 
≤
400 A/µs, peak V
 
< V  
DS (BR)DSS  
SD  
T
a
ble 3.  
Symbol  
Thermal data  
Value  
Parameter  
Unit  
D
P
A
K TO-220FP  
I
P
A
K  
R

thj-case

Thermal resistance junction-case max  
R

thj-pcb

Thermal resistance junction-pcb max  
R

thj-amb

Thermal resistance junction-amb max  
2.78  
50  
6.25  
62.5  
2.78  
°C/W  
°C/W  
°C/W  
100  
T
a
ble 4.  
Symbol  
Avalanche characteristics  
Parameter  
Max value  
Unit  
Avalanche current, repetitive or not-repetitive  
(pulse width limited by T

j

max)  
I

AR  

2
A
Single pulse avalanche energy  
E

AS  

80  
mJ  
(starting T

j

= 25 °C, I

D

= I

AR

, V

DD

= 50 V)  
Doc ID 023500 Rev 1  
3/20  

Electrical characteristics  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
2
Electrical characteristics  
(T

C

= 25 °C unless otherwise specified)  
T
a
ble 5.  
Symbol  
On /off states  
Parameter  
Test conditions  
I

D

= 1 mA, V

GS

= 0  
V

DS

= 600 V  
Min.  
Typ.  
Max. Unit  
Drain-source  
breakdown voltage  
V

(BR)DSS  

600  
V
Zero gate voltage  
1
µA  
µA  
I

DSS  

drain current (V

GS

= 0)
 
V

DS

= 600
V
,
T

C

=125 °C  
50  
Gate-body leakage  
I

GSS  

V

GS  

=
20 V  
10  
µA  
V
current (V

DS

= 0)  
V

GS(th)  

R

DS(on  

Gate threshold voltage
 
V

DS

= V

GS

, I

D

= 50 µA  
3
3.75  
4
4.5  
4.5  
Static drain-source on-  
V

GS

= 10
V
,
I

D

= 1 A  
resistance  
Ω
T
a
ble 6.  
Symbol  
Dynamic  
Parameter  
Test conditions  
Min.  
Typ.  
Max. Unit  
Input capacitance  
Output capacitance  
C

iss  

C

oss  

C

rss  

235  
22  
pF  
V

DS

= 50
V
, f = 1
M
Hz, V

GS

= 0  
–
–
pF  
pF  
Reverse transfer  
capacitance  
3.5  
Eq. capacitance time  
related  
(1)  
C

o(tr)  

–
–
–
14  
10  
7
–
–
–
pF  
pF  
Ω
V

GS

= 0, V

DS

= 0 to 480 V  
Eq. capacitance  
energy related  
(2)  
C

o(er)  

Intrinsic gate  
resistance  
R

G  

f = 1 MHz open drain  
V

DD

= 480
V
,
I

D

= 1 A,  
Q

g  

Q

gs  

Q

gd  

T
o
tal gate charge  
Gate-source charge  
Gate-drain charge  
12  
1.8  
7.7  
nC  
nC  
nC  
V

GS

= 10 V  
–
–
(see

)  
1.  
2.  
C
. time related is defined as a constant equivalent capacitance giving the same charging time as C  
oss eq
 
oss  
when V
 
increases from 0 to 80% V  
DS  
DSS  
C
C
. energy related is defined as a constant equivalent capacitance giving the same stored energy as  
oss eq  
oss  
when V
 
S increases from 0 to 80% V  
DSS  
D
4/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Electrical characteristics  
Min. Typ.
 
Max. Unit  
T
a
ble 7.  
Symbol  
Switching times  
Parameter  
Test conditions  
t

d(on)  

t

r  

t

d(off)  

t

f  

T
u
rn-on delay time  
Rise time  
10  
8.5  
23.5  
21  
ns  
ns  
ns  
ns  
V

DD

= 300
V
,
I

D

=1 A,  
R

G

= 4.7
Ω
,
V

GS

= 10 V  
–
–
T
u
rn-off-delay time  
Fall time  
(see

)  
T
a
ble 8.  
Symbol  
Source drain diode  
Parameter  
Test conditions  
Min. Typ. Max.
 
Unit  
I

SD  

Source-drain current  
2
8
A
A
–
–
(1)  
I

SDM  

Source-drain current (pulsed)  
(2)  
V

SD  

Forward on voltage  
I

SD

= 2 A, V

GS

= 0  
1.5  
V
t

rr  

Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
200  
800  
8
ns  
nC  
A
I

SD

= 2 A, di/dt = 100 A/µs  
Q

rr  

–
–
V

DD

= 60 V (see

)  
I

RRM  

t

rr  

Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
I

SD

= 2 A, di/dt = 100 A/µs  

DD

= 60
V
,
T

j

= 150 °C  
(see

)  
230  
950  
8.5  
ns  
nC  
A
Q

rr  

V
I

RRM  

1. Pulse
 
width limited by safe operating area.  
2. Pulsed:
 
Pulse duration = 300 µs, duty cycle 1.5%  
Table 9.  
Symbol  
Gate-source Zener diode  
Parameter  
Test conditions  
Min. Typ. Max.
 
Unit  
Gate-source breakdown  
voltage  
(1)  
BV

GSO  

Igs= 1
 
mA (open drain)  
30  
–
V
1. The
 
built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s  
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be  
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and  
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the  
usage of external components.  
Doc ID 023500 Rev 1  
5/20  

Electrical characteristics  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
2.1  
Electrical characteristics (curves)  
Figure 2.  
Safe operating area for D
P
A
K and
 
Figure 3.  
I
P
A
K  
Thermal impedance for DPAK and  
IPAK  
AM1
3
051v1  
I
D
(A)  
Tj=150°C  
Tc=25°C  
S
ingle p
u
l
s
e  
10  
10
µs  
100
µs  
1
1m
s  
10m
s  
0.1  
0.01  
10  
V
D
S
(V)  
0.1  
1
100  
Figure 4.  
Safe operating area for TO-220FP  
Figure 5.  
Thermal impedance for TO-220FP  
AM1
3
052v1  
I
D
(A)  
10
µs  
1
100
µs  
1m
s  
10m
s  
0.1  
Tj=150°C  
Tc=25°C  
S
ingle p
u
l
s
e  
0.01  
10  
V
D
S
(V)  
0.1  
1
100  
Figure 6.  
Output characteristics  
Figure 7.  
Transfer characteristics  
AM1
3
054v1  
AM1
3
055v1  
I
D
(A)  
I
D
(A)  
V
G
S
=10V  
V
D
S
=15V  
2.5  
2.0  
2.0  
1.5  
1.0  
6V  
1.5  
1.0  
0.5  
0
0.5  
0
5V  
2
8
V
D
S
(V)  
8
V
G
S
(V)  
0
2
4
6
0
4
6
6/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Electrical characteristics  
Figure 8.  
Gate charge vs gate-source voltage
 
Figure 9.  
Static drain-source on-resistance  
AM1
3
056v1  
D
S  
(V)  
AM1
3
057v1  
V
(V)  
G
S  
R
D
S
(on)  
(
Ω
)  
V
V
DD
=4
8
0V  
V
G
S
=10V  
I
D
=2A  
12  
10  
8
4.2  
500  
V
D
S  
4.0  
400  
3
00  
200  
3
.
8  
3
.6  
3
.4  
6
4
2
0
100  
0
3
.2  
3
.0  
1.0 1.2  
0.4 0.6 0.
8  
0.2  
10  
Q
g
(nC)  
I
D
(A)  
0
5
0
Figure 10.
 
Capacitance variations  
Figure 11.
 
Output capacitance stored energy  
AM1
3
05
8
v1  
AM1
3
059v1  
C
E
o
ss  
(pF)  
(
µ
J)  
Ci
ss  
1.5  
100  
1
10  
1
Co
ss  
Cr
ss  
0.5  
0
0.1  
100  
200  
400 500  
600  
1
10  
V
D
S
(V)  
0
100  
3
00  
V
D
S
(V)  
Figure 12.
 
Normalized gate threshold voltage
 
Figure 13.
 
Normalized on-resistance vs  
vs temperature
 
temperature  
AM1
3
060v1  
AM1
3
061v1  
V
G
S
(th)  
R
D
S
(on)  
(norm)  
(norm)  
I
V
D
=1.1A  
I
D
=50
µ
A  
G
S
=10V  
1.10  
1.00  
0.90  
2.5  
2.0  
1.5  
1.0  
0.
8
0  
0.5  
0
0.70  
-75  
-75  
-25  
25  
75  
T
J
(°C)  
-25  
25  
75  
T
J
(°C)  
125  
125  
Doc ID 023500 Rev 1  
7/20  

Electrical characteristics  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
Figure 14.
 
Normalized BV

DSS

vs temperature
 
Figure 15.
 
Source-drain diode forward  
characteristics  
AM1
3
062v1  
AM1
3
06
3
v1  
BV
D
SS  

S
D

(V)  
0.9  
V
(norm)  
T
J
=-50°C  
I
D
=1mA  
T
J
=25°C  
1.10  
0.
8  
0.7  
0.6  
T
J
=150°C  
1.05  
1.00  
0.5  
0.4  
0.
3  
0.2  
0.95  
0.90  
0.1  
0
-75  
0
-25  
25  
75  
T
J
(°C)  
1
2
3
4
5
I
S
D
(A)  
125  
Figure 16.
 
Maximum avalanche energy vs  
temperature  
AM1
3
064v1  
E

A
S

(mJ)  
90  
I
D
=2 A  
V
DD
=50 V  
8
0  
70  
60  
50  
40  
3
0  
20  
10  
0
0
20  
40  
60
8
0 100  
120  
140 T  
J
(°C)  
8/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Test circuits  
3
Test circuits  
Figure 17.
 
Switching times test circuit for  
resistive load  
Figure 18.
 
Gate charge test circuit  
V
DD  
12V  
47k
Ω  
1k
Ω  
100nF  
2200  
3
.
3  
μ
F  
R
L  
μ
F  
I
G
=CON
S
T  
V

DD  

100
Ω  
V

i

=20V=V
GMAX  
D.U.
T
.  
V

G  

V
D  
R
G  
V
G
S
 
2200  
μ
F  
D.U.
T
.  
2.7k
Ω  
47k
Ω  
P
W  
1k
Ω  
P
W  
AM0146
8
v1  
AM01469v1  
Figure 19.
 
Test circuit for inductive load  
switching and diode recovery times  
Figure 20.
 
Unclamped Inductive load test  
circuit  
L
A
A
A
B
D
FA
S
T  
DIODE  
L=100
μ
H  
V
D  
G
2200  
μ
F  
D.U.
T
.  
B
3
.
3  
μ
F  
V
DD  
S
3
.
3  
μ
F  
1000  
μ
F  
B
V

DD  

25  
Ω
I
D  
D
G
R

G  

S
V
i  
D.U.
T
.  
P
w  
AM01470v1  
AM01471v1  
Figure 21.
 
Unclamped inductive waveform  
Figure 22.
 
Switching time waveform  
t
on  
td
on  
t
off  
td
off  
V
(BR)D
SS  
t
r  
t
f  
V
D  
90
%  
10
%  
90
%  
I
DM  
10
%  
V
D
S  
I
D  
0
0
V
DD  
V
DD  
90
%  
V

G
S  

10
%  
AM01472v1  
AM0147
3
v1  
Doc ID 023500 Rev 1  
9/20  

Package mechanical data  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECO
P
A
CK

®

packages, depending on their level of environmental compliance. ECO
P
ACK

®  

ECO
P
A
CK is an ST trademark.  
10/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Package mechanical data  
Table 10.
 
DPAK (TO-252) mechanical data  
mm  
Dim.  
Min.  
Typ.  
Max.  
A
A1  
A2  
b
2.20  
0.90  
0.03  
0.64  
5.20  
0.45  
0.48  
6.00  
2.40  
1.10  
0.23  
0.90  
5.40  
0.60  
0.60  
6.20  
b4  
c
c2  
D
D1  
E
5.10  
6.40  
6.60  
E1  
e
4.70  
2.28  
e1  
H
4.40  
9.35  
1
4.60  
10.10  
L
L1  
L2  
L4  
R
2.80  
0.80  
0.60  
0°  
1
0.20  
V2  
8°  
Doc ID 023500 Rev 1  
11/20  

Package mechanical data  
Figure 23.
 
D
P
A
K (TO-252) drawing  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
006
8
772_I  
12/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
T
a
ble 11.
 
TO-220FP mechanical data  
Package mechanical data  
mm  
Dim.  
Min.  
Typ.  
Max.  
A
B
4.4  
2.5  
4.6  
2.7  
D
2.5  
2.75  
0.7  
E
0.45  
0.75  
1.15  
1.15  
4.95  
2.4  
F
1
F1  
F2  
G
1.70  
1.70  
5.2  
G1  
H
2.7  
10  
10.4  
L2  
L3  
L4  
L5  
L6  
L7  
Dia  
16  
28.6  
9.8  
2.9  
15.9  
9
30.6  
10.6  
3.6  
16.4  
9.3  
3
3.2  
Doc ID 023500 Rev 1  
13/20  

Package mechanical data  
Figure 24.
 
TO-220FP drawing  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
7012510_Rev_K_B  
14/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Package mechanical data  
Table 12.
 
IPAK (TO-251) mechanical data  
mm.  
typ  
DIM.  
min.  
max.  
A
A1  
b
2.20  
0.90  
0.64  
2.40  
1.10  
0.90  
0.95  
5.40  
b2  
b4  
5.20  
0.3  
B5  
c
c2  
D
0.45  
0.48  
6.00  
6.40  
0.60  
0.60  
6.20  
6.60  
E
e
2.28  
e1  
H
4.40  
4.60  
16.10  
L
9.00  
0.80  
9.40  
1.20  
1.00  
L1  
L2  
V1  
0.80  
10

o  

Doc ID 023500 Rev 1  
15/20  

Package mechanical data  
Figure 25.
 
I
P
A
K (TO-251) drawing  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
006
8
771_H  
AM09214V1  
16/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Packaging mechanical data  
5
Packaging mechanical data  
Table 13.
 
DPAK (TO-252) tape and reel mechanical data  
Tape  
Reel  
mm  
mm  
Dim.  
Dim.  
Min.  
Max.  
Min.  
Max.  
A0  
B0  
B1  
D
6.8  
7
A
B
C
D
G
N
T
330  
10.4  
10.6  
12.1  
1.6  
1.5  
12.8  
20.2  
16.4  
50  
13.2  
18.4  
22.4  
1.5  
1.5  
D1  
E
1.65  
7.4  
1.85  
7.6  
F
K0  
P0  
P1  
P2  
R
2.55  
3.9  
2.75  
4.1  
Base qt
y
.  
Bulk qt
y
.  
2500  
2500  
7.9  
8.1  
1.9  
2.1  
40  
T
0.25  
15.7  
0.35  
16.3  
W
Figure 26.
 
D
P
A
K footprint

(a)  

6.7  
3
1.
8
 
1.6  
2.
3  
2.
3  
6.7  
1.6  
AM0
88
50v1  
a. All
 
dimension are in millimeters  
Doc ID 023500 Rev 1  
17/20  

Packaging mechanical data  
Figure 27.
 
Tape for D
P
A
K (TO-252)  
STD2LN60K3, STF2LN60K3, STU2LN60K3  
10 pitche
s
c
u
m
u
l
a
tive  
toler
a
nce on t
a
pe +/- 0.2 mm  
P0  
D
Top cover  
t
a
pe  
P2  
T
E
F
W
K0  
B1  
B0  
For m
a
chine ref. only  
incl
u
ding dr
a
ft
a
nd  
A0  
D1  
P1  
r
a
dii concentric
a
ro
u
nd B0  
U
s
er direction of feed  
R
Bending r
a
di
us  
U
s
er direction of feed  
AM0
88
52v1  
Figure 28.
 
Reel for DPAK (TO-252)  
T
REEL DIMEN
S
ION
S  
40mm min.  
Acce
ss
hole  
At
s
l ot
 
loc
a
tion  
B
D
C
N
A
G me
asu
red
a
t h
ub  
F
u
ll r
a
di
us  
T
a
pe
s
lot  
in core for  
t
a
pe
s
t
a
rt 25 mm min.  
width  
AM0
88
51v2  
18/20  
Doc ID 023500 Rev 1  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
Revision history  
6
Revision history  
T
a
ble 14.
 
Document revision history  
Date  
Revision  
Changes  
05-Jul-2012  
1
First release.  
Doc ID 023500 Rev 1  
19/20  

STD2LN60K3, STF2LN60K3, STU2LN60K3  
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