STMicroelectronics-STD40NF03LT4

STD40NF03L  

N-channel 30V – 0.0090

Ω

– 40A – D

P

A

K  

Low gate charge S

T

r

ipFET™ II Power MOSFET  

General features  

Type  

V

DSS  

R

DS(on)  

I

D  

STD40NF03L  

30V  

<0.011

Ω

 

40A  

■

Logic level device  

■

Optimal R

 

x Q

 

trade-off  

3

DS(on)  

g

1

■

Conduction losses reduced  

■

Switching losses reduced  

■

Low threshold drive  

DPAK  

Description  

This application specific Power MOSFET is the  

third generation of STMicroelectronics unique  

“Single Feature Size™” strip-based process. The  

resulting transistor shows the best trade-off  

between on-resistance and gate charge. When  

used as high and low side in buck regulators, it  

gives the best performance in terms of both  

conduction and switching losses. This is  

extremely important for motherboards where fast  

switching and high efficiency are of paramount  

importance.  

Internal schematic diagram  

Applications  

■

Switching application  

Order codes  

Part number  

Marking  

Package  

Packaging  

STD40NF03LT4  

D40NF03L  

D

P

A

K  

T

a

pe & reel  

February 2007  

Rev 11  

1/13  

13  

Contents  

STD40NF03L  

Contents  

2/13  

STD40NF03L  

Electrical ratings  

1

Electrical ratings  

Table 1.  

Symbol  

Absolute maximum ratings  

Parameter  

Value  

Unit  

V

DS  

V

DGR  

V

GS  

Drain-source voltage (V

GS

= 0)  

Drain-gate voltage (R

GS

= 20 k

Ω

)  

Gate- source voltage  

30  

30  

V

V

20  

V

(1)  

I

D  

Drain current (continuous) at T

C

= 25°C  

Drain current (continuous) at T

C

= 100°C  

Drain current (pulsed)  

40  

A

I

D  

28  

A

(2)  

I

DM  

160  

80  

A

P

tot  

T

o

tal dissipation at T

C

= 25°C  

Derating Factor  

W

0.53  

5.5  

850  

W/°C  

V/ns  

mJ  

dv/dt

(3)  

Peak diode recovery voltage slope  

Single pulse avalanche energy  

Storage temperature  

(4)  

E

AS  

T

stg  

T

j  

-55 to 175  

°C  

Max. operating junction temperature  

1. Current

 

limited by package  

2. Pulse

 

width limited by safe operating area.  

3. I

SD

≤

40A, di/dt

≤

350A/µs, V

DD

≤

V

(BR)DSS

, T

j

≤

T

JMAX  

4. Starting

 

T

j

= 25 °C, I

D

= 20A, V

DD

= 25V  

Table 2.  

Thermal data  

Rthj-case Thermal

 

resistance junction-case max  

1.88  

100  

300  

°C/W  

°C/W  

°C  

Rthj-amb Thermal

 

resistance junction-ambient max  

T

J  

Maximum lead temperature for soldering purpose  

3/13  

Electrical characteristics  

STD40NF03L  

2

Electrical characteristics  

(T  

=25°C unless otherwise specified)  

CASE  

Table 3.  

Symbol  

On/off states  

Parameter  

Test conditions  

Min.  

Typ.  

Max.  

Unit  

Drain-source  

V

(BR)DSS  

I

D

= 250

µ

A, V

GS

=0  

30  

V

breakdown voltage  

V

Zero gate voltage  

1

µA  

µA  

I

DSS  

V

DS

= max rating,  

T

C

= 125°C  

drain current (V

GS

= 0)  

10  

Gate-body leakage  

current (V

DS

= 0)  

I

GSS  

V

GS  

=

20V  

100  

nA  

V

V

GS(th)  

R

DS(on)  

Gate threshold voltage  

V

DS

= V

GS

, I

D

= 250µA  

1

V

GS

= 10

V

,

I

D

= 20A  

V

GS

= 5

V

,

I

D

= 10A  

0.0090 0.0110  

0.0150 0.0195  

Ω

Ω

Static drain-source on  

resistance  

Table 4.  

Symbol  

Dynamic  

Parameter  

Test conditions  

Min.  

Typ.  

Max.  

Unit  

Forward  

transconductance  

(1)  

g

fs  

V

23  

S

, D  

Input capacitance  

Output capacitance  

C

iss  

C

oss  

C

rss  

1440  

560  

pF  

pF  

pF  

V

DS

= 25

V

, f =

1

MHz,  

V

GS

= 0  

Reverse transfer  

capacitance  

135  

t

d(on)  

t

r  

t

d(off)  

t

f  

T

u

rn-on delay time  

Rise time  

22  

165  

21  

ns  

ns  

ns  

ns  

V

DD

= 15

V

,

I

D

= 20A  

R

G

= 4.7

Ω

V

GS

= 5V  

(see

)  

T

u

rn-off delay time  

Fall time  

25  

Q

g  

Q

gs  

Q

gd  

T

o

tal gate charge  

Gate-source charge  

Gate-drain charge  

V

DD

=

15

V

,

I

D

= 40A,  

V

GS

= 5

V

,

R

G

= 4.7

Ω  

(see

)  

22.5  

9

30  

nC  

nC  

nC  

12  

1. Pulsed:

 

Pulse duration = 300 µs, duty cycle 1.5%.  

4/13  

STD40NF03L  

Electrical characteristics  

Table 5.  

Source drain diode  

Parameter  

Symbol  

Test conditions  

Min.  

Typ.  

Max. Unit  

Source-drain current  

I

SD  

40  

A

A

Source-drain current  

(pulsed)  

(1)  

I

SDM  

160  

(2)  

V

SD  

Forward on voltage  

I

SD

= 20A, V

GS

= 0  

1.3  

V

t

rr  

Reverse recovery time  

I

SD

= 40A, di/dt = 100A/µs,  

42  

52  

ns  

nC  

A

Q

rr  

Reverse recovery charge

 

V

DD

= 20

V

,

T

j

= 150°C  

I

RRM  

Reverse recovery current

 

(see

)  

2.5  

1. Pulse

 

width limited by safe operating area.  

2. Pulsed:

 

Pulse duration = 300 µs, duty cycle 1.5%  

5/13  

Electrical characteristics  

STD40NF03L  

2.1  

Electrical characteristics (curves)  

Figure 1.

 

Safe operating area  

Figure 2.

 

Thermal impedance  

Figure 3.

 

Output characteristics  

Figure 4.

 

Transfer characteristics  

Figure 5.

 

Transconductance  

Figure 6.

 

Static drain-source on resistance  

6/13  

STD40NF03L  

Electrical characteristics  

Figure 7.

 

Gate charge vs. gate-source voltage

 

Figure 8.

 

Capacitance variations  

Figure 9.

 

Normalized gate threshold voltage

 

Figure 10.

 

Normalized on resistance vs.  

vs. temperature  

temperature  

Figure 11.

 

Source-drain diode forward  

characteristics  

Figure 12.

 

Normalized breakdown voltage vs.  

temperature  

7/13  

Test circuit  

STD40NF03L  

3

Test circuit  

Figure 13.

 

Switching times test circuit for  

resistive load  

Figure 14.

 

Gate charge test circuit  

Figure 15.

 

Test circuit for inductive load  

switching and diode recovery times  

Figure 16.

 

Unclamped Inductive load test  

circuit  

Figure 17.

 

Unclamped inductive waveform  

Figure 18.

 

Switching time waveform  

8/13  

STD40NF03L  

Package mechanical data  

4

Package mechanical data  

In order to meet environmental requirements, ST offers these devices in ECO

P

A

CK®  

packages. These packages have a Lead-free second level interconnect. The category of  

second level interconnect is marked on the package and on the inner box label, in  

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  

conditions are also marked on the inner box label. ECO

P

ACK is an ST trademark.  

ECO

P

ACK specifications are available at:

9/13  

Package mechanical data  

STD40NF03L  

DPAK MECHANICAL DATA  

mm.  

inch  

TYP.  

DIM.  

MIN.  

TYP  

MAX.  

MIN.  

MAX.  

A

A1  

A2  

B

2.2  

0.9  

2.4  

1.1  

0.23  

0.9  

5.4  

0.6  

0.6  

6.2  

0.086  

0.035  

0.001  

0.025  

0.204  

0.017  

0.019  

0.236  

0.094  

0.043  

0.009  

0.035  

0.212  

0.023  

0.023  

0.244  

0.03  

0.64  

5.2  

b4  

C

0.45  

0.48  

6

C2  

D

D1  

E

5.1  

0.200  

6.4  

6.6  

0.252  

0.260  

E1  

e

4.7  

0.185  

0.090  

2.28  

e1  

H

4.4  

9.35  

1

4.6  

0.173  

0.368  

0.039  

0.181  

0.397  

10.1  

L

(L1)  

L2  

L4  

R

2.8  

0.8  

0.110  

0.031  

0.6  

0°  

1

0.023  

0°  

0.039  

8°  

0.2  

0.008  

V2  

8°  

0068772-F  

10/13  

STD40NF03L  

Packing mechanical data  

5

Packing mechanical data  

DPAK FOOTPRINT  

All dimensions are in millimeters  

TAPE AND REEL SHIPMENT  

REEL MECHANICAL DATA  

mm  

MIN. MAX. MIN. MAX.  

330 12.992  

inch  

DIM.  

A

B

C

D

G

N

T

1.5  

12.8  

20.2  

16.4  

50  

0.059  

13.2 0.504

 

0.520  

0.795  

18.4 0.645

 

0.724  

1.968  

22.4  

0.881  

BASE QTY  

BULK QTY  

2500  

TAPE MECHANICAL DATA  

2500  

mm  

MIN. MAX. MIN. MAX.  

6.8 0.267

 

0.275  

10.4 10.6

 

0.409 0.417  

12.1 0.476  

inch  

DIM.  

A0  

B0  

B1  

D

7

1.5  

1.5  

1.6 0.059

 

0.063  

0.059  

D1  

E

1.65 1.85

 

0.065 0.073  

7.4 7.6

 

0.291 0.299  

2.55 2.75

 

0.100 0.108  

F

K0  

P0  

P1  

P2  

R

3.9  

7.9  

1.9  

40  

4.1 0.153

 

0.161  

8.1 0.311

 

0.319  

2.1 0.075

 

0.082  

1.574  

W

15.7  

16.3 0.618

 

0.641  

11/13  

Revision history  

STD40NF03L  

6

Revision history  

Table 6.  

Date  

Revision history  

Revision  

Changes  

21-Jun-2004  

11-Jul-2006  

20-Feb-2007  

9

Preliminary data  

10  

11  

New template, no content change  

T

y

po mistake on page 1  

12/13  

STD40NF03L  

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13/13