STMicroelectronics-STE53NC50
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STE53NC50
N-CHANNEL 500V – 0.070
Ω
– 53A ISOTOP
PowerMesh™II MOSFET
TYPE
V
DSS
R
I
D
DS(on)
STE53NC50
500V
< 0.08
Ω
53 A
TYPICAL R
(on) = 0.07
Ω
DS
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
NEW HIGH VOLTAGE BENCHMARK
GATE CHARGE MINIMIZED
ISOTOP
DESCRIPTION
The PowerMESH
™
II is the evolution of the first
generation of MESH OVERLAY
™.
The layout re-
finements introduced greatly improve the Ron*area
figure of merit while keeping the device at the lead-
ing edge for what concerns swithing speed, gate
charge and ruggedness.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
HIGH CURRENT, HIGH SPEED SWITCHING
SWITH MODE POWER SUPPLIES (SMPS)
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
500
Unit
V
V
DS
Drain-source Voltage (V
= 0)
GS
V
Drain-gate Voltage (R
= 20 k
Ω
)
500
V
DGR
GS
V
GS
Gate- source Voltage
±30
V
I
D
Drain Current (continuos) at T
= 25°C
53
A
C
I
Drain Current (continuos) at T
= 100°C
33
A
D
C
I
( )
Drain Current (pulsed)
212
A
DM
P
TOT
Total Dissipation at T
= 25°C
460
W
C
Derating Factor
3.68
3
W/°C
V/ns
V
dv/dt (1)
Peak Diode Recovery voltage slope
Insulation Winthstand Voltage (AC-RMS)
Storage
T
e
mperature
V
2500
– 65 to 150
150
ISO
T
stg
°C
°C
T
Max. Operating Junction
T
e
mperature
j
(1) I
≤
53A, di/dt
≤
100 A/
µ
s, V
≤
24
V
, Tj
≤
T
jMAX
SD
DD
(•)Pulse width limited by safe operating area
May 2002
1/8
STE53NC50
THERMAL DATA
Rthj-case
Thermal Resistance Junction-case
Max
0.272
°C/W
°C/W
Rthc-h
Thermal Resistance Case-heatsink with Conductive
Grease Applied
0.05
AVALANCHE CHARACTERISTICS
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
53
A
(pulse width limited by T
max)
j
E
AS
Single Pulse Avalanche Energy
1043
mJ
(starting T
= 25 °C, I
= I
, V
= 50 V)
j
D
AR
DD
ELECTRICAL CHARACTERISTICS
(TCASE
= 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
Parameter
Drain-source
Test Conditions
Min.
T
y
p.
Max.
Unit
V
I
D
= 250 µA, V
= 0
500
V
(BR)DSS
GS
Breakdown Voltage
I
Zero Gate Voltage
V
V
V
= Max Rating
10
µA
µA
nA
DSS
DS
Drain Current (V
= 0)
GS
= Max Rating, T
= 125 °C
100
DS
GS
C
I
Gate-body Leakage
= ± 30V
±100
GSS
Current (V
= 0)
DS
ON (1)
Symbol
Parameter
Test Conditions
Min.
T
y
p.
3
Max.
4
Unit
V
V
GS(th)
V
V
= V
, I
= 250µA
Gate Threshold Voltage
2
DS
GS
D
R
Static Drain-source On
Resistance
= 10
V
, I
=
2
7A
0.07
0.08
Ω
DS(on)
GS
D
DYNAMIC
Symbol
Parameter
Test Conditions
Min.
T
y
p.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
> I
D(on)
x R
DS(on)max,
42
S
I
D
= 15 A
C
C
V =
25V, f = 1 MHz, V
= 0
DS GS
Input Capacitance
Output Capacitance
1
1
.2
1350
115
nF
pF
pF
iss
oss
C
rss
Reverse Transfer
Capacitance
Note: 1.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2/8
STE53NC50
ELECTRICAL CHARACTERISTICS
(CONTINUED)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
V
R
= 250
V
, I
= 26.5A
Turn-on Delay Time
46
ns
d(on)
DD
D
= 4.7
Ω
V =
10V
G
GS
t
r
Rise Time
70
ns
(see test circuit, Figure 3)
Q
V
V
= 400
V
, I
= 53A,
= 10V
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
310
46
434
nC
nC
nC
g
DD
D
GS
Q
gs
Q
150
gd
SWITCHING OFF
Symbol
Parameter
Off-voltage Rise Time
Fall Time
Test Conditions
Min.
Typ.
45
Max.
Unit
ns
t
V
R
= 400
V
, I
= 53A,
r(Voff)
DD
D
= 4.7
Ω,
V =
10V
G
GS
t
38
ns
f
(see test circuit, Figure 5)
t
Cross-over Time
85
ns
c
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
53
Unit
A
I
Source-drain Current
SD
I
(2)
(1)
Source-drain Current (pulsed)
Forward On Voltage
212
1.6
A
SDM
V
I
I
= 53A, V
= 0
V
SD
SD
GS
t
rr
= 53A, di/dt = 100A/µs,
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
760
17.86
47
ns
µC
A
SD
V
= 70
V
, T
= 150°C
j
DD
Q
rr
(see test circuit, Figure 5)
I
RRM
Note: 1.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse
width limited by safe operating area.
Safe Operating Area
Thermal Impedence
3/8
STE53NC50
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STE53NC50
Normalized Gate Thereshold Voltage vs Temp.
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STE53NC50
Fig. 1:
Unclamped Inductive Load Test Circuit
Fig. 2:
Unclamped Inductive Waveform
Fig. 3:
Switching Times Test Circuit For
Fig. 4:
Gate Charge test Circuit
Resistive Load
Fig. 5:
Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STE53NC50
ISOTOP MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
11.8
8.9
TYP.
MAX.
12.2
9.1
MIN.
0.466
0.350
0.076
0.029
0.496
0.990
1.240
0.157
0.161
0.586
1.185
1.488
0.157
0.307
MAX.
0.480
0.358
0.080
0.033
0.503
1.003
1.248
A
B
C
D
E
F
1.95
0.75
12.6
25.15
31.5
4
2.05
0.85
12.8
25.5
31.7
G
H
J
4.1
4.3
0.169
0.594
1.193
1.503
K
L
14.9
30.1
37.8
4
15.1
30.3
38.2
M
N
O
7.8
8.2
0.322
A
G
B
O
N
J
C
K
L
M
7/8
STE53NC50
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics – Printed in Italy – All Rights Reserved
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