STMicroelectronics-STF3LN80K5

STF3LN80K5  

N-

channel 800 V, 2.75 Ω typ., 2 A MDmesh™ K5  

Power MOSFET in a TO-220FP package  

Datasheet – production data  

Features  

Order code  

V

DS  

R

DS(on)

max  

I

D  

STF3LN80K5  

800 V  

3.25 Ω  

2 A  











Industry’s lowest R

DS(on)

x area  

Industry’s best FoM (figure of merit)  

Ultra-low gate charge  

100% avalanche tested  

Zener-protected  

TO-220FP  

Applications  



Switching applications  

Figure 1: Internal schematic diagram  

D(2)  

Description  

This very high voltage N-channel Power  

MOSFET is designed using MDmesh™ K5  

technology based on an innovative proprietary  

vertical structure. The result is a dramatic  

reduction in on-resistance and ultra-low gate  

charge for applications requiring superior power  

density and high efficiency.  

G(1)  

S(3)  

AM15572v1_no_tab  

Table 1: Device summary  

Order code  

Marking  

Package  

Packing  

STF3LN80K5  

3LN80K5  

TO-220FP  

Tube  

July 2016  

DocID027715 Rev 2  

1/13  

This is information on a product in full production.  

Contents  

STF3LN80K5  

Contents  

2/13  

DocID027715 Rev 2  

STF3LN80K5  

Electrical ratings  

1

Electrical ratings  

Table 2: Absolute maximum ratings  

Symbol  

Parameter  

Value  

± 30  

2

Unit  

V

V

GS  

Gate-source voltage  

I

Drain current (continuous) at T

C

= 25 °C  

Drain current (continuous) at T

C

= 100 °C  

Drain current (pulsed)  

A

I

1.25  

8

A

I

A

P

TOT  

V

ISO  

Total dissipation at T

C

= 25 °C  

20  

W

Insulation withstand voltage (RMS) from all three leads to external  

heat sink (t = 1 s; T

C

= 25 °C)  

2500  

V

dv/d

Peak diode recovery voltage slope  

dv/d

MOSFET dv/dt ruggedness  

4.5  

50  

V/ns  

T

stg  

T

j  

Storage temperature range  

– 55 to 150  

°C  

Operating junction temperature range  

Notes:  

(3)  

I

≤ 2 A, di/dt ≤ 100 A/µs; V

DSpeak

< V

(BR)DSS

, V

DD

= 640 V  

SD  

(4)  

V

≤ 640 V.  

DS  

Table 3: Thermal data  

Parameter  

Symbol  

R

thj-case  

R

thj-amb  

Value  

6.25  

Unit  

Thermal resistance junction-case  

Thermal resistance junction-ambient  

°C/W  

°C/W  

62.5  

Table 4: Avalanche characteristics  

Parameter  

Symbol  

I

AR  

Value Unit  

Avalanche current, repetitive or not repetitive (pulse width limited by T

jmax  

)

0.7  

A

E

AS  

Single pulse avalanche energy (starting T

j

= 25°C, I

D

= I

AR

; V

DD

= 50 V)  

155  

mJ  

DocID027715 Rev 2  

3/13  

Electrical characteristics  

STF3LN80K5  

2

Electrical characteristics  

(T

C

= 25 °C unless otherwise specified)  

Table 5: On /off states  

Symbol  

Parameter  

Test conditions  

I

D

= 1 mA, V

GS

= 0 V  

V

DS

= 800 V, V

GS

= 0 V  

Min. Typ. Max. Unit  

Drain-source breakdown  

voltage  

V

(BR)DSS  

800  

V

1

µA  

µA  

Zero gate voltage  

drain current  

I

DSS  

V

DS

= 800 V, V

GS

= 0 V,  

T

C

= 125

50  

Gate body leakage  

current  

I

GSS  

V

GS

= ± 20 V, V

GS

= 0 V  

V

DS

= V

GS

, I

D

= 100 µA  

V

GS

= 10 V, I

D

= 1 A  

±10  

5

µA  

V

V

GS(th)  

R

DS(on)  

Gate threshold voltage  

3

4

Static drain-source  

on-resistance  

2.75 3.25  

Ω

Notes:  

Table 6: Dynamic  

Test conditions  

Symbol  

C

iss  

Parameter  

Input capacitance  

Output capacitance  

Min. Typ. Max. Unit  

–

–

102  

11  

–

–

pF  

pF  

C

oss  

V

DS

= 100 V, f = 1 MHz,  

V

GS

= 0 V  

Reverse transfer  

capacitance  

C

rss  

–

–

–

0.1  

20  

7

–

–

–

pF  

pF  

pF  

Equivalent capacitance  

time related  

C

o

V

DS

= 0 to 640 V, V

GS

= 0 V  

f = 1 MHz, I

D

= 0 A  

Equivalent capacitance  

energy related  

C

R

G  

Q

g  

Intrinsic gate resistance  

Total gate charge  

–

–

–

–

12  

–

–

–

–

Ω

V

DD

= 640 V, I

D

= 2 A,  

V

GS

= 10 V ( see

)  

2.63  

0.91  

1.53  

nC  

nC  

nC  

Q

gs  

Q

gd  

Gate-source charge  

Gate-drain charge  

Notes:  

increases from 0 to 80% V

DSS  

increases from 0 to 80% V

DSS  

4/13  

DocID027715 Rev 2  

STF3LN80K5  

Electrical characteristics  

Min. Typ. Max. Unit  

Table 7: Switching times  

Test conditions  

Symbol  

t

d(on)  

t

r  

t

d(off)  

t

f  

Parameter  

Turn-on delay time  

Rise time  

–

–

–

–

6.2  

7

–

–

–

–

ns  

ns  

ns  

ns  

V

DD

= 400 V, I

D

= 1 A, R

G

= 4.7

Ω,  

V

GS

= 10 V ( see

)  

Turn-off delay time  

Fall time  

30  

26  

Table 8: Source drain diode  

Test conditions  

Symbol  

Parameter  

Min. Typ. Max. Unit  

I

SD  

Source-drain current  

–

–

2

8

A

A

Source-drain current  

(pulsed)  

I

S

V

Forward on voltage  

I

SD

= 2 A, V

GS

= 0 V  

–

–

1.5  

V

t

rr  

Reverse recovery time  

210  

0.8  

ns  

I

SD

= 2 A, di/dt = 100 A/µs,  

Reverse recovery  

charge  

Q

rr  

V

DD

= 60 V ( see

)  

–

µC  

Reverse recovery  

current  

I

RRM  

t

rr  

–

–

–

7.6  

345  

1.2  

A

Reverse recovery time  

ns  

µC  

I

SD

= 2 A, di/dt = 100 A/µs,  

V

DD

= 60 V, T

j

= 150 °C, (see  

)  

Reverse recovery  

charge  

Q

rr  

Reverse recovery  

current  

I

RRM  

–

7.2  

A

Notes:  

Table 9: Gate-source Zener diode  

Symbol  

Parameter  

Test conditions  

Min. Typ. Max. Unit  

30  

V

(BR)GSO

Gate-source breakdown voltage  

I

GS

= ± 1 mA, I

D

= 0 A  

–

–

V

The built-in back-to-back Zener diodes are specifically designed to enhance the ESD  

performance of the device. The Zener voltage facilitates efficient and cost-effective device  

integrity protection, thus eliminating the need for additional external componentry.  

DocID027715 Rev 2  

5/13  

Electrical characteristics  

STF3LN80K5  

2.1  

2.1 Electrical characteristics (curves)  

Figure 2: Safe operating area  

Figure 3: Thermal impedance  

Figure 4: Output characteristics  

Figure 5: Transfer characteristics  

Figure 6: Gate charge vs gate-source voltage  

Figure 7: Static drain-source on-resistance  

6/13  

DocID027715 Rev 2  

STF3LN80K5  

Electrical characteristics  

Figure 9: Source-drain diode forward  

characteristics  

Figure 8: Capacitance variations  

Figure 10: Normalized gate threshold voltage  

vs temperature  

Figure 11: Normalized on-resistance vs  

temperature  

Figure 13: Maximum avalanche energy vs  

starting TJ  

Figure 12: Normalized V(BR)DSS vs  

temperature  

DocID027715 Rev 2  

7/13  

Test circuits  

STF3LN80K5  

3

Test circuits  

Figure 14: Test circuit for resistive load  

switching times  

Figure 15: Test circuit for gate charge  

behavior  

V

DD  

RL  

I

G

= CONST  

D.U.

T

.  

100 Ω  

V

GS  

pulse width  

+

2.7 kΩ  

V

G  

2200  

μF  

47 kΩ  

1 kΩ  

AM01469v10  

Figure 16: Test circuit for inductive load  

switching and diode recovery times  

Figure 17: Unclamped inductive load test  

circuit  

Figure 19: Switching time waveform  

Figure 18: Unclamped inductive waveform  

8/13  

DocID027715 Rev 2  

STF3LN80K5  

Package information  

4

Package information  

In order to meet environmental requirements, ST offers these devices in different grades of  

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®  

specifications, grade definitions and product status are available at:

.  

ECOPACK

®

is an ST trademark.  

DocID027715 Rev 2  

9/13  

Package information  

STF3LN80K5  

4.1  

TO-220FP package information  

Figure 20: TO-220FP package outline  

10/13  

DocID027715 Rev 2  

STF3LN80K5  

Package information  

Table 10: TO-220FP package mechanical data  

mm  

Dim.  

Min.  

4.4  

Typ.  

Max.  

4.6  

A

B

2.5  

2.7  

D

2.5  

2.75  

0.7  

E

0.45  

0.75  

1.15  

1.15  

4.95  

2.4  

F

1

F1  

F2  

G

1.70  

1.70  

5.2  

G1  

H

2.7  

10  

10.4  

L2  

L3  

L4  

L5  

L6  

L7  

Dia  

16  

28.6  

9.8  

2.9  

15.9  

9

30.6  

10.6  

3.6  

16.4  

9.3  

3

3.2  

DocID027715 Rev 2  

11/13  

Revision history  

STF3LN80K5  

5

Revision history  

Table 11: Document revision history  

Changes  

Date  

Revision  

13-May-2015  

1

Initial release  

Updated title and features in cover page.  

Updated

and

01-Jul-2016  

2

Added

Minor text changes.  

12/13  

DocID027715 Rev 2  

STF3LN80K5  

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–

All rights reserved  

DocID027715 Rev 2  

13/13