STMicroelectronics-STF5N60M2

Part #STMicroelectronics-STF5N60M2
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STMicroelectronics-STF5N60M2
STF5N60M2  
N-
channel 600 V, 1.3 Ω typ., 3.5 A MDmesh™ M2  
Power MOSFET in a TO-220FP package  
Datasheet – production data  
Features  
Order code  
V

DS

@ T

Jmax  

R

DS(on)

max.  
I

D  

STF5N60M2  
650 V  
1.4 Ω  
3.5 A  
Extremely low gate charge  
Excellent output capacitance (C

OSS

) profile  
100% avalanche tested  
Zener-protected  
Applications  
TO-220FP  
Switching applications  
Figure 1: Internal schematic diagram  
Description  
This device is an N-channel Power MOSFET  
developed using MDmesh™ M2 technology.  
Thanks to its strip layout and an improved vertical  
structure, the device exhibits low on-resistance  
and optimized switching characteristics,  
rendering it suitable for the most demanding high  
efficiency converters.  
Table 1: Device summary  
Order code  
Marking  
Package  
Packing  
STF5N60M2  
5N60M2  
TO-220FP  
Tube  
June 2016  
DocID025320 Rev 2  
1/13  
This is information on a product in full production.  

STF5N60M2  
Electrical ratings  
1
Electrical ratings  
Table 2: Absolute maximum ratings  
Symbol  
Parameter  
Value  
Unit  
V

GS  

Gate-source voltage  
±25  
3.5  
2.2  
14  
V
Drain current (continuous) at T

C

= 25 °C  
Drain current (continuous) at T

C

= 100 °C  
Drain current (pulsed)  
A
A
P

TOT  

Total dissipation at T

C

= 25 °C  
20  
W
Insulation withstand voltage (RMS) from all three leads to  
external heat sink (t = 1 s; T

C

= 25 °C)  
V

ISO  

2500  
V
dv/d

Peak diode recovery voltage slope  
dv/d

MOSFET dv/dt ruggedness  
15  
50  
V/ns  
T

stg  

T

j  

Storage temperature range  
-55 to 150  
°C  
Operating junction temperature range  
Notes:  

(1)

Limited by package.  

(2)

Pulse width limited by safe operating area.  
(3)  
I
≤ 3.5 A, di/dt ≤ 400 A/μs; V

DS

peak < V

(BR)DSS

, V

DD

= 400 V.  
SD  
(4)  
V
≤ 480 V.  
DS  
Table 3: Thermal data  
Parameter  
Symbol  
R

thj-case  

R

thj-amb  

Value  
6.25  
Unit  
°C/W  
°C/W  
Thermal resistance junction-case max.  
Thermal resistance junction-ambient max.  
62.5  
Table 4: Avalanche characteristics  
Symbol  
Parameter  
Value  
Unit  
Avalanche current, repetitive or not repetitive  
I

AR  

0.5  
A
(pulse width limited by T

jmax  

)
Single pulse avalanche energy  
E

AS  

80  
mJ  
(starting T

j

= 25 °C, I

D

= I

AR

; V

DD

= 50 V)  
DocID025320 Rev 2  
3/13  
 
 
 
 
 

Electrical characteristics  
STF5N60M2  
2
Electrical characteristics  
(T

case

= 25 °C unless otherwise specified)  
Table 5: On /off states  
Symbol  
Parameter  
Test conditions  
V

GS

= 0 V, I

D

= 1 mA  
Min. Typ. Max. Unit  
Drain-source breakdown  
voltage  
V

(BR)DSS  

600  
V
V

GS

= 0 V, V

DS

= 600 V  
1
Zero gate voltage drain  
current  
I

DSS  

µA  
V

GS

= 0 V, V

DS

= 600 V,  
T

C

= 125

100  
Gate-body leakage  
current  
I

GSS  

V

DS

= 0 V, V

GS

= ±25 V  
V

DS

= V

GS

, I

D

= 250 µA  
V

GS

= 10 V, I

D

= 1.7 A  
±10  
4
μA  
V
V

GS(th)  

R

DS(on)  

Gate threshold voltage  
2
3
Static drain-source  
on-resistance  
1.3  
1.4  
Ω
Notes:  

(1)

Defined by design, not subject to production test.  
Table 6: Dynamic  
Test conditions  
Symbol  
C

iss  

Parameter  
Input capacitance  
Output capacitance  
Min. Typ. Max. Unit  
–
–
211  
13  
–
–
C

oss  

V

DS

= 100 V, f = 1 MHz,  
V

GS

= 0 V  
pF  
Reverse transfer  
capacitance  
C

rss  

–
–
0.75  
19.5  
–
–
Equivalent output  
capacitance  
C

oss eq

V

DS

= 0 to 480 V, V

GS

= 0 V  
f = 1 MHz open drain  
pF  
R

G  

Q

g  

Intrinsic gate resistance  
Total gate charge  
–
–
–
6.2  
8
–
–
–
Ω
V

DD

= 480 V, I

D

= 3.5 A,  
V

GS

= 10 V  
Q

gs  

Gate-source charge  
1.6  
nC  
Q

gd  

Gate-drain charge  
–
4.4  
–
Notes:  
(1)  
C
oss eq.  
is defined as a constant equivalent capacitance giving the same charging time as C

oss

when V

DS  

increases from 0 to 80% V

DSS  

.
Table 7: Switching times  
Test conditions  
Symbol  
Parameter  
Min. Typ. Max. Unit  
Turn-on  
delay time  
t

d(on)  

t

r  

t

d(off)  

t

f  

–
–
–
–
12  
3
–
–
–
–
V

DD

= 300 V, I

D

= 1.7 A R

G

= 4.7
Ω,  
Rise time  
ns  
Turn-off  
delay time  
70  
15  
Fall time  
4/13  
DocID025320 Rev 2  
 
 
 

STF5N60M2  
Electrical characteristics  
Min. Typ. Max. Unit  
Table 8: Source-drain diode  
Test conditions  
Symbol  
Parameter  
I

SD  

Source-drain current  
–
–
3.5  
14  
A
A
Source-drain current  
(pulsed)  
Forward on voltage  
V

GS

= 0 V, I

SD

= 3.5 A  
–
–
1.6  
V
t

rr  

Reverse recovery time  
220  
ns  
I

SD

= 3.5 A, di/dt = 100 A/µs,  
V

DD

= 60 V (see

Reverse recovery  
charge  
Q

rr  

–
1.05  
µC  
Reverse recovery  
current  
I

RRM  

t

rr  

–
–
–
9.5  
314  
1.5  
A
Reverse recovery time  
ns  
µC  
I

SD

= 3.5 A, di/dt = 100 A/µs,  
V

DD

= 60 V, T

j

= 150 °C (see  
Reverse recovery  
charge  
Q

rr  

Reverse recovery  
current  
I

RRM  

–
9.5  
A
Notes:  

(1)

Pulse width is limited by safe operating area.  

(2)

Pulse test: pulse duration = 300 µs, duty cycle 1.5 %.  
DocID025320 Rev 2  
5/13  
 
 

Electrical characteristics  
STF5N60M2  
2.1  
Electrical characteristics (curves)  
Figure 2: Safe operating area  
Figure 3: Thermal impedance  
Figure 4: Output characteristics  
Figure 5: Transfer characteristics  
Figure 6: Gate charge vs gate-source voltage  
Figure 7: Static drain-source on-resistance  
6/13  
DocID025320 Rev 2  
 

STF5N60M2  
Electrical characteristics  
Figure 8: Capacitance variations  
Figure 9: Output capacitance stored energy  
Figure 10: Normalized gate threshold voltage  
vs temperature  
Figure 11: Normalized on-resistance vs  
temperature  
Figure 13: Source- drain diode forward  
characteristics  
Figure 12: Normalized V

(BR)DSS

vs temperature  
DocID025320 Rev 2  
7/13  

Test circuits  
STF5N60M2  
3
Test circuits  
Figure 14: Test circuit for resistive load  
switching times  
Figure 15: Test circuit for gate charge  
behavior  
Figure 16: Test circuit for inductive load  
switching and diode recovery times  
Figure 17: Unclamped inductive load test  
circuit  
Figure 19: Switching time waveform  
Figure 18: Unclamped inductive waveform  
8/13  
DocID025320 Rev 2  

STF5N60M2  
Package information  
4
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®  

specifications, grade definitions and product status are available at:

.  
ECOPACK

®

is an ST trademark.  
DocID025320 Rev 2  
9/13  

Package information  
STF5N60M2  
4.1  
TO-220FP package information  
Figure 20: TO-220FP package outline  
10/13  
DocID025320 Rev 2  

STF5N60M2  
Package information  
Table 9: TO-220FP package mechanical data  
mm  
Dim.  
Min.  
4.4  
Typ.  
Max.  
4.6  
A
B
2.5  
2.7  
D
2.5  
2.75  
0.7  
E
0.45  
0.75  
1.15  
1.15  
4.95  
2.4  
F
1
F1  
F2  
G
1.70  
1.70  
5.2  
G1  
H
2.7  
10  
10.4  
L2  
L3  
L4  
L5  
L6  
L7  
Dia  
16  
28.6  
9.8  
2.9  
15.9  
9
30.6  
10.6  
3.6  
16.4  
9.3  
3
3.2  
DocID025320 Rev 2  
11/13  

Revision history  
STF5N60M2  
5
Revision history  
Table 10: Document revision history  
Changes  
Date  
Revision  
30-Sep-2013  
1
First release.  
Updated title, features and description in cover page.  
15-Jun-2016  
2
Minor text changes.  
12/13  
DocID025320 Rev 2  

STF5N60M2  
IMPORTANT NOTICE
–
PLEASE READ CAREFULLY  
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, and  
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der  
acknowledgement.  
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the  
design of Purchasers’ products.  
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2016 STMicroelectronics
–
All rights reserved  
DocID025320 Rev 2  
13/13