STMicroelectronics-STF8N60DM2

Part #STMicroelectronics-STF8N60DM2
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STMicroelectronics-STF8N60DM2
STF8N60DM2  
N-
channel 600 V, 550 mΩ typ., 8 A MDmesh™ DM2  
Power MOSFET in a TO-220FP package  
Datasheet – production data  
Features  
Order code  
V

DS  

R

DS(on)

max.  
I

D  

P

TOT  

STF8N60DM2  
600 V  
600 mΩ  
8 A
 
25 W  
Fast-recovery body diode  
Extremely low gate charge and input  
capacitance  
Low on-resistance  
100% avalanche tested  
Extremely high dv/dt ruggedness  
Zener-protected  
TO-220FP  
Figure 1: Internal schematic diagram  
Applications  
D(2)  
Switching applications  
Description  
This high voltage N-channel Power MOSFET is  
part of the MDmesh™ DM2 fast recovery diode  
series. It offers very low recovery charge (Q

rr

)  
and time (t

rr

) combined with low R

DS(on)

, rendering  
it suitable for the most demanding high efficiency  
converters and ideal for bridge topologies and  
ZVS phase-shift converters.  
G(1)  
S(3)  
AM15572v1_no_tab  
Table 1: Device summary  
Order code  
Marking  
Package  
Packing  
STF8N60DM2  
8N60DM2  
TO-220FP  
Tube  
November 2016  
DocID027864 Rev 2  
1/13  
This is information on a product in full production.  

STF8N60DM2  
Electrical ratings  
1
Electrical ratings  
Table 2: Absolute maximum ratings  
Symbol  
Parameter  
Value  
±25  
8
Unit  
V

GS  

Gate-source voltage  
V
Drain current (continuous) at T

case

= 25 °C  
Drain current (continuous) at T

case

= 100 °C  
Drain current (pulsed)  
A
5
32  
A
P

TOT  

Total dissipation at T

case

= 25 °C  
Peak diode recovery voltage slope  
MOSFET dv/dt ruggedness  
25  
W
50  
V/ns  
kV  
50  
Insulation withstand voltage (RMS) from all three leads to external  
heat sink (t = 1 s; T

C

= 25 °C)  
V

ISO  

2.5  
T

stg  

T

j  

Storage temperature range  
–
55 to 150  
°C  
Operating junction temperature range  
Notes:  

(1)

Current is limited by package.  

(2)

Pulse width is limited by safe operating area.  
(3)  
I
≤ 8 A, di/dt=900 A/μs; V

DS

peak < V

(BR)DSS

, V

DD

= 400 V.  
SD  
(4)  
V
≤ 480 V.  
DS  
Table 3: Thermal data  
Symbol  
R

thj-case  

R

thj-amb  

Parameter  
Thermal resistance junction-case  
Thermal resistance junction-ambient  
Value  
Unit  
5
°C/W  
62.5  
Table 4: Avalanche characteristics  
Symbol  
Parameter  
Avalanche current, repetitive or not repetitive  
Single pulse avalanche energy  
Value  
Unit  
A
2.5  
430  
mJ  
Notes:  

(1)

Pulse width limited by T

jmax  

(2)

starting T

j

= 25 °C, I

D

= I

AR

, V

DD

= 50 V.  
.
DocID027864 Rev 2  
3/13  
 
 
 
 
 
 
 

Electrical characteristics  
STF8N60DM2  
2
Electrical characteristics  
(T

case

= 25 °C unless otherwise specified)  
Table 5: Static  
Test conditions  
Symbol  
Parameter  
Min. Typ. Max. Unit  
Drain-source breakdown  
voltage  
V

(BR)DSS  

V

GS

= 0 V, I

D

= 1 mA  
600  
V
V

GS

= 0 V, V

DS

= 600 V  
1
Zero gate voltage drain  
current  
I

DSS  

µA  
V

GS

= 0 V, V

DS

= 600 V,  
T

case

= 125

100  
Gate-body leakage  
current  
I

GSS  

V

DS

= 0 V, V

GS

= ±25 V  
V

DS

= V

GS

, I

D

= 250 µA  
V

GS

= 10 V, I

D

= 4 A  
±5  
5
µA  
V
V

GS(th)  

R

DS(on)  

Gate threshold voltage  
3
4
Static drain-source on-  
resistance  
550  
600  
mΩ  
Notes:  

(1)

Defined by design, not subject to production test.  
Table 6: Dynamic  
Test conditions  
Symbol  
C

iss  

Parameter  
Input capacitance  
Output capacitance  
Min. Typ. Max. Unit  
–
–
449  
24  
–
–
C

oss  

V

DS

= 100 V, f = 1 MHz,  
V

GS

= 0 V  
pF  
Reverse transfer  
capacitance  
C

rss  

–
–
0.89  
42  
–
–
Equivalent output  
capacitance  
C

oss eq

V

DS

= 0 to 480 V, V

GS

= 0 V  
f = 1 MHz, I

D

= 0 A  
pF  
R

G  

Q

g  

Intrinsic gate resistance  
Total gate charge  
–
–
–
–
6.5  
13.5  
3
–
–
–
–
Ω
V

DD

= 480 V, I

D

= 8 A,  
V

GS

= 10 V (see

Q

gs  

Q

gd  

Gate-source charge  
Gate-drain charge  
nC  
7.7  
Notes:  
(1)  
C
oss eq.  
is defined as a constant equivalent capacitance giving the same charging time as C

oss

when V

DS  

increases from 0 to 80% V

DSS  

.
Table 7: Switching times  
Test conditions  
Symbol  
t

d(on)  

t

r  

Parameter  
Turn-on delay time  
Rise time  
Min. Typ. Max. Unit  
V

DD

= 300 V, I

D

= 4 A  
–
–
–
10  
6
–
–
–
R

G

= 4.7
Ω, V

GS

= 10 V (see  
ns  
t

d(off)  

Turn-off delay time  
25.4  
t

f  

Fall time  
–
9.5  
–
4/13  
DocID027864 Rev 2  
 
 
 

STF8N60DM2  
Electrical characteristics  
Min. Typ. Max. Unit  
Table 8: Source-drain diode  
Test conditions  
Symbol  
I

SD  

Parameter  
Source-drain current  
–
–
8
A
A
Source-drain current  
(pulsed)  
32  
1.6  
t

rr  

Forward on voltage  
V

GS

= 0 V, I

SD

= 8 A  
–
–
–
V
Reverse recovery time  
Reverse recovery charge  
I

SD

= 8 A, di/dt = 100 A/µs,  
V

DD

= 60 V (see

80  
ns  
nC  
Q

rr  

188  
I

RRM  

Reverse recovery current  
–
4.7  
A
t

rr  

Reverse recovery time  
I

SD

= 8 A, di/dt = 100 A/µs,  
V

DD

= 60 V, T

j

= 150 °C (see  
–
–
160  
640  
ns  
Q

rr  

Reverse recovery charge  
nC  
I

RRM  

Reverse recovery current  
–
8
A
Notes:  

(1)

Pulse width is limited by safe operating area.  

(2)

Pulse test: pulse duration = 300 µs, duty cycle 1.5%.  
DocID027864 Rev 2  
5/13  
 
 

Electrical characteristics  
STF8N60DM2  
2.1  
Electrical characteristics (curves)  
Figure 2: Safe operating area  
Figure 3: Thermal impedance  
Figure 4: Output characteristics  
Figure 5: Transfer characteristics  
Figure 6: Gate charge vs gate-source voltage  
Figure 7: Static drain-source on resistance  
6/13  
DocID027864 Rev 2  
 

STF8N60DM2  
Figure 8: Capacitance variations  
Electrical characteristics  
Figure 9: Normalized gate threshold voltage vs  
temperature  
Figure 10: Normalized on-resistance vs temperature  
Figure 11: Normalized V(BR)DSS vs temperature  
Figure 12: Source-drain diode forward  
characteristics  
Figure 13: Output capacitance stored energy  
DocID027864 Rev 2  
7/13  

Test circuits  
STF8N60DM2  
3
Test circuits  
Figure 14: Test circuit for resistive load  
switching times  
Figure 15: Test circuit for gate charge  
behavior  
Figure 16: Test circuit for inductive load  
switching and diode recovery times  
Figure 17: Unclamped inductive load test  
circuit  
Figure 19: Switching time waveform  
Figure 18: Unclamped inductive waveform  
8/13  
DocID027864 Rev 2  

STF8N60DM2  
Package information  
4
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®  

specifications, grade definitions and product status are available at:

.  
ECOPACK

®

is an ST trademark.  
DocID027864 Rev 2  
9/13  

Package information  
STF8N60DM2  
4.1  
TO-220FP package information  
Figure 20: TO-220FP package outline  
10/13  
DocID027864 Rev 2  

STF8N60DM2  
Package information  
Table 9: TO-220FP package mechanical data  
mm  
Dim.  
Min.  
4.4  
Typ.  
Max.  
4.6  
A
B
2.5  
2.7  
D
2.5  
2.75  
0.7  
E
0.45  
0.75  
1.15  
1.15  
4.95  
2.4  
F
1
F1  
F2  
G
1.70  
1.70  
5.2  
G1  
H
2.7  
10  
10.4  
L2  
L3  
L4  
L5  
L6  
L7  
Dia  
16  
28.6  
9.8  
2.9  
15.9  
9
30.6  
10.6  
3.6  
16.4  
9.3  
3
3.2  
DocID027864 Rev 2  
11/13  

Revision history  
STF8N60DM2  
5
Revision history  
Table 10: Document revision history  
Changes  
Date  
Revision  
12-May-2015  
1
First release.  
Document status promoted from preliminary to production data.  
24-Nov-2016  
2
12/13  
DocID027864 Rev 2  

STF8N60DM2  
IMPORTANT NOTICE
–
PLEASE READ CAREFULLY  
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, and  
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der  
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design of Purchasers’ products.  
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2016 STMicroelectronics
–
All rights reserved  
DocID027864 Rev 2  
13/13