STMicroelectronics-STFI10NK60Z
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STFI10NK60Z
N-channel 600
V
,
0
.65
Ω
, 10 A, Zener-protected SuperMESH™
Power MOSFET in I²
P
A
KFP package
Datasheet — production data
Features
R
DS(on)
max
Type
V
DSS
I
D
P
TOT
STFI10NK60Z
600 V
< 0.75
Ω
10 A
35 W
■
Fully insulated and low profile package with
increased creepage path from pin to heatsink
plate
1
2
■
Extremely high dv/dt capability
■
100% avalanche tested
■
Gate charge minimized
3
I²
P
A
KFP
(TO-281)
Applications
■
Switching applications
Figure 1.
Internal schematic diagram
D(2)
Description
This device is an N-channel Zener-protected
Power MOSFET developed using
STMicroelectronics’ SuperMESH™ technolog
y
,
achieved through optimization of ST’s well-
established strip-based PowerMESH™ layout. In
addition to a significant reduction in on-
resistance, this device is designed to ensure a
high level of dv/dt capability for the most
demanding applications.
G(1)
S(3)
AM01476v1
Table 1.
Device summary
Order code
Marking
Package
Packaging
I
2
P
A
KFP
(TO-281)
STFI10NK60Z
10NK60Z
T
u
be
March 2012
Doc ID 018968 Rev 3
1/13
This is information on a product in full production.
13
Contents
STFI10NK60Z
Contents
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
Doc ID 018968 Rev 3
STFI10NK60Z
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V
DS
V
GS
I
D
Drain-source voltage
600
30
V
V
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
10
(1)
5.7
(1)
36
(1)
35
A
I
D
A
(2)
I
DM
A
P
TOT
T
o
tal dissipation at T
C
= 25 °C
Gate-source human body model (R=1,5 k
Ω
, C=100 pF)
Peak diode recovery voltage slope
W
kV
V/ns
ESD
4
dv/dt
(3)
4.5
Insulation withstand voltage (RMS) from all three
leads
to external heat sink (t=1 s;T
C
=25 °C)
V
ISO
2500
V
T
j
Operating junction temperature
Storage temperature
-55 to 150
°C
T
stg
1. Limited
by maximum junction temperature
2. Pulse
width limited by safe operating area
3.
I
< 10A,
di/dt <
200A/µs, V
=80% V
SD DD
(BR)DSS
T
a
ble 3.
Symbol
R
thj-case
R
thj-amb
Thermal data
Parameter
Value
3.6
Unit
°C/W
°C/W
Thermal resistance junction-case Max
Thermal resistance junction-amb Max
62.5
T
a
ble 4.
Avalanche characteristics
Parameter
Symbol
Value
Unit
I
AR
Repetitive or non repetitive avalanche current
9
(1)
A
Single pulse avalanche energy
E
AS
300
mJ
(starting Tj=25 °C, I
D
=I
AR
, V
DD
= 50 V)
1. Limited
by maximum junction temperature
Doc ID 018968 Rev 3
3/13
Electrical characteristics
STFI10NK60Z
2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified).
T
a
ble 5.
Symbol
On /off states
Parameter
Test conditions
I
D
= 250 µA
Min.
Typ.
Max. Unit
Drain-source breakdown
voltage, (V
GS
= 0)
V
(BR)DSS
600
V
V
DS
= 600 V
1
µA
µA
Zero gate voltage drain
current (V
GS
= 0)
I
DSS
V
DS
= 600
V
,
T
C
= 125 °C
50
Gate body leakage
current (V
DS
= 0)
I
GSS
V
GS
= 20
V
10
4.5
µA
V
V
GS(th)
R
DS(on)
Gate threshold voltage
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10
V
,
I
D
= 4.5 A
3
3.75
0.65
Static drain-source on
resistance
0.75
Ω
T
a
ble 6.
Symbol
Dynamic
Parameter
Test conditions
Min.
Typ.
Max. Unit
Forward
transconductance
(1)
g
fs
V
DS
=15
V
,
I
D
= 4.5 A
–
7.8
S
Input capacitance
Output capacitance
C
iss
C
oss
C
rss
1370
156
37
pF
pF
pF
V
DS
=25
V
,
f
=1 MHz, V
GS
=0
–
Reverse transfer
capacitance
Equivalent output
capacitance
(2)
C
oss eq
V
GS
=0, V
DS
=0 to 480 V
–
–
90
pF
Q
g
Q
gs
Q
gd
T
o
tal gate charge
Gate-source charge
Gate-drain charge
50
10
25
70
nC
nC
nC
V
DD
=480
V
,
I
D
= 8 A
1. Pulsed:
pulse duration = 300µs, duty cycle 1.5%
2. .
is defined as a constant equivalent capacitance giving the same charging time as C
C
when V
DS
oss eq
oss
increases from 0 to 80%
T
a
ble 7.
Symbol
Switching times
Parameter
Test conditions
Min. Typ.
Max Unit
V
DD
=300
V
,
I
D
=4 A,
R
G
=4.7
Ω
,
V
GS
=10 V
t
d(on)
t
r
T
u
rn-on delay time
Rise time
20
20
ns
ns
–
–
–
–
V
DD
=300
V
,
I
D
=4 A,
R
G
=4.7
Ω
,
V
GS
=10 V
t
d(off)
t
f
T
u
rn-off delay time
Fall time
55
30
ns
ns
4/13
Doc ID 018968 Rev 3
STFI10NK60Z
Electrical characteristics
Min. Typ. Max.
Unit
T
a
ble 8.
Source drain diode
Parameter
Symbol
Test conditions
I
SD
Source-drain current
10
36
A
A
–
–
(1)
I
SDM
Source-drain current (pulsed)
(2)
V
SD
Forward on voltage
I
SD
=10 A, V
GS
=0
1.6
V
t
rr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
570
4.3
15
ns
µC
A
I
SD
=8 A, di/dt = 100 A/µs,
Q
rr
–
V
DD
=40
V
,
T
j=150 °C
I
RRM
1. Pulse
width limited by safe operating area
2. Pulsed:
pulse duration = 300µs, duty cycle 1.5%
Table 9.
Symbol
Gate-source Zener diode
Parameter
Test conditions
Min. Typ. Max.
Unit
30
Gate-source breakdown
V
(BR)GSO
I
GS
=
1 mA
–
V
voltage (I
D
=0)
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capabilit
y
, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrit
y
.
T
hese integrated Zener diodes thus avoid the usage of external components.
Doc ID 018968 Rev 3
5/13
Electrical characteristics
STFI10NK60Z
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
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6/13
Doc ID 018968 Rev 3
STFI10NK60Z
Electrical characteristics
Figure 8.
Gate charge vs gate-source voltage
Figure 9.
Capacitance variations
Figure 10.
Normalized gate threshold voltage
Figure 11.
Normalized on resistance vs
vs temperature
temperature
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Figure 12.
Source-drain diode forward
characteristics
Figure 13.
Maximum avalanche energy vs
temperature
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Doc ID 018968 Rev 3
7/13
Electrical characteristics
STFI10NK60Z
Figure 14.
Normalized B
VDSS
vs temperature
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8/13
Doc ID 018968 Rev 3
STFI10NK60Z
Test circuits
3
Test circuits
Figure 15.
Switching times test circuit for
resistive load
Figure 16.
Gate charge test circuit
V
DD
12V
47k
Ω
1k
Ω
100nF
2200
3
.
3
μ
F
R
L
μ
F
I
G
=CON
S
T
V
DD
100
Ω
V
i
=20V=V
GMAX
D.U.
T
.
V
G
V
D
R
G
V
G
S
2200
μ
F
D.U.
T
.
2.7k
Ω
47k
Ω
P
W
1k
Ω
P
W
AM0146
8
v1
AM01469v1
Figure 17.
Test circuit for inductive load
switching and diode recovery times
Figure 18.
Unclamped inductive load test
circuit
L
A
A
A
B
D
FA
S
T
DIODE
L=100
μ
H
V
D
G
2200
μ
F
D.U.
T
.
B
3
.
3
μ
F
V
DD
S
3
.
3
μ
F
1000
μ
F
B
V
DD
25
Ω
I
D
D
G
R
G
S
V
i
D.U.
T
.
P
w
AM01470v1
AM01471v1
Figure 19.
Unclamped inductive waveform
Figure 20.
Switching time waveform
t
on
td
on
t
off
td
off
V
(BR)D
SS
t
r
t
f
V
D
90
%
10
%
90
%
I
DM
10
%
V
D
S
I
D
0
0
V
DD
V
DD
90
%
V
G
S
10
%
AM01472v1
AM0147
3
v1
Doc ID 018968 Rev 3
9/13
Package mechanical data
STFI10NK60Z
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in
different grades of
ECO
P
A
CK® packages, depending on their level of environmental compliance. ECO
P
ACK®
ECO
P
A
CK is an ST trademark.
10/13
Doc ID 018968 Rev 3
STFI10NK60Z
Package mechanical data
T
a
ble 10.
I
2
P
A
KFP (TO-281) mechanical data
mm
Dim.
Min.
Typ.
Max.
A
B
4.40
2.50
2.50
0.65
0.45
0.75
4.60
2.70
2.75
0.85
0.70
1.00
1.20
5.20
10.40
23.00
14.10
10.85
3.20
1.25
7.50
D
D1
E
F
F1
G
4.95
10.00
21.00
13.20
10.55
2.70
–
H
L1
L2
L3
L4
L5
L6
0.85
7.30
Figure 21.
I
2
P
A
KFP (TO-281) drawing
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Doc ID 018968 Rev 3
11/13
Revision history
STFI10NK60Z
5
Revision history
T
a
ble 11.
Document revision history
Date
Revision
Changes
27-Jun-2011
1
First release
have been added.
03-Nov-2011
19-Mar-2012
2
3
Document status promoted from preliminary data to production data.
Package name has been updated.
12/13
Doc ID 018968 Rev 3
STFI10NK60Z
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Doc ID 018968 Rev 3
13/13
