STMicroelectronics-STGIPN3H60-H
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STGIPN3H60-H
SLLIMM™
-nano small low-loss intelligent molded module
IPM, 3 A, 600 V, 3-phase IGBT inverter bridge
Datasheet – production data
Applications
3-phase inverters for motor drives
Dish washers, refrigerator compressors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
This intelligent power module implements a
compact, high performance AC motor drive in a
simple, rugged design. It is composed of six
IGBTs with freewheeling diodes and three half-
bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics
with optimized switching speed. The package is
optimized for thermal performance and
compactness in built-in motor applications, or
other low power applications where assembly
space is limited. This IPM includes an operational
amplifier, completely uncommitted, and a
comparator that can be used to design a fast and
efficient protection circuit. SLLIMM™ is a
trademark of STMicroelectronics.
Features
IPM 3 A, 600 V, 3-phase IGBT inverter
bridge including control ICs for gate driving
and freewheeling diodes
Optimized for low electromagnetic
interference
V
CE(sat)
negative temperature coefficient
3.3 V, 5 V, 15 V CMOS/TTL inputs
comparators with hysteresis and pull
down/pull up resistors
Undervoltage lockout
Internal bootstrap diode
Interlocking function
Smart shutdown function
Comparator for fault protection against
overtemperature and overcurrent
Op amp for advanced current sensing
Optimized pinout for easy board layout
Table 1: Device summary
Order code
Marking
Package
Packing
STGIPN3H60-H
GIPN3H60-H
NDIP-26L
Tube
September 2016
DocID024132 Rev 4
1/23
This is information on a product in full production.
Contents
STGIPN3H60-H
Contents
2/23
DocID024132 Rev 4
STGIPN3H60-H
Internal schematic
diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1: Internal schematic diagram
DocID024132 Rev 4
3/23
Internal schematic
diagram and pin configuration
Table 2: Pin description
Description
STGIPN3H60-H
Pin
Symbol
1
GND
Ground
SD /
OD
2
Shut down logic input (active low) / open drain (comparator output)
3
4
V
CC
W
Low voltage power supply W phase
High side logic input for W phase
Low side logic input for W phase
Op amp non inverting input
Op amp output
HIN W
LIN W
OP+
5
6
7
OP
OUT
OP-
8
Op amp inverting input
9
V
CC
V
Low voltage power supply V phase
High side logic input for V phase
Low side logic input for V phase
Comparator input
10
11
12
13
14
HIN V
LIN V
CIN
V
CC
U
Low voltage power supply for U phase
High side logic input for U phase
HIN U
SD /
OD
LIN U
15
Shut down logic input (active low) / open drain (comparator output)
16
17
18
19
20
21
22
23
24
25
26
Low side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
V
BOOT
P
U
U, OUT
U
N
U
U phase output
Negative DC input for U phase
Bootstrap voltage for V phase
V phase output
V
BOOT
V
V, OUT
V
N
V
Negative DC input for V phase
Bootstrap voltage for W phase
W phase output
V
BOOT
W
W, OUT
W
N
W
Negative DC input for W phase
4/23
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STGIPN3H60-H
Internal schematic
diagram and pin configuration
Figure 2: Pin layout (top view)
PIN17
(*)
(*)
PIN26
PIN #1 ID
PIN16
PIN1
(*) Dummy pin internally connected to
P (positive DC input).
AM09368V1
DocID024132 Rev 4
5/23
Electrical ratings
STGIPN3H60-H
2
Electrical ratings
2.1
Absolute maximum ratings
Table 3: Inverter part
Symbol
Parameter
Each IGBT continuous collector current at T
C
= 25°C
Each IGBT pulsed collector current
Value
600
3
Unit
V
V
CES
A
18
A
P
TOT
Each IGBT total dissipation at T
C
= 25°C
8
W
Notes:
(1)
Applied between HIN
i
, LIN
i
and G
ND
for i = U, V, W.
(2)
Calculated according to the iterative formula:
(3)
Pulse width limited by max junction temperature.
Table 4: Control part
Parameter
Symbol
Min.
Max.
Unit
Output voltage applied between OUT
U
, OUT
V
, OUT
W
GND
–
V
OUT
V
boot
– 21
V
boot
+ 0.3
V
V
CC
V
CIN
V
op+
V
op-
V
boot
V
IN
Low voltage power supply
Comparator input voltage
OPAMP non-inverting input
OPAMP inverting input
Bootstrap voltage
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
21
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
620
V
V
V
V
V
Logic input voltage applied between HIN, LIN and GND
Open drain voltage
15
V
V
SD OD
15
V
⁄
∆V
OUT/dT
Allowed output slew rate
50
V/ns
Table 5: Total system
Symbol
Parameter
Value
Unit
Isolation withstand voltage applied between each pin and
heatsink plate (AC voltage, t = 60 s.)
V
ISO
1000
V
T
j
Power chips operating junction temperature range
Module operation case temperature range
-40 to 150
-40 to 125
°C
°C
T
C
6/23
DocID024132 Rev 4
STGIPN3H60-H
Electrical ratings
2.2
Thermal data
Table 6: Thermal data
Parameter
Symbol
Value
Unit
R
thJA
Thermal resistance junction-ambient
50
°C/W
DocID024132 Rev 4
7/23
Electrical characteristics
STGIPN3H60-H
3
Electrical characteristics
3.1
Inverter part
T
J
= 25 °C unless otherwise specified.
Table 7: Static
Test conditions
Symbol
Parameter
Min. Typ. Max. Unit
–
–
2.15
1.65
2.6
Collector-emitter saturation
voltage
T
J
= 125 °C
V
CE(sat)
V
Collector-cut off current
I
CES
V
F
V
CE
= 550 V, V
CC
= V
Boot
= 15 V
–
–
250
1.7
µA
V
Diode forward voltage
Notes:
(1)
Applied between HIN
i
, LIN
i
and G
ND
for i = U, V, W.
Table 8: Inductive load switching time and energy
Test conditions
Min. Typ. Max. Unit
Symbol
Parameter
Turn-on time
–
–
–
–
–
–
–
275
90
–
–
–
–
–
–
–
Crossover time (on)
Turn-off time
V
DD
= 300 V,
890
125
50
ns
µJ
V
CC
= V
boot
= 15 V,
Crossover time (off)
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
I
C
= 1 A
t
rr
E
on
E
off
18
13
Notes:
(1)
t
and t
OFF
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are the switching time of IGBT itself under
ON
the internally given gate driving condition.
(2)
Applied between HIN
i
, LIN
i
and G
ND
for i = U, V, W.
8/23
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STGIPN3H60-H
Electrical characteristics
Figure 3: Switching time test circuit
INPUT
BOOT
Lin
BUS
VBOOT>VCC
+5V
/SD
Hin
Vcc
DT
HVG
OUT
RSD
L
VCC
IC
LVG
CP+
VCE
GND
0
1
AM06019v3
Notes:
DocID024132 Rev 4
9/23
Electrical characteristics
STGIPN3H60-H
3.2
Control part
Table 9: Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V
CC_hys
V
CC
UV hysteresis
1.2
11.5
10
1.5
12
1.8
12.5
11
V
V
V
V
CC_thON
V
CC
UV turn ON threshold
V
CC_thOFF
V
CC
UV turn OFF threshold
10.5
V
CC
= 10 V,
SD /OD
= 5 V, LIN = 0,
H
IN
= 0, C
IN
= 0
Undervoltage quiescent supply
current
I
qccu
150
1
µA
V
cc
= 15 V,
SD /OD
= 5 V, LIN = 0,
H
IN
= 0, C
IN
= 0
I
qcc
Quiescent current
mA
V
Internal comparator (CIN)
reference voltage
V
ref
0.5
0.54 0.58
Table 10: Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V
BS_hys
V
BS
UV hysteresis
1.2
1.5
1.8
V
V
V
V
BS_thON
V
BS
UV turn ON threshold
V
BS_thOFF
V
BS
UV turn OFF threshold
11.1 11.5 12.1
9.8
10
70
10.6
110
V
BS
< 9 V,
SD /OD
= 5 V, LIN = 0,
HIN=5 V, C
IN
= 0
Undervoltage V
BS
quiescent
current
I
QBSU
µA
V
BS
=15 V,
SD /OD
= 5 V, LIN = 0,
HIN=5 V, C
IN
= 0
I
QBS
V
BS
quiescent current
150
120
210
µA
Bootstrap driver on-
resistance
R
DS(on)
LVG ON
Ω
10/23
DocID024132 Rev 4
STGIPN3H60-H
Symbol
Electrical characteristics
Table 11: Logic inputs (V
CC
= 15 V unless otherwise specified)
Test conditions
Min. Typ. Max. Unit
Parameter
V
il
Low logic level voltage
High logic level voltage
0.8
V
V
V
ih
2.25
20
HIN logic “1” input bias
current
I
HINh
I
HINI
I
LINh
I
LINI
HIN = 15 V
HIN = 0 V
LIN = 15 V
LIN = 0 V
40
40
100
1
µA
µA
µA
µA
HIN logic “0” input bias
current
LIN logic “1” input bias
current
20
30
100
1
LIN logic “0” input bias
current
SD
logic “0” input bias
SD =
15 V
SD =
0 V
I
SDh
120
300
3
µA
current
SD
logic “1” input bias
I
SDI
µA
ns
current
D
t
Dead time
180
Table 12: OPAMP characteristics (V
CC
= 15 V unless otherwise specified)
Test condition
Min. Typ. Max. Unit
V
ic
= 0 V, V
o
= 7.5 V
Symbol Parameter
V
io
I
io
Input offset voltage
6
mV
nA
nA
Input offset current
4
40
V
ic
= 0 V, V
o
= 7.5 V
I
ib
100
200
Input common mode voltage
range
V
icm
0
V
V
OL
V
OH
Low level output voltage
High level output voltage
R
L
= 10 kΩ to V
CC
R
L
= 10 kΩ to GND
Source, V
id
= + 1 V; V
o
= 0 V
Sink, V
id
= -1 V; V
o
= V
CC
V
i
= 1 – 4 V; C
L
= 100 pF; unity gain
V
o
= 7.5 V
75
14.7
30
150
mV
V
14
16
50
2.5
8
mA
mA
V/µs
MHz
dB
I
o
Output short-circuit current
80
SR
GBWP
A
vd
Slew rate
3.8
12
Gain bandwidth product
Large signal voltage gain
Supply voltage rejection ratio
Common mode rejection ratio
R
L
= 2 kΩ
70
60
55
85
SVR
vs. V
CC
75
dB
CMRR
70
dB
Notes:
(1)
The direction of input current is out of the IC.
DocID024132 Rev 4
11/23
Electrical characteristics
STGIPN3H60-H
Table 13: Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol
Parameter
Input bias current
Test conditions
V
CIN
= 1 V
Min. Typ. Max.
Unit
µA
V
I
ib
3
V
ol
Open drain low level output voltage
I
od
= 3 mA
0.5
SD /OD
pulled to 5 V through
100 kΩ resistor
t
d_comp
Comparator delay
90
130
ns
SR
t
sd
Slew rate
C
L
= 180 pF; R
pu
= 5 kΩ
60
V/µsec
Shutdown to high / low side driver
propagation delay
V
OUT
= 0, V
boot
= V
CC
, V
IN
= 0 to
3.3 V
50
50
125
200
250
ns
Comparator triggering to high / low
side driver turn-off propagation delay
step from 0 V to 3.3 V to pin CIN
Measured applying a voltage
t
isd
200
Table 14: Truth table
Logic input (V
I
)
Output
Condition
SD /OD
LIN
HIN
LVG
HVG
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
L
H
H
L
L
L
H
L
L
L
L
L
H
H
H
H
H
0 “logic state” half
-bridge tri-state
1 “logic state” low side direct driving
1
“logic state” high side direct driving
L
L
H
L
L
H
Notes:
(1)
X: don’t care.
12/23
DocID024132 Rev 4
STGIPN3H60-H
Electrical characteristics
3.3
Waveform definitions
Figure 5: Dead time and interlocking waveform definitions
DocID024132 Rev 4
13/23
Smart shutdown
function
STGIPN3H60-H
4
Smart shutdown function
The STGIPN3H60-H integrates a comparator for fault sensing purposes. The comparator
has an internal voltage reference V
REF
connected to the inverting input, while the
noninverting input, available on pin (CIN), can be connected to an external shunt resistor in
order to implement a simple over-current protection function. When the comparator
triggers, the device is set in shutdown state and both its outputs are set to low-level leading
the halfbridge in tri-state. In the common overcurrent protection architectures the
comparator output is usually connected to the shutdown input through a RC network, in
order to provide a mono-stable circuit, which implements a protection time that follows the
fault condition. Our smart shutdown architecture allows to immediately turn-off the output
gate driver in case of overcurrent, the fault signal has a preferential path which directly
switches off the outputs. The time delay between the fault and the outputs turn-off is no
more dependent on the RC values of the external network connected to the shutdown pin.
At the same time the DMOS connected to the open-drain output is turned on by the internal
logic which holds it on until the shutdown voltage is lower than the logic input lower
threshold (V
il
). Finally, the smart shutdown function provides the possibility to increase the
real disable time without increasing the constant time of the external RC network.
14/23
DocID024132 Rev 4
STGIPN3H60-H
Smart shutdown
function
Figure 6: Smart shutdown timing waveforms
comp Vref
CP+
HIN/LIN
PROTECTION
HVG
/
L
V
G
SD/OD
open drain gate
(internal)
disable time
Fast shut down
:
the driver outputs are set in SD state immediately after the comparator
triggering even if the SD signal
has not yet reach the lower input threshold
An approximation of the disable time is given by:
SHUT DOWN CIRCUIT
V
BIAS
where:
R
SD
SD/OD
FROM/TO
CONTROLLER
SMART
SD
LOGIC
R
ON_OD
R
P
D_SD
C
SD
AM12947v1
specified)”
for internal propagation delay time details.
DocID024132 Rev 4
15/23
Application circuit
example
STGIPN3H60-H
5
Application circuit example
Figure 7: Application circuit example
AM09367v1
Application designers are free to use a different scheme according with the specifications
of the device.
16/23
DocID024132 Rev 4
STGIPN3H60-H
Application circuit
example
5.1
Guidelines
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull down resistor i
s built-
in for each input. If an external RC filter is used, for noise immunity, pay attention to
the variation of the input signal level.
To prevent input signal oscillation, the wiring of each input should be as short as
possible.
By integrating an application-specific type HVIC inside the module, direct coupling to
the MCU terminals without an opto-coupler is possible.
Each capacitor should be located as close as possible to the pins of the IPM.
Low inductance shunt resistors should be used for phase leg current sensing.
Electrolytic bus capacitors should be mounted as close to the module bus terminals as
possible. Additional high frequency ceramic capacitors mounted close to the module
pins will further improve performance.
The SD /OD
signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: “Smart shutdown function”
for detailed info).
These guidelines are useful for application design to ensure the specifications of the
device. For further details, please refer to the relevant application note AN4043.
Table 15: Recommended operating conditions
Symbol
V
PN
Parameter
Supply voltage
Test conditions
Min. Typ. Max. Unit
Applied between P-Nu, Nv, Nw
Applied between V
CC
-GND
300
15
500
18
V
V
V
CC
Control supply voltage
13.5
13
Applied between V
BOOTi
-OUT
i
for i = U, V, W
V
BS
t
dead
f
PWM
T
C
High side bias voltage
18
V
µs
Blanking time to prevent
Arm-short
For each input signal
1.5
-40°C < T
c
< 100 °C
-40°C < T
j
< 125 °C
PWM input signal
25
kHz
°C
Case operation
temperature
100
DocID024132 Rev 4
17/23
Package information
STGIPN3H60-H
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
18/23
DocID024132 Rev 4
STGIPN3H60-H
Package information
6.1
NDIP-26L type C package information
Figure 8: NDIP-26L type C package outline
8278949_7
DocID024132 Rev 4
19/23
Package information
STGIPN3H60-H
Table 16: NDIP-26L type C mechanical data
mm
Dim.
Min.
Typ.
Max.
4.40
1.20
3.20
1.90
6.10
0.72
0.68
1.02
0.98
0.59
0.55
29.25
1.00
0.70
29.55
12.55
1.90
2.60
16.70
21.78
1.54
A
A1
A2
A3
A4
b
0.80
3.00
1.70
5.70
0.53
0.52
0.83
0.82
0.46
0.45
29.05
0.50
0.35
1.00
3.10
1.80
5.90
b1
b2
b3
c
0.60
0.90
c1
D
0.50
29.15
0.77
D1
D2
D3
E
0.53
12.35
1.70
12.45
1.80
e
e1
eB1
eB2
L
2.40
2.50
16.10
21.18
1.24
16.40
21.48
1.39
20/23
DocID024132 Rev 4
STGIPN3H60-H
Package information
6.2
NDIP-26L packing information
Figure 9: NDIP-26L tube dimensions (dimensions are in mm)
Notes:
8313150_3
Table 17: Shipping details
Parameter
Base quantity
Bulk quantity
Value
17 pcs
476 pcs
DocID024132 Rev 4
21/23
Revision history
STGIPN3H60-H
7
Revision history
Table 18: Document revision history
Changes
Date
Revision
15-Jan-2013
1
Initial release.
Modified:
Figure 3 on page 8
,
Section 4 on page 14
and
Figure 6 on
page 15
.
02-May-2013
14-Mar-2014
2
3
Updated
Figure 3: Switching time test circuit, Table 9: Bootstrapped
voltage (VCC = 15 V unless otherwise specified)
and
Table 10: Logic
inputs (VCC = 15 V unless otherwise specified).
Updated
Section 6: Package mechanical data.
08-Sep-2016
4
Minor text changes
22/23
DocID024132 Rev 4
STGIPN3H60-H
IMPORTANT NOTICE
–
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DocID024132 Rev 4
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