STMicroelectronics-STH290N4F6-2AG
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UM1575
User manual
Spice model tutorial for Power MOSFE
T
s
Introduction
This document describes ST’s Spice model versions available for Power MOSFE
T
s
. This is
a guide designed to support user choosing the best model for his goals. In fact, it explains
the features of different model versions both in terms of static and dynamic characteristics
and simulation performance, in order to find the right compromise between the computation
time and accuracy. For example, the self-heating model (V3 version), which accurately
reproduces the thermal response of all electrical parameters, requires a considerable
simulation effort.
Finally, an example shows how the self-heating model works.
Spice models describe the characteristics of typical devices and don’t guarantee the
absolute representation of product specifications and operating characteristics; the
datasheet is the only document providing product specifications.
Although simulation is a very important tool to evaluate the device’s performance, the exact
device’s behavior in all situations is not predictable, therefore the final laboratory test is
necessary.
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Spice model versions
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1
Spice model versions
ST provides 6 model versions on each part number:
•
•
•
•
•
•
partnumber_V1C
partnumber_V1T
partnumber_V2
partnumber_V3
partnumber_V4
partnumber_TN
V1C version
It is the basic model (LEVEL =3) enclosing C
oss
and C
rss
modeling through capacitance
profile tables. It is an empirical model, and it assumes a 27 °C constant temperature.
V1T version
It comes directly from V1C version and it also includes the package thermal modeling
through a thermal equivalent network and presents two additional external thermal nodes T
j
and T
case
. This version hasn’t the dynamic link between Power MOSFET temperature and
internal parameters.
V2 version
It is more advanced than V1C, in fact it takes into account the temperature dependence and
capacitance profiles too. It allows the static and dynamic behavior to be reproduced by user
at fixed temperatures. By using this version, the simulation of self-heating effects isn’t
possible.
V3 version
It comes directly from V2 version and includes the package thermal model through a
thermal equivalent network and presents two additional external thermal nodes: T
j
and
T
case
. In this version, during each transient, the current power dissipation is calculated and a
current proportional to this power is fed into the thermal network. In this way, the voltage at
T
j
node contains all the information about the junction temperature, which changes internal
device’s parameters. Since it is a monitoring node, usually T
j
pin is not connected (however,
On contrary, T
case
node has to be connected, either to a constant voltage source
Vdc
representing the ambient temperature or to a heat sink modeled by its own thermal network
V4 version
It comes directly from V3 version considering the device sited in free air. It includes the
package thermal modeling through a thermal equivalent network and presents three
additional external thermal nodes: T
j
,
T
case
and T
amb
. The voltage at T
j
node and
T
case
node
contains all the information about the junction temperature and case temperature which
change internal device’s parameters. Since they are monitoring nodes, usually T
j
and T
case
pins are not connected (however, to avoid warning messages on this node, the user has to
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Spice model versions
TN version
It includes the RC thermal network only, which represents the thermal model of the package.
Its symbol has two pins: T
j
and T
case
.
Figure 1. Self-heating model (V3 version)
D
S
D
R1
R2
TJ
TJ
Zth
Zth
G
G
Tcase
Tamb
Tcase
Tamb
C1
C2
S
25
25
0
0
GIPD081020130954FSR
Note:
T
j
is a monitoring node and it is not connected; T
case
is connected either by using a Vdc,
representing the ambient temperature (on the left-side), or by heat-sink thermal network (on
the right-side).
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Spice model symbol
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2
Spice model symbol
For each model version, ST provides the appropriate symbol as shown below:
Figure 2. Model symbols
V1C version
V2 version
V4 version
D
TJ
Zth
G
Tcase
Tamb
S
V1T version
V3 version
TN version
D
TJ
TJ
1
2
Zth
TJ
TCASE
G
Tcase
Tcase
S
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Spice models – instructions to simulate
3
Spice models – instructions to simulate
In Spice simulator, user has to upload the device symbol (.OLB file) and the Spice model
(.LIB file) to simulate transistors in the schematic.
3.1
Installation
In the package model, there are the following files:
•
•
name.lib text file representing the model library written as a Spice code;
name.olb symbol file to use the model into Orcad capture user interface.
In Capture open the menu dialog window “Pspice” “Edit Simulation Profile”. Go to
“Configuration Files” tab and “Library” category. Select the library (*.lib) path by “Browse…”
Figure 3. Capture dialog window to select the library (*.lib)
GIPD081020131721FSR
To
i
nclude the symbol *.olb in the schematic view, open the menu dialog window “Place”
“Part” (or simply pressing “P” key in keyboard) and click the “Add Library…” button (or
pressing Alt+”A”) to select the file (see figure below).
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Spice models – instructions to simulate
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Figure 4. Capture dialog window to include the symbol (*.olb)
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Finally, you can simulate your circuit choosing the simulation type and parameters.
3.2
Typical simulation parameters / options
As our models contain many non-linear elements, the standard simulation parameters are
often not suitable.
The following values can facilitate convergence (set them in dialog window “Pspice”
“Edit
Simulation Profile”
“Options” tab):
ABSTOL= 1nA
(best accuracy of currents)
CHGTOL= 1 pC..10 pC
ITL1= 150
(best accuracy of charges)
(DC and bias ‘blind’ iteration limit)
(DC and bias ‘best guess’ iteration limit)
(transient time point iteration limit)
(relative accuracy of voltages and currents)
ITL2= 20…150
ITL4= 20…150
RELTOL= 0.001…0.01
Note:
If the following error message appears during the simulation of one of device models:
==> INTERNAL ERROR — Overflow in device….. <==
you have to edit the ‘PSPICE.INI’ file by inserting the following line behind the headline
[PSPICE] as follows:
[PSPICE]
MathExceptions = off
……
DO NOT CHANGE ANY OTHER LINES ALREADY PRESENT
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A brief description of self-heating model (V3 version)
4
A brief description of self-heating model (V3 version)
Power MOSFET’s Spice models are behavioral and achieved by fitting simulated data with
static and dynamic characterization results.
The behavioral model is the best approach because it reproduces the electrical and thermal
behavior of the power device through a simplified physical description of the device
consisting in a set of equations ruling its behavior at terminal level.
The self-heating model (V3 version) includes different analog behavioral models (ABM) to
describe resistors, voltage and current generator, which are temperature-dependent.
A curve fit optimization algorithm extracts the mathematical expression for ABM, which
yields a good representation of Power MOSFET’s static and dynamic characteristics.
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A brief description of self-heating model (V3 version)
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Figure 5. Power MOSFET self-heating model schematic
2
1
1
2
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A brief description of self-heating model (V3 version)
4.1
Thermal network
Thermal impedance network represents the basic element, which is featured inside the
macro-model. It is used to transform the power dissipated inside the junction into a voltage
representing the temperature (T
j
).
Figure 6. Physical structure
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The voltage drop across the network is detected and used as emitter value inside behavioral
equations used to model other parameters.
Thermal impedance is the experimental data required to obtain the Cauer model (see
Figure 6
).
Figure 7. Thermal impedance profile and Cauer model
.
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A brief description of self-heating model (V3 version)
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4.2
Experimental data used to fit the model
The model implementation requires the following experimental data:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Typ. output characteristics at different temperatures
Typ. transfer characteristics at different temperatures
Typ. drain source breakdown voltage at different temperatures
Typ. drain source on state resistance vs temperature
Typ. gate threshold voltage vs temperature
Typ. forward diode characteristics
Typ. capacitances profile vs VDS
Typ. gate charge
Typ. switching on resistive load
Typ. switching on inductive load
Typ. free-wheeling diode characteristics
Unclamped inductive switching
Switching losses vs gate resistance
Equivalent capacitance time related (C
o(tr)
)
Equivalent capacitance energy related (C
o(er)
)
Max. transient thermal impedance
Figure 8. Simulated and measured output
characteristics
Figure 9. Simulated curves at V
GS
= 10 V
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A brief description of self-heating model (V3 version)
Figure 10. Normalized R
DS(on)
vs temperature
Figure 11. Normalized gate threshold voltage vs
temperature
AM06484v1
AM06483v1
V
GS(th)
(norm)
R
DS(on)
(norm)
I
D
=2.5A
2.1
1.10
I
D
=250µA
1.9
1.00
0.90
1.7
1.5
1.3
1.1
0.9
0.80
0.70
0.7
0.5
-50
-50
-25
0
25 50 75
T
J
(°C)
-25
0
25 50
75
T
J
(°C)
100
100
4.3
C
and C
model
RSS
OSS
Charge and current formulas for a linear capacitor are:
dV
i
(
t
)
=
C
•
–
—-
–
–
dt
Q
=
C
•
V
For a non linear (voltage-dependent) time-independent capacitor these formulas become:
dV
Q
=
i
(
t
)
=
C
(
V
) •
–
—-
–
–
dt
C
(
V
)
dV
The C(V) function is obtained by lookup table.
Figure 12. Capacitance profiles
AM06481v1
C
(pF)
1000
100
Ciss
Coss
Crss
10
1
0.1
100
1
10
V
DS
(V)
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4.4
Example of dynamic characteristics
4.4.1
Gate charge
Figure 13. Gate charge – schematic
Rload1
Vdd1
Ipulse1
R127
0
0
0
0
GIPD251020131424FSR
Figure 14. Gate charge – simulated waveforms
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A brief description of self-heating model (V3 version)
Figure 15. Gate charge – experimental waveforms
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4.4.2
Switching on inductive load
Figure 16. Switching on inductive load – schematic
Iload1
Lpar1
R127
Vdd1
Rgate1
Vpulse1
L33
0
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Figure 17. Switching on inductive load – simulated waveforms
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Figure 18. Switching on inductive load – experimental waveforms
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A brief description of self-heating model (V3 version)
4.4.3
E
vs R
off gate
Figure 19. E
off
vs R
gate
– schematic
Iload1
Lpar1
R127
Vdd1
Rgate1
Vpulse1
L33
0
GIPD251020131432FSR
Figure 20. E
off
vs R
gate
– experimental waveforms
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Table 1. E
off
(comparison simulated/measured)
R
G
(
Ω
)
Measured E
off
(µJ)
Simulated E
off
(µJ)
4.7
10
4.1
4.31
6.8
27
3.9
4.4
7.1
29
47
200
4.4.4
Recovery diode
Figure 21. Recovery diode – schematic
Iload1
Lpar1
R127
Vdd1
Rgate1
Vpulse1
L33
0
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A brief description of self-heating model (V3 version)
Figure 22. Recovery diode – simulated waveforms
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4.4.5
Unclamped inductive switching
Table 2. Simulated test conditions
Test
T
C
Energy
I
drain
Δ
T
j
1
2
110 °C
110 °C
0.3 J
0.3 J
83 A
83 °C
203 A
133 °C
Figure 23. Unclamped inductive switching – schematic
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Figure 24. Unclamped inductive switching – simulated waveforms (test 1)
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A brief description of self-heating model (V3 version)
Figure 25. Unclamped inductive switching – simulated waveforms (test 2)
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Figure 26. Unclamped inductive switching – experimental waveforms
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4.4.6
Short-circuit test
Figure 27. Short-circuit test – schematic
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Figure 28. Short-circuit test – waveforms
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A brief description of self-heating model (V3 version)
4.4.7
Flyback simulated by self-heating model
Figure 29. Flyback simulated by self-heating model – schematic
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Figure 30. Flyback simulated by self-heating model – simulated waveforms
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where:
•
•
•
Blue line = (Tx current sec)/10
Black line = (Tx current Pri)
Red line = MOSFET drain current
If you have further questions, feel free to contact us via our local sale offices.
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Revision history
5
Revision history
Table 3. Document revision history
Changes
Date
Revision
25-Nov-2013
1
Initial release.
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