STMicroelectronics-STIPNS1M50T-H
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STIPNS1M50T-H
Datasheet
SLLIMM-nano IPM, 3-phase inverter, 1 A, 3.6 Ω max., 500 V MOSFET
16
Features
•
IPM 1 A, 500
V
,
R
DS(on)
= 3.6 Ω, 3-phase MOSFET inverter bridge including
control ICs for gate driving
17
•
•
Optimized for low electromagnetic interference
1
3.3
V
, 5 V,
1
5 V CMOS/TTL input comparators with hysteresis and pull-down/
pull-up resistors
26
•
•
•
•
•
•
•
•
•
Undervoltage lockout
Internal bootstrap diode
Interlocking function
Shutdown function
Comparator for fault protection against overcurrent
Op-amp for advanced current sensing
Optimized pinout for easy board layout
NTC for temperature control (UL 1434 CA 2 and 4)
Moisture sensitive level (MSL) 3 for SMD package
NSDIP-26L
Applications
•
•
3-phase inverters for small power motor drives
Roller shutters, dishwashers, refrigerator fans, air-conditioning fans, draining
and recirculation pumps
Description
This SLLIMM (small low-loss intelligent molded module) nano provides a compact,
high-performance AC motor drive in a simple, rugged design. It is composed of six
MOSFE
T
s
a
nd three half-bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics with optimized switching speed.
The package is optimized for thermal performance and compactness in built-in motor
applications, or other low power applications where assembly space is limited. This
IPM includes an operational amplifier, completely uncommitted, and a comparator
that can be used to design a fast and efficient protection circuit. SLLIMM is a
trademark of STMicroelectronics.
Product status link
Product summary
Order code
Marking
STIPNS1M50T-H
IPNS1M50T-H
NSDIP-26L
Package
Packing
T
a
pe and reel
DS12106
–
Rev 3
–
August 2019
For further information contact your local STMicroelectronics sales office.
STIPNS1M50T-H
Internal schematic diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1.
Internal schematic diagram
GND(
1
)
(26)N W
NTC
T/SD/OD (2)
(25)W,OUT W
GND
VccW(3 )
HinW(4 )
LinW(5 )
OP+(
6
)
HVG
(24)Vboot W
OUT
VCC
HIN
LVG
SD/OD
LIN
Vboot
(23)N V
OPOUT(7 )
OP-(
8
)
GND
OP+
OPOUT
OP-
(22)
V
,
OUT V
HVG
OUT
LVG
VCC
HIN
VccV(9 )
HinV(10)
LinV(11 )
Cin(12)
SD/OD
LIN
Vboot
(21)Vboot V
(20)N U
GND
CIN
HVG
OUT
LVG
VccU(13 )
HinU(14)
(19)U,OUT U
(18) P
VCC
HIN
SD/OD
LIN
Vboot
T/SD/OD(15)
LinU(16 )
(17)Vboot U
GIPD120120170806SA
DS12106
–
Rev 3
page 2/23
STIPNS1M50T-H
Internal schematic diagram and pin configuration
Table 1.
Pin description
Pin
1
Symbol
Description
GND
Ground
2
T/SD/OD NTC
thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)
V
W
3
Low voltage power supply W phase
High-side logic input for W phase
Low-side logic input for W phase
Op-amp non inverting input
Op-amp output
CC
4
HIN W
LIN W
OP+
5
6
OP
7
OUT
8
OP-
Op-amp inverting input
V
V
9
Low voltage power supply V phase
High-side logic input for V phase
Low-side logic input for V phase
Comparator input
CC
10
11
12
13
14
15
16
17
18
19
HIN V
LIN V
CIN
V
U
Low voltage power supply for U phase
High-side logic input for U phase
CC
HIN U
T/SD/OD NTC
thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)
LIN U
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
V
U
BOOT
P
U, OUT
U phase output
U
N
20
21
22
23
24
25
26
Negative DC input for U phase
Bootstrap voltage for V phase
V phase output
U
V
V
BOOT
V,
O
UT
V
N
Negative DC input for V phase
Bootstrap voltage for W phase
W phase output
V
V
W
BOOT
W, OUT
W
N
W
Negative DC input for W phase
DS12106
–
Rev 3
page 3/23
STIPNS1M50T-H
Internal schematic diagram and pin configuration
Figure 2.
Pin layout (top view)
(*)
(*)
PIN #1 ID
(*) Dummy pin internally connected to P (positive DC input).
DS12106
–
Rev 3
page 4/23
STIPNS1M50T-H
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Table 2.
Inverter part
Symbol
Parameter
Value
Unit
MOSFET blocking voltage (or drain-source voltage) for each
V
DSS
500
V
IN
± I
Continuous current each MOSFET (T
= 25 °C)
1
2
A
A
D
C
± I
DP
Peak drain current each MOSFET (less than 1 ms)
P
T
o
tal power dissipation for each MOSFET (T
= 25 °C)
10
W
TOT
C
1. Applied
among HINi, LINi and GND for i = U, V, W.
2. Pulse
width limited by max. junction temperature.
Table 3.
Control part
Symbol
Parameter
Min.
– 21
Max.
V +
0.3
boot
Unit
V
V
Output voltage applied among OUT
, OUT
, OUT
– GND
V
OUT
U
V
W
boot
V
Low voltage power supply
Comparator input voltage
Op-amp non-inverting input
Op-amp inverting input
Bootstrap voltage
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
21
+ 0.3
V
CC
V
V
V
CIN
CC
CC
CC
V
V
V
+ 0.3
+ 0.3
V
op+
V
V
op-
V
620
V
boot
V
Logic input voltage applied among HIN, LIN and GND
Open-drain voltage
15
15
50
V
IN
V
V
T/SD/OD
dV
/dt
Allowed output slew rate
V/ns
OUT
Table 4.
Total system
Parameter
Symbol
Value
Unit
Isolation withstand voltage applied between each pin and heat sink
plate (AC voltage, t = 60 s)
V
V
rms
1000
ISO
T
Power chip operating junction temperature range
Module case operation temperature range
-40 to 150
-40 to 125
°C
°C
J
T
C
DS12106
–
Rev 3
page 5/23
STIPNS1M50T-H
Thermal data
2.2
Thermal data
Table 5.
Thermal data
Symbol
Parameter
Value
12.5
24
Unit
°C/W
°C/W
R
Thermal resistance junction-case single MOSFET
Thermal resistance junction-ambient (per module)
th(j-c)
th(j-a)
R
DS12106
–
Rev 3
page 6/23
STIPNS1M50T-H
Electrical characteristics
3
Electrical characteristics
T
J
= 25 °C unless otherwise specified.
3.1
Inverter part
Table 6.
Static
Symbol
Parameter
Test conditions
= 500
V
, V
=
1
5
V
, V
=
1
5 V
Boot
Min.
Typ. Max. Unit
Zero-gate voltage drain
current
I
V
V
1
mA
V
DSS
DS
CC
= V
IN
CC
boot
Drain-source breakdown
voltage
V
500
(BR)DSS
I
= 1 mA
= V
D
V
CC
IN
boot
Static drain-source turn-on
resistance
R
DS(on)
3.2
0.9
3.6
1.6
Ω
V
I
= 0.5 A
D
Drain-source diode forward
voltage
V
SD
V
D
IN
1. Applied
among HINx, LINx and GND for x=U,V,W.
Table 7.
Inductive load switching time and energy
Symbol
Parameter
Turn-on time
Test conditions
Min.
Typ. Max. Unit
t
–
–
–
–
–
–
–
226
130
248
56
–
–
–
–
–
–
–
on
t
Crossover time (on)
Turn-off time
c(on)
V
V
V
= 300
V
,
DD
t
ns
= V
= 15
V
,
off
CC
boot
t
Crossover time (off)
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
IN
c(off)
I
= 0.5 A
D
t
155
25
rr
E
on
µJ
E
3.8
off
1.
t
and t
include the propagation delay time of the internal drive. t
and t
are the switching time of MOSFET
C(OFF)
ON
OFF
C(ON)
itself under the internally given gate driving conditions.
2. Applied
among HINx, LINx and GND for x=U,V,W.
DS12106
–
Rev 3
page 7/23
STIPNS1M50T-H
Inverter part
Figure 3.
Switching time test circuit
GIPD161120151702RV
Figure 4.
Switching time definition
100% I
D
100%
I
D
t
rr
V
DS
I
D
I
D
V
DS
V
IN
V
IN
t
ON
t
OFF
t
C(OFF)
t
C(ON)
10%
V
DS
10%
I
D
V
IN(ON)
V
IN(OFF)
10% I
D
90%
I
D
10%
V
DS
(a) turn-on
(b) turn-off
AM09223V2
Figure 4. Switching time definition
refers to HIN, LIN inputs (active high).
DS12106
–
Rev 3
page 8/23
STIPNS1M50T-H
Control part
3.2
Control part
(V
CC
= 15 V unless otherwise specified).
Table 8.
Low voltage power supply
Symbol
Parameter
UV hysteresis
Test conditions
Min.
Typ. Max. Unit
V
V
CC
V
CC
V
CC
1.2
11.5
10
1.5
12
1.8
12.5
11
V
V
V
CC_hys
V
UV turn ON threshold
UV turn OFF threshold
CC_thON
V
10.5
CC_thOFF
V
= 15 V, T/SD/OD = 5 V, LIN = 0 V,
Undervoltage quiescent supply
current
CC
I
150
1
µA
mA
V
qccu
HIN = 0
V
,
C
IN = 0 V
V
= 15 V, T/SD/OD = 5 V, LIN = 0 V,
CC
I
Quiescent current
qcc
HIN = 0
V
,
C
IN = 0 V
Internal comparator (CIN)
reference voltage
V
0.5
0.54
0.58
ref
Table 9.
Bootstrapped voltage
Test conditions
Symbol
Parameter
UV hysteresis
Min.
1.2
Typ. Max. Unit
V
V
BS
V
BS
V
BS
1.5
11.5
10
1.8
V
V
V
BS_hys
V
UV turn-ON threshold
UV turn-OFF threshold
11.1
9.8
12.1
10.6
BS_thON
V
BS_thOFF
V
< 9
V
,
T
/SD/OD = 5
V
,
BS
Undervoltage V
quiescent
current
BS
I
70
110
300
µA
QBSU
LIN = 0 V and HIN = 5
V
,
C
IN = 0 V
= 15
V
,
T
/SD/OD = 5
V
,
V
BS
I
V
quiescent current
BS
200
120
µA
Ω
QBS
LIN = 0 V and HIN = 5
V
,
C
IN = 0 V
LVG ON
R
Bootstrap driver on-resistance
DS(on)
Table 10.
Logic inputs
Test conditions
Symbol
Parameter
Min.
Typ. Max. Unit
V
Low logic level voltage
0.8
V
il
V
High logic level voltage
2.25
20
V
ih
I
HIN logic “1” input bias current
HIN logic “0” input bias current
LIN logic “1” input bias current
LIN logic “0” input bias current
SD logic “0” input bias current
SD logic “1” input bias current
HIN = 15 V
HIN = 0 V
LIN = 15 V
LIN = 0 V
SD = 15 V
SD = 0 V
40
40
100
1
µA
µA
µA
µA
µA
µA
HINh
I
HINI
I
20
100
1
LINh
I
LINI
I
200
350
500
3
SDh
I
SDI
Dt
Dead time
180
ns
DS12106
–
Rev 3
page 9/23
STIPNS1M50T-H
Control part
Table 11.
Op-amp characteristics
Test conditions
Symbol
Parameter
Input offset voltage
Min.
Typ. Max. Unit
V
V
ic
= 0
V
, V
= 7.5 V
o
6
mV
nA
io
I
Input offset current
4
100
75
40
io
V
= 0
V
, V
= 7.5 V
ic
o
Low level output voltage
High level output voltage
I
200
150
nA
ib
V
R =
10 kΩ to V
L CC
mV
V
OL
V
OH
R =
10 kΩ to GND
L
14
16
50
2.5
8
14.7
30
Source, V
= +1
V
, V
= 0 V
mA
mA
V/µs
MHz
dB
id
o
I
Output short-circuit current
o
Sink, V
= -1
V
, V
= V
CC
80
id
o
V =
1 – 4
V
, C
=
1
00 p
F
,
u
nity gain
SR
Slew rate
3.8
12
i
L
V =
7.5 V
GBWP
Gain bandwidth product
Large signal voltage gain
Supply voltage rejection ratio
Common mode rejection ratio
o
A
R =
2 kΩ
L
70
60
55
85
vd
vs. V
SVR
75
dB
CC
CMRR
70
dB
1. The
direction of input current is out of the IC.
Table 12.
Sense comparator characteristics
Symbol
Parameter
Test conditions
Min.
Typ. Max. Unit
I
V
= 1 V
CIN
Input bias current
1
µA
V
ib
Open-drain low level output
voltage
V
I
= 3 mA
= 3 mA
0.5
od
od
Open-drain low level output
resistance
R
I
od
166
125
90
Ω
kΩ
ON_OD
Comparator delay
Slew rate
R
PD_SD
T/SD/OD pulled to 5 V through 100 kΩ
resistor
t
130
ns
d_comp
C =
180 p
F
, R
= 5
k
Ω
SR
60
V/µs
L
pu
Shutdown to high- / low-side
driver propagation delay
t
V
= 0
V
, V
= V
, V
= 0 to 3.3 V
50
50
125
200
250
sd
OUT
boot CC
IN
ns
Comparator triggering to high- /
low-side driver turn-off
propagation delay
Measured applying a voltage step from
0 V to 3.3 V to pin CIN
t
200
isd
1. Equivalent
values as a result of the resistances of three drivers in parallel.
DS12106
–
Rev 3
page 10/23
STIPNS1M50T-H
Control part
Table 13.
Truth table
Logic input (V )
Output
I
Condition
T/SD/OD
LIN
HIN
H
LVG
L
HVG
H
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
L
L
L
L
L
H
H
H
H
H
L
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
L
L
L
H
L
H
L
H
L
1. X:
don’t care.
3.2.1
NTC thermistor
Figure 5.
Internal structure of SD and NTC
Vbias
R SD
LIN
Vboot
V
T/SD/OD
SD/OD
HIN
HVG
OUT
LVG
CIN
C SD
NTC
VCC
RPD_SD
GND
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
DS12106
–
Rev 3
page 11/23
STIPNS1M50T-H
Control part
Figure 6.
Equivalent resistance (NTC//R
PD_SD
)
140
120
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 7.
Equivalent resistance (NTC//R
PD_SD
) zoom
14
12
10
8
6
4
2
0
70
80
90
100
110
120
Temperature (°C)
DS12106
–
Rev 3
page 12/23
STIPNS1M50T-H
Control part
Figure 8.
Voltage of T/SD/OD pin according to NTC temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
SD/OD: high
V
Bias
= 5 V
R
SD
= 2.2 kΩ
V
Bias
= 3.3 V
R
SD
= 1.0 kΩ
25
50
75
100
125
Temperature (°C)
DS12106
–
Rev 3
page 13/23
STIPNS1M50T-H
Waveform definitions
3.3
Waveform definitions
Figure 9.
Dead time and interlocking waveform definitions
DS12106
–
Rev 3
page 14/23
STIPNS1M50T-H
Shutdown function
4
Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.
The comparator has an internal voltage reference V
REF
connected to the inverting input, while the non-inverting
input pin (CIN) can be connected to an external shunt resistor for current monitoring.
Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs,
whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which
fixes the disabling time.
For an effective design of the shutdown circuit, please refer to Application note AN4966.
Figure 10.
Shutdown timing waveforms
GADG250120171515FSR
V
REF
CI N
HIN or LIN
U
V, W
PROTECT ION
HVG
o
r L
V
G
SD/OD
or
T/SD/OD
A
B
open -drain gate
(internal)
A
B
∗
∗
∗
∗
≅
∗
∗
_
R
SD
and C
SD
external circuitry must be designed to ensure
Please refer to AN4966 for further details.
* R
NTC
to be considered only when the NTC is internally connected to the T/SD/OD pin.
DS12106
–
Rev 3
page 15/23
STIPNS1M50T-H
Application circuit example
5
Application circuit example
Figure 11.
Application circuit example
MICROCONTROLLE R
GADG100620160912FSR
Application designers are free to use a different scheme according to the specifications of the device.
DS12106
–
Rev 3
page 16/23
STIPNS1M50T-H
Guidelines
5.1
Guidelines
•
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input.
T
o
avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC
filters (R
1
, C
1
) on each input signal is suggested. The filters should be with a time constant of about 100 ns
and placed as close as possible to the IPM input pins.
•
The use of a bypass capacitor C
VCC
(aluminum or tantalum) can reduce the transient circuit demand on the
power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a
decoupling capacitor C
2
(100 to 220 n
F
,
w
ith low ESR and low ESL) should be placed as close as possible
to the V
cc
pin and in parallel with the bypass capacitor.
•
•
The use of an RC filter (R
SF
, C
SF
) is recommended to prevent protection circuit malfunction. The time
constant (R
SF
x C
SF
) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.
The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally
connected between the SD pin and GND. The voltage V
SD
-GND decreases as the temperature increases,
due to the pull-up resistor R
SD
. In order to keep the voltage always higher than the high-level logic threshold,
the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The
capacitor C
SD
of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation
time τ
A
≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
•
The decoupling capacitor C
3
(from 100 to 220 n
F
,
c
eramic with low ESR and low ESL), in parallel with each
C
boot
, filters high-frequency disturbance. Both C
boot
and C
3
(if present) should be placed as close as
possible to the U,
V
, W and V
boot
pins. Bootstrap negative electrodes should be connected to U,
V
, W
terminals directly and separated from the main output wires.
•
•
To
a
void overvoltage on the V
cc
pin, a Zener diode (Dz1) can be used. Similarly on the V
boot
pin, a Zener
diode (Dz2) can be placed in parallel with each C
boot
.
The use of the decoupling capacitor C
4
(100 to 220 n
F
,
w
ith low ESR and low ESL) in parallel with the
electrolytic capacitor C
vdc
is useful to prevent surge destruction. Both capacitors C
4
and C
vdc
should be
placed as close as possible to the IPM (C
4
has priority over C
vdc
).
•
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals
without an opto-couplers is possible.
•
•
Low-inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and P
WR_GND
should be as short as
possible.
•
The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can
reduce the impact of power ground fluctuation.
These guidelines ensure the specifications of the device for application designs. For further details, please refer to
the relevant application note.
Table 14.
Recommended operating conditions
Symbol
Parameter
Supply voltage
Test conditions
Min.
Typ. Max. Unit
V
Applied among P-Nu, Nv, Nw
300
15
400
18
V
V
PN
V
Applied to V
-GND
Control supply voltage
13.5
13
1
CC
CC
V
Applied to V
-OUT for
i = U,
V
, W
BOOTi i
High-side bias voltage
18
V
BS
t
Blanking time to prevent arm-short
For each input signal
-40 °C < T
< 100 °C
µs
dead
C
f
PWM input signal
25
kHz
°C
PWM
-40 °C < T
< 125 °C
J
T
C
Case operation temperature
100
DS12106
–
Rev 3
page 17/23
STIPNS1M50T-H
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
6.1
NSDIP-26L package information
Figure 12.
NSDIP-26L package outline
8374968_4
DS12106
–
Rev 3
page 18/23
STIPNS1M50T-H
NSDIP-26L package information
Table 15.
NSDIP-26L package mechanical data
mm
Dim.
Min.
Typ.
Max.
3.45
0.25
3.20
1.50
0.57
0.55
0.67
0.57
0.55
29.25
A
A1
A2
A3
b
0.10
3.00
1.10
0.47
0.45
0.63
0.47
0.45
29.05
0.70
0.45
0.90
3.10
1.30
b1
b2
c
0.50
c1
D
0.50
29.15
D1
D2
D3
D4
E
29.65
12.55
17.30
12.35
16.70
0.35
1.70
2.40
1.24
1.00
12.45
17.00
E1
E2
e
1.80
2.50
1.90
2.60
1.54
1.30
e1
L
1.39
L1
L2
L3
R1
R2
S
1.15
0.25 BSC
2.275 REF
0.40
0.25
0.25
0.55
0.55
0.55
8°
0.40
0.39
ϴ
0°
ϴ1
ϴ2
3° BSC
12°
10°
14°
DS12106
–
Rev 3
page 19/23
STIPNS1M50T-H
NSDIP-26L package information
Figure 13.
NSDIP-26L recommended footprint (dimensions are in mm)
8374968_4_fp
DS12106
–
Rev 3
page 20/23
STIPNS1M50T-H
Revision history
Table 16.
Document revision history
Changes
Date
Revision
13-Apr-2017
1
Initial release.
Datasheet status promoted from preliminary to production data.
Updated
features
on cover page.
08-Jan-2018
2
Updated
T
a
ble 3: “Inverter part”
,
T
a
ble 5: “
T
o
tal system”
,
T
a
ble 6: “Thermal data”
and
T
a
ble
13: “Sense comparator characteristics”
.
Updated
Section 6.1: “NSDIP-26L package information”
.
Removed maturity status indication from cover page.
19-Aug-2019
3
Minor text changes.
DS12106
–
Rev 3
page 21/23
STIPNS1M50T-H
Contents
Contents
Internal schematic diagram and pin configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
5
Absolute maximum ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Thermal data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
7
Inverter part
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Control part
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
NTC thermistor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Waveform definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
14
Shutdown function
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Application circuit example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Guidelines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
17
Package information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
NSDIP-26L package informatio
n
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
18
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
DS12106
–
Rev 3
page 22/23
STIPNS1M50T-H
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of S
T
.
F
or additional information about ST trademarks, please refer to
www.st.com/trademarks
. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12106
–
Rev 3
page 23/23
