STMicroelectronics-STL105N8F7AG
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STL105N8F7AG
Datasheet
Automotive N-channel 80
V
,
5
.6 mΩ typ., 95 A, STripFET F7
Power MOSFET in a PowerFLAT 5×6 package
Features
V
R
DS(on)
max.
I
D
Order code
DS
STL105N8F7AG
80 V
6.5 mΩ
95 A
4
3
2
•
•
•
•
•
•
AEC-Q101 qualified
1
Among the lowest R
DS(on)
on the market
Excellent FoM (figure of merit)
Low C
rss
/C
iss
ratio for EMI immunity
High avalanche ruggedness
PowerFLAT 5×6
D(5, 6, 7, 8)
8
7
6
5
Wettable flank package
G(4)
Applications
•
Switching applications
1
2
3
4
T
o
p View
Description
S(1, 2, 3)
AM15540v2
This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced
trench gate structure that results in very low on-state resistance, while also reducing
internal capacitance and gate charge for faster and more efficient switching.
Product status link
Product summary
Order code
STL105N8F7AG
Marking
Package
Packing
105N8F7
PowerFLAT 5×6
T
a
pe and reel
DS13615
–
Rev 2
–
March 2021
For further information contact your local STMicroelectronics sales office.
STL105N8F7AG
Electrical ratings
1
Electrical ratings
Table 1.
Absolute maximum ratings
Parameter
Symbol
Value
80
Unit
V
V
Drain-source voltage
Gate-source voltage
DS
GS
V
±20
95
V
Drain current (continuous) at T
= 25 °C
C
I
A
D
Drain current (continuous) at T
= 100 °C
68
C
I
Drain current (pulsed)
380
127
A
DM
P
T
o
tal power dissipation at T
= 25 °C
W
TOT
C
Avalanche current, repetitive or not repetitive
I
AV
40
A
(pulse width limited by maximum junction temperature)
Single pulse avalanche energy
E
135
mJ
AS
(T =
25 °C, I
= I
, V
= 60
V
, R
m
in = 47 Ω)
J
D
AV
DD
G
T
Operating junction temperature range
Storage temperature range
°C
°C
J
-55 to 175
T
stg
1. Pulse
width limited by safe operating area.
Table 2.
Thermal data
Parameter
Symbol
Value
1.18
Unit
°C/W
°C/W
R
thJC
Thermal resistance, junction-to-case
Thermal resistance, junction-to-board
1. When
mounted on an FR-4 board of 1 inch², 2oz Cu, t < 10s.
R
31.3
thJB
DS13615
–
Rev 2
page 2/14
STL105N8F7AG
Electrical characteristics
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 3.
On/off states
Symbol
Parameter
Test conditions
Min.
Typ. Max. Unit
V
I =
250 μA, V
= 0 V
D GS
Drain-source breakdown voltage
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
80
V
(BR)DSS
I
V
GS
V
GS
V
DS
V
GS
= 0
V
, V
=
8
0 V
1
µA
nA
V
DSS
DS
I
= 20
V
, V
= 0 V
100
4.5
6.5
GSS
DS
V
= V
, I
= 250 μA
2.5
GS(th)
DS(on)
GS
D
R
= 10 V, I
= 25 A
D
Static drain-source on-resistance
5.6
mΩ
Table 4.
Dynamic
Symbol
Parameter
Input capacitance
Test conditions
Min.
Typ.
Max.
Unit
pF
C
iss
–
–
–
–
–
3475
904
88
–
–
–
–
–
C
oss
V
= 25 V, f = 1 MHz, V
= 0 V
Output capacitance
Reverse transfer capacitance
T
o
tal gate charge
pF
DS
GS
C
pF
rss
Q
V
V
= 40
V
, I
=
9
5 A,
46
nC
nC
g
DD
D
= 0 to 10 V
Q
GS
Gate-source charge
24
gs
Q
Gate-drain charge
–
10
–
nC
gd
Table 5.
Switching times
Test conditions
Symbol
Parameter
Turn-on delay time
Rise time
Min.
Typ.
19
Max.
Unit
ns
t
V
= 40
V
, I
=
5
0 A,
–
–
–
–
–
–
d(on)
DD
D
R
G
= 4.7 Ω, V
= 10 V
t
r
GS
22
ns
t
Turn-off delay time
31
ns
d(off)
t
Fall time
–
13
–
ns
f
Table 6.
Source-drain diode
Test conditions
Symbol
Parameter
Source-drain current
Source-drain voltage
Reverse recovery time
Reverse recovery charge
Min.
Typ.
Max.
95
Unit
A
I
SD
V
I
I
= 95 A, V
= 0 V
–
–
–
1.2
V
SD
GS
SD
t
= 50 A, di/dt = 100 A/µs,
= 64 V
37
37
ns
nC
rr
SD
V
DD
Q
rr
I
Reverse recovery current
–
1.5
A
RRM
1. Pulsed:
pulse duration = 300 µs, duty cycle 1.5%.
DS13615
–
Rev 2
page 3/14
STL105N8F7AG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Maximum transient thermal impedance
GADG211220201122SOA
Operation in this area
is limited by R
DS(on)
GADG211220201122ZTH
I
D
(A)
K
δ = 0.5
10
2
10
1
10
0
0.2
t
p
=10 µs
0.1
t
p
=100 µs
t
p
=1 ms
10
-1
0.02 0.05
0.01
10
-1
10
-2
Single pulse
t
p
=10 ms
T
J
≤
175 °C
T
C
= 25°C
Single pulse
10
-2
10
-1
10
0
10
1
10
-5
10
-4
10
-3
10
-2
10
-1
V
DS
(V)
t
p
(s)
Figure 3.
Typical output characteristics
Figure 4.
Typical transfer characteristics
GADG211220201123OCH
GADG211220201124TCH
I
D
I
D
(A)
(A)
V
GS
= 8, 9, 10 V
160
140
120
100
80
100
80
V
DS
= 6 V
7 V
60
T
J
= 175 °C
60
40
6 V
5 V
T
J
= 25 °C
40
20
0
T
J
= -55 °C
20
0
0
1
2
3
4
5
6
7
8
9
V
DS
(V)
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 V
GS
(V)
Figure 5.
Typical gate charge characteristics
Figure 6.
Typical drain-source on-resistance
GADG040120210949QVG
GADG040120210950RID
V
GS
R
DS(on)
(V)
(mΩ)
6.6
12
6.4
6.2
6.0
5.8
5.6
5.4
V
DS
= 40 V
I
D
= 95 A
10
8
6
4
V
GS
= 10 V
2
0
5.2
5.0
0
10
20
30
40
50
Q
g
(nC)
0
10 20 30 40 50 60 70 80 90 I
D
(A)
DS13615
–
Rev 2
page 4/14
STL105N8F7AG
Electrical characteristics (curves)
Figure 8.
Normalized gate threshold voltage vs
temperature
Figure 7.
Typical capacitance characteristics
GADG211220201127CVR
C
(pF)
GADG211220201139VTH
V
GS(th)
(norm.)
C
iss
1.15
1.05
I
D
= 250 µA
10
3
0.95
0.85
0.75
0.65
C
oss
f = 1 MHz
10
2
C
rss
0.55
0.45
10
1
10
-1
10
0
10
1
V
DS
(V)
-75
-25
25
75
125 175
T
J
(°C)
Figure 10.
Normalized V
(BR)DSS
vs temperature
Figure 9.
Normalized on-resistance vs temperature
GADG211220201145RON
R
DS(on)
(norm.)
GADG211220201145BDV
V
(BR)DSS
(norm.)
2.1
1.06
1.04
1.02
1.00
0.98
0.96
1.9
I
D
= 250 µA
V
GS
= 10 V
I
D
= 25 A
1.7
1.5
1.3
1.1
0.9
0.7
0.94
0.92
0.5
0.3
-75
-25
25
75
125 175
T
J
(°C)
-75
-25
25
75
125 175
T
J
(°C)
Figure 11.
Typical reverse diode forward characteristics
GADG211220201146SDF
V
SD
(V)
1.1
1.0
T
J
= -55 °C
T
J
= 25 °C
0.9
0.8
T
J
= 175 °C
0.7
0.6
0.5
0.4
10 20 30 40 50 60 70 80 I
SD
(A)
DS13615
–
Rev 2
page 5/14
STL105N8F7AG
Test circuits
3
Test circuits
Figure 12.
Test circuit for resistive load switching times
Figure 13.
Test circuit for gate charge behavior
V
DD
12 V
47 kΩ
1 kΩ
100 nF
R
L
2200
μF
3.3
μF
V
DD
+
I
G
= CONST
2.7 kΩ
V
D
R
G
D.U.
T
.
100 Ω
V
GS
pulse width
+
D.U.
T
.
V
GS
V
G
2200
μF
pulse width
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 14.
Test circuit for inductive load switching and
diode recovery times
Figure 15.
Unclamped inductive load test circuit
L
A
A
A
D
S
V
D
100 µH
D
fast
G
D.U.
T
.
B
diode
2200
3.3
µF
+
V
DD
1000
µF
B
µF
3.3
µF
B
+
V
DD
25 Ω
I
D
G
D.U.
T
.
R
G
S
+
_
D.U.
T
.
V
i
pulse width
AM01471v1
AM01470v1
Figure 17.
Switching time waveform
Figure 16.
Unclamped inductive waveform
t
on
t
d(on)
t
off
t
d(off)
V
(BR)DSS
t
r
t
f
V
D
90%
90%
I
DM
V
DS
10%
V
GS
10%
I
D
0
0
V
DD
V
DD
90%
10%
AM01472v1
AM01473v1
DS13615
–
Rev 2
page 6/14
STL105N8F7AG
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
4.1
PowerFLAT 5×6 WF type C package information
Figure 18.
PowerFLAT 5×6 WF type C package outline
8231817_WF_typeC_r20
DS13615
–
Rev 2
page 7/14
STL105N8F7AG
PowerFLAT 5×6 WF type C package information
Table 7.
PowerFLAT 5×6 WF type C mechanical data
mm
Dim.
Min.
0.80
0.00
Typ.
Max.
1.00
0.05
A
A1
A2
b
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
C
6.00
5.20
D
D2
D3
D4
D5
D6
e
4.20
5.00
0.40
0.30
1.27
6.40
E
6.20
3.50
2.35
0.40
0.08
0.20
0.85
4.00
3.55
1.05
0.90
0.175
0°
6.60
3.70
2.55
0.60
0.28
0.45
1.15
4.40
3.85
1.35
1.10
0.375
12°
E2
E3
E4
E5
E6
E7
E9
E10
K
0.325
1.00
4.20
3.70
L
1.00
L1
θ
0.275
DS13615
–
Rev 2
page 8/14
STL105N8F7AG
PowerFLAT 5×6 WF type C package information
Figure 19.
PowerFLAT 5×6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_rev20
DS13615
–
Rev 2
page 9/14
STL105N8F7AG
PowerFLAT 5×6 WF packing information
4.2
PowerFLAT 5×6 WF packing information
Figure 20.
PowerFLAT 5×6 WF tape (dimensions are in mm)
P2
Po
Do
1.50
0.0
E1
1.75
0.1
T
2.0
0.05(I)
4.0
0.1(II)
+
0.1
0.30 0.05
Y
D1
1.50
MIN
R0.30
MAX
Y
A
o
(6.70±0.1)
Ko (1.20±0.1)
P1(8.00±0.1)
SECTION
Y
–
Y
(I)
Measured from centreline of sprocket hole
to centreline of pocket.
(II)
(III)
Cumulative tolerance of 10 sprocket
holes is ± 0.20 .
Base and bulk qua ntity 3000 pcs
Measured from centreline of sprocket
hole to centreline of pocket.
8234350
_
T
a
peWF_rev_C
Figure 21.
PowerFLAT 5×6 package orientation in carrier tape
Pin 1
identification
DS13615
–
Rev 2
page 10/14
STL105N8F7AG
PowerFLAT 5×6 WF packing information
Figure 22.
PowerFLAT 5×6 reel (dimensions are in mm)
R0.60
W3
11.9/15.4
PART NO.
1.90
2.50
W2
18.4 (max)
R25.00
ØN
178(±2.0)
A
330 (+0/-4.0)
∅
4.00
∅
2.50
ESD LOGO
W1
12.4 (+2/-0)
ØA
R1.10
Ø21.2
All dimensions are in millimeters
∅
13.00
8234350_Reel_rev_C
CORE DETAIL
DS13615
–
Rev 2
page 11/14
STL105N8F7AG
Contents
Contents
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
6
Package information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
7
PowerFLAT 5×6 WF type C package information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
PowerFLAT 5×6 WF packing informatio
n
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
10
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
DS13615
–
Rev 2
page 13/14
STL105N8F7AG
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T
.
F
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DS13615
–
Rev 2
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