STMicroelectronics-STL110N10F7
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STL110N10F7
N-channel 100
V
, 5
m
Ω typ., 107 A, STripFET F7 Power MOSFET
in a PowerFLAT 5×6 package
Features
V
R
DS(on)
max.
I
D
P
TOT
Order code
DS
STL110N10F7
100 V
6 mΩ
107 A
136 W
•
•
•
•
Among the lowest R
DS(on)
on the market
Excellent FoM (figure of merit)
Low C
rss
/C
iss
ratio for EMI immunity
High avalanche ruggedness
PowerFLAT 5×6
D(5, 6, 7, 8)
8
7
6
5
Applications
•
Switching applications
G(4)
Description
This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced
trench gate structure that results in very low on-state resistance, while also reducing
internal capacitance and gate charge for faster and more efficient switching.
1
2
3
4
T
o
p View
S(1, 2, 3)
AM15540v2
Product status link
Product summary
Order code
STL110N10F7
Marking
Package
Packing
110N10F7
PowerFLAT 5×6
T
a
pe and reel
DS9392
–
Rev 6
–
March 2020
For further information contact your local STMicroelectronics sales office.
STL110N10F7
Electrical ratings
1
Electrical ratings
Table 1.
Absolute maximum ratings
Parameter
Symbol
Value
100
±20
107
75
Unit
V
V
Drain-source voltage
Gate-source voltage
DS
GS
V
V
Drain current (continuous) at T
= 25 °C
A
C
I
D
Drain current (continuous) at T
= 100 °C
A
C
I
I
Drain current (pulsed)
428
21
A
DM
Drain current (continuous) at T
= 25 °C
A
C
I
D
Drain current (continuous) at T
=100 °C
14
A
C
Drain current (pulsed)
84
A
DM
T
o
tal power dissipation at T
= 25 °C
P
P
136
4.8
W
W
mJ
C
TOT
T
o
tal power dissipation at T
= 25 °C
pcb
TOT
E
Single pulse avalanche energy
490
AS
T
J
Operating junction temperature range
Storage temperature range
-55 to 175
°C
T
stg
1. This
value is rated according to R
thj-c.
2. Pulse
width limited by safe operating area.
3. This
value is rated according to R
thj-pcb.
4. Starting
T =
25 °C, I
= 18 A, V
= 50 V.
J
D
DD
Table 2.
Thermal resistance
Parameter
Symbol
Value
1.1
Unit
°C/W
°C/W
R
thj-case
Thermal resistance junction-case
Thermal resistance junction-pcb
R
31.3
thj-pcb
1. When
mounted on an FR-4 board of 1 inch², 2oz Cu, t < 10 s.
DS9392
–
Rev 6
page 2/14
STL110N10F7
Electrical characteristics
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 3.
On/off states
Symbol
Parameter
Test conditions
Min.
Typ. Max. Unit
V
V
GS
V
GS
V
GS
V
DS
V
DS
V
GS
= 0
V
, I
=
2
50 µA
Drain-source breakdown voltage
100
V
(BR)DSS
D
= 0
V
, V
=
1
00 V
1
DS
I
Zero gate voltage drain current
µA
DSS
10
DS
C
I
= 0, V
= 20 V
Gate body leakage current
Gate threshold voltage
100
4.5
6
nA
V
GSS
GS
V
= V
, I
= 250 µA
2.5
GS(th)
DS(on)
GS
D
R
= 10 V, I
= 10 A
D
Static drain-source on
‑
resistance
5
mΩ
1. Defined
by design, not subject to production test.
Table 4.
Dynamic
Symbol
Parameter
Input capacitance
Test conditions
Min.
Typ. Max. Unit
C
iss
–
–
–
–
–
–
5117
992
39
–
–
–
–
–
–
C
oss
V
V
= 50 V, f = 1 MHz, V
= 0 V
Output capacitance
Reverse transfer capacitance
T
o
tal gate charge
pF
nC
DS
GS
C
rss
Q
72
g
= 50 V, I
= 21 A, V
= 0 to 10 V
DD
D
GS
Q
Gate-source charge
Gate-drain charge
30
gs
Q
17
gd
Table 5.
Switching times
Test conditions
Symbol
Parameter
Turn-on delay time
Rise time
Min.
Typ. Max. Unit
t
–
–
–
–
25
36
52
21
–
–
–
–
ns
ns
ns
ns
V
= 50
V
, I
=
1
0 A,
d(on)
DD
D
R
G
= 4.7 Ω, V
= 10 V
t
r
GS
t
Turn-off delay time
Fall time
d(off)
t
f
Table 6.
Source-drain diode
Test conditions
Symbol
Parameter
Forward on voltage
Min.
Typ. Max. Unit
V
I
I
= 21 A, V
= 0 V
–
–
–
1.2
V
SD
GS
SD
t
= 21 A, di/dt = 100 A/µs,
= 80
V
, T
=
1
50 °C
Reverse recovery time
Reverse recovery charge
77
ns
nC
rr
SD
V
Q
rr
DD
J
150
I
Reverse recovery current
–
4.3
A
RRM
1. Pulsed:
pulse duration = 300 µs, duty cycle 1.5%.
DS9392
–
Rev 6
page 3/14
STL110N10F7
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
AM
1
6096v1
AM
1
6083v1
I
D
K
δ=0.5
(A)
0.2
0.1
10
-1
10
0.05
0.02
Z
th
= K R
thj-pcb
0.01
10
-2
1
10ms
Tj=175°C
Single pulse
Tpcb=25°C
Single pulse
100ms
10
-3
10
-4
1s
V
DS
(V)
0.1
0.1
1
0
1
10
-3
10
-2
10
-1
1
0
0
t
p
(s)
10
1
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
AM
1
6084v1
AM
1
6085v1
I
D
I
D
(A)
160
(A)
70
V
GS
= 8, 9, 10 V
V
DS
=2V
7V
140
120
100
60
50
40
30
20
6V
80
60
40
20
0
5V
4V
10
0
4
V
D
S
(V)
2
0
2
8
8
6
4
V
GS
(
V
)
0
6
Figure 5.
Gate charge vs gate-source voltage
Figure 6.
Static drain-source on-resistance
AM
1
6087v1
GADG020320200919QVG
V
DS
R
D
S
(
on)
(m
Ω
)
(V)
V
GS
=10V
5.06
12
5.04
10
V
DD
= 50 V
I
D
= 21 A
8
5.02
5.00
6
4
4.98
4.96
4.94
2
0
0
10 20 30 40 50 60 70 80 90 Q
g
(nC)
6
8
10 12 14 16 18 20
I
D
(A)
2
4
DS9392
–
Rev 6
page 4/14
STL110N10F7
Electrical characteristics (curves)
Figure 8.
Normalized gate threshold voltage vs
temperature
Figure 7.
Capacitance variations
AM
1
6088v1
C
AM
1
6089v1
V
GS(
t
h)
(pF)
(
n
orm)
6000
1.2
I
D
=250µA
1.1
1
C
i
s
s
5000
4000
3000
2000
0.9
0.8
0.7
0.6
1000
0
Coss
Crss
V
D
S
(V)
0.5
0.4
0
30 40
50
70 80
60
10
20
-75
-50
-25
0
25 50
100
75
150
125
T
J
(°C)
Figure 9.
Normalized on-resistance vs temperature
Figure 10.
Source-drain diode forward characteristics
AM
1
6090v1
AM
1
6092v1
R
D
S
(
on)
(norm)
S
D
(V)
V
T
J
=-55°C
I
D
=10 A
2
V
GS
=10 V
0.9
0.8
1.8
T
J
=25°C
1.6
1.4
1.2
1
0.7
0.6
T
J
=175°C
0.8
0.5
0.4
0.6
0.4
-75
16
18 20
-50
-25
0
25 50
100 150T
J
(°C)
2
75
125
4
8
I
S
D
(A)
6
10
12
14
Figure 11.
Normalized V
(BR)DSS
vs temperature
AM
1
6091v1
V
(BR)DSS
(
n
orm)
I
D
=1mA
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0
25 50 75
T
J
(°C)
100
DS9392
–
Rev 6
page 5/14
STL110N10F7
Test circuits
3
Test circuits
Figure 12.
Test circuit for resistive load switching times
Figure 13.
Test circuit for gate charge behavior
V
DD
12 V
47 kΩ
1 kΩ
100 nF
R
L
2200
μF
3.3
μF
V
DD
+
I
G
= CONST
2.7 kΩ
V
D
R
G
D.U.
T
.
100 Ω
V
GS
pulse width
+
D.U.
T
.
V
GS
V
G
2200
μF
pulse width
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 14.
Test circuit for inductive load switching and
diode recovery times
Figure 15.
Unclamped inductive load test circuit
L
A
A
A
D
S
V
D
100 µH
D
fast
G
D.U.
T
.
B
diode
2200
3.3
µF
+
V
DD
1000
µF
B
µF
3.3
µF
B
+
V
DD
25 Ω
I
D
G
D.U.
T
.
R
G
S
+
_
D.U.
T
.
V
i
pulse width
AM01471v1
AM01470v1
Figure 17.
Switching time waveform
Figure 16.
Unclamped inductive waveform
t
on
t
d(on)
t
off
t
d(off)
V
(BR)DSS
t
r
t
f
V
D
90%
90%
I
DM
V
DS
10%
V
GS
10%
0
0
I
D
V
DD
V
DD
90%
10%
AM01472v1
AM01473v1
DS9392
–
Rev 6
page 6/14
STL110N10F7
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
4.1
PowerFLAT 5×6 type C package information
Figure 18.
PowerFLAT 5×6 type C package outline
Bottom view
Side view
T
o
p view
8231817_typeC_Rev20
DS9392
–
Rev 6
page 7/14
STL110N10F7
PowerFLAT 5×6 type C package information
Table 7.
PowerFLAT 5×6 type C package mechanical data
mm
Dim.
Min.
0.80
0.02
Typ.
Max.
1.00
0.05
A
A1
A2
b
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
0.50
6.20
5.40
4.45
4.35
5.20
0.55
0.45
C
6.00
5.20
D
D2
D3
D4
D5
D6
e
4.20
5.00
0.40
0.30
1.27
6.15
E
5.95
3.50
2.35
0.40
0.08
0.20
0.75
1.05
0.725
0.05
0°
6.35
3.70
2.55
0.60
0.28
0.45
1.05
1.35
1.025
0.25
12°
E2
E3
E4
E5
E6
E7
K
0.325
0.90
L
L1
θ
0.15
DS9392
–
Rev 6
page 8/14
STL110N10F7
PowerFLAT 5×6 type C package information
Figure 19.
PowerFLAT 5×6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_simp_Rev_20
DS9392
–
Rev 6
page 9/14
STL110N10F7
PowerFLAT 5×6 packing information
4.2
PowerFLAT 5×6 packing information
Figure 20.
PowerFLAT 5×6 tape (dimensions are in mm)
(I) Measured
from centreline of sprocket hole
to centreline of pocket.
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
(II) Cumulative
tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
8234350_
T
a
pe_rev_C
Figure 21.
PowerFLAT 5×6 package orientation in carrier tape
Pin 1
identification
DS9392
–
Rev 6
page 10/14
STL110N10F7
PowerFLAT 5×6 packing information
Figure 22.
PowerFLAT 5×6 reel
DS9392
–
Rev 6
page 11/14
STL110N10F7
Revision history
Table 8.
Document revision history
Date
Revision
Changes
03-Dec-2012
1
First release.
Modified: P
value and
Figure 1
in cover page
TOT
Modified: I
, I
and P
values in
T
a
ble 2
TOT
D
DM
Added: E
value in
T
a
ble 2
AS
Modified: all values in
T
a
ble 3
12-Dec-2013
2
Modified: I
, I
and I
for R
DSS GSS
D DS(on)
Updated: the entire typical values in
Table 5, 6
and
7
Updated:
Figure 13, 14, 15
and
16
Minor text changes
Updated title and features on cover page.
Added P
value at T
= 25 °C in
T
a
ble 2: Absolute maximum ratings
.
C
25-Mar-2014
20-Aug-2014
3
4
TOT
Updated
Section 4: Package mechanical data
.
Modified: title, features and description
Modified:
Figure 2
and
3
Updated:
Section 4: Package mechanical data
.
Minor text changes
Removed maturity status indication.
Updated title and description on cover page.
17-Sep-2018
03-Mar-2020
5
6
Updated
T
a
ble 1. Absolute maximum ratings
and
T
a
ble 6. Source-drain diode
.
Updated
Section 4.1 PowerFLAT™ 5×6 type C package information
.
Minor text changes
Minor text changes.
DS9392
–
Rev 6
page 12/14
STL110N10F7
Contents
Contents
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
6
Package information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
7
PowerFLAT 5×6 type C package information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
PowerFLAT 5×6 packing information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
10
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
DS9392
–
Rev 6
page 13/14
STL110N10F7
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of S
T
.
F
or additional information about ST trademarks, please refer to
www.st.com/trademarks
. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS9392
–
Rev 6
page 14/14
