STMicroelectronics-STL140N4LLF5
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STL140N4LLF5
N-
channel 40 V, 2.2 mΩ typ., 32 A STripFET™ F5
Power MOSFET in a PowerFLAT™ 5×6 package
Datasheet – production data
Features
Order code
V
DS
R
DS(on)
max.
I
D
STL140N4LLF5
40 V
2.75 mΩ
32 A
Low on-resistance R
DS(on)
High avalanche ruggedness
Low gate drive power loss
Applications
Switching applications
Description
Figure 1: Internal schematic diagram
This N-channel Power MOSFET is developed
using the STripFET™ F5 technology and has
been optimized to achieve very low on-state
resistance, contributing to a FoM that is among
the best in its class.
Table 1: Device summary
Order code
Marking
140N4LF5
Package
Packing
STL140N4LLF5
PowerFLAT™ 5×6
Tape and reel
August 2017
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This is information on a product in full production.
Contents
STL140N4LLF5
Contents
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Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
DS
Parameter
Value
40
Unit
V
Drain-source voltage
V
GS
Gate-source voltage
±22
140
88
V
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (continuous) at T
pcb
= 25 °C
Drain current (continuous) at T
pcb
= 100 °C
Drain current (pulsed)
A
A
32
A
20
A
128
80
A
Total dissipation at T
C
= 25 °C
W
W
Total dissipation at T
pcb
= 25 °C
Storage temperature range
4
T
stg
T
j
-55 to 150
°C
Operating junction temperature range
Notes:
(1)
This value is rated according to R
thj-case.
(2)
This value is rated according to R
thj-pcb.
(3)
Pulse width limited by safe operating area.
Table 3: Thermal data
Parameter
Symbol
Value
1.56
Unit
°C/W
°C/W
R
thj-case
Thermal resistance junction-case
Thermal resistance junction-pcb
31.3
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2 oz Cu t <10 sec
Table 4: Avalanche characteristics
Parameter
Not-repetitive avalanche current,
(pulse width limited by T
jmax
Symbol
Value
Unit
I
AV
16
A
)
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
= I
AV
, V
DD
= 24 V)
E
AS
300
mJ
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Electrical characteristics
STL140N4LLF5
2
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 5: On/off-state
Symbol
Parameter
Test conditions
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 40 V
Min. Typ. Max. Unit
Drain-source breakdown
voltage
V
(BR)DSS
40
V
1
µA
µA
Zero gate voltage drain
current
I
DSS
V
GS
= 0 V, V
DS
= 40 V,
10
Gate body leakage
current
I
GSS
V
DS
= 0 V, V
GS
= ±22 V
±100
µA
V
GS(th)
Gate threshold voltage
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 16 A
V
GS
= 4.5 V, I
D
= 16 A
1
V
2.2
2.4
2.75
3.1
mΩ
mΩ
Static drain-source
on-resistance
R
DS(on)
Notes:
(1)
Defined by design, not subject to production test.
Table 6: Dynamic
Test conditions
Symbol
C
iss
Parameter
Input capacitance
Output capacitance
Min. Typ. Max. Unit
5900
870
–
–
–
–
pF
pF
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
C
oss
Reverse transfer
capacitance
C
rss
–
130
–
pF
Q
g
Total gate charge
V
DD
= 15 V, I
D
= 32 A
V
GS
= 0 to 4.5 V,
–
–
45
14
–
–
nC
nC
Q
gs
Gate-source charge
Q
gd
Gate-drain charge
–
17
–
nC
f=1 MHz,
gate DC bias = 0 V, test signal
level = 20 mV, I
D
= 0 A
R
G
Gate input resistance
–
1.2
–
Ω
Table 7: Switching times
Test conditions
Symbol
t
d(on)
t
r
Parameter
Turn-on delay time
Rise time
Min. Typ. Max. Unit
V
DD
= 15 V, I
D
= 16 A,
R
G
= 4.7 Ω
–
–
–
19
29
90
–
–
–
ns
ns
ns
V
GS
= 10 V,
t
d(off)
Turn-off delay time
t
f
Fall time
–
21
–
ns
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Electrical characteristics
Min. Typ. Max. Unit
Table 8: Source-drain diode
Test conditions
Symbol
I
SD
Parameter
Forward on voltage
–
–
32
128
1.1
A
A
Source-drain current
(pulsed)
t
rr
Forward on voltage
I
SD
= 32 A, V
GS
=0 V
–
–
–
V
Reverse recovery time
Reverse recovery charge
44
57
ns
nC
I
SD
= 32 A, di/dt = 100 A/
μ
s,
V
DD
= 25 V
Q
rr
I
RRM
Reverse recovery current
–
2.6
A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration=300μs, duty cycle 1.5%.
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Electrical characteristics
STL140N4LLF5
2.1
Electrical characteristics (curves)
Figure 3: Thermal impedance
Figure 2: Safe operating area
K
10
-1
10
-2
10
-3
10
-4
10
0
10
1
10
2
-3
-2
-1
t
p
(s)
10
10
10
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
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Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs
temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 12: Source- drain diode forward characteristics
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Test circuits
STL140N4LLF5
3
Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 18: Switching time waveform
Figure 17: Unclamped inductive waveform
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Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
4.1
PowerFLAT™ 5×6 type C package information
Figure 19
: PowerFLAT™ 5×6 type C package outline
Bottom view
Side view
T
o
p view
8231817_typeC_A0ER_Rev15
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Package information
STL140N4LLF5
Table 9: PowerFLAT™ 5×6 type C package mechanical data
mm
Dim.
Min.
0.80
0.02
Typ.
Max.
1.00
0.05
A
A1
A2
b
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
0.50
6.20
5.40
4.45
4.35
5.20
0.55
0.45
C
6.00
5.20
D
D2
D3
D4
D5
D6
e
4.20
5.00
0.40
0.30
1.27
6.15
E
5.95
3.50
2.35
0.40
0.08
0.20
0.75
1.05
0.725
0.05
0°
6.35
3.70
2.55
0.60
0.28
0.45
1.05
1.35
1.025
0.25
12°
E2
E3
E4
E5
E6
E7
K
0.325
0.90
L
L1
θ
0.15
Figure 20
: PowerFLAT™ 5×6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_simp_Rev_15
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Package information
4.2
PowerFLAT™ 5×6 packing information
Figure 21:
PowerFLAT™ 5×6 tape (dimensions are in mm)
(I) Measured
from centreline of sprocket hole
to centreline of pocket.
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
(II) Cumulative
tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
8234350
_
T
a
pe_rev_C
Figure 22
: PowerFLAT™ 5×6 package orientation in carrier tape
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Package information
STL140N4LLF5
Figure 23
: PowerFLAT™ 5×6 reel
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Revision history
5
Revision history
Table 10: Document revision history
Changes
Date
Revision
03-Jun-2010
29-Apr-2011
1
2
First release.
Document status promoted from preliminary data to datasheet.
Section 4: Package mechanical data has been updated.
Minor text changes.
10-Nov-2011
3
Minor text changes.
08-Aug-2017
4
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STL140N4LLF5
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–
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der
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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All rights reserved
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