STMicroelectronics-STL20N6F7
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STL20N6F7
N-
channel 60 V, 0.0046 Ω typ., 20 A STripFET™ F7 Power
MOSFET in a PowerFLAT™ 3.3×3.3 package
Datasheet – production data
Features
Order code
V
DS
R
DS(on)
max
I
D
STL20N6F7
60 V
0.0054 Ω
20 A
1
2
•
•
•
•
Among the lowest R
DS(on)
on the market
Excellent figure of merit (FoM)
Low C
rss
/C
iss
ratio for EMI immunity
High avalanche ruggedness
3
4
PowerFLAT™ 3.3×3.3 HV
Applications
•
Switching applications
Figure 1: Internal schematic diagram
Description
This N-channel Power MOSFET utilizes
D(5, 6, 7, 8)
8
7
6
5
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
G(4)
S(1, 2, 3)
1
2
3
4
AM15810v1
Table 1: Device summary
Package
Order code
Marking
Packing
STL20N6F7
20N6F
PowerFLAT™ 3.3×3.3
Tape and reel
June 2015
DocID027433 Rev 3
1/13
This is information on a product in full production.
Contents
STL20N6F7
Contents
2/13
DocID027433 Rev 3
STL20N6F7
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
60
Unit
V
V
DS
V
GS
Drain-source voltage
Gate-source voltage
± 20
100
61
V
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
A
A
400
20
A
Drain current (continuous) at T
pcb
= 25 °C
Drain current (continuous) at T
pcb
= 100 °C
Drain current (pulsed)
A
12
A
80
A
Total dissipation at T
C
= 25 °C
Total dissipation at T
pcb
= 25 °C
Storage temperature
78
W
W
3
T
stg
T
j
-55 to 150
°C
Operating junction temperature
Notes:
(1)
This value is rated according to R
thj-c
(2)
Pulse width limited by safe operating area.
.
(3)
This value is rated according to R
thj-pcb
.
Table 3: Thermal data
Parameter
Symbol
Value
42.8
1.6
Unit
°C/W
°C/W
Thermal resistance junction-pcb max.
Thermal resistance junction-case max.
R
thj-case
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec.
DocID027433 Rev 3
3/13
Electrical characteristics
STL20N6F7
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4: On /off states
Symbol
Parameter
Drain-source
Test conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
I
D
= 1 mA, V
GS
= 0 V
60
V
breakdown voltage
Zero gate voltage
drain current
V
GS
= 0 V
I
DSS
1
100
4
µA
nA
V
V
DS
= 60 V
Gate-body leakage
current
I
GSS
V
GS(th)
R
DS(on)
V
GS
= 20 V, V
DS
= 0
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= 10 V, I
D
= 10 A
Gate threshold
voltage
2
Static drain-source
on-resistance
0.0046
0.0054
Ω
Table 5: Dynamic
Test conditions
Symbol
C
iss
Parameter
Input capacitance
Output capacitance
Min.
Typ.
1600
880
Max.
Unit
pF
–
–
–
–
V
DS
= 25 V, f = 1 MHz,
C
oss
pF
V
GS
= 0 V
Reverse transfer
capacitance
66
C
rss
–
–
pF
Q
g
Q
gs
Q
gd
Total gate charge
Gate-source charge
Gate-drain charge
–
–
–
25
7.2
8.1
–
–
–
nC
nC
nC
V
DD
= 30 V, I
D
= 20 A,
V
GS
= 10 V
Table 6: Switching times
Test conditions
Symbol
Parameter
Turn-on delay time
Rise time
Min.
Typ.
15
Max.
Unit
ns
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
–
–
–
–
17.6
24.4
7.8
ns
V
DD
= 30 V, I
D
= 10 A,
R
G
= 4.7 Ω, V
GS
= 10 V
Turn-off delay time
Fall time
ns
ns
Table 7: Source-drain diode
Test conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Forward on voltage
I
SD
= 20 A, V
GS
= 0
–
1.2
V
Reverse recovery
time
t
rr
–
–
–
39.6
36
ns
nC
A
I
D
= 20 A,
di/dt = 100 A/µs
Reverse recovery
charge
Q
rr
V
DD
= 48 V
Reverse recovery
current
I
RRM
1.8
Notes:
(1)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
4/13
DocID027433 Rev 3
STL20N6F7
Electrical characteristics
2.1
Electrical characteristics
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID027433 Rev 3
5/13
Electrical characteristics
Figure 8: Capacitance variations
STL20N6F7
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs
temperature
Figure 12: Source-drain diode forward characteristics
6/13
DocID027433 Rev 3
STL20N6F7
Test circuits
3
Test circuits
Figure 13: Switching times test circuit for resistive
load
Figure 14: Gate charge test circuit
Figure 15: Test circuit for inductive load switching
and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 18: Switching time waveform
Figure 17: Unclamped inductive waveform
DocID027433 Rev 3
7/13
Package mechanical
data
STL20N6F7
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
8/13
DocID027433 Rev 3
STL20N6F7
Package mechanical
data
4.1
PowerFLAT 3.3×3.3 package information
Figure 19: PowerFLAT™ 3.3×3.3 HV package outline
BOTTOM VIEW
SIDE VIEW
TOP VIEW
8465286
_
A
DocID027433 Rev 3
9/13
Package mechanical
data
STL20N6F7
Table 8: PowerFLAT™ 3.3×3.3 HV package mechanical data
mm
Dim.
Min.
0.70
0.25
0.14
3.10
3.05
2.15
0.55
3.10
2.90
1.60
0.25
0.65
030
Typ.
0.80
0.30
0.15
3.30
3.15
2.25
0.65
3.30
3.00
1.70
0.40
0.75
0.45
0.15
Max.
0.90
0.39
0.20
3.50
3.25
2.35
0.75
3.50
3.10
1.80
0.55
0.85
0.60
0.25
0.5
A
b
c
D
D1
D2
e
E
E1
E2
H
K
L
L1
L2
ϑ
0.05
8°
10°
12°
10/13
DocID027433 Rev 3
STL20N6F7
Package mechanical
data
Figure 20: PowerFLAT™ 3.3×3.3 HV recommended footprint
8465286_footprint
DocID027433 Rev 3
11/13
Revision history
STL20N6F7
5
Revision history
Table 9: Document revision history
Changes
Date
Revision
28-Jan-2015
03-Feb-2015
1
2
First release.
In Section 2 Electrical characteristics:
– updated Table 5: Dynamic
10-Jun-2015
3
– updated Table 6: Switching times
– updated Table 7: Source-drain diode
Added Section 2.1 Electrical characteristics (curves)
12/13
DocID027433 Rev 3
STL20N6F7
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DocID027433 Rev 3
13/13
