STMicroelectronics-STL21N65M5

Part #STMicroelectronics-STL21N65M5
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STMicroelectronics-STL21N65M5
STL21N65M5  
N-channel 650
V
,
0
.175
Ω
, 17 A ultra low gate charge MDmesh™ V  
Power MOSFET in PowerFL
A
T
™ 8×8 HV package  
Datasheet — production data  
Features  
V

DSS  

T

Jmax  

@
R

DS(on)  

max  
Order code  
I

D  

“OTTOM VIEW  
3ꢀꢁꢂ  
3ꢀꢁꢂ  
3ꢀꢁꢂ  
< 0.190
Ω
17 A

(1)  

‘ꢀꢃꢂ  
STL21N65M5  
710 V  
$ꢀꢄꢂ  
1. The
 
value is rated according to R  
thj-case  
■
100% avalanche tested  
■
Low input capacitance and gate charge  
■
Low gate input resistance  
0OWER&,
!
4
˜ ꢅXꢅ (6  
Applications  
■
Switching applications  
Figure 1.  
Internal schematic diagram  
Description  
This device is an N-channel MDmesh™ V Power  
MOSFET based on an innovative proprietary  
vertical process technology, which
 
is combined  
with STMicroelectronics’ well-known  
$ꢀꢄꢂ  
PowerMESH™ horizontal layout structure. The  
resulting product has extremely low on-  
resistance, which is unmatched among silicon-  
based Power MOSFETs, making it especially  
suitable for applications which require superior  
power density and outstanding efficienc
y
.  
‘ꢀꢃꢂ  
3ꢀꢁꢂ  
!-ꢆꢃꢇꢈꢉVꢃ  
Table 1.  
Order code  
STL21N65M5  
Device summary  
Marking  
Package  
Packaging  
T
a
pe and reel  
21N65M5  
PowerFL
A
T
™ 8×8 HV  
May 2012  
Doc ID 17438 Rev 5  
1/16  
This is information on a product in full production.  
16  

STL21N65M5  
Electrical ratings  
1
Electrical ratings  
Table 2.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
V

DS  

V

GS  

Drain-source voltage  
650  
25  
V
V
Gate-source voltage  
(1)  
I

D  

Drain current (continuous) at T

C

= 25 °C  
Drain current (continuous) at T

C

= 100 °C  
Drain current (pulsed)  
17  
A
(1)  
I

D  

11  
A
(1),(2)  
I

DM  

68  
A
(3)  
I

D  

Drain current (continuous) at
T

amb

= 25 °C  
Drain current (continuous) at
T

amb

= 100 °C  
Drain current (pulsed)  
2.7  
1.7  
10.8  
3
A
(3)  
I

D  

A
(2),(3)  
I

DM  

A
(3)  
P

TOT  

T
o
tal dissipation at
T

amb

= 25 °C  
T
o
tal dissipation at T

C

= 25 °C  
W
W
(1)  
P

TOT  

125  
Avalanche current, repetitive or not-  
repetitive (pulse width limited by T

j

max)  
I

AR  

5
A
Single pulse avalanche energy  
E

AS  

400  
mJ  
(starting T

j

= 25 °C, I

D

= I

AR

, V

DD

= 50 V)  
dv/dt

(4)

Peak diode recovery voltage slope  
15  
– 55 to 150  
150  
V/ns  
°C  
T

stg  

T

j  

Storage temperature  
Max. operating junction temperature  
°C  
1. The
 
value is rated according to R  
thj-case.  
2. Pulse
 
width limited by safe operating area.  
3. When
 
mounted on FR-4 board of inch², 2oz Cu.  
4.  
I
≤
17 A, di/dt
 
≤
400 A/µs, V  
< V  
, V
 
= 400 V.  
SD  
Peak  
(BR)DSS DD  
T
a
ble 3.  
Symbol  
Thermal data  
Parameter  
Value  
Unit  
R

thj-case

Thermal resistance junction-case max  
1
°C/W  
°C/W  
(1)  
R

thj-amb  

Thermal resistance junction-amb max  
45  
1. When
 
mounted on 1inch² FR-4 board, 2 oz Cu.  
Doc ID 17438 Rev 5  
3/16  

Electrical characteristics  
STL21N65M5  
2
Electrical characteristics  
(T

C

= 25 °C unless otherwise specified)  
T
a
ble 4.  
Symbol  
On /off states  
Parameter  
Test conditions  
I

D

= 1 mA, V

GS

= 0  
V

DS

= 650 V  
Min.  
Typ.  
Max. Unit  
Drain-source  
breakdown voltage  
V

(BR)DSS  

650  
V
Zero gate voltage  
1
µA  
µA  
I

DSS  

drain current (V

GS

= 0)
 
V

DS

= 650
V
,
T

C

=125 °C  
100  
Gate-body leakage  
I

GSS  

V

GS  

=
25 V  
100 nA  
current (V

DS

= 0)  
V

GS(th)  

R

DS(on)  

Gate threshold voltage
 
V

DS

= V

GS

, I

D

= 250 µA  
Static drain-source  
3
4
5
V
V

GS

= 10
V
,
I

D

= 8.5 A  
0.175 0.190  
Ω
on-resistance  
T
a
ble 5.  
Symbol  
Dynamic  
Parameter  
Test conditions  
Min.  
Typ.  
Max. Unit  
Input capacitance  
Output capacitance  
C

iss  

C

oss  

C

rss  

1950  
46  
pF  
V

DS

= 100
V
, f = 1
M
Hz,  

GS

= 0  
–
–
–
pF  
pF  
V
Reverse transfer  
capacitance  
3
Equivalent  
capacitance time  
related  
(1)  
C

o(tr)  

–
133  
pF  
V

DS

= 0 to 520
V
,
V

GS

= 0  
f = 1 MHz open drain  
Equivalent  
capacitance energy  
related  
(2)  
C

o(er)  

–
–
44  
–
–
pF  
Intrinsic gate  
resistance  
R

G  

2.5  
Ω
Q

g  

Q

gs  

Q

gd  

T
o
tal gate charge  
Gate-source charge  
Gate-drain charge  
V

DD

= 520
V
,
I

D

= 8.5 A,  
V

GS

= 10 V  
44  
12  
17  
nC  
nC  
nC  
–
–
(see

)  
1.  
2.  
C
time related is defined as a constant equivalent capacitance giving the same charging time as C  
oss eq.
 
oss  
when V
 
increases from 0 to 80% V  
DS  
DSS  
C
C
energy related is defined as a constant equivalent capacitance giving the same stored energy as  
oss eq.  
oss  
when V
 
increases from 0 to 80% V  
DSS  
DS  
4/16  
Doc ID 17438 Rev 5  
 

STL21N65M5  
Electrical characteristics  
T
a
ble 6.  
Switching times  
Parameter  
Symbol  
Test conditions  
Min. Typ.  
Max Unit  
t

d(off)  

T
u
rn-off delay time  
Rise time  
37  
ns  
V

DD

= 400
V
,
I

D

= 11 A,  
t

r  

t

c  

t

f  

10  
ns  
R

G

= 4.7
Ω
,
V

GS

= 10 V  
(see

),  
(see

)  
–
–
Cross time  
Fall time  
24  
ns  
12  
ns  
T
a
ble 7.  
Symbol  
Source drain diode  
Parameter  
Test conditions  
Min. Typ. Max.
 
Unit  
I

SD  

Source-drain current  
17  
68  
A
A
–
–
(1)  
I

SDM  

Source-drain current (pulsed)  
(2)  
V

SD  

Forward on voltage  
I

SD

= 17 A, V

GS

= 0  
1.5  
V
t

rr  

Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
294  
4
ns  
µC  
A
I

SD

= 17 A, di/dt = 100 A/µs  
Q

rr  

–
–
V

DD

= 100 V (see

)  
I

RRM  

28  
t

rr  

Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
I

SD

= 17 A, di/dt = 100 A/µs  

DD

= 100
V
,
T

j

= 150 °C  
(see

)  
340  
5
ns  
µC  
A
Q

rr  

V
I

RRM  

29  
1. Pulse
 
width limited by safe operating area  
2. Pulsed:
 
pulse duration = 300 µs, duty cycle 1.5%  
Doc ID 17438 Rev 5  
5/16  

Electrical characteristics  
STL21N65M5  
2.1  
Electrical characteristics (curves)  
Figure 2.  
Safe operating area  
Figure 3.  
Thermal impedance  
AM0706
8
v2  
Zth PowerFL
A
T
8
x
8
HV  
I
D
(A)  
K
δ
=0.5  
0.2  
0.1  
10  
10
µs  
10

-1  

0.05  
100
µs  
0.02  
1
0.01  
1m
s  
S
ingle p
u
l
s
e  
Tj=150°C  
Tc=25°C  
S
ingle p
u
l
s
e  
10m
s  
10

-2  

10

-5  

0.1  
10

-2  

t
10

-4  

10

–
3
 

10  
V
D
S
(V)  

p

(
s
)  
0.1  
1
100  
Figure 4.  
Output characteristics  
Figure 5.  
Transfer characteristics  
AM0549
3
v1  
AM05494v1  
I
D
(A)  
I
D
(A)  
V
D
S
=15V  
V
G
S
=10V  
3
5  
3
5  
3
0  
3
0  
7V  
25  
25  
20  
15  
10  
20  
15  
10  
5
6V  
5V  
5
0
0
0
5
2
20 25  
3
0  
V
D
S
(V)  
8
10 V

G
S

(V)  
10  
15  
0
4
6
Figure 6.  
Gate charge vs gate-source voltage
 
Figure 7.  
Static drain-source on-resistance  
AM05496v1  
AM05495v1  
V
G
S  
V
D
S  
R
D
S
(on)  
(
Ω
)  
(V)  
(V)  
V
G
S
= 10 V  
V
DD
=520V  
Q
g  
12  
10  
8
0.1
8
 
500  
I
D
=
8
.5A  
V
D
S  
0.16  
0.14  
400  
3
00  
6
0.12  
200  
100  
4
2
0.10  
0
0
0.0
8  
8
14  
2
4
6
10  
12  
16  
I
D
(A)  
0
0
3
0  
40  
10  
20  
50  
Q
g
(nC)  
6/16  
Doc ID 17438 Rev 5  
 
 
 

STL21N65M5  
Electrical characteristics  
Figure 8.  
Output capacitance stored energy
 
Figure 9.  
Capacitance variations  
AM0549
8
v1  
AM05497v1  
C
(pF)  

o
ss

(
µ
J)  
E
9
8
10000  
1000  
7
6
Ci
ss  
5
4
3
2
100  
10  
1
Co
ss  
Cr
ss  
1
0
0
200  
400 500  
0.1  
100  
100  
3
00  
600  
V
D
S
(V)  
1
10  
V
D
S
(V)  
Figure 10.
 
Normalized gate threshold voltage
 
Figure 11.
 
Normalized on-resistance vs  
vs temperature
 
temperature  
AM05500v1  
AM05501v1  
V
G
S
(th)  
R
D
S
(on)  
(norm)  
(norm)  
2.1  
1.10  
I
D
=250
µ
A  
I
D
=
8
.5 A  
1.9  
1.7  
V
G
S
= 10 V  
1.00  
0.90  
1.5  
1.
3  
1.1  
0.9  
0.
8
0  
0.7  
0.5  
-50  
-25  
0.70  
-50  
-25  
0
25 50 75  
125  
T
J  
(°C)  
0
25 50 75  
T
J
(°C)  
125  
100  
100  
Figure 12.
 
Source-drain diode forward  
characteristics  
Figure 13.
 
Normalized V

DS

vs temperature  
AM05502v1  
AM10
3
99v1  
V
(V)  
S
D  
V
D
S  
(norm)  
T
J
=-50°C  
1.0
8  
1.0  
I
D
= 1mA  
1.06  
1.04  
1.02  
1.00  
0.9  
0.
8  
T
J
=25°C  
0.7  
0.6  
T
J
=150°C  
0.9
8  
0.96  
0.5  
0.4  
0.94  
0.92  
0
-50  
-25  
10  
20  
3
0  
40  
50 I

S
D

(A)  
0
25 50 75  
T
J
(°C)  
100  
Doc ID 17438 Rev 5  
7/16  

Electrical characteristics  
STL21N65M5  
Figure 14.
 
Switching losses vs gate resistance  
(1)  
AM05541v1  
E
(
μ
J)  
Eon  
I
D
=11A  
V

DD

=400V  
V

G
S

=10V  
160  
140  
120  
Eoff  
100  
8
0  
60  
40  
20  
0
20  
3
0  
40  
10  
R

G

(
Ω
)  
0
1. Eon
 
including reverse recovery of a SiC diode  
8/16  
Doc ID 17438 Rev 5  

STL21N65M5  
Test circuits  
3
Test circuits  
Figure 15.
 
Switching times test circuit for  
resistive load  
Figure 16.
 
Gate charge test circuit  
V
DD  
12V  
47k
Ω  
1k
Ω  
100nF  
2200  
3
.
3  
μ
F  
R
L  
μ
F  
I
G
=CON
S
T  
V

DD  

100
Ω  
V

i

=20V=V
GMAX  
D.U.
T
.  
V

G  

V
D  
R
G  
V
G
S  
2200  
μ
F  
D.U.
T
.  
2.7k
Ω  
47k
Ω  
P
W  
1k
Ω  
P
W  
AM0146
8
v1  
AM01469v1  
Figure 17.
 
Test circuit for inductive load  
switching and diode recovery times  
Figure 18.
 
Unclamped inductive load test  
circuit  
L
A
A
A
B
D
FA
S
T  
DIODE  
L=100
μ
H  
V
D  
G
2200  
μ
F  
D.U.
T
.  
B
3
.
3  
μ
F  
V
DD  
S
3
.
3  
μ
F  
1000  
μ
F  
B
V

DD  

25  
Ω
I
D  
D
G
R

G  

S
V
i  
D.U.
T
.  
P
w  
AM01470v1  
AM01471v1  
Figure 19.
 
Unclamped inductive waveform  
Figure 20.
 
Switching time waveform  
Concept w
a
veform for Ind
u
ctive Lo
a
d
T
u
rn-off  
V
(BR)D
SS  
Id  
V
D  
90
%
Vd
s  
90
%
Id  
Tdel
a
y-off  
I
DM  
Vg
s  
90
%
Vg
s  
10
%
Vd
s  
on  
I
D  
Vg
s
(I(t))  
V
DD  
V
DD  
10
%
Id  
Vd
s  
Tri
s
e  
Tf
a
ll  
Tcro
ss
-over  
AM01472v1  
AM05540v2  
Doc ID 17438 Rev 5  
9/16  

Package mechanical data  
STL21N65M5  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECO
P
A
CK

®

packages, depending on their level of environmental compliance. ECO
P
ACK

®  

is an ST trademark.  
Table 8.  
PowerFLAT™ 8×8 HV mechanical data  
mm  
Dim.  
Min.  
Typ.  
Max.  
A
A1  
b
0.80  
0.00  
0.95  
0.90  
0.02  
1.00  
8.00  
8.00  
7.20  
4.30  
2.00  
0.50  
0.10  
0.10  
0.10  
1.00  
0.05  
1.05  
D
E
D2  
E2  
e
7.05  
4.15  
7.30  
4.40  
L
0.40  
0.60  
aaa  
bbb  
ccc  
10/16  
Doc ID 17438 Rev 5  
 

STL21N65M5  
Package mechanical data  
Figure 21.
 
PowerFLAT™ 8×8 HV drawing mechanical data  
BOTTOM VIEW  
b
bbb C
 
A B  
PIN#1 ID  
D2  
SIDE VIEW  
ccc C  
C
SEATING  
PLANE  
0.08 C  
D
A
B
INDEX AREA  
aaa C  
TOP VIEW  
aaa C  
8
222
8
71_Rev_B  
Doc ID 17438 Rev 5  
11/16  

Package mechanical data  
STL21N65M5  
Figure 22.
 
PowerFLAT™ 8×8 HV recommended footprint  
7.30  
1.05  
2.00  
Footprint  
12/16  
Doc ID 17438 Rev 5  

STL21N65M5  
Packaging mechanical data  
5
Packaging mechanical data  
Figure 23.
 
PowerFLAT™ 8×8 HV tape  
P0 (4.0
 
0.1)  
P2 (2.0
 
0.1)  
D0 ( 1.55
 
0.05)  
T (0.
3
0 0.05)  
E
(1.75 0.1)  
D1 ( 1.5 Min)  
P1 (12.00
 
0.1)  
A0 (
8
.
3
0 0.1)  
K0 (1.10
 
0.1)  
Note: B
as
e
a
nd B
u
lk
qua
ntity
3
000 pc
s  
8
229
8
19_
T
a
pe_revA  
Figure 24.
 
PowerFLAT™ 8×8 HV package orientation in carrier tape  
Doc ID 17438 Rev 5  
13/16  
 

Packaging mechanical data  
Figure 25.
 
PowerFLAT™ 8×8 HV reel  
STL21N65M5  
8
229
8
19_Reel_revA  
14/16  
Doc ID 17438 Rev 5  

STL21N65M5  
Revision history  
6
Revision history  
Table 9.  
Date  
Document revision history  
Revision  
Changes  
28-Apr-2010  
14-Jun-2010  
1
2
First release.  
R

DS(on)

typical value has been corrected.  
14-Mar-2011  
18-May-2011  
3
4
R

DS(on)

limits in

have been updated.  
Minor text changes.  
29-May-2011  
5
Doc ID 17438 Rev 5  
15/16  

STL21N65M5  
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16/16  
Doc ID 17438 Rev 5