STMicroelectronics-STL40N75LF3
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STL40N75LF3
N-channel 75
V
,
1
6 m
Ω
typ., 10 A S
T
r
ipFET™ III Power MOSFET
in a PowerFL
A
T
™ 5×6 package
Datasheet —
production data
Features
R
DS(on)
max
Order code
V
DSS
I
D
STL40N75LF3
75 V
< 19 m
Ω
10 A
(1)
1. The
value is rated according to R
thj-pcb
1
2
■
N-channel enhancement mode
■
Low gate charge
3
4
PowerFLAT™ 5×6
■
Low threshold voltage device
Applications
■
Switching applications
Description
Figure 1.
Internal schematic diagram
ꢉ
ꢁ
ꢃ
ꢈ
ꢈ
ꢃ
ꢁ
ꢉ
This device is an N-channel enhancement mode
Power MOSFET produced using
STMicroelectronics’ S
T
r
ipFET™ III technolog
y
,
which is specifically designed to minimize on-
resistance and gate charge to provide superior
switching performance.
$
$
$
$
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ꢇ
3
ꢆ
3
ꢅ
3
ꢄ
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“OTTOM 6IEW
4
O
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Table 1.
Order code
STL40N75LF3
Device summary
Marking
Package
Packaging
T
a
pe and reel
40N75LF3
PowerFL
A
T
™ 5×6
October 2012
Doc ID 023810 Rev 1
1/16
This is information on a product in full production.
16
Contents
STL40N75LF3
Contents
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
Doc ID 023810 Rev 1
STL40N75LF3
Electrical ratings
1
Electrical ratings
T
a
ble 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V
DS
V
GS
Drain-source voltage
75
+20-16
40
V
V
Gate-source voltage
(1)
I
D
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (continuous) at T
pcb
= 25 °C
Drain current (continuous) at T
pcb
=100 °C
Drain current (pulsed)
A
(1)
I
D
26
A
(2)
I
D
10
A
(3)
I
D
6
A
(3)
I
DM
160
62
A
(1)
P
TOT
T
o
tal dissipation at T
C
= 25 °C
T
o
tal dissipation at T
pcb
= 25 °C
W
W
(3)
P
TOT
4
T
J
Operating junction temperature
Storage temperature
-55 to 150
°C
T
stg
1. The
value is rated according to R
2. The
value is rated according to R
thj-case
thj-pcb
3. Pulse
width limited by safe operating area
Table 3.
Symbol
Thermal resistance
Parameter
Value
Unit
R
thj-case
Thermal resistance junction-case
Thermal resistance junction-ambient
2
°C/W
°C/W
(1)
R
thj-pcb
31.3
1. When
mounted on FR-4 board of 1inch², 2oz Cu., t < 10 sec.
Doc ID 023810 Rev 1
3/16
Electrical characteristics
STL40N75LF3
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified).
T
a
ble 4.
Symbol
On/off states
Parameter
Test conditions
I
D
= 250 µA
Min. Typ.
Max.
Unit
Drain-source breakdown
voltage (V
GS
= 0)
V
(BR)DSS
75
V
V
DS
= 75
V
,
1
µA
µA
Zero gate voltage drain
current (V
GS
= 0)
I
DSS
V
DS
= 75
V
,
T
C
= 125 °C
10
Gate body leakage current
(V
DS
= 0)
I
GSS
V
GS
= +20 / -16 V
100
nA
V
V
GS(th)
Gate threshold voltage
V
DS
= V
GS
, I
D
= 250 µA
1
V
GS
= 10
V
,
I
D
= 20 A
V
GS
= 5
V
,
I
D
= 20 A
16
19
22
m
Ω
m
Ω
Static drain-source on
resistance
R
DS(on)
18.7
T
a
ble 5.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Input capacitance
Output capacitance
C
iss
C
oss
C
rss
1300
228
15
pF
pF
pF
V
DS
= 25
V
,
f
=1 MHz,
–
–
V
GS
=0
Reverse transfer
capacitance
Q
g
Q
gs
Q
gd
T
o
tal gate charge
Gate-source charge
Gate-drain charge
V
DD
= 37.5
V
,
I
D
= 40 A
V
GS
= 10 V
12
5
nC
nC
nC
–
–
–
–
5.3
f=1 MHz Gate DC Bias = 0
T
e
st signal level = 20 mV
open drain
R
G
Gate input resistance
3.5
Ω
T
a
ble 6.
Symbol
Switching times
Parameter
Test conditions
Min. Typ. Max.
Unit
t
d(on)
t
r
t
d(off)
t
f
T
u
rn-on delay time
Rise time
12
25
25
3
ns
ns
ns
ns
V
DD
= 32.5
V
,
I
D
= 20 A,
R
G
= 4.7
Ω
,
V
GS
=10 V
–
–
T
u
rn-off delay time
Fall time
4/16
Doc ID 023810 Rev 1
STL40N75LF3
Electrical characteristics
Min Typ. Max Unit
T
a
ble 7.
Source drain diode
Parameter
Symbol
Test conditions
I
SD
Source-drain current
40
160
1.1
A
A
V
–
–
(1)
I
SDM
Source-drain current (pulsed)
Forward on voltage
(2)
V
SD
I
SD
= 40 A, V
GS
=0
t
rr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 40 A,
35
44
27
ns
nC
A
Q
rr
di/dt = 100 A/µs,
–
I
RRM
V
DD
=60
V
,
T
j
=25 °C
1. Pulse
width limited by safe operating area
2. Pulsed:
pulse duration=300µs, duty cycle 1.5%
Doc ID 023810 Rev 1
5/16
Electrical characteristics
STL40N75LF3
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
AM15409v1
I
D
(A)
100
10
1
10m
s
100m
s
1
s
Tj= 175°C
Tc=25°C
0.1
S
ingle
p
u
l
s
e
0.01
10
V
D
S
(V)
0.1
1
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
AM15410v1
AM15411v1
I
D
(A)
I
D
(A)
V
D
S
= 4 V
V
= 10 V
G
S
100
100
8
0
8
0
V
= 5 V
G
S
60
60
40
20
0
V
= 4 V
G
S
40
20
0
V
= 2 V
G
S
2
4
1
V
D
S
(V)
5
6
8
V
G
S
(V)
0
0
2
3
3
1
7
Figure 6.
Gate charge vs gate-source voltage
Figure 7.
Static drain-source on-resistance
AM15412v1
AM1541
3
v1
V
(V)
G
S
R
D
S
(on)
(m
Ω
)
V
DD
=
3
7V
=40A
V
G
S
=10V
3
0
10
I
D
25
20
15
8
6
4
10
2
0
5
0
Q
25
g
(nC)
40
I
D
(A)
0
0
10
20
3
0
20
5
10
15
6/16
Doc ID 023810 Rev 1
STL40N75LF3
Electrical characteristics
Figure 8.
Capacitance variations
Figure 9.
Normalized B
VDSS
vs temperature
AM15414v1
AM15415v1
C
(pF)
V
D
S
(norm)
1.15
3
500
I
D
= 1mA
3
000
1.1
1.05
2500
2000
1500
1
0.95
Ci
ss
0.9
0.
8
5
0.
8
1000
500
Co
ss
Cr
ss
D
S
(V)
0
0
20
-55
–
3
0 -5
20 45
70
10
3
0
V
T
J
(°C)
40
95
120
Figure 10.
Normalized gate threshold voltage
Figure 11.
Normalized on-resistance vs
vs temperature
temperature
AM15
3
44v1
AM15417v1
V
G
S
(th)
R
D
S
(on)
(norm)
(norm)
1.2
V
G
S
=5V
2
I
D
=250
µ
A
1
1.5
0.
8
1
0.6
0.5
0
0.4
0.2
-55
–
3
0
-5
20 45 70
T
J
(°C)
-55
-5 20
70
95
120
I
D
(A)
95
120
–
3
0
45
Figure 12.
Source-drain diode forward
characteristics
AM1541
8
v1
V
S
D
(V)
T
J
=-50°C
1
0.9
T
J
=25°C
0.
8
0.7
0.6
0.5
0.4
T
J
=175°C
0
10
I
S
D
(A)
20
3
0
40
Doc ID 023810 Rev 1
7/16
Test circuits
STL40N75LF3
3
Test circuits
Figure 13.
Switching times test circuit for
resistive load
Figure 14.
Gate charge test circuit
V
DD
12V
47k
Ω
1k
Ω
100nF
2200
3
.
3
μ
F
R
L
μ
F
I
G
=CON
S
T
V
DD
100
Ω
V
i
=20V=V
GMAX
D.U.
T
.
V
D
R
G
V
G
S
2200
μ
F
D.U.
T
.
V
G
2.7k
Ω
47k
Ω
P
W
1k
Ω
P
W
AM0146
8
v1
AM01469v1
Figure 15.
Test circuit for inductive load
switching and diode recovery times
Figure 16.
Unclamped inductive load test
circuit
L
A
A
A
B
D
FA
S
T
DIODE
L=100
μ
H
V
D
G
2200
μ
F
D.U.
T
.
B
3
.
3
μ
F
V
DD
S
3
.
3
μ
F
1000
μ
F
B
V
DD
25
Ω
I
D
D
G
R
G
S
V
i
D.U.
T
.
P
w
AM01470v1
AM01471v1
Figure 17.
Unclamped inductive waveform
Figure 18.
Switching time waveform
t
on
td
on
t
off
td
off
V
(BR)D
SS
t
r
t
f
V
D
90
%
10
%
90
%
I
DM
10
%
V
D
S
I
D
0
0
V
DD
V
DD
90
%
V
G
S
10
%
AM01472v1
AM0147
3
v1
8/16
Doc ID 023810 Rev 1
STL40N75LF3
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECO
P
A
CK
®
packages, depending on their level of environmental compliance. ECO
P
ACK
®
ECO
P
A
CK
®
is an ST trademark.
Doc ID 023810 Rev 1
9/16
Package mechanical data
STL40N75LF3
Table 8.
Dim.
PowerFLAT™ 5×6 type C-B mechanical data
mm
Min.
Typ.
Max.
A
A1
A3
b
0.80
0
0.83
0.02
0.20
0.40
5.00
4.75
4.20
6.00
5.75
3.48
2.63
1.27
0.80
0.93
0.05
0.35
4.15
0.47
4.25
D
D1
D2
E
E1
E2
E4
e
3.43
2.58
3.53
2.68
L
0.70
0.90
10/16
Doc ID 023810 Rev 1
STL40N75LF3
Figure 19.
PowerFLAT™ 5×6 type C-B drawing
Bottom View
Package mechanical data
e/2
e
1
PIN 1 IDENTIFIC
A
T
ION
EXPO
S
ED
P
A
D
E2
E4
b 8
x
D2/2
D2
T
o
p View
D/2
E/2
E1
E
PIN 1 IDENTIFIC
A
T
ION
1
D1
D
0.1
C
A
3
S
E
A
T
ING PLANE
A
A1
C
0.0
8
C
72
8
646
3
_Rev_H
Doc ID 023810 Rev 1
11/16
Package mechanical data
STL40N75LF3
Table 9.
Dim.
PowerFLAT™ 5×6 type S-C mechanical data
mm
Min.
Typ.
Max.
A
A1
A2
b
0.80
0.02
1.00
0.05
0.25
0.30
0.50
D
5.20
6.15
E
D2
E2
e
4.11
3.50
4.31
3.70
1.27
0.65
e1
L
0.715
1.05
1.015
1.35
K
12/16
Doc ID 023810 Rev 1
STL40N75LF3
Figure 20.
PowerFLAT™ 5×6 type S-C mechanical data
Package mechanical data
4
O
P VIEW
“OTTOM VIEW
3IDE VIEW
ꢉꢅꢆꢄꢉꢄꢁ?$?TYPE #
Doc ID 023810 Rev 1
13/16
Package mechanical data
STL40N75LF3
Figure 21.
PowerFLAT™ 5×6 recommended footprint (dimensions in mm)
2%6?$?TYPE #
14/16
Doc ID 023810 Rev 1
STL40N75LF3
Revision history
5
Revision history
T
a
ble 10.
Document revision history
Date
Revision
Changes
19-Oct-2012
1
First release.
Doc ID 023810 Rev 1
15/16
STL40N75LF3
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Doc ID 023810 Rev 1
