STMicroelectronics-STL52DN4LF7AG
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STL52DN4LF7AG
Automotive-grade dual N-
channel 40 V, 9 mΩ typ., 18 A
STripFET™ F7 Power MOSFET in a PowerFLAT™ 5×6 DI
Datasheet – production data
Features
Order code
V
DS
R
DS(on)
max.
I
D
STL52DN4LF7AG
40 V
16 mΩ
18 A
AEC-Q101 qualified
Among the lowest R
DS(on)
on the market
Excellent FoM (figure of merit)
Low C
rss
/C
iss
ratio for EMI immunity
High avalanche ruggedness
Wettable flank package
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
Figure 1: Internal schematic diagram
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
Table 1: Device summary
Package
PowerFLAT™ 5×6 double island
Order code
Marking
Packing
STL52DN4LF7AG
52DN4LF7
Tape and reel
December 2017
DocID029278 Rev 4
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This is information on a product in full production.
Contents
STL52DN4LF7AG
Contents
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STL52DN4LF7AG
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
V
DS
Parameter
Value
40
Unit
V
Drain-source voltage
V
GS
Gate-source voltage
±20
18
V
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
c
= 100 °C
Drain current (pulsed)
A
18
A
72
A
P
TOT
T
stg
T
J
Total dissipation at T
C
= 25 °C
Storage temperature range
65
W
-55 to 175
°C
Operation junction temperature range
Notes:
(1)
Drain current is limited by package, the current capability of the silicon is 46 A at 25 °C and 33 A at 100 °C.
(2)
Pulse width limited by safe operating area
Table 3: Thermal data
Symbol
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
Value
2.3
Unit
R
thj-case
°C/W
32
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s
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Electrical characteristics
STL52DN4LF7AG
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4: On/Off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Drain-source breakdown
voltage
V
(BR)DSS
I
D
= 1 mA, V
GS
= 0 V
40
V
Zero gate voltage
drain current
V
GS
= 0 V
I
DSS
10
µA
V
DS
= 40 V
Gate-body leakage
current
I
GSS
V
GS
= ± 20 V, V
DS
= 0 V
100
nA
V
V
GS(th)
Gate threshold voltage
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= 10 V, I
D
= 6 A
V
GS
= 4.5 V, I
D
= 6 A
1.5
2.5
16
20
9
Static drain-source
on-resistance
R
DS(on)
mΩ
12
Table 5: Dynamic
Test conditions
Symbol
C
iss
Parameter
Input capacitance
Output capacitance
Min. Typ. Max. Unit
–
–
500
140
–
–
pF
pF
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
C
oss
Reverse transfer
capacitance
C
rss
–
20
–
pF
Q
g
Total gate charge
V
DD
= 20 V, I
D
= 12 A,
V
GS
= 0 to 10 V
–
–
9.4
1.6
–
–
nC
nC
Q
gs
Gate-source charge
Q
gd
Gate-drain charge
–
2
–
nC
Table 6: Switching times
Test conditions
Symbol
t
d(on)
t
r
Parameter
Turn-on delay time
Rise time
Min. Typ. Max. Unit
V
DD
= 32 V, I
D
= 6 A,
6.5
5
–
–
–
–
–
–
ns
ns
ns
R
G
= 4.7 Ω, V
GS
= 10 V
48
t
d(off)
Turn-off delay time
t
f
Fall time
–
14.5
–
ns
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DocID029278 Rev 4
STL52DN4LF7AG
Symbol
Electrical characteristics
Min. Typ. Max. Unit
Table 7: Source-drain diode
Test conditions
Parameter
Source-drain
current
–
–
18
72
A
A
Source-drain
current
(pulsed)
Forward on
voltage
I
SD
= 12 A, V
GS
= 0 V
–
–
–
–
1.3
V
ns
nC
A
Reverse
recovery time
t
rr
18
7.5
0.8
I
SD
= 12 A, di/dt = 100 A/µs
V
DD
= 32 V
Reverse
recovery charge
Q
rr
Reverse
recovery current
I
RRM
Notes:
(1)
Drain current is limited by package, the current capability of the silicon is 46 A at 25 °C.
(2)
Pulse width limited by safe operating area.
(3)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
STL52DN4LF7AG
2.1
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
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STL52DN4LF7AG
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs
temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Source-drain diode forward characteristics
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Test circuits
STL52DN4LF7AG
3
Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 18: Switching time waveform
Figure 17: Unclamped inductive waveform
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STL52DN4LF7AG
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
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Package information
STL52DN4LF7AG
4.1
PowerFLAT™ 5×6 double island WF type R
package
information
Figure 19
: PowerFLAT™ 5×6 double island WF type R package outline
8256945_r16_typeR-WF
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STL52DN4LF7AG
Package information
Table 8: PowerFLAT™ 5×6 double island WF type R mechanical data
mm
Dim.
Min.
0.80
0.02
Typ.
Max.
1.00
0.05
A
A1
A2
b
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
1.68
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
1.98
C
6.00
5.20
D
D2
D3
D4
D5
D6
D7
e
4.20
5.00
0.40
0.30
1.27
6.40
E
6.20
3.50
2.35
0.40
0.08
0.20
0.85
0.55
4.00
3.55
1.275
0.725
0.175
0°
6.60
3.70
2.55
0.60
0.28
0.45
1.15
0.75
4.40
3.85
1.575
0.925
0.375
12°
E2
E3
E4
E5
E6
E7
E8
E9
E10
K
0.325
1.00
4.20
3.70
L
0.825
0.275
L1
θ
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Package information
STL52DN4LF7AG
Figure 20
: PowerFLAT™ 5×6 double island recommended footprint (dimensions
are in mm)
8256945_FP_std_R16
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STL52DN4LF7AG
Package information
4.2
Packing information
Figure 21
: PowerFLAT™ 5×6 WF tape (dimensions are in mm)
Figure 22
: PowerFLAT™ 5×6 package orientation in carrier tape
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Package information
STL52DN4LF7AG
Figure 23
: PowerFLAT™ 5×6 reel (dimensions are in mm)
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STL52DN4LF7AG
Revision history
5
Revision history
Table 9: Document revision history
Changes
Date
Revision
28-Apr-2016
1
First release.
Updated
Figure 1: “Internal schematic diagram”
and
Section 7.1:
“PowerFLAT™ 5×6 double island WF type R package information”
20-Jun-2016
13-Sep-2016
2
3
Minor text changes.
Updated
Section 5: “Electrical characteristics”
Datasheet promoted from preliminary data to production data.
Modified title.
18-Dec-2017
4
Minor text changes.
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STL52DN4LF7AG
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