STMicroelectronics-STL92N10F7AG
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STL92N10F7AG
Automotive-grade N-channel 100
V
,
0
.008
Ω
typ.,16 A
STripFET™ F7 Power MOSFET in a PowerFLAT™ 5×6 package
Datasheet
–
production data
Features
R
DS(on)
max
Order code
V
DS
I
D
P
TOT
STL92N10F7AG 100
V 0.0095
ꢀ
16 A
5 W
•
Designed for automotive applications and
1
2
AEC-Q101 qualified
3
4
•
Among the lowest R
DS(on)
on the market
•
Excellent figure of merit (FoM)
•
Low C
rss
/C
iss
ratio for EMI immunity
•
High avalanche ruggedness
PowerFLAT
™
5×6
•
Wettable flank package
Figure 1. Internal schematic diagram
Applications
D(5, 6, 7, 8)
8
7
6
5
•
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
G(4)
1
2
3
4
T
o
p View
S(1, 2, 3)
AM15540v2
Table 1. Device summary
Order code
STL92N10F7AG
Marking
92N10F7
Package
Packaging
PowerFLAT
TM
5×6
T
a
pe and reel
October 2015
DocID027022 Rev 2
1/16
This is information on a product in full production.
Contents
STL92N10F7AG
Contents
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
DocID027022 Rev 2
STL92N10F7AG
Electrical ratings
1
Electrical ratings
Table 2. Absolute maximum ratings
Parameter
Symbol
Value
Unit
V
DS
V
GS
Drain-source voltage
100
± 20
70
V
V
Gate-source voltage
(1)
I
D
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (continuous) at T
pcb
= 25 °C
Drain current (continuous) at T
pcb
= 100 °C
Drain current (pulsed)
A
(1)
I
D
50
A
(2)
I
D
16
A
(2)
I
D
11
A
(2)(3)
I
DM
64
A
(1)
P
TOT
T
o
tal dissipation at T
C
= 25 °C
T
o
tal dissipation at T
pcb
= 25 °C
Storage temperature
100
5
W
W
(2)
P
TOT
T
stg
T
j
-55 to 175 °C
°C
Operating junction temperature
1. This
value is rated according to R
2. This
value is rated according to R
thj-c
thj-pcb
3. Pulse
width limited by safe operating area.
Table 3. Thermal data
Symbol
Parameter
Value
Unit
(1)
R
thj-pcb
Thermal resistance junction-pcb max
31
°C/W
°C/W
R
thj-case
Thermal resistance junction-case max
1.5
2
1. When
mounted on FR-4 board of 1 inch , 2 oz Cu.
DocID027022 Rev 2
3/16
16
Electrical characteristics
STL92N10F7AG
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4. On /off states
Test conditions
Symbol
Parameter
Drain-source
Min.
Typ.
Max. Unit
V
(BR)DSS
I
D
= 250 µ
A
, V
GS
= 0
100
V
breakdown voltage
V
V
DS
= 100 V
DS
= 100
V
, T
C
=125 °C
1
µA
µA
Zero gate voltage
I
DSS
drain current (V
GS
= 0)
100
Gate-body leakage
current (V
DS
= 0)
I
GSS
V
GS
= ±20 V
±100
4.5
nA
V
V
GS(th)
R
DS(on)
Gate threshold voltage
V
DS
= V
GS
, I
D
= 250 µA
2.5
3.5
Static drain-source
V
GS
= 10 V, I
D
= 8 A
on-resistance
0.008 0.0095
ꢀ
Table 5. Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
C
iss
Input capacitance
–
–
3100
700
–
–
pF
pF
V
DS
= 50
V
, f = 1 MHz,
C
oss
Output capacitance
V
GS
= 0
Reverse transfer
capacitance
C
rss
–
45
–
pF
Q
g
Q
gs
Q
gd
T
o
tal gate charge
Gate-source charge
Gate-drain charge
–
–
–
45
18
13
–
–
–
nC
nC
nC
V
DD
= 50
V
,
I
D
= 16 A,
V
GS
= 10 V
Table 6. Switching times
Test conditions
Symbol
Parameter
Min.
Typ. Max. Unit
t
d(on)
t
r
t
d(off)
t
f
Turn-on delay time
Rise time
–
–
–
–
19
32
36
13
–
–
–
–
ns
ns
ns
ns
V
DD
= 50
V
,
I
D
= 8 A,
R
G
= 4.7
ꢀ
,
V
GS
= 10 V
Turn-off delay time
Fall time
4/16
DocID027022 Rev 2
STL92N10F7AG
Electrical characteristics
Min. Typ. Max.
Unit
Table 7. Source drain diode
Test conditions
Symbol
Parameter
I
SD
Source-drain current
–
–
–
–
–
–
16
64
A
A
(1)
I
SDM
Source-drain current (pulsed)
Forward on voltage
(2)
V
SD
t
rr
I
SD
= 16 A, V
GS
= 0
1.1
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
70
125
3.6
ns
nC
A
I
SD
= 16 A, di/dt = 100 A/µs
Q
rr
V
DD
= 80 V, T
j
=150 °C
I
RRM
1. Pulse
width limited by safe operating area.
2. Pulsed:
pulse duration = 300 µs, duty cycle 1.5%
DocID027022 Rev 2
5/16
16
Electrical characteristics
STL92N10F7AG
2.1
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
AM18088v1
AM18087v1
I
D
(A)
K
δ
=0.5
0.2
0.1
0.05
0.02
0.01
10
-1
10
100
µs
pcb
10
-2
10
-3
1
Single pulse
1ms
Tj=175°C
Tpcb=25°C
Single pulse
10ms
0.1
0.1
1
10
10
-4
10
-3
10
-1
10
1
10
-2
10
0
t
p
(s)
V
DS
(V)
Figure 4. Output characteristics
Figure 5. Transfer characteristics
AM18090v1
AM18089v1
I
D
(A)
I
D
(A)
V
GS
=10V
V
DS
=9V
300
300
250
200
150
100
9V
250
8V
7V
200
150
100
50
6V
50
0
5V
0
2
6
8
10
V
GS
(V)
4
6
V
DS
(V)
4
0
2
8
Figure 6. Gate charge vs gate-source voltage
Figure 7. Static drain-source on-resistance
AM18092v1
AM18091v1
V
GS
R
DS(on)
(m
Ω
)
(V)
V
DD
=50V
=16A
V
GS
=10V
12
10.00
8.00
6.00
4.00
I
D
10
8
6
4
2.00
0.00
2
0
30
I
D
(A)
Q
g
(nC)
0
10
15
20
0
10
20
40
50
5
6/16
DocID027022 Rev 2
STL92N10F7AG
Electrical characteristics
Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage vs
temperature
AM18094v1
AM18093v1
V
GS(th)
(norm)
C
(pF)
I
D
=250
µ
A
3500
1.2
Ciss
3000
2500
2000
1
0.8
0.6
0.4
0.2
0
1500
1000
500
0
Coss
Crss
DS
(V)
-55
0
80
-5
45
J
(°C)
145 T
V
95
20
40
60
Figure 10. Normalized on-resistance vs
temperature
Figure 11. Normalized V
(BR)DSS
vs temperature
AM18095v1
AM18096v1
R
DS(on)
V
(BR)DSS
(norm)
(norm)
I
V
D
=16A
1.04
I
D
=1mA
GS
=10V
2
1.03
1.02
1.01
1
1.5
1
0.99
0.98
0.5
0
0.97
0.96
-55
T
J
(°C)
-55
T
J
(°C)
145
-5
45
145
-5
45
95
95
Figure 12. Source-drain diode forward
characteristics
AM18097v1
SD
(V)
V
T
J
=-55°C
0.9
T
J
=25°C
0.8
0.7
T
J
=175°C
0.6
0.5
5
10
15
20
25
30
I
SD
(A)
DocID027022 Rev 2
7/16
16
Test circuits
STL92N10F7AG
3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
V
DD
12V
47k
Ω
1k
Ω
100nF
2200
μ
F
3.3
μ
F
R
L
I
G
=CONST
V
DD
100
Ω
V
i
=20V=V
GMAX
D.U.T.
V
D
R
G
V
GS
2200
μ
F
D.U.T.
V
G
2.7k
Ω
47k
Ω
P
W
1k
Ω
P
W
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
L
A
A
A
B
D
S
FAST
DIODE
L=100
μ
H
V
D
G
2200
μ
F
D.U.T.
B
3.3
μ
F
V
DD
3.3
μ
F
1000
μ
F
B
V
DD
25
Ω
I
D
D
G
R
G
S
V
i
D.U.T.
P
w
AM01470v1
AM01471v1
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
t
on
t
off
td
off
V
(BR)DSS
t
r
t
f
td
on
V
D
90%
10%
90%
I
DM
10%
V
GS
V
DS
I
D
0
0
V
DD
V
DD
90%
10%
AM01472v1
AM01473v1
8/16
DocID027022 Rev 2
STL92N10F7AG
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
DocID027022 Rev 2
9/16
16
Package mechanical data
STL92N10F7AG
4.1
PowerFLAT™ 5×6 WF type R package information
Figure 19. PowerFLAT™ 5×6 WF type R package outline
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10/16
DocID027022 Rev 2
STL92N10F7AG
Package mechanical data
Table 8. PowerFLAT™ 5×6 WF type R mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A2
b
0.80
0.02
1.00
0.05
0.25
0.30
5.00
6.20
4.15
3.50
0.50
5.40
6.60
4.45
3.70
D
5.20
6.40
E
D2
E2
e
1.27
L
0.70
0.90
L1
K
0.275
1.275
2.35
0.40
0.08
1.575
2.55
0.60
0.28
E3
E4
E5
DocID027022 Rev 2
11/16
16
Package mechanical data
STL92N10F7AG
Figure 20. PowerFLAT™ 5×6 recommended footprint
ꢂꢃꢄꢅꢂꢅꢆB)22735,17B5ꢅꢅ
12/16
DocID027022 Rev 2
STL92N10F7AG
Package mechanical data
4.2
PowerFLAT™ 5×6 packing information
Figure 21. PowerFLAT™ 5×6 type WF tape
(a)
P2
Po
4.0
0.1(II)
Do
1.50
0.0
E1
1.75
0.1
T
2.0
0.05(I)
+
0.1
0.30 0.05
Y
D1
1.50
MIN
R0.30
MAX
Y
Ao(6.70 0.1ꢀ
Ko (1.20
0.1ꢀ
P1(8.00 0.1ꢀ
SECTION Y-Y
(I)
Measured from centreline of sprocket hole
to centreline of pocket.
(II)
(III)
Cumulative tolerance of 10 sprocket
holes is
0.20 .
Measured from centreline of sprocket
hole to centreline of pocket.
Base and bulk quantity 3000 pcs
8234350_
T
a
peWF_rev_C
Figure 22. PowerFLAT™ 5×6 package orientation in carrier tape
Pin 1
identification
a. All
dimensions are in millimeters.
DocID027022 Rev 2
13/16
16
Package mechanical data
STL92N10F7AG
Figure 23. PowerFLAT™ 5×6 reel
R0.60
W3
11.9/15.4
P
A
RT NO.
1.90
2.50
W2
18.4 (max)
R25.00
ØN
178( 2.0)
A
330 (+0/-4.0)
4.00
2.50
ESD LOGO
W1
12.4 (+2/-0)
ØA
R1.10
Ø21.2
All dimensions are in millimeters
13.00
CORE DE
T
A
IL
8234350_Reel_rev_C
14/16
DocID027022 Rev 2
STL92N10F7AG
Revision history
5
Revision history
Table 9. Document revision history
Changes
Date
Revision
16-Oct-2014
1
First release.
12-Oct-2015
2
Datasheet promoted from preliminary data to production data
Minor text changes
DocID027022 Rev 2
15/16
16
STL92N10F7AG
IMPORTANT NOTICE – PLEASE READ CAREFUL
L
Y
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DocID027022 Rev 2
