STMicroelectronics-STM32WB55VCY7TR
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STM32WB55xx
STM32WB35xx
Multiprotocol wireless 32-bit MCU Arm
®
-based Cortex
®
-M4
with FPU, Bluetooth
®
5 and 802.15.4 radio solution
Datasheet
–
production data
Features
.
Includes ST state-of-the-art patented
technology
Radio
UFQFPN48
7 x 7 mm solder pad
VFQFPN68
8 x 8 mm solder pad
– 2.4
GHz
®
– RF
transceiver supporting Bluetooth
5
specification, IEEE 802.15.4-2011 PHY
and MAC, supporting Thread and
FBGA
®
Zigbee 3.0
®
– RX
sensitivity: -96 dBm (Bluetooth
Low
WLCSP100
0.4 mm pitch
UFBGA129
0.5 mm pitch
Energy at 1 Mbps), -100 dBm (802.15.4)
– Programmable
output power up to +6 dBm
with 1 dB steps
®
®
Core: Arm
32-bit Cortex
-M4 CPU with FPU,
adaptive real-time accelerator (ART
– Integrated
balun to reduce BOM
– Support
for 2 Mbps
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 64 MHz,
MPU, 80 DMIPS and DSP instructions
®
®
– Dedicated
Arm 32-bit
Cortex M0+
CPU
for real-time Radio layer
Performance benchmark
– Accurate
RSSI to enable power control
– 1.25
DMIPS/MHz (Drystone 2.1)
– Suitable
for systems requiring compliance
with radio frequency regulations ETSI EN
300 328, EN 300 440, FCC CFR47 Part 15
and ARIB STD-T66
®
– 219.48
CoreMark (3.43
CoreMark/MHz at
64 MHz)
Energy benckmark
– 303
ULPMark™ CP score
– Support
for external PA
– Available
integrated passive device (IPD)
companion chip for optimized matching
solution (MLPF-WB55-01E3 or
MLPF-WB55-02E3)
Supply and reset management
– High
efficiency embedded SMPS
step-down converter with intelligent bypass
mode
Ultra-low-power platform
– Ultra-safe,
low-power BOR (brownout
reset) with five selectable thresholds
– 1.71
to 3.6 V power supply
– –
40 °C to 85 / 105 °C temperature ranges
– 13
nA shutdown mode
– Ultra-low-power
POR/PDR
– Programmable
voltage detector (PVD)
– V
mode with RTC and backup registers
– 600
nA Standby mode + RTC + 32 KB
RAM
BAT
Clock sources
– 2.1
µA Stop mode + RTC + 256 KB RAM
– 32
MHz crystal oscillator with integrated
trimming capacitors (Radio and CPU clock)
– Active-mode
MCU: < 53 µA / MHz when RF
and SMPS on
– 32
kHz crystal oscillator for RTC (LSE)
– Radio:
Rx 4.5 mA / Tx at 0 dBm 5.2 mA
– Internal
low-power 32 kHz (±5%) RC (LSI1)
– Internal
low-power 32 kHz (stability
±500 ppm) RC (LSI2)
November 2020
DS11929 Rev 10
This is information on a product in full production.
STM32WB55xx STM32WB35xx
– Internal
multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25% accuracy)
– 1x
USB 2.0 FS device, crystal-less, BCD
and LPM
–
T
o
uch
sensing controller, up to 18 sensors
– LCD
8×40 with step-up converter
– 1x
16-bit, four channels advanced timer
– 2x
16-bit, two channels timer
– 1x
32-bit, four channels timer
– 2x
16-bit ultra-low-power timer
– 1x
independent Systick
– High
speed internal 16 MHz factory
trimmed RC (±1%)
– 2x
PLL for system clock, USB, SAI and
ADC
Memories
– Up
to 1 MB Flash memory with sector
protection (PCROP) against R/W
– 1x
independent watchdog
®
operations, enabling authentic Bluetooth
– 1x
window watchdog
Low Energy and 802.15.4 SW stack
Security and ID
– Up
to 256 KB SRAM, including 64 KB with
hardware parity check
– Secure
firmware installation (SFI) for
®
Bluetooth Low
Energy and 802.15.4 SW
– 20×32-bit
backup register
stack
– Boot
loader supporting USAR
T
,
S
PI, I2C
and USB interfaces
– 3x
hardware encryption AES maximum
®
®
256-bit for the application, the Bluetooth
Low Energy and IEEE802.15.4
– OTA
(over the air) Bluetooth
Low Energy
and 802.15.4 update
– Customer
key storage / key manager
services
– Quad
SPI memory interface with XIP
– 1
Kbyte (128 double words) OTP
– HW
public key authority (PKA)
Rich analog peripherals (down to 1.62 V)
– Cryptographic
algorithms: RSA,
– 12-bit
ADC 4.26 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
Diffie-Helman, ECC over GF(p)
– True
random number generator (RNG)
– 2x
ultra-low-power comparator
– Sector
protection against R/W operation
(PCROP)
– Accurate
2.5 V or 2.048 V reference
voltage buffered output
– CRC
calculation unit
System peripherals
– Die
information: 96-bit unique ID
– IEEE
64-bit unique ID. Possibility to derive
– Inter
processor communication controller
®
(IPCC) for communication with Bluetooth
Low Energy and 802.15.4
®
802.15.4 64-bit and Bluetooth
Low Energy
48-bit EUI
– HW
semaphores for resources sharing
between CPUs
Up to 72 fast I/Os, 70 of them 5 V-tolerant
Development support
– 2x
DMA controllers (7x channels each)
supporting ADC, SPI, I2C, USAR
T
,
Q
SPI,
SAI, AES, timers
– Serial
wire debug (SWD), JTAG for the
application processor
– Application
cross trigger with input / output
– 1x
USART (ISO 7816, IrDA, SPI Master,
Modbus and Smartcard mode)
– Embedded
Trace Macrocell™ for
application
– 1x
LPUART (low power)
– 2x
SPI 32 Mbit/s
All packages are ECOPACK2 compliant
– 2x
I2C (SMBus/PMBus)
– 1x
SAI (dual channel high quality audio)
Table 1. Device summary
Part numbers
Reference
STM32WB55CC, STM32WB55CE, STM32WB55CG, STM32WB55RC, STM32WB55RE, STM32WB55RG,
STM32WB55VC, STM32WB55VE, STM32WB55VG, STM32WB55VY
STM32WB55xx
STM32WB35xx
STM32WB35CC, STM32WB35CE
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Contents
Contents
Introduction .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Architecture .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Memories .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
RF subsystem
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
RF pin description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low-power modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
VBAT operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.10 Clocks
and startup
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.13 Interrupts
and events
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
DS11929 Rev 10
6
Contents
STM32WB55xx STM32WB35xx
3.14 Analog
to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
3.14.1
T
e
mperature
sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.16 Comparators
(COMP) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
3.17
T
o
uch
sensing controller (TSC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
3.18 Liquid
crystal display controller (LCD)
. . . . . . . . . . . . . . . . . . . . . . . . . . .
49
3.20 Timers
and watchdogs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
3.20.1 Advanced-control
timer (TIM1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.20.6 SysTick
timer .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.22 Inter-integrated
circuit interface (I
2
C) .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
53
3.25 Serial
peripheral interface (SPI1, SPI2)
. . . . . . . . . . . . . . . . . . . . . . . . . .
55
3.26 Serial
audio interfaces (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
3.28 Development
support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Parameter conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Contents
Typical values
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical curves
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Loading capacitor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Pin input voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Operating conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
6.3.10 External
clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.11 Internal
clock source characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.12 PLL
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.13 Flash
memory characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.14 EMC
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.15 Electrical
sensitivity characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.3.16 I/O
current injection characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.17 I/O
port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.18 NRST
pin characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.19 Analog
switches booster
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.22 Comparator
characteristics .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
monitoring characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
BAT
6.3.26 LCD
controller characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.27 Timer
characteristics .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.28 Clock
recovery system (CRS)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DS11929 Rev 10
6
Contents
STM32WB55xx STM32WB35xx
Thermal characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
183
Ordering information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS11929 Rev 10
STM32WB55xx STM32WB35xx
List of tables
List of tables
Device summar
y
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Access status vs. readout protection level and execution modes
. . . . . . . . . . . . . . . . . . . 20
Power supply typical components
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DMA implementation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Internal voltage reference calibration values
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I2C implementatio
n
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3
STM32WB55xx pin and ball definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STM32WB35xx pin and ball definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RF transmitter BLE characteristics (1 Mbps)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RF transmitter BLE characteristics (2 Mbps)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
RF receiver BLE characteristics (1 Mbps)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
RF receiver BLE characteristics (2 Mbps)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
RF transmitter 802.15.4 characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
RF receiver 802.15.4 characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Operating conditions at power-up / power-down
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Embedded internal voltage referenc
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
8
running from SRAM1, VDD = 3.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
with different codes running from SRAM1, VDD = 3.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . 103
DS11929 Rev 10
9
List of tables
STM32WB55xx STM32WB35xx
Current consumption in Standby mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Current consumption in VBAT mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Low-power mode wakeup timings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
MSI oscillator characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Flash memory endurance and data retentio
n
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
30
EMS characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Output voltage characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
NRST pin characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Analog switches booster characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
39
ADC characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
monitoring characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
BAT
LC
D controller characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
56
DS11929 Rev 10
STM32WB55xx STM32WB35xx
List of tables
Table 100.
UFBGA129 mechanical data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 101.
UFBGA129 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 102.
WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 103.
WLCSP100 recommended PCB design rules
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 104.
VFQFPN68 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 105.
UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 106.
Package thermal characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
83
Table 107.
Document revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS11929 Rev 10
9
List of figures
STM32WB55xx STM32WB35xx
List of figures
Power-up/down sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32WB55xx – Power supply overvie
w
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
9
STM32WB35xx – Power supply overvie
w
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
0
Figure 12.
STM32WB55Vx WLCSP100 ballout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 13.
STM32WB55Vx UFBGA129 ballout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
. . . . . . . . . . . . . . . . . . . . . . 58
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
(1)
Figure 14.
Pin loading condition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
1
Figure 15.
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 16.
Power supply scheme (all packages except UFBGA129 and WLCSP100) . . . . . . . . . . . . 82
Figure 17.
Power supply scheme (UFBGA129 and WLCSP100 packages) . . . . . . . . . . . . . . . . . . . . 83
Figure 18.
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 19.
Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 20.
Typical energy detection (T = 27°C, VDD = 3.3 V
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
5
Figure 21.
VREFINT vs. temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 22.
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 23.
Low-speed external clock source AC timing diagra
m
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
21
Figure 24.
HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 25.
Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 26.
HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 27.
I/O input characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 28.
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 29.
ADC accuracy characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
51
Figure 30.
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 31.
SPI timing diagram – slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 32.
SPI timing diagram – slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33.
SPI timing diagram – master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 34.
Quad-SPI timing diagram – SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 35.
Quad-SPI timing diagram – DDR mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 36.
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 37.
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 38.
UFBGA129 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 39.
UFBGA129 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 40.
UFBGA129 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 41.
WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 42.
WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 43.
WLCSP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 44.
VFQFPN68 package outlin
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
77
Figure 45.
VFQFPN68 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 46.
VFQFPN68 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 47.
UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 48.
UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DS11929 Rev 10
STM32WB55xx STM32WB35xx
List of figures
Figure 49.
STM32WB55xx UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . 182
Figure 50.
STM32WB35xx UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . 182
DS11929 Rev 10
11
Introduction
STM32WB55xx STM32WB35xx
1
Introduction
This document provides the ordering information and mechanical device characteristics of
®
(a)
the STM32WB55xx and STM32WB35xx microcontrollers, based on Arm
cores
.
This document must be read in conjunction with the reference manual (RM0434), available
®
®
®
For information on the Arm
Cortex -M4
and Cortex
-M0+ cores, refer, respectively, to the
®
®
Cortex -M4
T
e
chnical Reference Manual and to the Cortex
-M0+
T
e
chnical Reference
For information on 802.15.4 refer to the IEEE website (www.ieee.org).
®
a. Arm
is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Description
2
Description
The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power
®
devices embed a powerful and ultra-low-power radio compliant with the Bluetooth
Low
®
Energy SIG specification v5.0 and with IEEE 802.15.4-2011. They contain a dedicated Arm
®
Cortex -M0+
for performing all the real-time low layer operation.
The devices are designed to be extremely low-power and are based on the high-
®
®
performance Arm
Cortex -M4
32-bit RISC core operating at a frequency of up to 64 MHz.
®
This core features a Floating point unit (FPU) single precision that supports all Arm
single-precision data-processing instructions and data types. It also implements a full set of
DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional
channels. The HSEM provides hardware semaphores used to share common resources
between the two processors.
The devices embed high-speed memories (up to 1 Mbyte of Flash memory for
STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for
STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI Flash memory interface
(available on all packages) and an extensive range of enhanced I/Os and peripherals.
Direct data transfer between memory and peripherals and from memory to memory is
supported by fourteen DMA channels with a full flexible channel mapping by the DMAMUX
peripheral.
The devices feature several mechanisms for embedded Flash memory and SRAM: readout
protection, write protection and proprietary code readout protection. Portions of the memory
®
can be secured for Cortex
-M0+ exclusive access.
The two AES encryption engines, PKA and RNG enable lower layer MAC and upper layer
cryptography. A customer key storage feature may be used to keep the keys hidden.
The devices offer a fast 12-bit ADC and two ultra-low-power comparators associated with a
high accuracy reference voltage generator.
These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose
32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers.
In addition, up to 18 capacitive sensing channels are available for STM32WB55xx (not on
UFQFPN48 package). The STM32WB55xx also embed an integrated LCD driver up to 8×40
or 4×44, with internal step-up converter.
The STM32WB55xx and STM32WB35xx also feature standard and advanced
communication interfaces, namely one USART (ISO 7816, IrDA, Modbus and Smartcard
mode), one low- power UART (LPUART), two I2Cs (SMBus/PMBus), two SPIs (one for
STM32WB35xx) up to 32 MHz, one serial audio interface (SAI) with two channels and three
PDMs, one USB 2.0 FS device with embedded crystal-less oscillator, supporting BCD and
LPM and one Quad-SPI with execute-in-place (XIP) capability.
The STM32WB55xx and STM32WB35xx operate in the -40 to +105 °C (+125 °C junction)
and -40 to +85 °C (+105 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes enables the design of low-power applications.
The devices include independent power supplies for analog input for ADC.
DS11929 Rev 10
57
Description
STM32WB55xx STM32WB35xx
The STM32WB55xx and STM32WB35xx integrate a high efficiency SMPS step-down
converter with automatic bypass mode capability when the V
falls below V
(x=1, 2, 3,
DD
BORx
4) voltage level (default is 2.0 V). It includes independent power supplies for analog input for
ADC and comparators, as well as a 3.3 V dedicated supply input for USB.
A V
dedicated supply allows the devices to back up the LSE 32.768 kHz oscillator, the
BAT
RTC and the backup registers, thus enabling the STM32WB55xx and STM32WB35xx to
supply these functions even if the main V
is not present through a CR2032-like battery, a
DD
Supercap or a small rechargeable battery.
The STM32WB55xx offer four packages, from 48 to 129 pins. The STM32WB35xx offer one
package, 48 pins.
Table 2. STM32WB55xx and STM32WB35xx devices features and peripheral counts
Feature
STM32WB55Cx
STM32WB55Rx
STM32WB55Vx
STM32WB35Cx
Flash
256 K
512 K
1 M
256 K
512 K
1 M
256 K
512 K
1 M
640 K
256 K
512 K
Memory
density
(bytes)
SRAM
128 K
256 K
256 K
128 K
256 K
256 K
128 K
256 K
64 K
192 K
64 K
192 K
64 K
64 K
256 K
192 K
96 K
SRAM1
SRAM2
32 KB
BLE
V5.0 (2 Mbps)
Yes
802.15.4
Advanced
1 (16 bits)
General
purpose
2 (16 bits) + 1 (32 bits)
Timers
Low power
SysTick
SPI
2 (16 bits)
1
1
2
1
I2C
2
USART
(1)
LPUART
SAI
1
1
2 channels
USB FS
QSPI
Yes
1
RTC
1
T
a
mper pin
1
2
3
1
Wakeup pin
5
2
LCD, COMxSEG
GPIOs
Y
e
s, 4×13
Y
e
s, 4×28
Yes, 8×40 or 4×44
No
30
No
30
49
6
72
18
Capacitive sensing
No
12-bit ADC
Number of channels
13 channels
(incl. 3 internal)
19 channels
(incl. 3 internal)
13 channels
(incl. 3 internal)
Internal V
ref
Yes
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Description
Table 2. STM32WB55xx and STM32WB35xx devices features and peripheral counts (continued)
Feature
STM32WB55Cx
STM32WB55Rx
STM32WB55Vx
STM32WB35Cx
Analog comparator
Max CPU frequency
2
64 MHz
-4
0
t
o
+85
°C
-40 to +85 and –
40 to +105 °C
Ambient
-40 to +85 and -40 to +105 °C
-40 to +105 and -40 to +125 °C
-4
0
t
o
+105
°C
-40 to +105 and
-40 to +125 °C
Junction
Operating voltage
1.71 to 3.6 V
WLCSP100
0.4 mm pitch
UFQFPN48
7 mm x 7 mm
0.5 mm pitch,
solder pad
VFQFPN68
8 mm x 8 mm
0.4 mm pitch,
solder pad
UFQFPN48
7 mm x 7 mm
0.5 mm pitch,
solder pad
Package
UFBGA129
0.5 mm pitch
–
1. USART
peripheral can be used as SPI.
DS11929 Rev 10
57
Description
STM32WB55xx STM32WB35xx
Figure 1. STM32WB55xx block diagram
APB asynchronous
RCC2
NVIC
BLE IP
802.15.4
LSI2
32 kHz
BLE / 802.15.4
HSE2
32 MHz
Cortex-M0+
RF IP
WKUP
BLE
32 KB SRAM2a
Backup
LSE
RTC2
I-WDG
TAMP
32 kHz
32 KB SRAM2b
LSI1
32 kHz
PKA + RAM
HSEM
RNG
PLL1
ETM
NVIC
HSI 1%
16 MHz
and
IPCC
Cortex-M4
(DSP)
MSI up to
48 MHz
PLL2
RCC + CSS
PWR
Power supply POR/
PDR/BOR/PVD/AVD
FPU
MPU
QSPI – XIP
DMA1
7 channels
DMA2
7 channels
DMAMUX
EXTI
CRS
RC48
AES2
USB FS + RAM
WWDG
Up to 192 KB
SRAM1
DBG
T
e
mp (
o
C) sensor
GPIO Ports
A, B, C, D, E, H
SPI1
SPI2
ADC1 16-bit ULP
4.26 Msps / 19 ch
CRC
TSC
LCD
I2C1
AES1
LPTIM1
LPTIM2
SAI1
I2C3
APB
TIM1
LPUART1
TIM2
USART1
SYSCFG/COMP/VREF
TIM16, TIM17
MS41407V6
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Description
Figure 2. STM32WB35xx block diagram
APB asynchronous
RCC2
NVIC
BLE IP
802.15.4
LSI2
32 kHz
BLE / 802.15.4
HSE2
32 MHz
Cortex-M0+
RF IP
WKUP
BLE
32 KB SRAM2a
Backup
LSE
RTC2
I-WDG
TAMP
32 kHz
32 KB SRAM2b
LSI1
32 kHz
PKA + RAM
HSEM
RNG
PLL1
HSI 1%
16 MHz
NVIC
And
IPCC
PLL2
MSI up to
48 MHz
Cortex-M4
(DSP)
RCC + CSS
PWR
Power supply POR/
PDR/BOR/PVD/AVD
FPU
MPU
QSPI – XIP
DMA1
7 channels
DMA2
7 channels
DMAMUX
EXTI
CRS
RC48
AES2
USB FS + RAM
WWDG
32 KB SRAM1
DBG
T
e
mp (
o
C) sensor
GPIO Ports
A, B, C, E, H
SPI1
ADC1 16-bit ULP
4.26 Msps / 19 ch
CRC
I2C1
I2C3
AES1
APB
TIM1
LPTIM1
LPTIM2
SAI1
LPUART1
USART1
TIM2
TIM16, TIM17
SYSCFG/COMP
MS53592V1
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
3
Functional overview
3.1
Architecture
The STM32WB55xx and STM32WB35xx multiprotocol wireless devices embed a BLE and
an 802.15.4 RF subsystem that interfaces with a generic microcontroller subsystem using
®
®
an Arm
Cortex -M4
CPU (called CPU1) on which the host application resides.
The RF subsystem is composed of an RF analog front end, BLE and 802.15.4 digital MAC
®
®
blocks as well as of a dedicated Arm
Cortex -M0+
microcontroller (called CPU2), plus
proprietary peripherals. The RF subsystem performs all of the BLE and 802.15.4 low layer
stack, reducing the interaction with the CPU1 to high level exchanges.
Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU
(CPU1):
Flash memories
SRAM1, SRAM2a and SRAM2b (SRAM2a can be retained in Standby mode)
Security peripherals (RNG, AES1, PKA)
Clock RCC
Power control (PWR)
The communication and the sharing of peripherals between the RF subsystem and the
®
Cortex -M4
CPU is performed through a dedicated inter processor communication
controller (IPCC) and semaphore mechanism (HSEM).
3.2
Arm
®
Cortex
®
-M4 core with FPU
®
®
The Arm
Cortex -M4
with FPU is a processor for embedded systems. It has been
developed to provide a low-cost platform that meets the needs of MCU implementation, with
a reduced pin count and low-power consumption, while delivering outstanding
computational performance and an advanced response to interrupts.
®
®
The Arm
Cortex -M4
with FPU 32-bit RISC processor features exceptional
®
code-efficiency, delivering the high-performance expected from an Arm
core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions enabling efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
®
With its embedded Arm
core, the STM32WB55xx and STM32WB35xx are compatible with
®
all Arm
tools and software.
and STM32WB35xx devices.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.3
Memories
3.3.1
Adaptive real-time memory accelerator (ART Accelerator)
®
The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm
®
®
Cortex -M4
processors. It balances the inherent performance advantage of the Arm
®
Cortex -M4
over Flash memory technologies, which normally require the processor to wait
for the Flash memory at higher frequencies.
To
r
elease the processor near 80 DMIPS performance at 64 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 64 MHz.
3.3.2
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas, which can be divided
up into eight subareas. The protection area sizes are between 32 bytes and the whole
4 Gbytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system). If a program accesses a memory location prohibited by the
MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3.3
Embedded Flash memory
The STM32WB55xx
and STM32WB35xx devices feature, respectively, up to 1 Mbyte and
512 Kbytes of embedded Flash memory available for storing programs and data, as well as
some customer keys.
Flexible protections can be configured thanks to option bytes:
Readout protection (RDP) to protect the whole memory. Three levels are available:
–
–
Level 0: no readout protection
Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in SRAM or bootloader is
selected
®
®
–
Level 2: chip readout protection: debug features (Cortex
-M4 and Cortex
-M0+
JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG
fuse). This selection is irreversible.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
Table 3. Access status vs. readout protection level and execution modes
Debug, boot from SRAM or boot
User execution
Protection
level
from system memory (loader)
Area
Read
Write
Erase
Read
Write
Erase
1
2
1
2
1
2
1
2
1
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Y
e
s
Yes
Yes
Y
e
s
Y
e
s
No
Yes
Yes
No
N/A
Y
e
s
N/A
Y
e
s
N/A
No
No
N/A
No
No
N/A
No
Main
memory
No
System
memory
No
No
N/A
Yes
N/A
No
N/A
Yes
Y
e
s
No
(1)
Y
e
s
Y
e
s
Y
e
s
Y
e
s
Yes
Option
bytes
N/A
(2)
N/A
N/A
N/A
(2)
N/A
No
(2)
N/A
Backup
registers
N/A
No
N/A
No
Yes
(2)
SRAM2a
SRAM2b
Yes
N/A
N/A
1. The
option byte can be modified by the RF subsystem.
2. Erased
when RDP changes from Level 1 to Level 0.
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4-Kbyte granularity.
Proprietary code readout protection (PCROP): two parts of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2-Kbyte granularity. An additional option bit
(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the
RDP protection is changed from Level 1 to Level 0.
A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be
accessed by the host CPU1.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
single error detection and correction
double error detection
the address of the ECC fail can be read in the ECC register
The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.3.4
Embedded SRAM
The STM32WB55xx devices feature up to 256 Kbytes of embedded SRAM, split in three
blocks:
SRAM1
: up to 192 Kbytes mapped at address 0x2000 0000
SRAM2a
: 32 Kbytes located at address 0x2003 0000 (contiguous to SRAM1) also
mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in
Standby mode)
SRAM2b
: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and
mirrored at 0x1000 8000 with hardware parity check
The STM32WB35xx devices feature 96 Kbytes of embedded SRAM, split in three blocks:
SRAM1
: 32 Kbytes mapped at address 0x2000 0000
SRAM2a
: 32 Kbytes located at address 0x2003 0000 (contiguous to SRAM1) also
mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in
Standby mode)
SRAM2b
: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and
mirrored at 0x1000 8000 with hardware parity check
SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the
SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the
host CPU1.
The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock
speeds.
3.4
Security and safety
The STM32WB55xx and STM32WB35xx contain many security blocks both for the BLE or
IEEE 802.15.4 and the Host application.
It includes:
Customer storage of the BLE and 802.15.4 keys
Secure Flash memory partition for RF subsystem-only access
Secure SRAM partition, that can be accessed only by the RF subsystem
True random number generator (RNG)
Advance encryption standard hardware accelerators (AES-128bit and AES-256bit,
supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)
Private key acceleration (PKA) including:
–
Modular arithmetic including exponentiation with maximum modulo size of 3136
bits
–
Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA
verification with maximum modulo size of 521 bits
Cyclic redundancy check calculation unit (CRC)
A specific mechanism is in place to ensure that all the code executed by the RF subsystem
CPU2 can be secure, whatever the Host application. For the AES1 a customer key can be
managed by the CPU2 and used by the CPU1 to encrypt/decrypt data.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
3.5
Boot modes and FW update
At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The devices always boot on CPU1 core. The embedded bootloader code makes it possible
to boot from various peripherals:
USB
UART
I2C
SPI
Secure Firmware update (especially BLE and 802.15.4) from system boot and over the air is
provided.
3.6
RF subsystem
The STM32WB55xx and STM32WB35xx embed an ultra-low power multi-standard radio
®
®
Bluetooth Low
Energy (BLE) and 802.15.4 network processor, compliant with Bluetooth
®
specification v5.0 and IEEE
802.15.4-2011. The BLE features 1 Mbps and 2 Mbps transfer
®
rates, supports multiple roles simultaneously acting at the same time as Bluetooth
Low
Energy sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key
agreement protocol, thus ensuring a secure connection.
®
®
The Bluetooth
Low Energy stack and 802.15.4 Low Level layer run on an embedded Arm
®
Cortex -M0+
core (CPU2). The stack is stored on the embedded Flash memory, which is
also shared with the Arm
Cortex -M4
(CPU1) application, making it possible in-field stack
update.
®
®
3.6.1
RF front-end block diagram
The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF
architecture in Rx mode.
Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna
(single ended connection, impedance close to 50
Ω
). The natural bandpass behavior of the
internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band
interferer rejection.
In Transmit mode, the maximum output power is user selectable through the programmable
LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean
power ramp-up.
In receive mode the circuit can be used in standard high performance or in reduced power
consumption (user programmable). The Automatic gain control (AGC) is able to reduce the
chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the
use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent
linearity can be achieved.
The bill of material is reduced thanks to the high degree of integration. The radio frequency
source is synthesized form an external 32 MHz crystal that does not need any external
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
trimming capacitor network thanks to a dual network of user programmable integrated
capacitors.
Figure 3. STM32WB55xx and STM32WB35xx RF front-end block diagram
Timer and Power
AGC
control
EXT_
PA_TX
RF control
G
Interrupt
Wakeup
BLE
BP
filter
LNA
modulator
BLE
controller
AHB
APB
G
BLE
demodulator
RF1
802.15.4
modulator
APB
802.15.4
MAC
Interrupt
Wakeup
802.15.4
demodulator
PLL
See
notes
Adjust
Adjust
HSE
Trimmed
bias
Max PA
level
SMPS
LDO
LDO
LDO
V
DDSMPS
V
SSSMPS
V
LXSMPS
OSC_OUT
V
FBSMPS
V
DDRF
OSC_IN
32 MHz
Notes:
– UFQFPN48 and VFQFPN68: V
SS
through exposed pad, and V
SSRF
pin must be connected to ground plane
– WLCSP100 and UFBGA129: V
SSRF
pins must be connected to ground plane
MS45477V6
3.6.2
BLE general description
®
The BLE block is a master/slave processor, compliant with Bluetooth
specification 5.0
standard (2 Mbps).
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
®
It integrates a 2.4 GHz RF transceiver and a powerful Cortex
-M0+ core, on which a
®
complete power-optimized stack for Bluetooth
Low Energy protocol runs, providing
master / slave role support
GAP: central, peripheral, observer or broadcaster roles
ATT/GAT
T
:
c
lient and server
SM: privacy, authentication and authorization
L2CAP
Link layer: AES-128 encryption and decryption
®
In addition, according to Bluetooth
specification v5.0, the BLE block provides:
Multiple roles simultaneous support
Master/slave and multiple roles simultaneously
LE data packet length extension (making it possible to reach 800 kbps at application
level)
LE privacy 1.2
LE secure connections
Flexible Internet connectivity options
High data rate (2 Mbps)
The device allows the applications to meet the tight peak current requirements imposed by
the use of standard coin cell batteries. When the high efficiency embedded SMPS
step-down converter is used, the RF front end consumption (I
) is only 8.1 mA at the
tmax
highest output power (+6 dBm).
The power efficiency of the subsystem is optimized: while running with the radio and the
®
applicative cores simultaneously using the SMPS, the Cortex
-M4 core consumption
reaches 53 µA / MHz in active mode.
Ultra-low-power sleep modes and very short transition time between operating modes result
in very low average current consumption during real operating conditions, resulting in longer
battery life.
The BLE block integrates a full bandpass balun, thus reducing the need for external
components.
®
The link between the Cortex
-M4 application processor (CPU1) running the application, and
®
the BLE stack running on the dedicated Cortex
-M0+ (CPU2) is performed through a
normalized API, using a dedicated IPCC.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.6.3
802.15.4 general description
The STM32WB55xx and STM32WB35xx embed a dedicated 802.15.4 hardware MAC:
Support for 802.15.4 release 2011
Advanced MAC frame filtering; hardwired firewall: Programmable filters based on
source/destination addresses, frame version, security enabled, frame type
256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean
RSSI, LQI)
128-byte TX FIFO with retention
–
Content not lost, retransmissions possible under CPU2 control
Automatic frame acknowledgment, with programmable delay
Advanced channel access features
–
–
–
–
Full CSMA-CA support
Superframe timer
Beaconing support (require LSE)
Flexible TX control with programmable delay
Configuration registers with retention available down to Standby mode for
software/auto-restore
Autonomous sniffer, Wakeup based on timer or CPU2 request
Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on
particular events
3.6.4
RF pin description
:
Table 4. RF pin list
Name
Type
Description
RF1
RF Input/output, must be connected to the antenna through a low-pass matching network
OSC_OUT
OSC_IN
32 MHz main oscillator, also used as HSE source
External PA transmit control
I/O
RF_TX_
MOD_EXT_PA
VDDRF
V
DD
Dedicated supply, must be connected to V
DD
V
SS
T
o
b
e connected to GND
VSSRF
(1)
1. On
packages with exposed pad, this pad must be connected to GND plane for correct RF operation.
3.6.5
Typical RF application schematic
indicative. For more details refer to the “Reference design” provided in separate documents.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
Figure 4. External components for the RF part
OSC_IN
OSC_OUT
VDDRF
X1
32 MHz
V
DD
C1
(including exposed pad)
STM32WB
microcontroller
Antenna
Cf2
VSSRF
Lf1
Cf1
RF1
Antenna filter
MS53575V1
Table 5. Typical external components
Description
Component
Value
C1
X1
Decoupling capacitance for RF
32 MHz crystal
(1)
100 nF // 100 pF
32 MHz
Antenna filter
Antenna
Antenna filter and matching network
2.4 GHz band antenna
–
1. e.g.
NDK reference: NX2016SA 32 MHz EXS00A-CS06654.
Note:
For more details refer to AN5165 “Development of RF hardware using STM32WB
3.7
Power supply management
3.7.1
Power supply distribution
The device integrate an SMPS step-down converter to improve low power performance
when the V
voltage is high enough. This converter has an intelligent mode that
DD
automatically enters in bypass mode when the V
voltage falls below a specific BORx
DD
(x = 1, 2, 3 or 4) voltage.
By default, at Reset the SMPS is in bypass mode.
The device can be operated without the SMPS by just wiring its output to V
. This is the
DD
case for applications where the voltage is low, or where the power consumption is not
critical.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
Figure 5. Power distribution
V
DD
V
DD
VDDSMPS
VDDSMPS
SMPS
SMPS
(not used)
SMPS mode or
BYPASS mode
VLXSMPS
VLXSMPS
L1
LPR
LPR
VFBSMPS
VFBSMPS
C2
RFR
MR
RFR
MR
SMPS configuration
LDO configuration
MS41409V4
Table 6. Power supply typical components
Description
Component
Value
C2
SMPS output capacitor
(1)
4.7 µF
2.2 µH
10 µH
For 8 MHz
(3)
For 4 MHz
(4)
L1
(2)
SMPS inductance
1. e.g.
GRM155R60J475KE19.
2. An
extra 10 nH inductor in series with L1 is needed to improve the receiver performance,
e.g Murata LQG15WZ10NJ02D
3. e.g.
Wurth 74479774222.
4. e.g.
Murata LQM21FN100M70L.
The SMPS can also be switched on or set in bypass mode at any time by the application
software, for example when very accurate ADC measurement are needed.
3.7.2
Power supply schemes
within the following voltage ranges:
V
= 1.71 to 3.6 V: external power supply for I/Os (V
), the internal regulator and
DDIO
DD
system functions such as R
F
,
S
MPS, reset, power management and internal clocks. It
is provided externally through VDD pins. V
connected to VDD pins.
and V
must be always
DDRF
DDSMPS
V
= 1.62 (ADC/COMPs) to 3.6 V: external analog power supply for ADC,
DDA
comparators and voltage reference buffer. The V
voltage level can be independent
DDA
from the V
voltage. When not used V
must be connected to V
.
DD
DDA
DD
V
= 3.0 to 3.6 V: external independent power supply for USB transceivers. When
DDUSB
not used V
must be connected to V
.
DDUSB
DD
V
= 2.5 to 3.6 V: the LCD controller can be powered either externally through the
LCD
VLCD pin, or internally from an internal voltage generated by the embedded step-up
converter. This converter can generate a V
voltage up to 3.6 V if V
is higher than
LCD
DD
2.0
V
.
N
ote that the LCD is available only on STM32WB55xx devices.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
During power up/down, the following power sequence requirements must be respected:
When V
is below 1 V the other power supplies (V
, V
, V
), must remain
LCD
DD
DDA
DDUSB
below V
+ 300 mV
DD
When V
is above 1 V all power supplies are independent.
DD
Figure 6. Power-up/down sequence
V
3.6
(1)
V
DDX
V
DD
V
BOR0
1
0.3
Power-on
Invalid supply area
Operating mode
V
DDX
< V
DD
+ 300 mV
Power-down
time
V
DDX
independent from V
DD
MSv47490V1
1. V
DDX
refers to any power supply among V
DDA
, V
DDUSB
and V
LCD
.
During the power down phase, V
can temporarily become lower than other supplies only
DD
if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling
capacitors to be discharged with different time constants during the power down transient
phase.
Note:
V
, V
and V
must be wired together, so they can follow the same voltage
DDSMPS
DD
DDRF
sequence.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
Figure 7. STM32WB55xx – Power supply overview
Interruptible domain (V
DD12I
)
On domain (V
DD12O
)
(CPU1, CPU2,
peripherals,
SysConfig, AIEC,
RCC, PwrCtrl,
LPTIM, LPUSART
IO
logic
SRAM1,
IOs
SRAM2b)
Power
switch
Power
switch
V
SS
V
SS
V
SS
V
FBSMPS
V
LXSMPS
MR
SMPS
V
DDSMPS
RFR
V
SSSMPS
LPR
V
DDRF
RF domain
Backup domain
Radio
V
BKP12
SRAM2a
Power switch
V
SSRF
V
SS
V
SS
(including exposed pad)
Wakeup domain (V
DDIO
)
HSI, HSE1,
2xPLL,
LSI1, LSI2,
IWDG, RF
V
DD
Power switch
V
SW
V
BAT
V
SS
Switch domain (V
SW
)
LSE, RTC,
backup
registers
VBAT
IOs
IO
logic
V
SS
V
SS
V
LCD
V
DDA
LCD
Analog domain
REF_BUF
ADC
V
REF+
=
=
V
REF+
V
REF-
V
SSA
V
DDUSB
USB
VUSB
IOs
transceiver
(1)
V
SS
USB domain (V
USB
)
V
SS
MS41410V7
1. The
USB transceiver is powered by V
DDUSB
, and the GPIOs associated with USB are powered by V
DDUSB
when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected
the GPIOs associated with USB are powered as standard GPIOs.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
Figure 8. STM32WB35xx – Power supply overview
Interruptible domain (V
DD12I
)
On domain (V
DD12O
)
(CPU1, CPU2,
peripherals,
SysConfig, AIEC,
RCC, PwrCtrl,
LPTIM, LPUSART
IO
logic
SRAM1,
IOs
SRAM2b)
Power
switch
Power
switch
V
SS
V
SS
V
SS
V
FBSMPS
V
LXSMPS
V
DDSMPS
V
SSSMPS
MR
SMPS
LPR
RFR
V
DDRF
RF domain
Backup domain
Radio
V
BKP12
SRAM2a
Power switch
V
SSRF
V
SS
V
SS
(including exposed pad)
Wakeup domain (V
DDIO
)
HSI, HSE1,
2xPLL,
LSI1, LSI2,
IWDG, RF
V
DD
Power switch
V
SW
V
BAT
V
SS
Switch domain (V
SW
)
LSE, RTC,
backup
registers
VBAT
IOs
IO
logic
V
SS
V
SS
V
DDA
Analog domain
ADC
V
REF+
=
=
V
REF-
V
SS
V
DDUSB
USB
transceiver
(1)
VUSB
IOs
V
SS
USB domain (V
USB
)
V
SS
MS53593V1
1. The
USB transceiver is powered by V
DDUSB
, and the GPIOs associated with USB are powered by V
DDUSB
when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected
the GPIOs associated with USB are powered as standard GPIOs.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.7.3
Linear voltage regulator
Three embedded linear voltage regulators supply most of the digital and RF circuitries, the
main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the SRAM2a in Standby with retention.
The RFR is used to supply the RF analog part, its activity is automatically managed by
the RF subsystem.
All the regulators are in power-down in Standby and Shutdown modes: the regulator output
is in high impedance, and the kernel circuitry is powered down, inducing zero consumption.
The ultralow-power STM32WB55xx and STM32WB35xx support dynamic voltage scaling to
optimize its power consumption in run mode. The voltage from the main regulator that
supplies the logic (VCORE) can be adjusted according to the system’s maximum operating
frequency.
There are two voltage and frequency ranges:
Range 1, with the CPU running up to 64 MHz
Range 2, with a maximum CPU frequency of 16 MHz (note that HSE can be active in
this mode). All peripheral clocks are also limited to 16 MHz.
VCORE can also be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode. In this case the CPU is running at up to
2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the
RF subsystem is not available).
3.7.4
Power supply supervisor
An integrated ultra-low-power brown-out reset (BOR) is active in all modes except
Shutdown ensuring proper operation after power-on and during power down. The devices
remain in reset mode when the monitored supply voltage V
is below a specified
DD
threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V
power supply and compares it with the V
threshold. An
DD
PVD
interrupt can be generated when V
drops below the V
threshold and/or when V
is
DD
PVD
DD
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor (PVM) that compares the
independent supply voltage V
functional supply range.
with a fixed threshold to ensure that the peripheral is in its
DDA
Any BOR level can also be used to automatically switch the SMPS step-down converter in
bypass mode when the V
voltage drops below a given voltage level. The mode of
DD
operation is selectable by register bit, the BOR level is selectable by option byte.
3.7.5
Low-power modes
These ultra-low-power devices support several low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
By default, the microcontroller is in Run mode, Range 1, after a system or a power on
Reset. It is up to the user to select one of the low-power modes described below:
Sleep
In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,
continue to operate and can wake up the CPU when an interrupt/event occurs.
Low-power run
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator operating current. The code can be executed from SRAM or from the
Flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16. The RF subsystem is not available in this
mode and must be OF
F
.
Low-power sleep
This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the
low-power run mode. The RF subsystem is not available in this mode and must be
OF
F
.
Stop 0, Stop 1 and Stop 2
Stop modes achieve the lowest power consumption while retaining the content of all
the SRAM and registers. The LSE (or LSI) is still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes
to detect their wakeup condition.
Three modes are available: Stop 0, Stop 1 and Stop 2. In Stop 2 mode, most of the
VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode the main regulator
remains ON, allowing a very fast wakeup time but with higher consumption.
In these modes the RF subsystem can wait for incoming events in all Stop modes.
The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI
up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem or the
SMPS is used the exits must be set to HSI16 only. If used, the SMPS is restarted
automatically.
Standby
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off.
The RTC can remain active (Standby mode with RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1, SRAM2b and register contents are lost except
for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be
retained in Standby mode, supplied by the low-power regulator (Standby with 32 KB
SRAM2a retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or
from the RF system wakeup).
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
The system clock after wakeup is 16 MHz, derived from the HSI16. If used, the SMPS
is restarted automatically.
In this mode the RF can be used.
Shutdown
The Shutdown mode allows to achieve the ultimate lowest power consumption. The
internal regulator is switched off so that the VCORE domain is powered off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is 4 MHz, derived from the MSI.
In this mode the RF is no longer operational.
When the RF subsystem is active, it changes the power state according to its needs (Run,
Stop, Standby). This operation is transparent for the CPU1 host application and managed by
a dedicated HW state machine. At any given time the effective power state reached is the
higher one needed by both the CPU1 and RF sub-system.
detailed in gray cells.
(1)
Table 7. Features over all modes
Stop0/Stop1
Stop 2
Standby Shutdown
Peripheral
(2)
–
–
–
–
CPU1
CPU2
Y
Y
–
–
Y
Y
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Radio system
(BLE, 802.15.4)
Y
Y
(3)
Y
–
–
Y
Y
Y
Y
Y
(4)
Y
(4)
Flash memory
SRAM1
Y
(5)
Y
Y
Y
(7)
Y
(7)
Y
(7)
O
O
(6)
O
(6)
R
R
R
R
–
–
–
R
R
R
R
–
–
–
R
–
–
–
R
–
–
–
–
–
–
–
–
R
–
Y
Y
Y
O
Y
Y
Y
(7)
Y
(7)
Y
(7)
O
SRAM2a
Y
–
–
R
(8)
–
–
–
SRAM2b
Y
–
–
–
–
–
–
Quad-SPI
O
–
–
–
–
–
–
Backup registers
Brown-out reset (BOR)
Y
Y
Y
R
Y
–
R
Y
–
R
Y
–
R
–
R
–
Y
Y
Y
Y
Y
Y
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
(1)
Table 7. Features over all modes
(continued)
Stop0/Stop1 Stop
2
Standby Shutdown
Peripheral
(2)
–
–
–
–
Programmable voltage
detector (PVD)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
Peripheral voltage monitor
PVMx (x=1, 3)
SMPS
O
O
O
O
O
O
O
O
O
(9)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DMAx (x = 1, 2)
High speed internal
(HSI16)
O
O
O
O
O
O
O
–
O
–
O
(10)
–
–
–
O
(10)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Oscillator HSI48
–
–
–
–
High speed external
(HSE)
(11)
O
O
Low speed internal
(LSI1 or LSI2)
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
O
O
–
–
–
–
O
O
–
–
–
–
–
O
–
–
–
–
–
O
–
Low speed external (LSE)
Multi-speed internal
(MSI)
(12)
48
24
48
PLLx VCO maximum
frequency
344 128
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Clock security system
(CSS)
O
O
O
O
(13)
O
O
(13)
Clock security system on
LSE
O
O
3
O
O
3
O
O
3
O
O
3
O
O
3
O
O
O
O
O
3
O
O
O
O
O
3
O
O
O
–
–
–
RTC / Auto wakeup
O
3
O
O
O
3
Number of RTC
tamper pins
LCD
O
O
O
O
O
–
O
–
O
–
O
O
O
–
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB FS
USART1
O
–
O
O
O
O
O
(14)
O
(14)
–
–
Low-power UART
(LPUART1)
O
O
O
O
(14)
O
(14)
O
(14)
O
(14)
O
(15)
O
(15)
O
(15)
O
(15)
O
(15)
O
(15)
–
–
–
–
–
I2C1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2C3
SPIx (x=1, 2)
SAI1
–
–
–
–
–
–
–
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
Standby Shutdown
(1)
Table 7. Features over all modes
(continued)
Stop0/Stop1 Stop
2
Peripheral
(2)
–
–
–
–
ADC1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VREFBUF
O
O
–
COMPx (x=1, 2)
T
e
mperature sensor
O
–
O
–
O
–
Timers TIMx
(x=1, 2, 16, 17)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Low-power Timer 1
(LPTIM1)
O
O
O
O
O
O
O
–
O
–
Low-power Timer 2
(LPTIM2)
–
–
Independent watchdog
(IWDG)
O
O
O
O
Window watchdog
(WWDG)
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SysTick timer
T
o
uch sensing controller
(TSC)
True random number
generator (RNG)
O
–
O
–
–
–
–
–
–
–
–
–
–
–
AES2 hardware accelerator
O
O
O
O
O
O
O
–
O
O
O
O
O
O
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CRC calculation unit
IPCC
HSEM
PKA
–
–
O
O
5
pins
5
pins
(16)
(17)
GPIOs
O
O
O
O
O
O
O
O
–
1. Legend:
Y = Yes (Enabled), O = Optional (Disabled by default, can be enabled by software), R = Data retained,
– = Not available.
2. Available
peripherals depend upon package, STM32WB35xx features one SPI, no LCD, no TSC and two wakeup pins. See
3. Bluetooth
®
Low Energy not possible in this mode.
4. Standby
with SRAM2a retention mode only.
5. Flash
memory programming only possible in Range 1 voltage, not in Range 2 and not in Low Power mode.
6. The
Flash memory can be configured in Power-down mode. By default, it is not in Power-down mode.
7. The
SRAM clock can be gated on or off.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
8. SRAM2a
content is preserved when the bit RRS is set in PWR_CR3 register.
9. Stop
0 only. SMPS is automatically switched to Bypass or Open mode during Low power operation.
10. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
11. The
HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).
12. MSI maximum frequency.
13. In case RF will be used and HSE will fail.
14. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
15. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
16. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
17. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
DS11929 Rev 10
Table 8. STM32WB55xx and STM32WB35xx modes overview
Mode
Regulator CPU1
Flash
SRAM
Clocks
DMA and peripherals
(1)
Wakeup source
Consumption
(2)
Wakeup time
Range 1
Yes
Range 2
All
107 µA/MHz
100 µA/MHz
Run
ON
(3)(4)
ON
Any
Any
N/A
N/A
All except RNG and USB-FS
LPRun
Sleep
LPR
Yes
No
No
ON
(3)
ON
(3)
ON
(3)
ON
except All
except R
F
,
R
NG and USB-FS
PLL
N/A
103 µA/MHz
15.33 µs
9 cycles
9 cycles
Range 1
Range 2
All
41 µA/MHz
46 µA/MHz
Any interrupt
or event
ON
(5)
ON
(5)
Any
All except RNG and USB-FS
Any
Any interrupt
or event
LPSleep
LPR
All except R
F
,
R
NG and USB-FS
except
PLL
45 µA/MHz
Reset pin, all I/Os,
R
F
,
B
OR, PVD, PVM
R
F
,
B
OR, PVD, PVM
RTC, LCD, IWDG
Range 1
RTC, LCD, IWDG
COMPx (x=1, 2)
USART1
COMPx (x=1, 2)
LSE,
USART1
(8)
LSI,
Stop 0
No
OFF
ON
100 µA
1.7 µs
HSE
(6)
,
LPUART1
(8)
I2Cx (x=1, 3)
(9)
LPUART1
HSI16
(7)
Range 2
I2Cx (x=1, 3)
LPTIMx (x=1, 2)
USB
LPTIMx (x=1, 2), SMPS
All other peripherals are frozen.
Reset pin, all I/Os
R
F
,
B
OR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1, 2)
USART1
R
F
,
B
OR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1, 2)
LSE,
LSI,
USART1
(8)
LPUART1
(8)
I2Cx (x=1, 3)
(9)
9.2 µA w/o RTC
9.6 µA w RTC
Stop 1
LPR
No
OFF
ON
4.7 µs
HSE
(6)
,
HSI16
(7)
LPUART1
I2Cx (x=1, 3)
LPTIMx (x=1, 2)
USB
LPTIMx (x=1, 2)
All other peripherals are frozen.
Table 8. STM32WB55xx and STM32WB35xx modes overview (continued)
Mode
Regulator CPU1
Flash
SRAM
Clocks
DMA and peripherals
(1)
Wakeup source
Consumption
(2)
Wakeup time
R
F
,
B
OR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1, 2)
LPUART1
(8)
Reset pin, all I/Os
R
F
,
B
OR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1, 2)
LPUART1
1.85 µA w/o RTC
2.1 µA w RTC
LSE,
LSI
Stop 2
LPR
No
OFF
ON
5.71 µs
I2C3
(9)
LPTIM1
I2C3
All other peripherals are frozen.
LPTIM1
R
F
,
B
OR, RTC, IWDG
0.32 µA w/o RTC
0.60 µA w RTC
SRAM2a
ON
(10)
LPR
OFF
R
F
,
R
eset pin
5 I/Os (WKUPx)
(11)
BOR, RTC, IWDG
All other peripherals are
powered off.
LSE,
LSI
Standby
No
No
OFF
OFF
51 µs
0.11 µA w/o RTC
0.390 µA w RTC
I/O configuration can be floating,
pull-up or pull-down
OFF
RTC
All other peripherals are
powered off.
5 I/Os (WKUPx)
(11)
RTC
,
0.028 µA w/o RTC
0.315 µA w/ RTC
Shutdown
OFF
OFF
LSE
–
I/O configuration can be floating,
pull-up or pull-down
(12)
1. Available
peripherals depend upon packa
ge, STM32WB35xx feat
ures one SPI, no LCD, no TSC and two wakeup pins. See
T
a
ble 2: STM32WB55xx and STM32WB35xx
devices features and peripheral counts
for more details.
3. The
Flash memory controller can be placed in power-dow
n mode if
the RF subsystem is not in use and all the program is run from the SRAM.
7. HSI16
(16 MHz) automatically used by some peripherals.
8. U(S)ART
and LPUART reception is functional in Stop mode
, and
generates a wakeup interrupt on Start, Address match or Received frame event.
9. I2C
address detection is functional in Stop mode, and gene
rates a wakeup interr
upt in case of address match.
10. SRAM1 and SRAM2b are OF
F
.
12. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.
STM32WB55xx STM32WB35xx
Functional overview
3.7.6
Reset mode
To
i
mprove the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.8
VBAT operation
The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)
from an external battery, an external supercapacitor, or from V
when no external battery
DD
nor an external supercapacitor are present. Three anti-tamper detection pins are available
in VBAT mode.
VBAT operation is automatically activated when V
is not present.
DD
An internal VBAT battery charging circuit is embedded and can be activated when V
is
DD
present.
Note:
When the microcontroller is supplied only from VBA
T
,
e
xternal interrupts and RTC
alarm/events do not exit it from VBAT operation.
3.9
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU1 resources and, consequently, reducing
power supply consumption. In addition, these hardware connections result in fast and
predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run and Sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix
Source
Destination
Action
TIMx
ADC1
DMA
Timers synchronization or chaining
Conversion triggers
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
–
–
–
–
TIMx
Memory to memory transfer trigger
Comparator output blanking
COMPx
TIM1
TIM2
Timer input channel, trigger, break
from analog signals comparison
Y
Y
Y
Y
–
–
COMPx
ADC1
Low-power timer triggered by analog
signals comparison
LPTIMERx
TIM1
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
Y
(1)
–
Timer triggered by analog watchdog
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix (continued)
Source
Destination
Action
TIM16
Timer input channel from RTC events
Y
Y
Y
Y
Y
Y
Y
Y
–
–
RTC
Low-power timer triggered by RTC
alarms or tampers
LPTIMERx
Y
Y
(1)
All clock sources
(internal and external)
TIM2
TIM16, 17
Clock source used as input channel
for RC measurement and trimming
Y
Y
Y
Y
Y
–
Y
–
–
–
–
–
USB
TIM2
Timer triggered by USB SOF
CSS
CPU (hard fault)
SRAM (parity error)
Flash memory (ECC error)
COMPx
TIM1
TIM16,17
Timer break
Y
Y
Y
Y
–
–
PVD
TIMx
External trigger
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
Y
–
–
Y
(1)
–
GPIO
LPTIMERx External
trigger
ADC1 Conversion
external trigger
1. LPTIM1
only.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.10
Clocks and startup
The STM32WB55xx and STM32WB35xx devices integrate several clock sources:
LSE: 32.768 kHz external oscillator, for accurate RTC and calibration with other
embedded RC oscillators
LSI1: 32 kHz on-chip low-consumption RC oscillator
LSI2: almost 32 kHz, on-chip high-stability RC oscillator, used by the RF subsystem
HSE: high quality 32 MHz external oscillator with trimming, needed by the RF
subsystem
HSI16: 16 MHz high accuracy on-chip RC oscillator
MSI: 100 kHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed
using the LSE signal
HSI48: 48 MHz on-chip RC oscillator, for USB crystal-less purpose
oscillators to the core and the peripherals including the RF subsystem. It also manages
clock gating for low power modes and ensures clock robustness. It features:
Clock prescaler:
to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching:
clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management:
to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source:
four different clock sources can be used to drive the master
clock SYSCLK:
–
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
–
System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of
64 MHz.
Auxiliary clock source:
two ultralow-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2
on-chip oscillator.
Peripheral clock sources:
Several peripherals (RNG, SAI, USAR
T
s
, I2Cs, LPTimers,
ADC) have their own independent clock whatever the system clock. Two PLLs, each
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
having three independent outputs for the highest flexibility, can generate independent
clocks for the ADC, the RNG and the SAI.
Startup clock:
after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS):
this feature can be enabled by software. If an HSE
clock failure occurs, the master clock is automatically switched to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and an interrupt
generated.
Clock-out capability:
–
MCO: microcontroller clock output:
it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSIx, LSE) are available
down to Stop 1 low power state.
–
LSCO: low speed clock output:
it outputs LSI or LSE in all low-power modes
down to Standby.
Several prescalers allow the user to configure the AHB frequencies, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 64 MHz.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
Figure 9. Clock tree
LSI1 RCC 32 kHz
to IWDG
LSI
LSI2 RCC 32 kHz
LSCO
LSI
to RTC and LCD
(1)
to BLE wakeup
LSE
LSE OSC
32.768 kHz
OSC32_OUT
LSE
OSC32_IN
to 802.15.4 wakeup
LSE CSS
LSI1
/32
CPU1
HPRE
/1,2,…,512
to CPU1, AHB1, AHB2, AHB3, and SRAM1
to CPU1 FCLK
LSI2
HCLK1
/32
LSE
to CPU1 system timer
/8
HSE
MCO
SYSCLK
PLLRCLK
HSI16
/1 – 16
APB1
PCLK1
x1 or
to APB1
PPRE1
SYS clock
/1,2,4,8,16
to APB1 TIMx
source control
x2
MSI
PLLRCLK
APB2
PPRE2
/1,2,4,8,16
PCLK2
to APB2
RC48
HSI16
HSE
HSE OSC
32 MHz
to APB2 TIMx
OSC_OUT
OSC_IN
x1 or
x2
SYSCLK
HSEPRE/1,2
CPU2
C2HPRE
1,2,…,512
to CPU2
MSI
HCLK2
HSE CSS
to CPU2 FCLK
HSI16 RC
16 MHz
to CPU2 system timer
/8
MSI RC
AHB4
to AHB4, Flash memory, SRAM2
HCLK4
HCLK5
100 kHz – 48 MHz
SHDHPRE
/1,2,…,512
HSI48 RC
48 MHz
to APB3
to AHB5
MSI
HSI16
HSE
HSI16
/2
/M
to RF
to
HSI16
PLL
MSI
SMPS
PLLPCLK
SMPSDIV
xN
/P
/Q
/R
/2
MSI
HSI48
to USB
/1,2,3,4,6,8,12
HSE
PLLQCLK
PLLRCLK
/3
PCLKn
SYSCLK
HSI16
to RNG
SMPS clock
source control
LSI
LSE
to SAI1
to USART1
HSI16
PLLSAI1
to LPUART1
PLLSAI1PCLK
PLLSAI1QCLK
PLLSAI1RCLK
LSE
xN
/P
/Q
/R
SAI1_EXTCLK
PCLKn
HSI16
LSI
PCLKn
SYSCLK
HSI16
to LPTIMx
to ADC1
to I2Cx
SYSCLK
LSE
MS45402V7
1. The
LCD is not available on STM32WB35xx devices.
3.11
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
The I/Os alternate function configuration can be locked, if needed, following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.12
Direct memory access controller (DMA)
Direct memory access (DMA) is used to provide high-speed data transfer between
peripherals and memory as well as between memories. Data can be quickly moved by DMA
without any CPU action. This keeps CPU resources free for other operations.
The two DMA controllers have fourteen channels in total, a full cross matrix allows any
peripheral to be mapped on any of the available DMA channels. Each DMA has an arbiter
for handling the priority between DMA requests.
The DMA supports:
fourteen independently configurable channels (requests)
A full cross matrix between peripherals and all the DMA channels exist. There is also a
HW trigger possibility through the DMAMUX.
Priorities between requests from DMA channels are software programmable (four
levels consisting in very high, high, medium and low) or hardware in case of equality
(request 1 has priority over request 2, etc.).
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
Support for circular buffer management.
Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically OR-ed together in a single interrupt request for each channel.
Memory-to-memory transfer.
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers.
Access to Flash memory, SRAM, APB and AHB peripherals as source and destination.
Programmable number of data to be transferred: up to 65536.
Table 10. DMA implementation
DMA features
DMA1
7
DMA2
7
Number of regular channels
A DMAMUX block makes it possible to route any peripheral source to any DMA channel.
3.13
Interrupts and events
3.13.1
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the
®
Cortex -M4
with FPU.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
The NVIC benefits are the following:
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.13.2
Extended interrupts and events controller (EXTI)
The EXTI manages wakeup through configurable and direct event inputs. It provides
wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC
and events to the CPUx event input.
Configurable events/interrupts come from peripherals able to generate a pulse, and make it
possible to select the Event/Interrupt trigger edge and/or a SW trigger.
Direct events/interrupts are coming from peripherals having their own clearing mechanism.
3.14
Analog to digital converter (ADC)
The device embeds a successive approximation analog-to-digital converter with the
following features:
12-bit native resolution, with built-in calibration
Up to 16-bit resolution with 256 oversampling ratio
4.26 Msps maximum conversion rate with full resolution
–
–
Down to 39 ns sampling time
Increased conversion rate for lower resolution (up to 7.11 Msps for 6-bit
resolution)
Up to sixteen external channels and three internal channels: internal reference
voltages, temperature sensor
Single-ended and differential mode inputs
Low-power design
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: two groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
–
The ADC supports multiple trigger inputs for synchronization with on-chip timers
and external signals
Results stored into three data register or in SRAM with DMA controller support
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
–
–
–
–
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.14.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADC1_IN17 input channel, which is
used to convert the sensor output voltage into a digital value.
To
i
mprove the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by S
T
.
T
he temperature sensor factory calibration data are
stored in the system memory area, accessible in read-only mode.
Table 11. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
V
DDA
= V
REF+
= 3.0 V (± 10 mV)
TS_CAL1
0x1FFF 75A8 – 0x1FFF 75A9
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
TS_CAL2
0x1FFF 75CA – 0x1FFF 75CB
V
DDA
= V
REF+
= 3.0 V (± 10 mV)
3.14.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 12. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
0x1FFF 75AA – 0x1FFF 75AB
V
DDA
= V
REF+
= 3.6 V (± 10 mV)
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.15
Voltage reference buffer (VREFBUF)
The STM32WB55xx devices embed a voltage reference buffer that can be used as voltage
reference for the ADC and also as voltage reference for external components through the
VREF+ pin. The internal voltage reference buffer supports two voltages:
2.048 V
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on UFQFPN48
package, hence the internal voltage reference buffer is not available on a dedicated pin, but
user can still use the V
value.
DDA
3.16
Comparators (COMP)
The STM32WB55xx and STM32WB35xx devices embed two rail-to-rail comparators with
programmable reference voltage (internal or external), hysteresis and speed (low speed for
low-power) and with selectable output polarity.
The reference voltage can be one of the following:
External I/O
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
3.17
Touch sensing controller (TSC)
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric such as
glass or plastic. The capacitive variation introduced by the finger (or any conductive object)
is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STM
T
o
uch touch sensing firmware
library (free to use) and enables reliable touch sensing functionality in the end application.
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
The main features of the touch sensing controller are the following:
Proven and robust surface charge transfer acquisition principle
Supports up to 18 capacitive sensing channels
Up to six capacitive sensing channels can be acquired in parallel offering a very good
response time
Spread spectrum feature to improve system robustness in noisy environments
Full hardware management of the charge transfer acquisition sequence
Programmable charge transfer frequency
Programmable sampling capacitor I/O pin
Programmable channel I/O pin
Programmable max count value to avoid long acquisition when a channel is faulty
Dedicated end of acquisition and max count error flags with interrupt capability
One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
Designed to operate with STM
T
o
uch touch sensing firmware library
Note:
The number of capacitive sensing channels is dependent upon the package (not available
on QFPN48) and subject to I/O availability.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.18
Liquid crystal display controller (LCD)
The STM32WB55xx devices embed an LCD controller with the following characteristics:
Highly flexible frame rate control.
Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.
Supports Static, 1/2, 1/3 and 1/4 bias.
Double buffered memory allows data in LCD_RAM registers to be updated at any time
by the application firmware without affecting the integrity of the data displayed.
–
LCD data RAM of up to 16 x 32-bit registers which contain pixel information
(active/inactive)
Software selectable LCD output voltage (contrast) from VLCD
No need for external analog components:
to VLCD
.
max
min
–
A step-up converter is embedded to generate an internal VLCD voltage higher
than V
(up to 3.6 V if V
> 2.0 V)
DD
DD
–
Software selection between external and internal VLCD voltage source. In case of
an external source, the internal boost circuit is disabled to reduce power
consumption
–
–
A resistive network is embedded to generate intermediate VLCD voltages
The structure of the resistive network is configurable by software to adapt the
power consumption to match the capacitive charge required by the LCD panel
–
Integrated voltage output buffers for higher LCD driving capability.
The contrast can be adjusted using two different methods:
–
When using the internal step-up converter, the software can adjust VLCD between
VLCD and
VLCD
min
max
–
Programmable dead time (up to eight phase periods) between frames.
Full support of low-power modes: the LCD controller can be displayed in Sleep,
Low-power run, Low-power sleep and Stop modes, or can be fully disabled to reduce
power consumption.
Built in phase inversion for reduced power consumption and EMI (electromagnetic
interference).
Start of frame interrupt to synchronize the software when updating the LCD data RAM.
Blink capability:
–
–
1, 2, 3, 4, 8 or all pixels can be programmed to blink at a configurable frequency
Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
Used LCD segment and common pins should be configured as GPIO alternate functions
and unused segment and common pins can be used for general purpose I/O or for another
peripheral alternate function.
Note:
When the LCD relies on the internal step-up converter, the VLCD pin should be connected
to V
with a capacitor. Its typical value is 1
μ
F
.
SS
3.19
True random number generator (RNG)
The devices embed a true RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
DS11929 Rev 10
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Functional overview
STM32WB55xx STM32WB35xx
3.20
Timers and watchdogs
The STM32WB55xx and STM32WB35xx include one advanced 16-bit timer, one general-
purpose 32-bit timer, two 16-bit basic timers, two low-power timers, two watchdog timers
purpose and basic timers.
Table 13. Timer features
DMA
request
generation
Capture/
compare
channels
Timer
type
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer
Advanced
control
Up, down,
Up/down
TIM1
TIM2
16-bits
32-bits
16-bits
16-bits
16-bits
4
4
2
2
1
3
No
1
General
purpose
Up, down,
Up/down
Any integer
between 1
and 65536
General
purpose
TIM16
TIM17
Up
Up
Up
Yes
General
purpose
1
LPTIM1
LPTIM2
Low power
1
3.20.1
Advanced-control timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0 to
100%)
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.20.2
) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
3.20.2
General-purpose timers (TIM2, TIM16, TIM17)
There are up to three synchronizable general-purpose timers embedded in the
timer can be used to generate PWM outputs, or act as a simple time base.
TIM2
Full-featured general-purpose timer
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
–
Features four independent channels for input capture/output compare, PWM or
one-pulse mode output. Can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
–
–
The counter can be frozen in debug mode.
Independent DMA request generation, support of quadrature encoders.
TIM16 and TIM17
–
–
–
–
General-purpose timers with mid-range features:
16-bit auto-reload upcounters and 16-bit prescalers.
1 channel and 1 complementary channel.
All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
–
–
The timers can work together via the Timer Link feature for synchronization or
event chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.20.3
Low-power timer (LPTIM1 and LPTIM2)
The devices embed two low-power timers, having an independent clock running in Stop
mode if they are clocked by LSE, LSIx or by an external clock. They are able to wakeup the
system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 modes.
The low-power timers support the following features:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
–
–
Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application)
Programmable digital glitch filter
Encoder mode (LPTIM1 only)
3.20.4
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
DS11929 Rev 10
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Functional overview
STM32WB55xx STM32WB35xx
3.20.5
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.20.6
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
a 24-bit down counter
autoreload capability
a maskable system interrupt generation when the counter reaches 0
a programmable clock source.
3.21
Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter, supporting the following features:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Three anti-tamper detection pins with programmable filter.
Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 20 backup registers are supplied through a switch that takes power either
from the V
supply (when present) or from the VBAT pin.
DD
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V
power is not present. They are not reset by a system or power reset, or when the
DD
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
a 32.768 kHz external crystal (LSE)
an external resonator or oscillator (LSE)
one of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of
32 kHz)
the high-speed external clock (HSE) divided by 32.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is
functional in all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or
T
a
mper) can generate an interrupt
and wakeup the device from the low-power modes.
3.22
Inter-integrated circuit interface (I2C)
2
The I
C bus interface handles communications between the microcontroller and the serial
2
2
I C
bus. It controls all I
C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
I
2
C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
™
Power System Management Protocol (PMBus
) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 14. I2C implementation
I2C features
(1)
I2C1
I2C3
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
X
X
X
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
DS11929 Rev 10
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Functional overview
STM32WB55xx STM32WB35xx
Table 14. I2C implementation (continued)
I2C features
(1)
I2C1
I2C3
Independent clock
X
X
–
X
X
X
Wakeup from Stop 0 / Stop 1 mode on address match
Wakeup from Stop 2 mode on address match
1. X:
supported
3.23
Universal synchronous/asynchronous receiver transmitter
(USART)
The devices embed one universal synchronous receiver transmitter.
This interface provides asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and has
LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals,
and RS485 driver enable.
The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart
Card mode (ISO 7816 compliant) and SPI-like communication capability.
The USART supports synchronous operation (SPI mode), and can be used as an SPI
master.
The USART has a clock domain independent from the CPU clock, allowing it to wake up the
MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop
mode are programmable and can be:
the start bit detection
any received data frame
a specific programmed data frame.
The USART interface can be served by the DMA controller.
3.24
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UAR
T
,
e
nabling asynchronous serial communication
with minimum power consumption. The LPUART supports half duplex single wire
communication and modem operations (CTS/RTS), allowing multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 kbaud. The wake up events from Stop
mode are programmable and can be:
the start bit detection
any received data frame
a specific programmed data frame.
Only a 32.768 kHz clock (LSE) is needed for LPUART communication up to 9600 baud.
Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
extremely low energy consumption. Higher speed clock can be used to reach higher
baudrates.
The LPUART interfaces can be served by the DMA controller.
3.25
3.26
Serial peripheral interface (SPI1, SPI2)
Two SPI interfaces enable communication up to 32 Mbit/s in master and up to 24 Mbit/s in
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.
The SPI interfaces can be served by the DMA controller.
Serial audio interfaces (SAI1)
The device embeds a dual channel SAI peripheral that supports full duplex audio operation.
The SAI bus interface handles communications between the microcontroller and the serial
audio protocol.
The SAI peripheral supports:
One independent audio sub-block that can be a transmitter or a receiver, with the
respective FIFO
8-word integrated FIFOs
Synchronous or asynchronous mode
Master or slave configuration
Clock generator to target independent audio frequency sampling when audio sub-block
is configured in master mode
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DS
P
,
T
DM, AC’97 and SPDIF
out
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
Number of bits by frame may be configurable
Frame synchronization active level configurable (offset, bit length, level)
First active bit position in the slot is configurable
LSB first or MSB first for data transfer
Mute mode
Stereo/Mono audio frame capability
Communication clock strobing edge configurable (SCK)
Error flags with associated interrupts if enabled respectively
–
–
–
–
Overrun and underrun detection
Anticipated frame synchronization signal detection in slave mode
Late frame synchronization signal detection in slave mode
Codec not ready for the AC’97 mode in reception
DS11929 Rev 10
57
Functional overview
STM32WB55xx STM32WB35xx
Interruption sources when enabled:
–
–
Errors
FIFO requests
DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of the SAI audio sub-block.
The PDM (Pulse Density Modulation) block allows the user to manage up to three digital
microphone pairs (with two different clocks). This block performs Right and Left microphone
de-interleaving and time alignment through programmable delay lines in order to properly
feed the SAI.
3.27
Quad-SPI memory interface (QUADSPI)
The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
Indirect mode: all the operations are performed using the QUADSPI registers
Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
Memory-mapped mode: the external Flash memory is mapped and is seen by the
system as if it were an internal memory. This mode can be used for the Execute In
Place (XIP)
The Quad-SPI interface supports:
Three functional modes: indirect, status-polling, and memory-mapped
SDR and DDR support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
–
–
–
–
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Programmable masking for external Flash memory flag management
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Functional overview
3.28
Development support
3.28.1
Serial wire JTAG debug port (SWJ-DP)
®
The Arm
SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are
shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is
used to switch between JTAG-DP and SW-D
P
.
3.28.2
Embedded Trace Macrocell™
®
The Arm
Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32WB55xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS11929 Rev 10
57
Pinouts and pin description
STM32WB55xx STM32WB35xx
4
Pinouts and pin description
Figure 10. STM32WB55Cx and STM32WB35Cx UFQFPN48 pinout
VBAT
1
36
35
34
33
32
31
30
29
28
27
26
25
PA10
PC14-OSC32_IN
2
VDD
PC15-OSC32_OUT
3
VDDSMPS
VLXSMPS
VSSSMPS
VFBSMPS
PE4
PH3-BOOT0
PB8
4
5
PB9
6
UFQFPN48
NRST
VDDA
PA0
7
8
PB1
9
PB0
PA1
10
11
12
AT1
PA2
AT0
PA3
OSC_IN
MS42406V4
1. The
above figure shows the package top view.
2. The
exposed pad must be connected to ground plane.
Figure 11. STM32WB55Rx VFQFPN68 pinout
VBAT
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
PA10
PC13
2
PC6
PC14-OSC32_IN
3
PB15
PC15-OSC32_OUT
4
PB14
PH3-BOOT0
PB8
PB13
5
PB12
6
PB9
VDD
7
NRST
PC0
VDDSMPS
VLXSMPS
VSSSMPS
VFBSMPS
PE4
8
9
VFQFPN68
PC1
10
11
12
13
14
15
16
17
PC2
PC3
VREF+
VDDA
PA0
PB1
PB0
AT1
PA1
AT0
PA2
OSC_IN
MS45417V3
1. The
above figure shows the package top view.
2. The
exposed pad must be connected to ground plane.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
(1)
Figure 12. STM32WB55Vx WLCSP100 ballout
1
2
3
PA14
VDDUSB
PD1
4
PA15
PC9
5
6
7
8
9
10
VDD
PE1
PA11
PA12
PA13
PA10
PC12
PD9
PC10
PC11
PD6
PB5
PE2
PD2
PD5
PB4
PB7
PD15
PB8
PA0
PA6
PA8
PB2
PD7
PB3
A
B
C
D
E
F
VDD
VSS
PD12
PE0
VSS
PB13
PD3
PD0
PD13
VBAT
PC14-
PC15-
VDDSMPS
VLXSMPS
VSSSMPS
PE4
PC6
PD4
PD8
PD14
PH3-BOOT0
PC0
OSC32_OUT OSC32_IN
PB14
PC7
PD10
PC8
PD11
PB6
PH1
NRST
PC2
PH0
PB9
VFBSMPS
PE3
PB15
PB12
AT0
PA2
PC4
PC13
PC5
PA1
PC1
PC3
G
H
J
PB1
PB0
AT1
PA7
VREF+
PA3
VDDA
VSS
VSSA
VDD
PA4
OSC_IN
VSSRF
OSC_OUT
VSSRF
VDDRF
VSSRF
VSSRF
RF1
VSS
VDD
PB11
PB10
PA9
PA5
K
Radio
USB
SMPS
VDD
VSS
MS42407V3
1. The
above figure shows the package top view.
(1)
Figure 13. STM32WB55Vx UFBGA129 ballout
1
2
3
4
5
6
7
8
VDD
_DCAP4
9
10
11
12
13
PE1
PB6
PB5
PD5
PD10
PA13
VDDUSB
PA12
A
B
C
D
E
F
VSS
PE2
PE0
PD15
VBAT
PB4
PB7
PD12
PB3
PD11
PD7
PD8
PD4
PD6
PD2
PD1
PC10
PA15
PC12
PA14
PC6
PD0
VSS
VSS
PA11
PC9
_DCAP4
PD13
PC11
PD3
PA10
PD14
PD9
PC8
PC7
PC15-
OSC32_OUT
PC14-
OSC32_IN
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
PB14
PB13
VDD
_DCAP1
VSS
_DCAP1
PH0
PH3-BOOT0
PC1
PC13
PB9
VDD
VDD
VDD
VDD
PB15
PB12
VLXSMPS
VLXSMPS
VFBSMPS
VSS_DCAP3
AT0
VDDSMPS
VSSSMPS
PE3
VDDSMPS
VSSSMPS
PE4
PH1
NRST
PC2
PB8
PC0
PC3
VDDA
PA4
G
H
J
VSS
VDD_DCAP3
AT1
VSSA
PA1
VSS
PA9
PA8
VSS
PB10
PB11
PB2
VSSRF
VSSRF
VSSRF
VSSRF
VSSRF
VSSRF
VSSRF
K
L
VREF+
PA0
PC5
PC4
VSSRF
VSSRF
RF1
VSSRF
VSSRF
VSSRF
PB1
PB0
VSS
_DCAP2
PA3
PA6
VSSRF
VDDRF
OSC_IN
OSC_OUT
M
N
VDD
_DCAP2
PA2
PA5
PA7
No pin
Power supply
SMPS
USB
Radio
MS51777V4
1. The
above figure shows the package top view.
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Definition
Table 15. Legend/abbreviations used in the pinout table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
RF
RST
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
RF I/O
Bidirectional reset pin with weak pull-up resistor
Option for TT or FT I/Os
I/O, Fm+ capable
I/O structure
_f
(1)
_l
(2)
I/O, with LCD function supplied by V
LCD
I/O, with USB function supplied by V
DDUSB
I/O, with Analog switch function supplied by V
DDA
_u
(3)
_a
(4) (5)
Notes
Alternate
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
5. Analog
switch for the TSC function is supplied by V
DD
.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
Table 16. STM32WB55xx pin and ball definitions
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
TIM1_ETR, TSC_G7_IO3,
LCD_SEG36, TIM16_CH1,
CM4_EVENTOUT
–
–
–
–
C8 B2
PE0
PE1
I/O FT_l
I/O FT_l
–
–
–
TSC_G7_IO2, LCD_SEG37,
TIM17_CH1,
CM4_EVENTOUT
B10 A1
E6 B1
–
–
TRACECK, SAI1_PDM_CK1,
TSC_G7_IO1, LCD_SEG38,
SAI1_MCLK_A,
–
–
PE2
I/O FT_l
I/O FT_l
–
CM4_EVENTOUT
TSC_G6_IO4, LCD_SEG33,
LPTIM2_OU
T
,
CM4_EVENTOUT
–
–
–
–
C9 C1
D8 D3
PD13
PD14
–
–
–
–
TIM1_CH1, LCD_SEG34,
CM4_EVENTOUT
I/O FT_l
I/O FT_l
TIM1_CH2, LCD_SEG35,
CM4_EVENTOUT
–
1
–
–
E7 C2
C10 D2
G5 F4
PD15
VBAT
PC13
–
–
–
–
1
2
S
–
–
(1)
(2)
RTC_TAMP1/RTC_TS/
RTC_OUT/WKUP2
I/O
FT
CM4_EVENTOUT
PC14-
OSC32_IN
2
3
3
4
D10 E3
D9 E2
I/O
I/O
FT
FT
CM4_EVENTOUT
CM4_EVENTOUT
OSC32_IN
PC15-
OSC32_OUT
OSC32_OUT
–
–
–
–
–
–
E5
F6
VSS
VDD
S
–
–
–
–
–
–
–
–
–
–
–
–
–
S
–
–
–
E10 F1
E9 G2
E8 G1
PH0
I/O
I/O
I/O
FT
FT
FT
CM4_EVENTOUT
CM4_EVENTOUT
CM4_EVENTOU
T
,
L
SCO
(3)
–
–
PH1
4
5
PH3-BOOT0
TIM1_CH2N,
SAI1_PDM_CK1, I2C1_SCL,
QUADSPI_BK1_IO1,
LCD_SEG16, SAI1_MCLK_A,
TIM16_CH1,
5
6
F7 G3
PB8
I/O FT_fl
–
–
CM4_EVENTOUT
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
TIM1_CH3N, SAI1_PDM_DI2,
I2C1_SDA, SPI2_NSS,
IR_OU
T
,
T
SC_G7_IO4,
QUADSPI_BK1_IO0,
LCD_COM3, SAI1_FS_A,
TIM17_CH1,
6
7
F10 H4
PB9
I/O FT_fla
–
–
–
CM4_EVENTOUT
7
–
8
9
F9 H2
F8 H3
NRST
PC0
I/O RST
I/O FT_fla
–
–
–
LPTIM1_IN1, I2C3_SCL,
LPUART1_RX, LCD_SEG18,
LPTIM2_IN1,
ADC1_IN1
CM4_EVENTOUT
LPTIM1_OU
T
,
S
PI2_MOSI,
I2C3_SDA, LPUART1_TX,
LCD_SEG19,
–
–
10 G8
H1
11 G9
J2
PC1
PC2
I/O FT_fla
I/O FT_la
–
–
ADC1_IN2
ADC1_IN3
CM4_EVENTOUT
LPTIM1_IN2, SPI2_MISO,
LCD_SEG20,
CM4_EVENTOUT
–
–
–
–
–
–
E7
H6
VSS
VDD
S
S
–
–
–
–
–
–
–
–
LPTIM1_ETR,
SAI1_PDM_DI1, SPI2_MOSI,
LCD_VLCD, SAI1_SD_A,
LPTIM2_ETR,
–
12 G10
J3
PC3
I/O FT_a
–
–
ADC1_IN4
CM4_EVENTOUT
–
–
–
H10 K2
VSSA
VREF+
VDDA
VSS
S
S
S
S
S
–
–
–
–
–
–
–
–
–
–
–
13 H8
L1
14 H9
K3
–
VREFBUF_OUT
(4)
8
–
–
–
–
–
–
J9 E9
J10 F8
–
–
–
VDD
TIM2_CH1, COMP1_OU
T
,
SAI1_EXTCLK, TIM2_ETR,
CM4_EVENTOUT
COMP1_INM, ADC1_IN5,
RTC_TAMP2/WKUP1
9
15 G7
M1
PA0
PA1
I/O FT_a
I/O FT_la
–
–
TIM2_CH2, I2C1_SMBA,
SPI1_SCK, LCD_SEG0,
CM4_EVENTOUT
10 16
G6 L2
COMP1_IN
P
,
A
DC1_IN6
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
LPUART1_TX,
QUADSPI_BK1_NCS,
LCD_SEG1, COMP2_OU
T
,
CM4_EVENTOUT
COMP2_INM, ADC1_IN7,
WKUP4
11 17
F6 N1
PA2
PA3
I/O FT_la
I/O FT_la
–
–
TIM2_CH4, SAI1_PDM_CK1,
LPUART1_RX,
QUADSPI_CLK, LCD_SEG2,
COMP2_IN
P
,
A
DC1_IN8
SAI1_MCLK_A,
12 18
J8 M2
CM4_EVENTOUT
SPI1_NSS, SAI1_FS_B,
COMP1_INM,
13 19 K10
L3
14 20
K9 N2
PA4
PA5
I/O FT_a
I/O FT_a
–
–
LPTIM2_OU
T
,
L
CD_SEG5,
COMP2_INM, ADC1_IN9
CM4_EVENTOUT
TIM2_CH1, TIM2_ETR,
SPI1_SCK, LPTIM2_ETR,
SAI1_SD_B,
COMP1_INM,
COMP2_INM, ADC1_IN10
CM4_EVENTOUT
TIM1_BKIN, SPI1_MISO,
LPUART1_CTS,
15 21
H7 M3
PA6
PA7
PA8
I/O FT_la
I/O FT_fla
I/O FT_la
–
–
–
QUADSPI_BK1_IO3,
LCD_SEG3, TIM16_CH1,
CM4_EVENTOUT
ADC1_IN11
ADC1_IN12
ADC1_IN15
TIM1_CH1N, I2C3_SCL,
SPI1_MOSI,
QUADSPI_BK1_IO2,
LCD_SEG4, COMP2_OU
T
,
TIM17_CH1,
16 22
H6 N3
CM4_EVENTOUT
MCO, TIM1_CH1,
SAI1_PDM_CK2,
USART1_CK, LCD_COM0,
SAI1_SCK_A, LPTIM2_OU
T
,
CM4_EVENTOUT
17 23
J7 M4
TIM1_CH2, SAI1_PDM_DI2,
I2C1_SCL, SPI2_SCK,
USART1_TX, LCD_COM1,
SAI1_FS_A,
18 24
K8 L4
PA9
PC4
I/O FT_fla
I/O FT_la
–
–
COMP1_INM, ADC1_IN16
COMP1_INM, ADC1_IN13
CM4_EVENTOUT
LCD_SEG22,
CM4_EVENTOUT
–
25 G4
M5
–
–
–
–
–
–
F3
VSS_DCAP1
VDD
S
S
–
–
–
–
–
–
–
–
G7
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
SAI1_PDM_DI3,
LCD_SEG23,
CM4_EVENTOUT
COMP1_IN
P
,
A
DC1_IN14,
WKUP5
–
26 H5
L5
PC5
PB2
I/O FT_la
I/O FT_a
–
–
RTC_OU
T
,
L
PTIM1_OU
T
,
I2C3_SMBA, SPI1_NSS,
LCD_VLCD, SAI1_EXTCLK,
CM4_EVENTOUT
19 27
K7 N6
COMP1_INP
TIM2_CH3, I2C3_SCL,
SPI2_SCK, LPUART1_RX,
TSC_SYNC, QUADSPI_CLK,
LCD_SEG10, COMP1_OU
T
,
SAI1_SCK_A,
–
–
28 K6
L6
PB10
PB11
I/O FT_fl
–
–
–
CM4_EVENTOUT
TIM2_CH4, I2C3_SDA,
LPUART1_TX,
QUADSPI_BK1_NCS,
LCD_SEG11, COMP2_OU
T
,
CM4_EVENTOUT
29 J6
M6
I/O FT_fl
–
–
–
–
–
–
–
G5
G9
VSS
VSS
S
S
S
S
S
S
S
I/O
S
S
S
S
S
S
S
S
S
O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
20 30
K5 H8
VDD
–
–
–
–
–
–
–
–
–
–
J4
–
N8
L7
VSSRF
VSSRF
VSSRF
VSSRF
RF1
–
–
L8
–
–
M8
–
–
(5)
21 31
K4 M9
22 32
K3 M10
RF
VSSRF
VSSRF
VSSRF
VSSRF
VSSRF
VSSRF
VDDRF
VSSRF
VSSRF
OSC_OUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
K2 M11
–
–
–
–
–
K8
L9
–
–
L10
N11
–
–
–
23 33
J3 N12
–
–
–
–
K1 K10
M12
–
–
–
–
(6)
24 34
J2 N13
RF
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
25 35
J1 M13
OSC_IN
VSSRF
AT0
I
RF
–
–
–
–
–
–
–
–
–
–
–
–
L11
S
O
O
–
(7)
26 36
H3 K11
27 37
H4 K12
RF
RF
(8)
AT1
COMP1_OU
T
,
28 38
H2 L13
29 39
H1 L12
PB0
PB1
I/O
I/O
TT
TT
CM4_EVENTOU
T
,
EXT_PA_TX
–
–
LPUART1_RTS_DE,
LPTIM2_IN1,
CM4_EVENTOUT
–
–
–
–
–
–
J5
–
–
VSS
VSS_DCAP2
PE3
S
S
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
M7
–
–
G2 H12
I/O
I/O
S
FT
CM4_EVENTOUT
30 40
G1 H13
31 41
F2 H11
PE4
FT
–
CM4_EVENTOUT
VFBSMPS
VSSSMPS
VSSSMPS
VLXSMPS
VLXSMPS
VDDSMPS
VDDSMPS
VSS
–
–
–
–
G13
S
–
–
32 42
F1 G12
33 43
E1 F11
S
–
–
S
–
–
–
–
–
G11
S
–
–
34 44
D1 F12
S
–
–
–
–
–
–
–
–
F13
K4
–
S
–
–
S
–
–
35 45
B1
VDD
S
–
–
TIM1_BKIN, I2C3_SMBA,
SPI2_NSS, LPUART1_RTS,
TSC_G1_IO1, LCD_SEG12,
SAI1_FS_A,
–
–
46 G3 H10
PB12
PB13
I/O FT_l
I/O FT_fl
–
–
–
–
CM4_EVENTOUT
TIM1_CH1N, I2C3_SCL,
SPI2_SCK, LPUART1_CTS,
TSC_G1_IO2, LCD_SEG13,
SAI1_SCK_A,
47 C1 E12
CM4_EVENTOUT
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
TIM1_CH2N, I2C3_SDA,
SPI2_MISO, TSC_G1_IO3,
LCD_SEG14, SAI1_MCLK_A,
CM4_EVENTOUT
–
–
48 E2 E11
PB14
PB15
I/O FT_fl
I/O FT_l
–
–
–
–
RTC_REFIN, TIM1_CH3N,
SPI2_MOSI, TSC_G1_IO4,
LCD_SEG15, SAI1_SD_A,
CM4_EVENTOUT
49 F3 F10
50 D2 D10
TSC_G4_IO1, LCD_SEG24,
CM4_EVENTOUT
–
–
–
PC6
PC7
PC8
I/O FT_l
I/O FT_l
I/O FT_l
–
–
–
–
–
–
TSC_G4_IO2, LCD_SEG25,
CM4_EVENTOUT
–
–
E3 D12
F4 D11
TSC_G4_IO3, LCD_SEG26,
CM4_EVENTOUT
TIM1_BKIN, TSC_G4_IO4,
USB_NOE, LCD_SEG27,
SAI1_SCK_B,
–
–
B4 C13
PC9
I/O FT_l
–
–
CM4_EVENTOUT
–
–
–
–
–
K6
–
VSS
VSS
S
S
–
–
–
–
–
–
–
–
B2
TIM1_CH3, SAI1_PDM_DI1,
I2C1_SDA, USART1_RX,
USB_CRS_SYNC,
LCD_COM2, SAI1_SD_A,
TIM17_BKIN,
36 51
B5 C12
PA10
I/O FT_fl
–
–
–
CM4_EVENTOUT
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, USART1_CTS,
USB_DM, CM4_EVENTOUT
37 52
A1 B13
38 53
A2 A13
PA11
PA12
I/O FT_u
I/O FT_u
I/O FT_u
–
–
–
TIM1_ETR, SPI1_MOSI,
LPUART1_RX,
USART1_RTS_DE, USB_D
P
,
CM4_EVENTOUT
–
JTMS-SWDIO, IR_OU
T
,
USB_NOE, SAI1_SD_B,
CM4_EVENTOUT
PA13
(JTMS_SWDIO)
(9)
39 54
A5 A11
40 55
B3 A12
VDDUSB
VSS
S
S
–
–
–
–
–
–
–
–
–
–
–
C11
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
JTCK-SWCLK, LPTIM1_OU
T
,
I2C1_SMBA, LCD_SEG5,
SAI1_FS_B,
PA14
(JTCK_SWCLK)
41 56
A3 C10
42 57
A4 C9
I/O FT_l
I/O FT_l
–
CM4_EVENTOUT
JTDI, TIM2_CH1, TIM2_ETR,
SPI1_NSS, TSC_G3_IO1,
LCD_SEG17,
PA15
(JTDI)
–
–
–
CM4_EVENTOU
T
,
M
CO
–
–
–
–
J11
VSS_DCAP3
PC10
S
–
–
–
–
TRACED1, TSC_G3_IO2,
LCD_COM4/LCD_SEG28/
LCD_SEG40,
58 A6
B9
I/O FT_l
I/O FT_l
CM4_EVENTOUT
TSC_G3_IO3,
LCD_COM5/LCD_SEG29/
LCD_SEG41,
–
–
59 B6
C8
PC11
PC12
–
–
–
CM4_EVENTOUT
TSC_G3_IO4,
LCD_COM6/LCD_SEG30/
LCD_SEG42,
60 C5 B10
I/O FT_l
RTC_TAMP3/WKUP3
CM4_EVENTOUT
–
–
61 C4 B11
62 C3
C7
PD0
PD1
I/O
I/O
FT
FT
–
–
SPI2_NSS, CM4_EVENTOUT
SPI2_SCK, CM4_EVENTOUT
–
–
TRACED2, TSC_SYNC,
–
–
–
–
–
–
A7 B7
C2 D8
D3 C6
PD2
PD3
PD4
I/O FT_l
–
–
–
LCD_COM7/LCD_SEG31/LC
D_SEG43, CM4_EVENTOUT
–
–
–
SPI2_SCK, SPI2_MISO,
QUADSPI_BK1_NCS,
CM4_EVENTOUT
I/O
I/O
FT
FT
SPI2_MOSI, TSC_G5_IO1,
QUADSPI_BK1_IO0,
CM4_EVENTOUT
TSC_G5_IO2,
QUADSPI_BK1_IO1,
SAI1_MCLK_B,
–
–
B7 A6
PD5
I/O
FT
–
–
CM4_EVENTOUT
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
SAI1_PDM_DI1,
TSC_G5_IO3,
–
–
–
–
C6 D6
PD6
PD7
I/O
FT
–
–
QUADSPI_BK1_IO2,
SAI1_SD_A,
CM4_EVENTOUT
–
–
TSC_G5_IO4,
QUADSPI_BK1_IO3,
LCD_SEG39,
A8 C5
I/O FT_l
CM4_EVENTOUT
–
–
–
–
B9 B12
D4 B6
VSS
PD8
S
–
–
–
–
–
–
TIM1_BKIN2, LCD_SEG28,
CM4_EVENTOUT
I/O FT_l
I/O FT_l
TRACED0, LCD_SEG29,
CM4_EVENTOUT
–
–
–
–
D5 D4
E4 A7
PD9
–
–
–
–
TRIG_INOU
T
,
T
SC_G6_IO1,
LCD_SEG30,
CM4_EVENTOUT
PD10
I/O FT_l
I/O FT_l
I/O FT_l
TSC_G6_IO2, LCD_SEG31,
LPTIM2_ETR,
CM4_EVENTOUT
–
–
–
–
E5 B5
B8 B4
PD11
PD12
–
–
–
–
TSC_G6_IO3, LCD_SEG32,
LPTIM2_IN1,
CM4_EVENTOUT
JTDO-TRACESWO,
TIM2_CH2, SPI1_SCK,
USART1_RTS_DE,
LCD_SEG7, SAI1_SCK_B,
CM4_EVENTOUT
PB3
(JTDO)
43 63
A9 C4
I/O FT_la
I/O FT_fla
COMP2_INM
COMP2_INP
NJTRS
T
,
I
2C3_SDA,
SPI1_MISO, USART1_CTS,
TSC_G2_IO1, LCD_SEG8,
SAI1_MCLK_B, TIM17_BKIN,
CM4_EVENTOUT
PB4
(NJTRST)
44 64
C7 B3
LPTIM1_IN1, I2C1_SMBA,
SPI1_MOSI, USART1_CK,
LPUART1_TX, TSC_G2_IO2,
LCD_SEG9, COMP2_OU
T
,
SAI1_SD_B, TIM16_BKIN,
CM4_EVENTOUT
45 65
D6 A3
PB5
I/O FT_l
–
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
Table 16. STM32WB55xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
Alternate functions
Additional functions
LPTIM1_ETR, I2C1_SCL,
USART1_TX, TSC_G2_IO3,
LCD_SEG6, SAI1_FS_B,
TIM16_CH1N, MCO,
46 66
F5 A2
PB6
PB7
I/O FT_fla
I/O FT_fla
–
–
COMP2_INP
CM4_EVENTOUT
LPTIM1_IN2, TIM1_BKIN,
I2C1_SDA, USART1_RX,
TSC_G2_IO4, LCD_SEG21,
COMP2_INM, PVD_IN
TIM17_CH1N,
47 67
D7 C3
CM4_EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
J5
J7
J9
B8
–
VSS
S
S
S
S
S
S
S
S
S
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VSS
VSS
VSS_DCAP4
VDD
48 68 A10
–
–
–
–
–
–
–
–
–
–
–
–
A8
F2
J12
N7
VDD_DCAP4
VDD_DCAP1
VDD_DCAP3
VDD_DCAP2
1. PC13,
PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA),
the use of the PC13, PC14 and PC15 GPIOs in output mode is limited:
– the speed must not exceed 2 MHz with a maximum load of 30 pF
– these GPIOs must not be used as current sources (e.g. to drive a LED).
2. After
a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
3. The
clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes.
4. On
UFQFPN48 VDDA is connected to VREF+.
5. RF
pin, use the nominal PCB layout.
6. 32
MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).
7. Reserved,
must be kept unconnected.
8. High
frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0 and
1) during RF operation.
9. After
reset these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and
PB4 pins and the internal pull-down on PA14 pin are activated.
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Table 17. STM32WB35xx pin and ball definitions
Pin
Alternate functions
Additional functions
Name (function
after reset)
1
2
3
4
VBAT
S
–
–
–
–
OSC32_IN
OSC32_OUT
–
(1) (2)
PC14-OSC32_IN
I/O
FT
FT
FT
CM4_EVENTOUT
PC15-OSC32_OUT I/O
CM4_EVENTOUT
PH3-BOOT0
I/O
–
CM4_EVENTOU
T
,
L
SCO
(3)
TIM1_CH2N, SAI1_PDM_CK1,
I2C1_SCL, QUADSPI_BK1_IO1,
SAI1_MCLK_A, TIM16_CH1,
CM4_EVENTOUT
5
6
PB8
I/O FT_f
–
–
–
–
TIM1_CH3N, SAI1_PDM_DI2,
I2C1_SDA, SPI2_NSS, IR_OU
T
,
QUADSPI_BK1_IO0, SAI1_FS_A,
TIM17_CH1, CM4_EVENTOUT
PB9
I/O FT_f
I/O RST
7
8
NRST
VDDA
–
–
–
–
–
–
S
–
TIM2_CH1, COMP1_OU
T
,
SAI1_EXTCLK, TIM2_ETR,
CM4_EVENTOUT
COMP1_INM, ADC1_IN5,
RTC_TAMP2/WKUP1
9
PA0
PA1
PA2
I/O FT_a
I/O FT_a
I/O FT_a
–
–
–
TIM2_CH2, I2C1_SMBA, SPI1_SCK,
CM4_EVENTOUT
10
11
COMP1_IN
P
,
A
DC1_IN6
QUADSPI_BK1_NCS, COMP2_OU
T
,
CM4_EVENTOUT
COMP2_INM, ADC1_IN7,
WKUP4
TIM2_CH4, SAI1_PDM_CK1,
LPUART1_RX, QUADSPI_CLK,
SAI1_MCLK_A, CM4_EVENTOUT
12
13
14
PA3
PA4
PA5
I/O FT_a
I/O FT_a
I/O FT_a
–
–
–
COMP2_IN
P
,
A
DC1_IN8
SPI1_NSS, SAI1_FS_B,
LPTIM2_OU
T
,
C
M4_EVENTOUT
COMP1_INM,
COMP2_INM, ADC1_IN9
TIM2_CH1, TIM2_ETR, SPI1_SCK,
LPTIM2_ETR, SAI1_SD_B,
CM4_EVENTOUT
COMP1_INM,
COMP2_INM, ADC1_IN10
TIM1_BKIN, SPI1_MISO,
15
16
17
PA6
PA7
PA8
I/O FT_a
I/O FT_fa
I/O FT_a
–
–
–
LPUART1_CTS
,
Q
UADSPI_BK1_IO3, ADC1_IN11
TIM16_CH1, CM4_EVENTOUT
TIM1_CH1N, I2C3_SCL, SPI1_MOSI,
QUADSPI_BK1_IO2, COMP2_OU
T
,
TIM17_CH1, CM4_EVENTOUT
ADC1_IN12
ADC1_IN15
MCO, TIM1_CH1, SAI1_PDM_CK2,
USART1_CK, SAI1_SCK_A,
LPTIM2_OU
T
,
C
M4_EVENTOUT
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Pinouts and pin description
Table 17. STM32WB35xx pin and ball definitions (continued)
Pin
Alternate functions
Additional functions
Name (function
after reset)
TIM1_CH2, SAI1_PDM_DI2,
18
19
PA9
PB2
I/O FT_fa
I/O FT_a
–
–
I2C1_SCL, SPI2_SCK, USART1_TX,
COMP1_INM, ADC1_IN16
SAI1_FS_A, CM4_EVENTOUT
RTC_OU
T
,
L
PTIM1_OU
T
,
I2C3_SMBA, SPI1_NSS,
COMP1_INP
SAI1_EXTCLK, CM4_EVENTOUT
20
21
22
23
24
25
26
27
VDD
RF1
S
I/O
S
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(4)
RF
–
VSSRF
VDDRF
OSC_OUT
OSC_IN
AT0
–
S
–
–
(5)
O
I
RF
RF
RF
RF
(6)
O
O
AT1
COMP1_OU
T
,
C
M4_EVENTOU
T
,
EXT_PA_TX
(7)
28
29
PB0
PB1
I/O
I/O
TT
TT
–
–
LPUART1_RTS_DE, LPTIM2_IN1,
CM4_EVENTOUT
30
31
32
33
34
35
PE4
I/O
S
FT
–
–
–
–
–
–
CM4_EVENTOUT
–
–
–
–
–
–
VFBSMPS
VSSSMPS
VLXSMPS
VDDSMPS
VDD
–
–
–
–
–
–
–
–
–
–
S
S
S
S
TIM1_CH3, SAI1_PDM_DI1,
I2C1_SDA, USART1_RX,
USB_CRS_SYNC, SAI1_SD_A,
TIM17_BKIN, CM4_EVENTOUT
36
PA10
I/O FT_f
–
–
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, USART1_CTS,
USB_DM, CM4_EVENTOUT
37
38
PA11
PA12
I/O FT_u
I/O FT_u
–
–
–
–
TIM1_ETR, SPI1_MOSI,
LPUART1_RX, USART1_RTS_DE,
USB_D
P
,
C
M4_EVENTOUT
PA13
(JTMS-SWDIO)
JTMS-SWDIO, IR_OU
T
,
U
SB_NOE,
SAI1_SD_B, CM4_EVENTOUT
(8)
39
40
I/O
S
FT
–
–
–
VDDUSB
–
–
DS11929 Rev 10
80
Pinouts and pin description
STM32WB55xx STM32WB35xx
Table 17. STM32WB35xx pin and ball definitions (continued)
Pin
Alternate functions
Additional functions
Name (function
after reset)
JTCK-SWCLK, LPTIM1_OU
T
,
I2C1_SMBA, SAI1_FS_B,
CM4_EVENTOUT
PA14
(JTCK-SWCLK)
41
42
43
I/O
I/O
FT
FT
–
–
JTDI, TIM2_CH1, TIM2_ETR,
SPI1_NSS, CM4_EVENTOU
T
,
M
CO
PA15 (JTDI)
PB3 (JTDO)
JTDO-TRACESWO, TIM2_CH2,
SPI1_SCK, USART1_RTS_DE,
SAI1_SCK_B, CM4_EVENTOUT
I/O FT_a
I/O FT_fa
–
COMP2_INM
COMP2_INP
NJTRS
T
,
I
2C3_SDA, SPI1_MISO,
USART1_CTS, SAI1_MCLK_B,
TIM17_BKIN, CM4_EVENTOUT
44
45
PB4 (NJTRST)
PB5
LPTIM1_IN1, I2C1_SMBA,
SPI1_MOSI, USART1_CK,
LPUART1_TX, COMP2_OU
T
,
SAI1_SD_B, TIM16_BKIN,
CM4_EVENTOUT
I/O FT_a
–
–
–
LPTIM1_ETR, I2C1_SCL,
USART1_TX, SAI1_FS_B,
TIM16_CH1N, MCO,
CM4_EVENTOUT
46
PB6
I/O FT_fa
I/O FT_fa
COMP2_INP
LPTIM1_IN2, TIM1_BKIN, I2C1_SDA,
USART1_RX, TIM17_CH1N,
CM4_EVENTOUT
47
48
PB7
–
–
COMP2_INM, PVD_IN
–
VDD
S
–
–
1. PC14
and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the
use of the PC14 and PC15 GPIOs in output mode is limited:
– the speed must not exceed 2 MHz with a maximum load of 30 pF
– these GPIOs must not be used as current sources (e.g. to drive a LED).
2. After
a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
3. The
clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes.
4. RF
pin, use the nominal PCB layout.
5. 32
MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).
6. Reserved,
must be kept unconnected.
7. High
frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0
and 1) during RF operation.
8. After
reset these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and
PB4 pins and the internal pull-down on PA14 pin are activated.
DS11929 Rev 10
Table 18. Alternate functions (STM32WB55xx)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2/
SAI1/
TIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
I2C1/
I2C3
SPI1/
SPI2
USB/
QUADSPI
SYS_AF
RF
USART1 LPUART1
TSC
LCD
SAI1
EVENTOUT
TIM2_
CH1
COMP1_
OUT
SAI1_
EXTCLK
TIM2_
ETR
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PA0
TIM2_
CH2
I2C1_
SMBA
SPI1_
SCK
CM4_
EVENTOUT
–
–
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG5
–
–
–
–
–
–
–
PA1
TIM2_
CH3
LPUART1
_TX
QUADSPI_
BK1_NCS
COMP2_
OUT
CM4_
EVENTOUT
LSCO
–
–
–
–
–
PA2
TIM2_
CH4
SAI1_
PDM_CK1
LPUART1
_RX
QUADSPI_
CLK
SAI1
_MCLK_A
CM4_
EVENTOUT
–
–
–
–
–
PA3
SPI1_
NSS
SAI1
_FS_B
LPTIM2_
OUT
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
PA4
TIM2_
CH1
TIM2_
ETR
SPI1_
SCK
SAI1
_SD_B
LPTIM2_
ETR
CM4_
EVENTOUT
–
–
PA5
TIM1_
BKIN
SPI1_
MISO
LPUART1
_CTS
QUADSPI_
BK1_IO3
TIM1_
BKIN
TIM16
_CH1
CM4_
EVENTOUT
PA6
–
–
–
–
–
–
–
LCD_SEG3
LCD_SEG4
LCD_COM0
LCD_COM1
LCD_COM2
–
–
–
TIM1_
CH1N
I2C3_
SCL
SPI1_
MOSI
QUADSPI_
BK1_IO2
COMP2_
OUT
TIM17
_CH1
CM4_
EVENTOUT
–
–
–
–
–
–
–
PA7
A
TIM1_
CH1
SAI1_
PDM_CK2
USART1_
CK
SAI1
_SCK_A
LPTIM2_
OUT
CM4_
EVENTOUT
MCO
–
–
–
–
–
–
PA8
TIM1_
CH2
SAI1_
PDM_DI2
I2C1_
SCL
SPI2_
SCK
USART1_
TX
SAI1
_FS_A
CM4_
EVENTOUT
PA9
–
–
–
–
–
–
TIM1_
CH3
SAI1_
PDM_DI1
I2C1_
SDA
USART1_
RX
USB_CRS
_SYNC
SAI1
_SD_A
TIM17
_BKIN
CM4_
EVENTOUT
–
PA10
PA11
PA12
PA13
PA14
PA15
TIM1_
CH4
TIM1_
BKIN2
SPI1_
MISO
USART1_
CTS
TIM1_
BKIN2
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
USB_DM
–
–
–
–
–
–
–
TIM1_
ETR
SPI1_
MOSI
USART1_ LPUART1
RTS_DE
CM4_
EVENTOUT
–
–
–
–
USB_DP
–
–
–
–
–
_RX
JTMS-
SWDIO
SAI1
_SD_B
CM4_
EVENTOUT
–
–
–
–
–
–
IR_OUT
USB_NOE
–
JTCK-
SWCLK
LPTIM1_
OUT
I2C1_
SMBA
SAI1
_FS_B
CM4_
EVENTOUT
–
–
–
–
–
–
LCD_SEG5
LCD_SEG17
TIM2_
CH1
TIM2_
ETR
SPI1_
NSS
CM4_
EVENTOUT
JTDI
MCO
–
Table 18. Alternate functions (STM32WB55xx) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2/
SAI1/
TIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
I2C1/
I2C3
SPI1/
SPI2
USB/
QUADSPI
SYS_AF
RF
USART1 LPUART1
TSC
LCD
SAI1
EVENTOUT
EXT
_PA
_TX
COMP1_
OUT
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PB0
LPUART1
_RTS_DE
LPTIM2_
IN1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PB1
PB2
RTC_
OUT
LPTIM1_
OUT
I2C3_
SMBA
SPI1_
NSS
SAI1_
EXTCLK
CM4_
EVENTOUT
–
–
–
–
LCD_VLCD
–
–
JTDO-
TRACE
SWO
TIM2_
CH2
SPI1_
SCK
USART1_
RTS_DE
SAI1_
SCK_B
CM4_
EVENTOUT
–
–
–
–
–
–
LCD_SEG7
–
–
PB3
I2C3_
SDA
SPI1_
MISO
USART1_
CTS
TSC_G2
_IO1
SAI1_
MCLK_B
TIM17_
BKIN
CM4_
EVENTOUT
PB4
NJTRST
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LCD_SEG8
LCD_SEG9
LCD_SEG6
LCD_SEG21
LCD_SEG16
LCD_COM3
LCD_SEG10
LCD_SEG11
LCD_SEG12
LCD_SEG13
LCD_SEG14
LCD_SEG15
LPTIM1_
IN1
I2C1_
SMBA
SPI1_
MOSI
USART1_ LPUART1 TSC_G2
COMP2_
OUT
SAI1_
SD_B
TIM16_
BKIN
CM4_
EVENTOUT
–
PB5
CK
_TX
_IO2
LPTIM1_
ETR
I2C1_
SCL
USART1_
TX
TSC_G2
_IO3
SAI1_
FS_B
TIM16_
CH1N
CM4_
EVENTOUT
MCO
–
–
–
–
–
–
–
–
PB6
LPTIM1_
IN2
TIM1_
BKIN
I2C1_
SDA
USART1_
RX
TSC_G2
_IO4
TIM17_
CH1N
CM4_
EVENTOUT
PB7
–
–
–
–
–
–
–
–
–
–
B
TIM1_
CH2N
SAI1_
PDM_CK1
I2C1_
SCL
QUADSPI_
BK1_IO1
SAI1_
MCLK_A
TIM16_
CH1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
PB8
TIM1_
CH3N
SAI1_
PDM_DI2
I2C1_
SDA
SPI2_
NSS
TSC_G7 QUADSPI_
_IO4
SAI1_
FS_A
TIM17_
CH1
CM4_
EVENTOUT
IR_OUT
PB9
BK1_IO0
TIM2_
CH3
I2C3_
SCL
SPI2_SC
K
LPUART1
_RX
TSC
_SYNC
QUADSPI_
CLK
COMP1_
OUT
SAI1_
SCK_A
CM4_
EVENTOUT
PB10
PB11
PB12
PB13
PB14
PB15
–
–
–
–
–
–
–
–
TIM2_
CH4
I2C3_
SDA
LPUART1
_TX
QUADSPI_
BK1_NCS
COMP2_
OUT
CM4_
EVENTOUT
–
–
–
TIM1_
BKIN
TIM1_
BKIN
I2C3_
SMBA
SPI2_
NSS
LPUART1 TSC_G1
_RTS _IO1
SAI1_
FS_A
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
TIM1_
CH1N
I2C3_
SCL
SPI2_
SCK
LPUART1 TSC_G1
SAI1_
SCK_A
CM4_
EVENTOUT
–
–
–
_CTS
_IO2
TIM1_
CH2N
I2C3_
SDA
SPI2_
MISO
TSC_G1
_IO3
SAI1_
MCLK_A
CM4_
EVENTOUT
–
RTC_
REFIN
TIM1_
CH3N
SPI2_
MOSI
TSC_G1
_IO4
SAI1_
SD_A
CM4_
EVENTOUT
–
–
Table 18. Alternate functions (STM32WB55xx) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2/
SAI1/
TIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
I2C1/
I2C3
SPI1/
SPI2
USB/
QUADSPI
SYS_AF
RF
USART1 LPUART1
TSC
LCD
SAI1
EVENTOUT
LPTIM1_
IN1
I2C3
_SCL
LPUART1
_RX
LPTIM2_
IN1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LCD_SEG18
LCD_SEG19
LCD_SEG20
LCD_VLCD
LCD_SEG22
LCD_SEG23
LCD_SEG24
LCD_SEG25
LCD_SEG26
–
–
–
–
–
–
–
–
–
–
–
–
–
PC0
LPTIM1_
OUT
SPI2_
MOSI
I2C3
_SDA
LPUART1
_TX
CM4_
EVENTOUT
–
–
–
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
LPTIM1_
IN2
SPI2_
MISO
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LPTIM1_
ETR
SAI1_
PDM_DI1
SPI2_
MOSI
SAI1
_SD_A
LPTIM2_
ETR
CM4_
EVENTOUT
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SAI1_
PDM_DI3
CM4_
EVENTOUT
TSC_G4
_IO1
CM4_
EVENTOUT
–
–
–
TSC_G4
_IO2
CM4_
EVENTOUT
TSC_G4
_IO3
CM4_
EVENTOUT
C
TIM1
_BKIN
TSC_G4
_IO4
SAI1
_SCK_B
CM4_
EVENTOUT
USB_NOE LCD_SEG27
LCD_COM4
TRACE
D1
TSC_G3
_IO2
CM4_
EVENTOUT
PC10
PC11
PC12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LCD_SEG28
LCD_SEG40
–
–
–
–
–
–
–
–
–
LCD_COM5
LCD_SEG29
LCD_SEG41
TSC_G3
_IO3
CM4_
EVENTOUT
–
LCD_COM6
LCD_SEG30
LCD_SEG42
TRACE
D3
TSC_G3
_IO4
CM4_
EVENTOUT
LSCO
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PC13
PC14
PC15
CM4_
EVENTOUT
CM4_
EVENTOUT
Table 18. Alternate functions (STM32WB55xx) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2/
SAI1/
TIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
I2C1/
I2C3
SPI1/
SPI2
USB/
QUADSPI
SYS_AF
RF
USART1 LPUART1
TSC
LCD
SAI1
EVENTOUT
SPI2_
NSS
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PD0
SPI2_
SCK
CM4_
EVENTOUT
PD1
PD2
LCD_COM7
LCD_SEG31
LCD_SEG43
TRACE
D2
TSC_
SYNC
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
SPI2_
MISO
QUADSPI_
BK1_NCS
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SPI2_SCK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PD3
SPI2_
MOSI
TSC_
G5_IO1
QUADSPI_
BK1_IO0
CM4_
EVENTOUT
–
–
–
PD4
TSC_
G5_IO2
QUADSPI_
BK1_IO1
SAI1_
MCLK_B
CM4_
EVENTOUT
PD5
–
–
–
–
–
–
–
–
–
–
–
–
SAI1_
PDM_DI1
TSC_
G5_IO3
QUADSPI_
BK1_IO2
SAI1_
SD_A
CM4_
EVENTOUT
–
PD6
TSC_
G5_IO4
QUADSPI_
BK1_IO3
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
LCD_SEG39
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
LCD_SEG32
LCD_SEG33
LCD_SEG34
LCD_SEG35
–
–
–
–
–
–
–
–
–
PD7
D
TIM1
_BKIN2
CM4_
EVENTOUT
PD8
–
–
–
–
–
–
–
–
–
–
TRACE
D0
CM4_
EVENTOUT
–
–
–
–
–
–
–
PD9
TRIG
_INOUT
TSC_
G6_IO1
CM4_
EVENTOUT
PD10
PD11
PD12
PD13
PD14
PD15
TSC_
G6_IO2
LPTIM2_
ETR
CM4_
EVENTOUT
–
–
–
–
–
TSC_
G6_IO3
LPTIM2_
IN1
CM4_
EVENTOUT
TSC_
G6_IO4
LPTIM2_
OUT
CM4_
EVENTOUT
TIM1_
CH1
CM4_
EVENTOUT
–
–
–
–
TIM1_
CH2
CM4_
EVENTOUT
Table 18. Alternate functions (STM32WB55xx) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
SPI2/
SAI1/
TIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
I2C1/
I2C3
SPI1/
SPI2
USB/
QUADSPI
SYS_AF
RF
USART1 LPUART1
TSC
LCD
SAI1
EVENTOUT
TIM1_
ETR
TSC_
G7_IO3
TIM16_
CH1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LCD_SEG36
–
–
–
–
–
–
–
–
–
–
PE0
TSC_
G7_IO2
TIM17_
CH1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
LCD_SEG37
PE1
PE2
PE3
PE4
PH0
PH1
PH3
SAI1_
PDM_CK1
TSC_
G7_IO1
SAI1_
MCLK_A
CM4_
EVENTOUT
TRACECK
LCD_SEG38
–
–
–
–
–
–
E
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CM4_
EVENTOUT
–
CM4_
EVENTOUT
–
–
CM4_
EVENTOUT
H
CM4_
EVENTOUT
LSCO
Table 19. Alternate functions (STM32WB35xx)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF10
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
SAI1/
TIM1
I2C1/
I2C3
USB/
QUADSPI
SYS_AF
SPI1
RF
USART1 LPUART1
SAI1
EVENTOUT
TIM2_
CH1
COMP1_
OUT
SAI1_
EXTCLK
TIM2_
ETR
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PA0
TIM2_
CH2
I2C1_
SMBA
SPI1_
SCK
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
PA1
TIM2_
CH3
LPUART1 QUADSPI_ COMP2_
CM4_
EVENTOUT
LSCO
–
–
–
–
–
PA2
_TX
BK1_NCS
OUT
TIM2_
CH4
SAI1_
PDM_CK1
LPUART1 QUADSPI_
SAI1
_MCLK_A
CM4_
EVENTOUT
–
–
–
PA3
_RX
–
CLK
–
SPI1_
NSS
SAI1
_FS_B
LPTIM2_
OUT
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
PA4
TIM2_
CH1
TIM2_
ETR
SPI1_
SCK
SAI1
_SD_B
LPTIM2_
ETR
CM4_
EVENTOUT
PA5
–
–
–
–
TIM1_
BKIN
SPI1_
MISO
LPUART1 QUADSPI_
_CTS
TIM1_
BKIN
TIM16
_CH1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
PA6
BK1_IO3
TIM1_
CH1N
I2C3_
SCL
SPI1_
MOSI
QUADSPI_ COMP2_
TIM17
_CH1
CM4_
EVENTOUT
–
–
–
PA7
BK1_IO2
OUT
A
TIM1_
CH1
SAI1_
PDM_CK2
USART1_
CK
SAI1
_SCK_A
LPTIM2_
OUT
CM4_
EVENTOUT
PA8
MCO
–
–
–
–
–
–
–
–
–
–
TIM1_
CH2
SAI1_
PDM_DI2
I2C1_
SCL
USART1_
TX
SAI1
_FS_A
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
PA9
TIM1_
CH3
SAI1_
PDM_DI1
I2C1_
SDA
USART1_
RX
USB_CRS
_SYNC
SAI1
_SD_A
TIM17
_BKIN
CM4_
EVENTOUT
–
PA10
PA11
PA12
PA13
PA14
PA15
TIM1_
CH4
TIM1_
BKIN2
SPI1_
MISO
USART1_
CTS
TIM1_
BKIN2
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
USB_DM
–
–
–
–
–
–
–
TIM1_
ETR
SPI1_
MOSI
USART1_ LPUART1
RTS_DE
CM4_
EVENTOUT
–
–
–
–
USB_DP
–
–
–
–
_RX
JTMS-
SWDIO
SAI1
_SD_B
CM4_
EVENTOUT
–
–
–
–
–
–
IR_OUT
USB_NOE
JTCK-
SWCLK
LPTIM1_
OUT
I2C1_
SMBA
SAI1
_FS_B
CM4_
EVENTOUT
–
–
–
–
–
–
TIM2_
CH1
TIM2_
ETR
SPI1_
NSS
CM4_
EVENTOUT
JTDI
MCO
–
Table 19. Alternate functions (STM32WB35xx) (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF10
AF12
AF13
AF14
AF15
TIM2/
TIM16/
TIM17/
LPTIM2
Port
TIM1/
TIM2/
LPTIM1
COMP1/
COMP2/
TIM1
TIM1/
TIM2
SAI1/
TIM1
I2C1/
I2C3
USB/
QUADSPI
SYS_AF
SPI1
RF
USART1 LPUART1
SAI1
EVENTOUT
EXT
_PA
_TX
COMP1_
OUT
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PB0
LPUART1
_RTS_DE
LPTIM2_
IN1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
PB1
PB2
RTC_
OUT
LPTIM1_
OUT
I2C3_
SMBA
SPI1_
NSS
SAI1_
EXTCLK
CM4_
EVENTOUT
–
–
–
–
–
–
JTDO-
TRACE
SWO
TIM2_
CH2
SPI1_
SCK
USART1_
RTS_DE
SAI1_
SCK_B
CM4_
EVENTOUT
–
–
–
–
–
–
–
PB3
I2C3_
SDA
SPI1_
MISO
USART1_
CTS
SAI1_
MCLK_B
TIM17_
BKIN
CM4_
EVENTOUT
PB4
PB5
PB6
PB7
PB8
PB9
PC14
PC15
PE4
PH3
NJTRST
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
B
LPTIM1_
IN1
I2C1_
SMBA
SPI1_
MOSI
USART1_ LPUART1
COMP2_
OUT
SAI1_
SD_B
TIM16_
BKIN
CM4_
EVENTOUT
–
CK
_TX
LPTIM1_
ETR
I2C1_
SCL
USART1_
TX
SAI1_
FS_B
TIM16_
CH1N
CM4_
EVENTOUT
MCO
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LPTIM1_
IN2
TIM1_
BKIN
I2C1_
SDA
USART1_
RX
TIM17_
CH1N
CM4_
EVENTOUT
–
–
–
TIM1_
CH2N
SAI1_
PDM_CK1
I2C1_
SCL
QUADSPI_
BK1_IO1
SAI1_
MCLK_A
TIM16_
CH1
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
TIM1_
CH3N
SAI1_
PDM_DI2
I2C1_
SDA
QUADSPI_
BK1_IO0
SAI1_
FS_A
TIM17_
CH1
CM4_
EVENTOUT
–
IR_OUT
CM4_
EVENTOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C
CM4_
EVENTOUT
–
–
CM4_
EVENTOUT
E
H
CM4_
EVENTOUT
LSCO
Memory mapping
STM32WB55xx STM32WB35xx
5
Memory mapping
The STM32WB55xx and STM32WB35xx devices feature a single physical address space
that can be accessed by the application processor and by the RF subsystem.
A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,
exclusively accessible by the CPU2, protected against execution, read and write from CPU1
and DMA.
In case of shared resources the SW should implement arbitration mechanism to avoid
access conflicts. This happens for peripherals Reset and Clock Controller (RCC), Power
Controller (PWC), EXTI and Flash interface, and can be implemented using the built-in
semaphore block (HSEM).
By default the RF subsystem and CPU2 operate in secure mode. This implies that part of
the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by
the CPU2. In this case the Host processor (CPU1) has no access to these resources.
The detailed memory map and the peripheral mapping can be found in the reference
manual RM0434.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
= 25 °C and T
= T
max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3
σ
).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T
= 25 °C, V
= V
= 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2
σ
)
.
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
Pin input voltage
Figure 14. Pin loading conditions
Figure 15. Pin input voltage
MCU pin
MCU pin
C = 50 pF
V
IN
MS19210V1
MS19211V1
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.1.6
Power supply scheme
Figure 16. Power supply scheme (all packages except UFBGA129 and WLCSP100)
VBAT
Backup circuitry
1.55 V to
3.6 V
(LSE, RTC and
backup registers)
Power switch
Regulator
V
DD
V
CORE
n x VDD
GPIOs
V
DDIO1
OUT
Kernel logic
IO
logic
(CPU, digital
n x 100 nF + 1 x 4.7 μF
IN
and memories
V
SS
V
DDA
VDDA
VREF+
(2)
ADC
COMPs
10 nF + 1 μF
100 nF + 1 μF
V
REF-
V
SS
V
DD
VDDSMPS
VLXSMPS
SMPS
Regulator
4.7 μF
L1
(1)
VFBSMPS
4.7 μF
VSSSMPS
VDDUSB
V
DD
USB
transceiver
V
DD
100 nF
VDDRF
VSSRF
100 nF
+ 100 pF
Radio
Exposed pad
V
SS
To
a
ll modules
MS53167V3
2. V
REF+
connection is not available on UFQFPN48 package.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 17. Power supply scheme (UFBGA129 and WLCSP100 packages)
VDD_DCAPx
(2)
1 x 100 nF
VSS_DCAPx
(2)
VBAT
Backup circuitry
(LSE, RTC and
backup registers)
1.55 to
3.6 V
Power switch
Regulator
V
DD
V
CORE
n x VDD
V
DDIO1
OUT
Kernel logic
IO
logic
(CPU, digital
GPIOs
1 x 4.7 μF
IN
and memories
n x VSS
V
DDA
VDDA
V
REF
ADCs
OPAMPs
COMPs
V
REF+
10 nF + 1 μF
100 nF
1 μF
V
REF-
VREFBUF
VSSA
V
DD
VDDSMPS
SMPS
Regulator
VLXSMPS
VFBSMPS
4.7 μF
L1
(1)
4.7 μF
VSSSMPS
VDDUSB
V
DD
USB
100 nF
transceiver
V
DD
VDDRF
VSSRF
100 nF
+ 100 pF
Radio
MS53132V2
2. For
UFBGA129 package VDD_DCAPx and VSS_DCAPx balls are connected to V
DD
and V
SS
internally, to
simplify the 2-layer board layout and especially the ground plane below the BGA.
V
DD
power supply can be made with a single connection to the center of the BGA on the board bottom
layer. The decoupling 100 nF capacitors are connected without cutting the board ground plane.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Caution:
Each power supply pair (V
/ V
, V
/ V
etc.) must be decoupled with filtering
SSA
DD
possible to (or below) the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
6.1.7
Current consumption measurement
Figure 18. Current consumption measurement scheme
I
DDSMPS
V
DDSMPS
I
DDRF
V
DDRF
I
DDUSB
V
DDUSB
I
DDVBAT
V
BAT
I
DD
V
DD
I
DDA
V
DDA
MS45416V1
6.2
Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)
Table 20. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage
V
DDX
– V
SS
(including V
DD
, V
DDA
, V
DDUSB
, V
LCD
, V
DDRF
,
-0.3
4.0
V
DDSMPS
, V
BAT
, V
REF+
)
min (V
DD
, V
DDA
, V
DDUSB
, V
LCD
V
DDRF
, V
DDSMPS
) + 4.0
(3)(4)
,
V
Input voltage on FT_xxx pins
(2)
V
SS
-0.3
V
IN
Input voltage on TT_xx pins
Input voltage on any other pin
4.0
4.0
Variations between different V
DDX
power pins
of the same domain
|
∆
V
DDx
|
–
50
mV
V
Variations between all the different ground
pins
(5)
|V
SSx
-V
SS
|
–
–
50
V
REF+
– V
DDA
Allowed voltage difference for V
REF+
> V
DDA
0.4
1. All
main power (V
DD
, V
DDRF
, V
DDA
, V
DDUSB
, V
LCD
, V
BAT
) and ground (V
SS
, V
SSA
) pins must always be connected to the
external power supply, in the permitted range.
2. V
IN
maximum must always be respected. Refer to
T
a
ble 21
for the maximum allowed injected current values.
3. This
formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4.
T
o
s
ustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include
VREF- pin.
Table 21. Current characteristics
Symbol
Ratings
Max
Unit
∑
IV
DD
∑
IV
SS
Total current into sum of all V
DD
power lines (source)
(1)
Output current sunk by any I/O and control pin except FT_f
Output current sunk by any FT_f pin
130
130
100
100
20
IV
DD(PIN)
IV
SS(PIN)
I
IO(PIN)
20
mA
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins
(2)
Injected current on FT_xxx, TT_xx, RST and B pins, except PB0 and PB1
Injected current on PB0 and PB1
20
100
100
–5 / +0
(4)
-5/0
25
∑
I
IO(PIN)
(3)
I
INJ(PIN)
∑
|I
INJ(PIN)
|
Total injected current (sum of all I/Os and control pins)
(5)
1. All
main power (V
DD
, V
DDRF
, V
DDA
, V
DDUSB
, V
BAT
) and ground (V
SS
, V
SSA
) pins must always be connected to the external
power supplies, in the permitted range.
2. This
current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count packages.
3. Positive
injection (when V
IN
> V
DD
) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A
negative injection is induced by V
IN
< V
SS
. I
INJ(PIN)
must never be exceeded. Refer also to
T
a
ble 20: Voltage
characteristics
for the maximum allowed input voltage values.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
5. When
several inputs are submitted to a current injection, the maximum
∑
|I
INJ(PIN)
| is the absolute sum of the negative
injected currents (instantaneous values).
Table 22. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
T
STG
T
J
–65 to +150
130
°C
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3
Operating conditions
6.3.1
Summary of main performance
Table 23. Main performance at V
= 3.3 V
DD
Parameter
Test conditions
Typ
Unit
VBAT (V
BAT
= 1.8
V
,
V
DD
= 0 V)
Shutdown (V
DD
= 1.8 V)
Standby (V
DD
= 1.8
V
,
3
2 Kbytes RAM retention)
Stop2
0.002
0.013
0.320
1.85
Core current
consumption
I
CORE
Sleep (16 MHz)
740
LP run (2 MHz)
320
Run (64 MHz)
5000
4500
5200
Radio RX
(1)
µA
Advertising
(2)
(Tx = 0 dBm; Period 1.28 s; 31 bytes, 3 channels)
13
4
BLE
(Tx = 0 dBm, 6 bytes; period 10.24 s, 3 channels)
Peripheral
I
PERI
current
consumption
LP timers
I2C3
–
–
–
–
6
7.1
7.7
2.5
LPUART
RTC
1. Power
consumption including RF subsystem and digital processing.
2. Power
consumption integrated over 100 s, including Cortex-M4, RF subsystem, digital processing and Cortex-M0+.
6.3.2
General operating conditions
Table 24. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
f
HCLK
Internal AHB clock frequency
f
PCLK1
Internal APB1 clock frequency
f
PCLK2
Internal APB2 clock frequency
–
0
64
64
64
3.6
–
0
0
MHz
–
–
V
DD
V
DDA
V
BAT
Standard operating voltage
1.71
(1)(2)
1.62
2.4
ADC or COMP used
VREFBUF used
Analog supply voltage
3.6
3.6
V
ADC, COM
P
,
V
REFBUF
0
not used
Backup operating voltage
–
1.55
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Table 24. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
V
FBSMPS
SMPS Feedback voltage
V
DDRF
Minimum RF voltage
–
–
1.4
1.71
3.0
0
3.6
3.6
USB used
3.6
V
DDUSB
USB supply voltage
USB not used
TT_xx I/O
3.6
V
–0.3
V
DD
+ 0.3
min (min (V
DD
, V
DDA
,
V
IN
I/O input voltage
All I/O except TT_xx
–0.3
V
DDUSB
, V
LCD
) + 3.6
V
,
5.5 V)
(3)(4)
UFQFPN48
–
–
–
–
803
425
558
481
85
Power dissipation at
T
A
= 85 °C for suffix 6
or
VFQFPN68
P
D
mW
WLCSP100
T
A
= 105 °C for suffix 7
(5)
UFBGA129
Maximum power dissipation
Low-power dissipation
(6)
Maximum power dissipation
Suffix 6 version
Ambient temperature for the
suffix 6 version
–40
–40
–40
105
105
125
105
125
T
A
T
J
Ambient temperature for the
suffix 7 version
°C
Junction temperature range
Suffix 7 version
1. When
RESET is released functionality is guaranteed down to V
BOR0
Min.
2. When
V
DDmin
is lower then 1.95
V
,
t
he SMPS operation mode must be conditioned by enabling the BORH configuration to
force SMPS bypass mode, or the SMPS must not be enabled.
3. This
formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between min (V
DD
, V
DDA
, V
DDUSB
, V
LCD
) + 3.6 V and 5.5
V
.
4. For
operation with voltage higher than min (V
DD
, V
DDA
, V
DDUSB
, V
LCD
) + 0.3
V
,
t
he internal pull-up and pull-down resistors
must be disabled.
5. If
T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
J
max (see
Section 7.5: Thermal
6. In
low-power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
J
max (see
Section 7.5:
6.3.3
RF BLE characteristics
RF characteristics are given at 1 Mbps, unless otherwise specified.
Table 25. RF transmitter BLE characteristics
Symbol
Parameter
Frequency operating range
Crystal frequency
Test conditions
Min
Typ
–
Max
Unit
MHz
kHz
F
op
F
xtal
∆
F
–
–
–
2402
2480
–
–
32
250
–
–
Delta frequency
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Table 25. RF transmitter BLE characteristics (continued)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
–
–
–
–
1
2
2
–
Rgfsk
On Air data rate
RF channel spacing
Mbps
MHz
PLLres
(1)
Table 26. RF transmitter BLE characteristics (1 Mbps)
Symbol
Parameter
Test conditions
Min Typ Max Unit
SMPS Bypass or
ON (V
FBSMPS
= 1.7 V and
–
–
6.0
3.7
–
–
V
DD
> 1.95 V)
(2)
Maximum output power
SMPS Bypass (V
DD
> 1.71 V) or
ON (V
FBSMPS
= 1.4 V and
dBm
P
rf
–
–
–
0
-20
–
–
–
0 dBm output power
–
Minimum output power
Tx = 0 dBm – Typical
-0.5
0.4
dB
P
band
Output power variation over the band
Tx = maximum output power
–
–
–
670
-50
-53
–
–
–
kHz
BW6dB 6
dB signal bandwidth
2 MHz
Bluetooth
®
Low Energy: -20 dBm
IBSE
In band spurious emission
dBm
≥
3 MHz
Bluetooth
®
Low Energy: -30 dBm
Bluetooth
®
Low Energy: ±50 kHz
-50
-20
–
–
+50
+20
kHz
f
d
Frequency drift
Bluetooth
®
Low Energy:
±20 kHz / 50 µs
kHz/
50 µs
maxdr
Maximum drift rate
Bluetooth
®
Low Energy:
±150 kHz
-150
225
–
–
–
+150
275
–
fo
Frequency offset
kHz
Bluetooth
®
Low Energy:
between 225 and 275 kHz
∆
f1
∆
fa
Frequency deviation average
Frequency deviation
∆
f2 (average) /
∆
f1 (average)
Bluetooth
®
Low Energy:> 0.80
0.80
–
< 1 GHz
≥
1 GHz
–
–
–
–
-61
-46
–
–
Out of band
spurious emission
OBSE
(3)
dBm
1. Measured
in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and
impedance matching networks to interface with a 50
ꢀ
antenna.
2. V
FBSMPS
and V
DD
must be set to different voltage levels, depending upon the desired TX signal (see AN5246
Usage of
3. Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 27. RF transmitter BLE characteristics (2 Mbps)
Symbol
Parameter
Test conditions
Min Typ Max Unit
SMPS Bypass or ON
(V
FBSMPS
= 1.7 V and
–
–
6.0
3.7
–
–
V
DD
> 1.95 V)
(2)
Maximum output power
SMPS Bypass or ON
(V
FBSMPS
= 1.4 V and
dBm
P
rf
–
–
–
0
-20
–
–
–
0 dBm output power
–
Minimum output power
Tx = 0 dBm – Typical
-0.5
0.4
dB
P
band
Output power variation over the band
Tx = maximum output power
–
–
–
670
-56
-57
-58
–
–
–
kHz
BW6dB
6 dB signal bandwidth
4 MHz
Bluetooth
®
Low Energy: -20 dBm
Bluetooth
®
Low Energy: -20 dBm
IBSE
f
d
In band spurious emission
5 MHz
dBm
kHz
≥
6 MHz
Bluetooth
®
Low Energy: -30 dBm
Bluetooth
®
Low Energy: ±50 kHz
-50
-20
–
–
–
–
50
20
Frequency drift
Bluetooth
®
Low Energy:
±20 kHz / 50 µs
kHz/
50 µs
maxdr
fo
Maximum drift rate
Frequency offset
Bluetooth
®
Low Energy: ±150 kHz
-150
150
550
Bluetooth
®
Low Energy:
450
kHz
∆
f1
Frequency deviation average
between 450 and 550 kHz
Frequency deviation
∆
f2 (average) /
∆
f1 (average)
Bluetooth
®
Low Energy:> 0.80
0.80
–
–
–
∆
fa
< 1 GHz
≥
1 GHz
–
–
–
–
-61
-46
–
–
Out of band
spurious emission
OBSE
(3)
dBm
1. Measured
in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and
impedance matching networks to interface with a 50
ꢀ
antenna.
2. V
FBSMPS
and V
DD
must be set to different voltage levels, depending upon the desired TX signal (see AN5246
Usage of
3. Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Table 28. RF receiver BLE characteristics (1 Mbps)
Parameter Test
conditions
Symbol
Typ
Unit
PER <30.8%
Prx_max
Maximum input signal
0
Bluetooth
®
Low Energy: min -10 dBm
High sensitivity mode (SMPS Bypass)
High sensitivity mode (SMPS ON)
-96
PER <30.8%
Bluetooth
®
Low Energy: max -70 dBm
Psens
(1)
dBm
-95.5
RSSI maximum value
RSSI minimum value
RSSI accuracy
–
-7
-94
2
Rssi
maxrange
Rssi
minrange
Rssi
accu
–
–
Co-channel rejection
Bluetooth
®
Low Energy: 21 dB
8
C/Ico
Adj
≥
5 MHz
-53
-53
-48
-33
-46
-39
-35
-2
Bluetooth
®
Low Energy: -27 dB
Adj
≤
-5 MHz
Bluetooth
®
Low Energy: -27 dB
Adj = 4 MHz
Bluetooth
®
Low Energy: -27 dB
Adj = -4 MHz
Bluetooth
®
Low Energy: -15 dB
dB
Adj = 3 MHz
Adjacent channel interference
C/I
Bluetooth
®
Low Energy: -27 dB
Adj = 2 MHz
Bluetooth
®
Low Energy: -17 dB
Adj = -2 MHz
Bluetooth
®
Low Energy: -15 dB
Adj = 1 MHz
Bluetooth
®
Low Energy: 15 dB
Adj = -1 MHz
2
Bluetooth
®
Low Energy: 15 dB
C/Image
P_IMD
Image rejection (F
image
= -3 MHz)
Intermodulation
Bluetooth
®
Low Energy: -9 dB
-29
-34
|f2-f1| = 3 MHz
Bluetooth
®
Low Energy: -50 dBm
|f2-f1| = 4 MHz
-30
-32
dBm
Bluetooth
®
Low Energy: -50 dBm
|f2-f1| = 5 MHz
Bluetooth
®
Low Energy: -50 dBm
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Table 28. RF receiver BLE characteristics (1 Mbps) (continued)
Parameter Test
conditions
Symbol
Typ
Unit
30 to 2000 MHz
-3
Bluetooth
®
Low Energy: -30 dBm
2003 to 2399 MHz
-5
-2
7
Bluetooth
®
Low Energy: -35 dBm
P_OBB
Out of band blocking
dBm
2484 to 2997 MHz
Bluetooth
®
Low Energy: -35 dBm
3 to 12.75 GHz
Bluetooth
®
Low Energy: -30 dBm
1. With
ideal TX.
Table 29. RF receiver BLE characteristics (2 Mbps)
Parameter Test
conditions
Symbol
Typ
Unit
PER <30.8%
Prx_max
Maximum input signal
0
Bluetooth
®
Low Energy: min -10 dBm
High sensitivity mode (SMPS Bypass)
High sensitivity mode (SMPS ON)
-93
PER <30.8%
Bluetooth
®
Low Energy: max -70 dBm
Psens
(1)
dBm
-92.5
RSSI maximum value
RSSI minimum value
RSSI accuracy
–
-7
-94
2
Rssi
maxrange
Rssi
minrange
Rssi
accu
–
–
Co-channel rejection
Bluetooth
®
Low Energy spec: 21 dB
9
C/Ico
Adj
≥
8MHz
-53
-50
-49
-46
-42
-3
Bluetooth
®
Low Energy: -27 dB
Adj
≤
-8 MHz
Bluetooth
®
Low Energy: -27 dB
Adj = 6 MHz
Bluetooth
®
Low Energy: -27 dB
dB
Adj = -6 MHz
Adjacent channel interference
C/I
Bluetooth
®
Low Energy: -15 dB
Adj = 4 MHz
Bluetooth
®
Low Energy: -17 dB
Adj = 2 MHz
Bluetooth
®
Low Energy:15 dB
Adj = -2 MHz
-3
Bluetooth
®
Low Energy:15 dB
C/Image
Image rejection (F
image
= -4 MHz)
Bluetooth
®
Low Energy: -9 dB
-26
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Table 29. RF receiver BLE characteristics (2 Mbps) (continued)
Parameter Test
conditions
Symbol
Typ
Unit
|f2-f1| = 6 MHz
-29
Bluetooth
®
Low Energy: -50 dBm
|f2-f1| = 8 MHz
P_IMD
Intermodulation
-30
-29
-3
Bluetooth
®
Low Energy: -50 dBm
|f2-f1| = 10 MHz
Bluetooth
®
Low Energy: -50 dBm
30 to 2000 MHz
dBm
Bluetooth
®
Low Energy: -30 dBm
2003 to 2399 MHz
-9
Bluetooth
®
Low Energy: -35 dBm
P_OBB
Out of band blocking
2484 to 2997 MHz
-3
Bluetooth
®
Low Energy: -35 dBm
3 to 12.75 GHz
4
Bluetooth
®
Low Energy: -30 dBm
1. With
ideal TX.
(1)
Table 30. RF BLE power consumption for V
= 3.3 V
DD
Symbol
Parameter
Typ Unit
TX maximum output power consumption (SMPS Bypass)
12.7
7.8
I
txmax
TX maximum output power consumption (SMPS On, V
FBSMPS
= 1.7 V)
TX 0 dBm output power consumption (SMPS Bypass)
TX 0 dBm output power consumption (SMPS On, V
FBSMPS
= 1.4 V)
Rx consumption (SMPS Bypass)
8.8
mA
5.2
I
tx0dbm
7.9
4.5
I
rxlo
Rx consumption (SMPS On, V
FBSMPS
= 1.4 V)
1. Power
consumption including RF subsystem and digital processing.
6.3.4
RF 802.15.4 characteristics
Table 31. RF transmitter 802.15.4 characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
F
op
F
xtal
∆
F
Frequency operating range
Crystal frequency
–
–
–
–
–
2405
–
32
5
2480
–
–
–
–
–
–
–
–
MHz
Delta frequency
Roqpsk On
air data rate
250
5
kbps
MHz
PLLres RF
channel spacing
DS11929 Rev 10
169
Electrical characteristics
Symbol
STM32WB55xx STM32WB35xx
Table 31. RF transmitter 802.15.4 characteristics (continued)
Parameter
Conditions
Min Typ Max Unit
SMPS Bypass or ON
(V
FBSMPS
= 1.7 V and
V
DD
> 1.95 V)
–
–
5.7
3.7
–
–
Maximum output power
(1)
SMPS Bypass
(V
DD
> 1.71 V) or ON
(V
FBSMPS
= 1.4 V and
V
DD
> 1.95 V)
Prf
dBm
0 dBm output power
–
–
–
0
-20
–
–
Minimum output power
–
–
0.4
–
Pband Output
power variation over the band
Tx = 0 dBm – Typical
-0.5
dB
%
EVMrms EVM
rms
Txpd Transmit
power density
Pmax
–
–
8
|f – fc| > 3.5 MHz
-35
–
dB
1. Measured
in conducted mode, based on reference design (see AN5165), using output power specific
external RF filter and impedance matching networks to interface with a 50
ꢀ
antenna.
Table 32. RF receiver 802.15.4 characteristics
Symbol
Parameter
Conditions
Typ
Unit
Prx_max
Maximum input signal
Min: -20 dBm and PER < 1%
-10
-100
-98
35
Sensitivity (SMPS Bypass)
Sensitivity (SMPS ON)
Adjacent channel rejection
Alternate channel rejection
dBm
Max: -85 dBm and PER < 1%
Rsens
–
–
C/adj
C/alt
dB
46
Figure 19. Typical link quality indicator code vs. Rx level
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 20. Typical energy detection (T = 27°C, V
= 3.3 V)
DD
(1)
Table 33. RF 802.15.4 power consumption for V
= 3.3 V
DD
Symbol
Parameter
Typ
Unit
TX maximum output power consumption (SMPS Bypass)
TX maximum output power consumption (SMPS On, V
FBSMPS
= 1.7 V)
TX 0 dBm output power consumption (SMPS Bypass)
TX 0 dBm output power consumption (SMPS On, V
FBSMPS
= 1.4 V)
Rx consumption (SMPS Bypass)
11.7
6.5
9.1
4.5
9.2
4.5
I
txmax
I
tx0dbm
mA
I
rxlo
Rx consumption (SMPS On)
1. Power
consumption including RF subsystem and digital processing.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.5
Operating conditions at power-up / power-down
Table 34. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
V
DD
rise time rate
–
10
0
∞
∞
∞
∞
∞
∞
∞
∞
t
VDD
–
V
DD
fall time rate
V
DDA
rise time rate
V
DDA
fall time rate
V
DDUSB
rise time rate
V
DDUSB
fall time rate
V
DDRF
rise time rate
t
VDDA
t
VDDUSB
t
VDDRF
–
–
–
10
0
µs/V
10
–
V
DDRF
fall time rate
–
6.3.6
Embedded reset and power control block characteristics
Table 35. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
(1)
Min
Typ
Max Unit
(2)
t
RSTTEMPO
Reset temporization after BOR0 is detected
V
DD
rising
–
250
400
μ
s
Rising edge
Brown-out reset threshold 0
1.62 1.66 1.70
1.60 1.64 1.69
2.06 2.10 2.14
1.96 2.00 2.04
2.26 2.31 2.35
2.16 2.20 2.24
2.56 2.61 2.66
2.47 2.52 2.57
2.85 2.90 2.95
2.76 2.81 2.86
2.10 2.15 2.19
2.00 2.05 2.10
2.26 2.31 2.36
2.15 2.20 2.25
2.41 2.46 2.51
2.31 2.36 2.41
(2)
V
BOR0
Falling edge
Rising edge
Brown-out reset threshold 1
V
BOR1
V
BOR2
V
BOR3
V
BOR4
V
PVD0
V
PVD1
V
PVD2
Falling edge
Rising edge
Brown-out reset threshold 2
Falling edge
Rising edge
Brown-out reset threshold 3
Falling edge
V
Rising edge
Brown-out reset threshold 4
Falling edge
Rising edge
Programmable voltage detector threshold 0
Falling edge
Rising edge
PVD threshold 1
Falling edge
Rising edge
PVD threshold 2
Falling edge
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Table 35. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
(1)
Min
Typ
Max Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.56 2.61 2.66
2.47 2.52 2.57
2.69 2.74 2.79
2.59 2.64 2.69
2.85 2.91 2.96
2.75 2.81 2.86
2.92 2.98 3.04
2.84 2.90 2.96
V
PVD3
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
PVD4
V
PVD5
V
PVD6
V
Hysteresis in
continuous mode
–
–
–
–
20
30
–
–
V
hyst_BORH0
Hysteresis voltage of BORH0
Hysteresis in
other mode
mV
Hysteresis voltage of BORH (except
BORH0) and PVD
V
hyst_BOR_PVD
–
–
100
1.1
–
BOR
(3)
(except BOR0) and PVD
consumption from V
DD
I
DD
(BOR_PVD)
(2)
V
PVM1
1.6
µA
V
V
DDUSB
peripheral voltage monitoring
–
1.18 1.22 1.26
1.61 1.65 1.69
Rising edge
V
PVM3
V
DDA
peripheral voltage monitoring
Falling edge
1.6
1.64 1.68
V
hyst_PVM3
V
hyst_PVM1
DD
(PVM1)
(2)
I
DD
(PVM3)
(2)
PVM3 hysteresis
–
–
–
–
–
–
–
–
10
10
0.2
2
–
–
–
–
mV
µA
PVM1 hysteresis
I
PVM1 consumption from V
DD
PVM3 consumption from V
DD
1. Continuous
mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Guaranteed
by design.
3. BOR0
is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current
characteristics tables.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.7
Embedded voltage reference
Table 36. Embedded internal voltage reference
Symbol
V
REFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltage
–40 °C < T
A
< +125 °C
1.182 1.212
1.232
V
ADC sampling time when reading
the internal reference voltage
(1)
t
S_vrefint
t
start_vrefint
I
DD
(V
REFINTBUF
ꢁ
V
REFINT
–
4
(2)
–
8
–
µs
Start time of reference voltage
buffer when ADC is enabled
–
–
–
–
12
(2)
20
(2)
V
REFINT
buffer consumption from
V
DD
when converted by ADC
)
–
12.5
µA
Internal reference voltage spread
over the temperature range
V
DD
= 3 V
5
7.5
(2)
50
(2)
mV
T
Coeff
A
Coeff
T
e
mperature coefficient
Long term stability
Voltage coefficient
–40 °C < T
A
< +125 °C
1000 hours, T = 25 °C
3.0 V < V
DD
< 3.6 V
–
–
30
ppm/°C
ppm
300 1000
(2)
V
DDCoeff
–
250 1200
(2)
ppm/V
V
REFINT_DIV1
1/4 reference voltage
V
REFINT_DIV2
1/2 reference voltage
V
REFINT_DIV3
3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
–
V
REFINT
1. The
shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed
by design.
Figure 21. V
vs. temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
40
60
80
100
120
Mean
Min
Max
MSv40169V1
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3.8
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
Typical and maximum current consumption
The MCU is put under the following conditions:
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “Number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the reference manual).
When the peripherals are enabled f
= f
PCLK
HCLK
PCLK
For Flash memory and shared peripherals f
= f
= f
HCLK HCLKS
DS11929 Rev 10
169
Table 37. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF), V
= 3.3 V
DD
Conditions
Typ
Max
(1)
Symbol
Parameter
Unit
Voltage
scaling
–
f
HCLK
25 °C
55 °C
85 °C
105 °C
25 °C
85 °C
105 °C
16 MHz
2 MHz
1.90
1.90
2.00
2.20
1.25
8.60
4.65
2.65
5.20
3.35
2.45
2.40
1.25
9.30
4.25
2.65
–
2.52
1.57
2.96
2.05
Range 2
0.960 0.985 1.10
f
HCLK
= f
HSI16
up to
16 MHz included,
f
HCLK
= f
HSE
= 32 MHz
64 MHz
8.15
4.20
2.25
5.00
3.15
2.30
8.25
4.25
2.30
5.00
3.15
2.30
8.40
4.40
2.40
5.10
3.25
2.35
9.60 10.02
Supply
Range 1
32 MHz
16 MHz
4.63
5.17
I
DD
(Run)
current in
f
HSI16
+ PLL ON
Run mode
above 32 MHz
All peripherals
2.91
3.52
64 MHz
SMPS
32 MHz
Range 1
–
–
–
–
–
–
disabled
mA
–
16 MHz
2 MHz
1 MHz
–
0.335 0.360
0.470 0.670 0.480 0.910
1.47
0.170 0.210
0.325 0.520 0.270 0.730
1.31
Supply
current in
f
HCLK
= f
MSI
Low-power All
peripherals disabled
run mode
I
DD
(LPRun)
400 kHz
0.0815 0.120 0.230
0.425 0.140 0.590
1.18
100 kHz
0.0415 0.076 0.190
0.385 0.070 0.550
1.14
1. Guaranteed
by characterization results, unless otherwise specified.
Table 38. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, V
= 3.3 V
DD
Conditions
Typ
Max
(1)
Symbol
Parameter
Unit
Voltage
scaling
–
f
HCLK
25 °C
55 °C
85 °C
105 °C
25 °C
85 °C
105 °C
16 MHz
2.00
2.05
2.15
1.10
9.00
4.70
2.55
5.35
3.35
2.40
2.30
1.25
2.57
1.62
3.04
1.90
3.64
2.55
Range 2
2 MHz
0.970 1.00
f
HCLK
= f
HSI16
up to
16 MHz included,
64 MHz
8.80
8.90
4.55
2.40
5.30
3.25
2.35
9.20 10.50
10.80 11.30
Supply
f
HCLK
= f
HSE
= 32 MHz
Range 1
32 MHz
4.50
16 MHz
2.40
4.90
2.70
5.45
3.45
2.45
4.63
4.89
5.62
I
DD
(Run)
current in
f
HSI16
+ PLL ON
2.50
2.70
3.21
Run mode
above 32 MHz
All peripherals
64 MHz
5.25
–
–
–
–
–
–
–
–
–
disabled
mA
SMPS
Range 1
32 MHz
3.25
16 MHz
2.35
2 MHz
0.265 0.285 0.385 0.550 0.440 0.940 1.620
1 MHz
0.135 0.170 0.270 0.430 0.290 0.760 1.480
400 kHz
0.066 0.097 0.195 0.360 0.200 0.670 1.380
100 kHz
0.031 0.0625 0.160
0.325 0.170
0.470 1.330
Supply
current in
f
HCLK
= f
MSI
Low-power All
peripherals disabled
run mode
I
DD
(LPRun)
1. Guaranteed
by characterization results, unless otherwise specified.
Electrical characteristics
STM32WB55xx STM32WB35xx
Table 39. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
,
V =
3.3 V
DD
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
–
Code
25 °C
25 °C
Reduced code
(1)
Coremark
1.90
1.85
1.85
1.75
1.60
8.15
8.00
8.10
7.60
6.85
5.00
4.95
4.95
4.75
4.40
4.07
3.99
4.04
3.79
3.42
320
119
116
116
109
100
127
125
127
119
107
78
Dhrystone 2.1
Fibonacci
mA
µA/MHz
While(1)
Coremark
Dhrystone 2.1
Fibonacci
mA
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
µA/MHz
While(1)
Supply current in
Run mode
I
DD
(Run)
Coremark
77
Dhrystone 2.1
Fibonacci
77
74
While(1)
69
64
Coremark
62
Dhrystone 2.1
Fibonacci
63
59
While(1)
53
160
175
175
195
113
Coremark
350
Supply current in
Low-power run
f
HCLK
= f
MSI
= 2 MHz
I
DD
(LPRun)
Dhrystone 2.1
Fibonacci
350
All peripherals disable
390
While(1)
225
2. Value
computed. MCU consumption when RF TX and SMPS are ON.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Table 40. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1
,
V =
3.3 V
DD
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
–
Code
25 °C
25 °C
Reduced code
(1)
Coremark
2.00
1.75
1.95
1.85
1.85
8.80
7.50
8.60
7.90
8.00
5.25
4.65
5.15
4.85
4.90
4.39
3.74
4.29
3.94
3.99
255
125
109
122
116
116
138
117
134
123
125
82
Dhrystone 2.1
Fibonacci
mA
µA/MHz
While(1)
Coremark
Dhrystone 2.1
Fibonacci
mA
mA
mA
µA
µA/MHz
µA/MHz
µA/MHz
µA/MHz
While(1)
Supply current in
Run mode
I
DD
(Run)
Coremark
73
Dhrystone 2.1
Fibonacci
80
76
While(1)
77
69
Coremark
58
Dhrystone 2.1
Fibonacci
67
62
While(1)
62
128
103
125
115
110
Coremark
205
Supply current in
Low-power run
f
HCLK
= f
MSI
= 2 MHz
All peripherals disable
I
DD
(LPRun)
Dhrystone 2.1
Fibonacci
250
230
While(1)
220
2. Value
computed. MCU consumption when RF TX and SMPS are ON.
DS11929 Rev 10
169
Table 41. Current consumption in Sleep and Low-power sleep modes, Flash memory ON
Conditions TYP
MAX
(1)
Symbol
Parameter
Unit
Voltage
scaling
–
f
HCLK
25 °C
55 °C
85 °C
105 °C
25 °C
85 °C
105 °C
f
HCLK
= f
HSI16
up
to 16 MHz
included,
f
HCLK
= f
HSE
up to
32 MHz
f
HSI16
+ PLL ON
above 32 MHz
All peripherals
disabled
Range 2
16 MHz
64 MHz
0.740 0.765
0.865
2.80
1.05
3.00
1.80
1.20
2.75
2.10
1.80
0.840 1.210
1.810
2.65
1.40
2.70
1.45
3.00
1.55
3.33
1.86
3.91
2.49
2.02
–
Range 1
32 MHz
16 MHz
64 MHz
32 MHz
16 MHz
2 MHz
1.60
Supply
current in
sleep mode,
I
DD
(Sleep)
0.845 0.875
0.990
2.65
0.970 1.40
2.60
1.90
1.70
2.60
1.95
1.70
–
–
–
–
–
–
SMPS
Range 1
2.00
–
mA
1.75
–
0.090 0.125
0.058 0.093
0.235
0.205
0.430 0.130
0.600
0.400 0.090
0.570
0.380 0.070
0.540
1.19
1.16
1.11
1.13
Supply
current in
1 MHz
f
HCLK
= f
MSI
low-power All
peripherals disabled
I
DD
(LPSleep)
400 kHz
0.044 0.0725 0.185
sleep mode
100 kHz
0.0315 0.0635 0.0175
0.370 0.055
0.530
1. Guaranteed
by characterization results, unless otherwise specified.
Table 42. Current consumption in Low-power sleep modes, Flash memory in Power down
Conditions
TYP
MAX
(1)
Symbol Parameter
Unit
–
f
HCLK
25 °C
55 °C
85 °C
105 °C
25 °C
85 °C
105 °C
2 MHz
1 MHz
94.0
56.5
40.5
27.5
115
86.0
66.5
57.5
200
170
150
140
335
305
285
275
135
94.2
68.0
54.6
610
560
540
539
1201
1171
1129
1131
Supply
current in
f
HCLK
= f
MSI
I
DD
µA
(LPSleep) low-power All
peripherals
400 kHz
100 kHz
sleep mode
disabled
1. Guaranteed
by characterization results, unless otherwise specified.
Table 43. Current consumption in Stop 2 mode
Conditions TYP
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
50.0 1.58
4.12 56.9 132.7
51.0
MAX
(1)
Symbol
Parameter
Unit
–
1.8 V
1.00 1.85
3.15 5.95 21.5
2.4 V
1.10 1.85
3.20 6.00 22.0
3.0 V
1.10 1.85
3.25 6.10 22.0
3.6 V
1.15 1.95
3.35 6.25 23.0
1.8 V
1.20 2.00
3.35 6.10 22.0
2.4 V
1.20 2.00
3.40 6.20 22.0
3.0 V
1.25 2.10
3.45 6.30 22.5
3.6 V
1.30 2.15
3.60 6.55 23.0
1.8 V
1.30 2.10
3.45 6.25 22.0
2.4 V
1.45 2.25
3.55 6.40 22.5
3.0 V
1.50 2.30
3.70 6.55 22.5
3.6 V
1.75 2.50
3.95 6.85 23.5
1.8 V
1.35 2.20
3.55 6.30 22.0
2.4 V
1.50 2.35
3.65 6.50 22.5
3.0 V
1.70 2.45
3.85 6.65 23.0
3.6 V
1.80 2.60
4.05 6.95 23.5
1.8 V
1.35 2.20
3.50 6.25 22.0
2.4 V
1.45 2.25
3.65 6.40 22.5
3.0 V
1.55 2.45
3.80 6.65 23.0
3.6 V
1.70 2.55
4.05 6.95 23.5
–
–
–
–
LCD disabled
BLE disabled
52.0 1.60
4.17 57.9 135.6
53.0 1.69
4.40 58.6 135.7
50.5 1.76
4.30 57.1 133.3
Supply current
in Stop 2
(Stop 2)
mode, RTC
disabled
I
DD
LCD enabled
(2)
and clocked
by LSI
51.0
–
–
–
–
52.0 1.85
4.41 58.1 135.8
53.5 1.97
4.66 59.4 136.6
50.5 1.91
4.50 57.2 133.0
BLE disabled
RTC clocked
by LSI,
LCD disabled
51.5
–
–
–
–
µA
52.5 2.11
4.64 58.3 136.1
53.5 2.26
5.12 59.7 136.9
50.5 1.99
4.57 57.4 133.8
Supply current
I
DD
in Stop 2
(Stop 2
mode, RTC
with
RTC clocked
by LSI,
51.5
–
–
–
–
enabled, BLE
LCD enabled
(2)
disabled
52.5 2.17
4.87 58.4 136.3
54.0 2.41
5.11 59.9 137.1
50.5 1.91
4.29 57.1 133.5
RTC)
RTC clocked by
LSE quartz
(3)
in low drive
mode
51.5
–
–
–
–
52.5 2.01
4.31 58.0 135.9
54.0 2.16
4.40 81.6 137.0
Table 43. Current consumption in Stop 2 mode (continued)
Conditions
TYP
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
MAX
(1)
Symbol
Parameter
Unit
–
Wakeup clock is
HSI16, voltage
3.0 V
–
–
389
320
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Range 2. See
(4)
.
Supply current
Wakeup clock is
I
DD
during
wakeup from
MSI = 32 MHz,
voltage
(wakeup
from
3.0 V
3.0 V
µA
Stop 2 mode
Range 1. See
(4)
.
Stop 2)
bypass mode
Wakeup clock is
MSI = 4 MHz,
voltage
–
528
–
–
–
–
–
–
–
–
Range 2. See
(4)
.
1. Guaranteed
based on test during characterization, unless otherwise specified.
2. LCD
enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for I
VLCD
3. Based
on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading
capacitors.
4. Wakeup
with code execution from Flash memory. Average value given for a typical wakeup time as specified in
T
a
ble 51: Low-power mode
wakeup timings
.
Table 44. Current consumption in Stop 1 mode
Conditions TYP
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
210 7.00
28.4 343.7 738.6
215
MAX
(1)
Symbol Parameter
Unit
–
1.8 V
5.05 9.20
15.5 28.0 96.0
2.4 V
5.10 9.25
15.5 28.5 96.5
3.0 V
5.15 9.30
15.5 28.5 97.0
3.6 V
5.25 9.45
16.0 29.0 97.5
1.8 V
5.05 9.30
15.5 28.5 96.0
2.4 V
5.10 9.35
16.0 28.5 96.5
3.0 V
5.20 9.65
16.0 28.5 97.0
3.6 V
5.55 9.85
16.0 29.0 98.5
1.8 V
5.30 9.35
16.0 28.5 96.5
2.4 V
5.40 9.45
16.0 28.5 97.0
3.0 V
5.70 9.55
16.5 29.0 98.5
3.6 V
5.85 10.0
16.5 29.5 96.5
1.8 V
5.25 9.60
16.0 28.5 96.5
2.4 V
5.30 9.75
16.0 29.0 97.0
3.0 V
5.85 9.80
16.5 29.0 97.5
3.6 V
5.90 10.5
16.5 29.0 98.5
1.8 V
5.35 9.55
16.0 28.5 96.5
2.4 V
5.40 9.70
16.0 29.0 96.5
3.0 V
5.75 9.70
16.0 29.0 97.5
3.6 V
5.90 10.0
16.5 29.5 99.0
–
–
–
–
BLE disabled
LCD disabled
Supply
current in
Stop 1 mode,
(Stop 1)
RTC
215 7.07
28.5 346.8 746.0
215 7.30
28.8 351.0 749.4
210 7.10
28.7 344.4 739.0
I
DD
BLE disabled
LCD enabled
(2)
clocked by LSI
215
–
–
–
–
disabled
,
215 7.26
29.6 345.0 747.0
215 7.62
29.8 349.0 750.8
215 7.30
29.5 343.7 739.2
215
–
–
–
–
RTC clocked by LSI
LCD disabled
µA
220 7.69
29.7 347.2 746.1
215 8.08
29.8 349.9 751.1
215 7.10
29.0 344.3 739.9
Supply
current in
I
DD
215
–
–
–
–
(Stop 1
Stop 1 mode,
RTC clocked by LSI
with
RTC) enabled,
BLE disabled
RTC
LCD enabled
(2)
215 7.53
29.8 347.4 746.2
220 8.18
29.9 350.6 751.8
215 6.00
28.7 343.9 738.7
RTC clocked by
LSE quartz
(3)
in
Low drive mode
215
–
–
–
–
215 7.40
28.9 346.6 743.8
220 7.58
29.2 349.0 749.9
Table 44. Current consumption in Stop 1 mode (continued)
Conditions
–
TYP
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
MAX
(1)
Symbol Parameter
Unit
Wakeup clock
HSI16,
3.0 V
3.0 V
3.0 V
–
–
–
129
124
207
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
voltage Range 2.
See
(4)
.
Supply
I
DD
(wakeup during
from
Stop1) Stop
1
bypass mode
current
Wakeup clock
MSI = 32 MHz,
µA
wakeup from
voltage Range 1.
See
(4)
.
Wakeup clock
MSI = 4 MHz,
voltage Range 2.
See
(4)
.
1. Guaranteed
based on test during characterization, unless otherwise specified.
2. LCD
enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for I
VLCD
3. Based
on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. Wakeup
with code execution from Flash. Average value given for a typical wakeup time as specified in
T
a
ble 51: Low-power mode wakeup
timings
.
Table 45. Current consumption in Stop 0 mode
Conditions TYP
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
MAX
(1)
Symbol
Parameter
Unit
–
1.8 V
95.5 100
2.4 V
97.5 105
3.0 V
98.5 105
3.6 V
100 105
110
110
110
115
120 195
125 195
125 195
125 200
315
315
320
320
110.0 114.2 458.1
874.8
Supply current
in Stop 0 mode,
RTC disabled,
BLE disabled,
LCD disabled
–
–
–
–
—
117.3 134.3 461.8
880.0
165.0 135.7 494.0
884.1
Wakeup clock
HSI16,
3.0 V
3.0 V
3.0 V
–
–
–
331
349
196
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
DD
(Stop 0)
voltage Range 2.
µA
See
(2)
.
Supply current
Wakeup clock is
during wakeup
MSI = 32 MHz,
from Stop 0
Bypass mode
voltage Range 1.
See
(2)
.
Wakeup clock is
MSI = 4 MHz,
voltage Range 2.
See
(2)
.
2. Wakeup
with code execution from Flash
memory
. Average value given for a typical wakeup time as specified in
T
a
ble 51: Low-power mode
wakeup timings
.
Table 46. Current consumption in Standby mode
Conditions
TYP
MAX
(1)
Symbol
Parameter
Unit
–
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
1.8 V
0.270 0.320 0.515 0.920
3.45
2.4 V
0.270 0.350 0.540 0.955
3.50
3.0 V
0.270 0.370 0.575
1.00 3.85
8.20
8.80
9.50
0.300 0.828 7.850 19.300
BLE disabled
No independent
watchdog
–
–
–
–
Suppl
y
c
urrent
in Standby
mode (backup
registers and
SRAM2a
0.380 0.945 8.505 21.200
3.6 V
0.300 0.410 0.645
1.15 4.20 10.50
0.400 1.040 8.980 22.400
I
DD
(Standby)
1.8 V
0.265 0.525 0.710
1.10 3.90
2.4 V
0.280 0.595 0.790
1.20 4.00
3.0 V
0.290 0.670 0.855
1.35 4.15
3.6 V
0.295 0.770 0.990
1.50 4.60
1.8 V
0.500 0.600 0.780
1.20 3.70
2.4 V
0.630 0.705 0.910
1.30 3.80
3.0 V
0.725 0.825 1.050
1.50 3.95
3.6 V
0.860 0.970 1.200
1.70 4.25
1.8 V
0.565 0.655 0.830
1.25 3.75
2.4 V
0.635 0.790 0.975
1.40 4.10
8.40
9.05
9.80
0.520 1.095 8.041 19.500
BLE disabled
With
independent
watchdog
retained),
RTC disabled
–
–
–
–
0.730 1.253 8.774 21.400
11.00 0.851
1.356 9.360 22.840
8.45
9.10
9.90
0.680 1.165 8.143 19.660
RTC clocked by
LSI, no
independent
watchdog
–
–
–
–
µA
0.930 1.463 8.977 21.440
Suppl
y
c
urrent
in Standby
11.00 1.050
1.628 9.634 23.080
8.55
9.20
0.734 1.196 8.187 19.710
mode (backup
RTC clocked by
registers and
LSI, with
I
DD
–
–
–
–
(Standby with
RTC)
SRAM2a
independent
watchdog
3.0 V
0.725 0.915 1.100
1.55 4.50 10.00
1.028 1.573 9.072 21.810
retained),
RTC enabled
BLE disabled
3.6 V
0.870 1.050 1.300
1.80 4.90
1.8 V
0.525 0.625 0.840
1.25 3.75
2.4 V
0.665 0.755 0.960
1.35 4.05
11.00 1.144
1.723 9.730 23.200
8.60
9.25
0.600 1.061 8.029 19.610
RTC clocked by
–
–
–
–
(2)
LSE quartz
in
3.0 V
0.775 0.880 1.100
1.55 4.40 10.00
0.600 1.100 8.719 21.570
3.6 V
0.935 1.050 1.300
1.80 5.00 11.00
0.750 1.171 9.460 23.030
low drive mode
Table 46. Current consumption in Standby mode (continued)
Conditions
TYP
MAX
(1)
Symbol
Parameter
Unit
–
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
1.8 V
0.160 0.210 0.380 0.660
2.30
2.4 V
0.165 0.245 0.375 0.650
2.15
3.0 V
0.155 0.250 0.385 0.630
2.25
3.6 V
0.155 0.235 0.375 0.670
2.20
5.15
5.20
5.20
5.20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Supply
current to be
subtracted in
Standby
mode when
SRAM2a is
not retained
I
DD
–
µ
A
(SRAM2a)
(3)
Suppl
y
c
urrent
during
wakeup from
Standb
y
m
ode
I
Wakeup clock is
HSI16. See
.
3.0 V
SMPS OFF
DD
(4)
(wakeup from
Standby)
–
1.73
–
–
–
–
–
–
–
–
mA
1. Guaranteed
by characterization results, unless otherwise specified.
2. Based
on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading
capacitors.
3. The
supply current in Standby with SRAM2a mode is: I
DD
(Standby) + I
DD
(SRAM2a). The supply current in Standby with RTC with
SRAM2a mode is: I
DD
(Standby + RTC) + I
DD
(SRAM2a).
4. Wakeup
with code execution from Flash memory. Average value given for a typical wakeup time as specified in
T
a
ble 51
.
Table 47. Current consumption in Shutdown mode
Conditions TYP
V
DD
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
85 °C
105 °C
MAX
(1)
Symbol
Parameter
Unit
–
1.8 V
0.039 0.013 0.030 0.100 0.635
2.4 V
0.059 0.014 0.055 0.120 0.785
3.0 V
0.064 0.037 0.070 0.180 1.000
3.6 V
0.071 0.093 0.140 0.280 1.300
1.8 V
0.320 0.315 0.355 0.420 0.985
2.4 V
0.425 0.405 0.460 0.540 1.200
3.0 V
0.535 0.535 0.595 0.700 1.500
3.6 V
0.695 0.720 0.790 0.940 2.000
1.950
2.350
2.900
3.700
2.300
2.800
3.450
4.350
–
–
–
–
–
–
–
–
–
–
2.099
–
6.200
–
Supply current in
Shutdown mode
(backup
I
DD
–
(Shutdown) registers
retained) RTC
0.185 2.670
0.247 3.120
0.572 2.702
7.490
8.450
6.180
–
disabled
µA
Supply current in
Shutdown mode
RTC clocked
(backup
registers
retained) RTC
enabled
I
–
–
DD
by LSE
(Shutdown
with RTC)
(2)
quartz in
low
0.664 2.990
0.790 3.730
7.800
9.140
drive mode
1. Guaranteed
by characterization results, unless otherwise specified.
2. Based
on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Table 48. Current consumption in VBAT mode
Conditions
TYP
MAX
(1)
Symbol Parameter
Unit
–
V
BAT
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
1.8 V
1.00 2.00 4.00 10.0 52.0
2.4 V
1.00 2.00 5.00 12.0 60.0
3.0 V
2.00 4.00 7.00 16.0 75.0
3.6 V
7.00 15.0 23.0 42.0
170
1.8 V
295 305 315 325 380
2.4 V
385 395 400 415 475
3.0 V
495 505 515 530 600
3.6 V
630 645 660 685 830
145
165
225
450
480
595
765
1150
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RTC disabled
Backup
domain
supply
current
I
DD
(VBAT)
nA
RTC enabled
and clocked
by LSE
quartz
(2)
1. Guaranteed
by characterization results, unless otherwise specified.
2. Based
on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Table 49. Current under Reset condition
TYP
MAX
(1)
25 °C
40 °C
55 °C
85 °C
105 °C
Symbol Conditions
Unit
0 °C
25 °C
40 °C
55 °C
85 °C
105 °C
0 °C
1.8 V
–
–
–
–
410
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.4 V
–
750
–
I
DD(RST)
µ
A
3.0 V
550
750
3.6 V
1. Guaranteed
by characterization results, unless otherwise specified.
Electrical characteristics
STM32WB55xx STM32WB35xx
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise.
T
o
a
void current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
the current consumption. When an I/O pin switches, it uses the current from the I/O supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:
I
SW
=
V
DD
f
SW
C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the I/O supply voltage
SW
V
f
DD
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C
+ C
IO
EXT
C
C
is the I/O pin capacitance
IO
is the PCB board capacitance plus any connected external device pin
EXT
capacitance.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
On-chip peripheral current consumption
under the following conditions:
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
The power consumption of the digital part of the on-chip peripherals is given in
Table 50
. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 50. Peripheral current consumption
Low-power
Peripheral
Bus matrix
(1)
Range 1
Range 2
Unit
run and sleep
2.40
1.25
0.465
1.90
2.00
4.15
12.0
4.00
2.55
2.25
7.45
7.60
3.80
2.00
0.170
8.35
6.95
4.40
17.5
2.00
1.05
0.375
1.55
1.65
3.40
10.0
3.30
2.10
1.90
6.20
6.25
N/A
1.80
1.05
0.380
1.80
1.80
4.45
11.5
3.90
2.10
1.90
6.60
7.10
N/A
TSC
CRC
AHB1
DMA1
DMA2
DMAMUX
All AHB1 peripherals
AES1
ADC1 independent clock domain
ADC1 clock domain
All AHB2 peripherals
QSPI
AHB2
(2)
AHB3
µA/MHz
TRNG independent clock domain
TRNG clock domain
SRAM2
N/A
N/A
0.135
6.90
5.75
3.65
14.5
0.135
8.45
7.00
4.25
16.0
AHB Shared
FLASH
AES2
PKA
All AHB shared peripherals
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Table 50. Peripheral current consumption (continued)
Low-power
run and sleep
Peripheral
Range 1
Range 2
Unit
RTCA
1.10
0.24
3.20
2.05
2.50
4.80
2.10
3.70
1.35
1.65
2.10
3.60
5.65
2.70
4.45
3.95
2.20
0.335
27.0
1.10
8.20
2.85
2.75
4.40
8.80
1.75
2.50
2.40
28.0
97.5
0.88
0.20
N/A
1.25
0.20
N/A
CRS
USB FS independent clock domain
USB FS clock domain
I2C1 independent clock domain
I2C1 clock domain
I2C3 independent clock domain
I2C3 clock domain
LCD
N/A
N/A
4.40
4.00
3.50
3.10
1.10
1.40
3.40
3.00
4.70
4.15
3.70
3.25
3.70
0.285
22.5
0.885
6.80
2.40
2.30
7.80
7.30
1.45
1.50
N/A
4.40
5.50
3.55
3.55
2.10
2.25
3.00
3.80
4.90
3.85
5.25
4.50
3.80
0.965
25.5
1.35
7.25
2.40
2.55
7.00
7.75
1.45
3.50
N/A
APB1
SPI2
LPTIM1 independent clock domain
LPTIM1 clock domain
TIM2
LPUART1 independent clock domain
LPUART1 clock domain
LPTIM2 clock domain
LPTIM2 independent clock domain
WWDG
µA/MHz
All APB1 peripherals
AHB to APB2
(3)
TIM1
TIM17
TIM16
USART1 independent clock domain
USART1 clock domain
SPI1
APB2
SAI1 independent clock domain
SAI1 clock domain
All APB2 on
23.0
80.5
25.5
90.0
ALL
1. The
BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. GPIOs
consumption during read and write accesses.
3. The
AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3.9
Wakeup time from Low-power modes and voltage scaling
transition times
the first user instruction.
The device goes in Low-power mode after the WFE (Wait For Event) instruction.
(1)
Table 51. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ Max
Unit
Wakeup time from
t
WUSLEEP
Sleep mode
–
9
9
10
10
No. of
CPU
cycles
to Run mode
Wakeup time from
Wakeup in Flash with memory in power-down
t
WULPSLEEP
Low-power sleep mode
during low-power sleep mode (FPDS = 1 in
to Low-power run mode
PWR_CR1) and with clock MSI = 2 MHz
Wakeup clock MSI = 32 MHz
2.38 2.96
1.69 2.00
1.70 2.01
7.43 8.59
2.63 3.00
1.80 2.00
1.82 2.02
7.58 8.70
4.67 5.56
5.09 6.03
5.08 6.00
8.36 9.28
4.88 5.55
5.29 5.95
5.28 5.96
8.49 9.30
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Wake up time from
Stop 0 mode
to Run mode in Flash
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 32 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 32 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 32 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
memory
t
WUSTOP0
Wake up time from
Stop 0 mode
to Run mode in SRAM1
Wake up time from
Stop 1 mode
to Run in Flash memory
SMPS bypassed
µs
Wake up time from
Stop 1 mode
to Run in SRAM1
SMPS bypassed
t
WUSTOP1
Wake up time from
Stop 1 mode to
Low-power run mode
in Flash memory
7.96 9.59
8.00 9.47
Regulator in
Low-power
mode (LPR = 1
in PWR_CR1)
Wakeup clock MSI = 4 MHz
Wake up time from
Stop 1 mode to
Low-power run mode
in SRAM1
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 51. Low-power mode wakeup timings
(continued)
Symbol
Parameter
Conditions
Typ Max
Unit
Wakeup clock MSI = 32 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 32 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock MSI = 4 MHz
5.27 6.07
5.71 6.52
5.72 6.52
9.10 9.93
5.20 5.94
5.64 6.42
5.64 6.43
9.05 9.85
Wake up time from
Stop 2 mode
to Run mode in Flash
memory
SMPS bypassed
Range 1
Range 2
Range 1
Range 2
t
WUSTOP2
µs
Wake up time from
Stop 2 mode to Run
mode in SRAM1
SMPS bypassed
Wakeup time from
Standby mode
to Run mode
t
WUSTBY
Range 1
Wakeup clock HSI16 = 16 MHz
51.0 58.1
µs
SMPS Bypassed
1. Guaranteed
by characterization results (V
DD
= 3 V, .T = 25 °C).
(1)
Table 52. Regulator modes transition times
Symbol
Parameter
Conditions
Typ
Max
Unit
Wakeup time from Low-power run mode to
Run mode
(2)
t
WULPRUN
Code run with MSI 2 MHz
15.33
21.4
16.30
µs
Regulator transition time from Range 2 to
Range 1 or Range 1 to Range 2
(3)
t
VOST
Code run with HSI16
28.9
1. Guaranteed
by characterization results (V
DD
= 3 V, T = 25 °C).
2. Time
until REGLPF flag is cleared in PWR_SR2.
3. Time
until VOSF flag is cleared in PWR_SR2.
(1)
Table 53. Wakeup time using LPUART
Symbol
Parameter
Conditions
Stop mode 0
Typ
Max
1.7
Unit
–
–
Wakeup time needed to calculate the maximum
t
WULPUART
LPUART baud rate allowing to wakeup up from Stop
mode when LPUART clock source is HSI16
µs
Stop mode 1/2
8.5
1. Guaranteed
by design.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3.10
External clock source characteristics
High-speed external user clock generated from an external source
The high-speed external (HSE) clock is supplied with a 32 MHz crystal oscillator or a sine
wave.
The devices include internal programmable capacitances that can be used to tune the
crystal frequency in order to compensate the PCB parasitic one.
conditions, unless otherwise specified. Typical values are referred to T
= 25 °C and
A
V
= 3.0 V.
DD
(1)
Table 54. HSE crystal requirements
Conditions
Symbol
Parameter
Min
Typ
Max Unit
f
NOM
Oscillator frequency
–
–
32
–
MHz
Includes initial accuracy, stability over
temperature, aging and frequency pulling
due to incorrect load capacitance.
(2)
f
TOL
Frequency tolerance
–
–
ppm
C
L
Load capacitance
–
–
6
–
–
–
8
pF
ESR
Equivalent series resistance
100
ꢀ
1. 32
MHz XTAL is specified for two specific references: NX2016SA and NX1612SA.
2. Refer
to the standard specification: 50 ppm for BLE, 40 ppm for 802.15.4 and when both BLE and 802.15.4 are used.
(1)
Table 55. HSE clock source requirements
Symbol
Parameter
Conditions
Min Typ Max
Unit
f
HSE_ext
User external clock source frequency
–
32
–
–
MHz
Includes initial accuracy, stability
over temperature and aging.
(2)
f
TOL
Frequency tolerance
–
ppm
V
HSE
Clock input voltage limits
Sine wave, AC-coupled
(3)
0.4
–
50
–
1.6
55
V
PP
%
DuCy(HSE) Duty
cycle
–
45
–
Offset = 10 kHz
Offset = 100 kHz
Offset = 1 MHz
-127
φ
n(HSE)
Phase noise for 32 MHz
–
–
-135 dBc/Hz
-138
–
–
1. Guaranteed
by design.
2. Refer
to the standard specification: 50 ppm for BLE, 40 ppm for 802.15.4 and when both BLE and 802.15.4 are used.
3. Only
AC coupled is supported (capacitor 470 pF to 100 nF).
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Table 56. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Startup time
for 80% amplitude stabilization
t
SUA(HSE)
–
1000
–
V
DDRF
stabilized, XOTUNE=000000,
µs
-40 to +125 °C range
Startup time
for XOREADY signal
t
SUR(HSE)
–
250
–
I
DDRF(HSE)
HSE current consumption
XOT
g(HSE)
XOTUNE granularity
HSEGMC=000, XOTUNE=000000
–
50
1
–
5
µA
–
ppm
XOT
fp(HSE)
XOTUNE frequency pulling
XOT
nb(HSE)
XOTUNE number of tuning bits
XOT
st(HSE)
XOTUNE setting time
±20
±40
0
–
Capacitor bank
–
–
–
bit
–
0.1
ms
Note:
For information about oscillator trimming refer to AN5165 “Development of RF hardware
Low-speed external user clock generated from an external source
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. The information provided in this section is based on design simulation results
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 57. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LSEDRV[1:0] = 00
Low drive capability
–
250
–
LSEDRV[1:0] = 01
Medium low drive capability
–
–
–
–
–
–
315
–
I
DD(LSE)
LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
–
LSEDRV[1:0] = 11
High drive capability
630
–
LSEDRV[1:0] = 00
Low drive capability
–
–
–
0.50
0.75
1.70
LSEDRV[1:0] = 01
Medium low drive capability
G
mcritmax
Maximum critical crystal g
m
µA/V
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
–
–
–
2.70
–
(2)
t
SU(LSE)
Startup time
V
DD
stabilized
2
s
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
1. Guaranteed
by design.
2. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) until a stable 32 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal refer to application note AN2867 “Oscillator design
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
C
L1
OSC32_IN
f
LSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
C
L2
MS30253V2
Note:
No external resistors are required between OSC32_IN and OSC32_OU
T
,
a
nd it is forbidden
to add one.
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
Figure 23. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
9
0
%
1
0
%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
(1)
Table 58. Low-speed external user clock characteristics
– Bypass mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock
source frequency
f
LSE_ext
–
21.2
32.768
44.4
kHz
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 58. Low-speed external user clock characteristics
– Bypass mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
OSC32_IN input pin
high level voltage
V
LSEH
–
0.7 V
DDx
–
V
DDx
V
OSC32_IN input pin
low level voltage
V
LSEL
–
–
V
SS
250
–
–
0.3 V
DDx
–
t
w(LSEH)
OSC32_IN high or
t
w(LSEL)
low time
ns
Includes initial
accuracy, stability over
temperature, aging and
frequency pulling
f
tolLSE
Frequency tolerance
-500
–
+500
ppm
1. Guaranteed
by design.
6.3.11
Internal clock source characteristics
conditions
. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 59. HSI16 oscillator characteristics
Symbol
Parameter
HSI16 Frequency
Conditions
Min
Typ
Max
Unit
f
HSI16
V
DD
=3.0
V
,
T
A
=30 °C
15.88
–
16.08
MHz
Trimming code is not a
multiple of 64
0.2
-4
0.3
-6
0.4
-8
TRIM
HSI16 user trimming step
Trimming code is a
multiple of 64
DuCy(HSI16)
(2)
Duty Cycle
–
45
-1
-2
–
–
–
55
1
%
T
A
= 0 to 85 °C
T
A
= -40 to 125 °C
HSI16 oscillator frequency drift over
temperature
ꢁ
T
e
mp
(HSI16)
1.5
HSI16 oscillator frequency drift over
V
DD
ꢁ
VDD
(HSI16)
V
DD
=1.62 V to 3.6 V
-0.1
–
0.05
HSI16 oscillator start-up time
–
–
–
–
–
–
0.8
3
1.2
5
μ
s
155
190
μ
A
1. Guaranteed
by characterization results.
2. Guaranteed
by design.
DS11929 Rev 10
Electrical characteristics
STM32WB55xx STM32WB35xx
Multi-speed internal (MSI) RC oscillator
(1)
Table 60. MSI oscillator characteristics
Parameter Conditions
Symbol
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
T
A
= -0 to 85 °C
98.7
100
200
101.3
197.4
202.6
kHz
405.2
394.8
400
789.6
800
810.4
1.013
2.026
4.052
0.987
1
1.974
2
MSI mode
3.948
4
7.896
8
8.104
MHz
16.21
15.79
16
23.69
24
24.31
32.42
48.62
–
31.58
32
MSI frequency
after factory
calibration, done
at V
DD
=3 V and
T
A
=30 °C
47.38
48
f
MSI
–
98.304
196.608
393.216
786.432
1.016
1.999
3.998
7.995
15.991
23.986
32.014
48.005
–
–
–
kHz
–
–
–
–
–
–
–
–
PLL mode
XTAL=
32.768 kHz
–
–
–
–
MHz
–
–
–
–
–
–
–
–
MSI oscillator
-3.5
3
ꢁ
TEMP
(MSI)
(2)
frequency drift
MSI mode
%
6
T
A
= -40 to 125 °C
-8
–
over temperature
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)
Table 60. MSI oscillator characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
V
DD
=
1.62 to
3.6 V
-1.2
–
Range 0 to 3
0.5
V
DD
=
-0.5
-2.5
-0.8
-5
–
–
–
–
–
2.4 to
3.6 V
V
DD
=
MSI oscillator
frequency drift
over V
DD
1.62 to
3.6 V
ꢁ
VDD
(MSI)
(2)
MSI mode
Range 4 to 7
0.7
V
DD
=
2.4 to
3.6 V
(reference is 3 V)
%
V
DD
=
1.62 to
3.6 V
Range 8 to 11
1
V
DD
=
-1.6
2.4 to
3.6 V
Frequency
T
A
= -40 to 85 °C
T
A
= -40 to 125 °C
–
–
1
2
2
4
variation in
MSI mode
sampling mode
(3)
For next
transition
–
–
–
–
–
–
–
–
–
–
–
–
3.458
P_USB
Period jitter for
USB clock
(4)
PLL mode
Range 11
For paired
transition
3.916
ns
For next
transition
–
2
MT_USB
Medium term jitter
PLL mode
for USB clock
(5)
Range 11
For paired
transition
–
1
RMS cycle-to-
cycle jitter
CC jitter(MSI)
(6)
PLL mode Range 11
60
–
ps
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50
10
5
–
Range 0
Range 1
20
10
Range 2
4
8
MSI oscillator
start-up time
t
μ
s
7
Range 3
3
Range 4 to 7
Range 8 to 11
3
6
6
2.5
10 % of final
frequency
–
–
–
–
–
–
0.25
0.5
–
0.5
MSI oscillator
stabilization time
Range 11
PLL mode
5 % of final
1.25 ms
2.5
frequency
1 % of final
frequency
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 60. MSI oscillator characteristics
(continued)
Symbol
Parameter
Conditions
Range 0
Min
Typ
Max Unit
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
0.8
1.2
1.9
4.7
6.5
11
1
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
1.2
1.7
2.5
6
MSI oscillator
power
consumption
9
MSI and
PLL mode
µA
15
18.5
62
25
80
85
110
130
190
110
155
1. Guaranteed
by characterization results.
2. This
is a deviation for an individual part once the initial frequency has been measured.
3. Sampling
mode means Low-power run/Low-power sleep modes with
T
e
mperature sensor disable.
4. Average
period of MSI at 48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI at 48 MHz clock.
5. Only
accumulated jitter of MSI at 48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI at 48 MHz, for 1000 captures over
28 cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI at 48 MHz, for 1000 captures over
56 cycles.
6. Guaranteed
by design.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 25. Typical current consumption vs. MSI frequency
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 61. HSI48 oscillator characteristics
Symbol
Parameter
HSI48 frequency
Conditions
Min
Typ
Max
Unit
f
HSI48
TRIM
V
DD
= 3.0 V, T
A
= 30 °C
–
–
–
48
–
MHz
HSI48 user trimming step
0.11
(2)
USER TRIM
COVERAGE
HSI48 user trimming coverage
±32 steps
–
±3
(3)
–
±3.5
(3)
–
DuCy(HSI48) Duty
cycle
–
–
±3
(3)
V
DD
= 3.0 V to 3.6
V
,
T
A
= –15 to 85 °C
%
Accuracy of the HSI48 oscillator
ACC
HSI48_REL
over temperature
V
DD
= 1.65 V to 3.6
V
,
T
A
= –40 to 125 °C
–
–
±4.5
(3)
(factory calibrated)
V
DD
= 3 V to 3.6 V
–
–
–
–
0.025
(3)
0.05
(3)
HSI48 oscillator frequency drift
with V
DD
D
VDD
(HSI48)
t
su
(HSI48)
V
DD
= 1.65 V to 3.6 V
0.05
(3)
0.1
(3)
HSI48 oscillator start-up time
–
–
μ
s
I
DD
(HSI48) HSI48
oscillator power consumption
μ
A
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 61. HSI48 oscillator characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Next transition jitter
N
T
jitter
–
–
–
Accumulated jitter on 28 cycles
(4)
ns
Paired transition jitter
P
T
jitter
–
–
–
Accumulated jitter on 56 cycles
(4)
1. V
DD
= 3 V,
T
A
= –40 to 125 °C unless otherwise specified.
2. Guaranteed
by design.
3. Guaranteed
by characterization results.
4. Jitter
measurement are performed without clock source activated in parallel.
Figure 26. HSI48 frequency vs. temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
70
90
110
130
°C
Avg
min
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
(1)
Table 62. LSI1 oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
V
DD
= 3.0
V
, T
A
= 30 °C
31.04
–
–
32.96
34
f
LSI
LSI1 frequency
kHz
V
DD
= 1.62 to 3.6 V, T
A
= -40 to 125 °C
29.5
t
SU
(LSI1)
(2)
LSI1 oscillator start-up time
–
–
–
80
130
μ
s
t
STAB
(LSI1)
(2)
LSI1 oscillator stabilization time
5% of final frequency
125 180
110 180
LSI1 oscillator power
consumption
I
DD
(LSI1)
(2)
–
–
nA
1. Guaranteed
by characterization results.
2. Guaranteed
by design.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Min Typ Max
Unit
(1)
Table 63. LSI2 oscillator characteristics
Symbol
Parameter
Conditions
V
DD
= 3.0
V
, T
A
= 30 °C
21.6
–
–
–
44.2
44.4
3.5
f
LSI2
LSI2 frequency
kHz
ms
V
DD
= 1.62 to 3.6
V
, T
A
= -40 to 125 °C
21.2
t
SU
(LSI2)
(2)
LSI2 oscillator start-up time
–
–
0.7
–
LSI2 oscillator power
I
DD
(LSI2)
(2)
500 1180
nA
consumption
1. Guaranteed
by characterization results.
2. Guaranteed
by design.
6.3.12
PLL characteristics
V
DD
(1)
Table 64. PLL, PLLSAI1 characteristics
Symbol
f
PLL_IN
Parameter
Conditions
Min
Typ Max
Unit
PLL input clock
(2)
–
–
2.66
45
2
–
–
16
55
64
16
64
16
64
16
344
128
40
–
MHz
%
PLL input clock duty cycle
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
–
–
f
PLL_P_OUT
PLL multiplier output clock P
f
PLL_Q_OUT
PLL multiplier output clock Q
f
PLL_R_OUT
PLL multiplier output clock R
f
VCO_OUT
PLL VCO output
2
–
8
–
8
–
MHz
8
–
8
–
96
64
–
–
–
t
LOCK
Jitter
PLL lock time
15
40
30
μ
s
RMS cycle-to-cycle jitter
RMS period jitter
–
System clock 64 MHz
ps
–
–
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
–
200 260
300 380
520 650
PLL power consumption
on V
DD
I
DD
(PLL)
–
μ
A
–
1. Guaranteed
by design.
2.
T
a
ke
care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.13
Flash memory characteristics
(1)
Table 65. Flash memory characteristics
Symbol
Parameter
Conditions
Typ
Max Unit
t
prog
64-bit programming time
–
81.7
5.2
90.8
5.5
4.0
43.0
31.0
24.5
25.0
–
µs
Normal programming
Fast programming
Normal programming
Fast programming
–
One row (64 double word)
programming time
t
prog_row
3.8
41.8
30.4
22.0
22.1
3.4
One page (4 Kbytes)
programming time
t
prog_page
ms
t
ERASE
t
ME
Page (4 Kbytes) erase time
Mass erase time
–
Write mode
I
DD
Average consumption from V
DD
mA
Erase mode
3.4
–
1. Guaranteed
by design.
Table 66. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min
(1)
Unit
N
END
T
A
= –40 to +105 °C
10
30
15
7
kcycles
1 kcycle
(2)
at T
A
= 85 °C
1 kcycle
(2)
at T
A
= 105 °C
1 kcycle
(2)
at T
A
= 125 °C
10 kcycles
(2)
at T
A
= 55 °C
10 kcycles
(2)
at T
A
= 85 °C
10 kcycles
(2)
at T
A
= 105 °C
t
RET
Data retention
Years
30
15
10
1. Guaranteed
by characterization results.
2. Cycling
performed over the whole temperature range.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3.14
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD)
(positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB
: A Burst of Fast Transient voltage (positive and negative) is applied to V
and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
Table 67. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
V
DD
= 3.3
V
,
T
A
= +25 °C,
f
HCLK
= 64 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
FESD
2B
Fast transient voltage burst limits to be
V
DD
= 3.3
V
,
T
A
= +25 °C,
V
EFTB
applied through 100 pF on V
DD
and V
SS
f
HCLK
= 64 MHz,
5A
pins to induce a functional disturbance
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flow must include the management of runaway conditions such as:
corrupted program counter
unexpected reset
critical data corruption (e.g. control registers)
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for
1 second.
To
c
omplete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, which specifies the test board and the pin loading.
Table 68. EMI characteristics
Peripheral ON
SMPS OFF or ON
[f
HSE
/ f
CPUM4,
f
CPUM0
Monitored
frequency band
]
Symbol Parameter
Conditions
Unit
32 MHz
/ 64 MHz, 32 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI level
1
4
V
DD
= 3.6
V
, T
A
= 25 °C,
Peak level
WLCSP100 package
dBµV
–
S
EMI
-1
7
compliant with IEC 61967-2
1.5
6.3.15
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 69. ESD absolute maximum ratings
Symbol
V
ESD(HBM)
Ratings
Conditions
Class Maximum
value
(1)
Unit
Electrostatic discharge voltage
T
A
= +25 °C, conforming to
(human body model)
2
2000
ANSI/ESDA/JEDEC JS-001
V
C2a
(2)
C1
(3)
Electrostatic discharge voltage
T
A
= +25 °C, conforming to
V
ESD(CDM)
(charge device model)
ANSI/ESD STM5.3.1 JS-002
1. Guaranteed
by characterization results.
2. UFQFPN48,
VFQPN68 and WLCSP100 packages.
3. UFBGA129
package.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Static latch-up
Electrical characteristics
Two complementary static tests are required on six parts to assess the latch-up
performance:
a supply overvoltage is applied to each power supply pin
a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 70. Electrical sensitivity
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
T
A
= +105 °C conforming to JESD78A
II
6.3.16
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V
or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA / 0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
(1)
Table 71. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on all pins except PB0, PB1
Injected current on PB0, PB1 pins
-5
-5
N/A
(2)
0
I
INJ
mA
1. Guaranteed
by characterization results.
2. Injection
not possible.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.17
I/O port characteristics
General input/output characteristics
I/Os are designed as CMOS- and TTL-compliant.
Table 72. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I/O input
–
–
0.3 x V
DD
low level voltage
(1)
V
IL
I/O input
0.39 x V
DD
– 0.06
low level voltage
(2)
V
I/O input
0.7 x V
DD
–
–
–
–
V
IH
I/O input
0.49 x V
DD
+ 0.26
TT_xx, FT_xxx
and NRST I/O
input hysteresis
V
hys
–
200
–
mV
(3)
0
≤
V
IN
≤
Max(V
DDXXX
)
–
–
–
–
±100
650
≤
FT_xx
input leakage current
≤
–
–
–
–
–
–
200
(7)
±150
2500
0
≤
V
IN
≤
Max(V
DDXXX
)
I
lkg
nA
FT_lu, FT_u and
PC3 IO
input leakage current
≤
–
–
–
–
–
–
250
±150
2000
V
IN
≤
Max(V
DDXXX
)
TT_xx
input leakage current
<
Weak pull-up
R
PU
V
IN
= V
SS
25
40
55
k
ꢀ
Weak pull-down
R
PD
C
IO
V
IN
= V
DD
25
–
40
5
55
–
I/O pin capacitance
–
pF
1.
T
e
sted
in production.
2. Guaranteed
by design, not tested in production.
3. Represents
the pad leakage of the I/O itself. The total product pad leakage is given by
I
T
o
tal_Ileak_max
= 10
μ
A + number of I/Os where V
IN
is applied on the pad x I
lkg(Max)
4. Max(V
DDXXX
) is the maximum value among all the I/O supplies.
5. V
IN
must be lower than [Max(V
DDXXX
) + 3.6 V].
.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
7.
T
o
s
ustain a voltage higher than Min(V
DD
, V
DDA
, V
DDUSB
, V
LCD
) + 0.3 V, the internal pull-up and pull-down resistors must
be disabled. All FT_xx IO except FT_lu, FT_u and PC3.
8. Pull-up
and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS, whose
contribution to the series resistance is minimal (~10%).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
Figure 27. I/O input characteristics
Vil-Vih (all IO except BOOT0)
3
2.5
TTL requirement Vih min = 2V
2
cmos vil spec 30%
cmos vih spec 70%
ttl vil spec ttl
1.5
1
ttl vih spec ttl
datasheet Vil_rule
datasheet Vih_rule
TTL requirement Vil min = 0.8V
0.5
0
1.5
2
2.5
3
3.5
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed V
/ V
).
OL
OH
In the user application, the number of I/O pins that can drive current must be limited to
The sum of the currents sourced by all the I/Os on V
, plus the maximum
DD
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
Σ
I
VDD
The sum of the currents sunk by all the I/Os on V
, plus the maximum consumption of
SS
the MCU sunk on V
, cannot exceed the absolute maximum rating
Σ
I
(see
VSS
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
unless otherwise specified).
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 73. Output voltage characteristics
Parameter Conditions
Symbol
Min
Max Unit
(2)
V
OL
V
OH
Output low level voltage for an I/O pin
CMOS port
(3)
|I
IO
| = 8 mA
–
0.4
–
Output high level voltage for an I/O pin
V
DD
– 0.4
V
DD
≥
2.7 V
V
OL
Output low level voltage for an I/O pin
TTL port
(3)
|I
IO
| = 8 mA
–
0.4
–
V
OH
Output high level voltage for an I/O pin
2.4
V
DD
≥
2.7 V
V
OL
V
OH
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
–
1.3
–
|I
IO
| = 20 mA
V
DD
≥
2.7 V
V
DD
– 1.3
–
V
V
OL
0.4
|I
IO
| = 4 mA
V
DD
≥
1.62 V
V
OH
V
DD
– 0.45
–
|I
IO
| = 20 mA
V
DD
≥
2.7 V
–
–
–
0.4
Output low level voltage for an FT I/O
|I
IO
| = 10 mA
V
OLFM+
0.4
0.4
pin in FM+ mode (FT I/O with “f” option)
V
DD
≥
1.62 V
|I
IO
| = 2 mA
1.62 V
≥
V
DD
≥
1.08 V
1. The
I
IO
current sourced or sunk by the device must always respect the absolute maximum rating specified
in
T
a
ble 20: Voltage characteristics
, and the sum of the currents sourced or sunk by all the I/Os (I/O ports
.
2. Guaranteed
by design.
3. TTL
and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
Unless otherwise specified, the parameters given are derived from tests performed under
(1)(2)
Table 74. I/O AC characteristics
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=50 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=50 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=50 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤ ≤
2.7 V
–
–
–
–
–
–
–
–
5
1
Fmax Maximum
frequency
MHz
10
1.5
25
52
17
37
00
Tr/Tf Output
rise and fall time
ns
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Speed Symbol
Electrical characteristics
(1)(2)
Table 74. I/O AC characteristics
(continued)
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=50 pF, 1.62 V
≤
V
DD
≤ ≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=50 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=50 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=50 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=50 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=50 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=50 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=30 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=30 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=30 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=30 pF, 1.62 V
≤
V
DD
≤
2.7 V
C=10 pF, 2.7 V
≤
V
DD
≤
3.6 V
C=10 pF, 1.62 V
≤
V
DD
≤
2.7 V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
25
10
Fmax Maximum
frequency
Tr/Tf Output
rise and fall time
Fmax Maximum
frequency
Tr/Tf Output
rise and fall time
Fmax Maximum
frequency
Tr/Tf Output
rise and fall time
MHz
50
15
01
10
11
9
16
ns
MHz
ns
4.5
9
50
25
100
(3)
37.5
5.8
11
2.5
5
50
MHz
3.3
6
ns
1.7
3.3
1. The
maximum frequency is defined with (T
r
+ T
f
)
≤
2/3
T
,
a
nd Duty cycle comprised between 45 and 55%.
2. The
fall and rise time are defined, respectively, between 90 and 10%, and between 10 and 90% of the
output waveform.
3. This
value represents the I/O capability but the maximum system frequency is limited to 64 MHz.
6.3.18
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
DS11929 Rev 10
169
Electrical characteristics
Symbol
STM32WB55xx STM32WB35xx
(1)
Table 75. NRST pin characteristics
Parameter
Conditions
Min
Typ
Max
Unit
NRST input
low level voltage
V
IL(NRST)
V
IH(NRST)
V
hys(NRST)
R
PU
–
–
–
0.3 x V
DD
V
NRST input
high level voltage
–
0.7 x V
DD
–
200
40
–
–
–
NRST Schmitt trigger
voltage hysteresis
–
–
25
–
mV
Weak pull-up
V
IN
= V
SS
55
70
–
k
ꢀ
equivalent resistor
(2)
NRST input
filtered pulse
V
F(NRST)
V
NF(NRST)
–
ns
NRST input
not filtered pulse
1.71 V
≤
V
DD
≤
3.6 V
350
–
1. Guaranteed
by design.
2. The
pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10%)
.
Figure 28. Recommended NRST pin protection
External
reset circuit
(1)
V
DD
R
PU
NRST
(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The
reset network protects the device against parasitic resets.
2. The
user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 75
, otherwise the reset will not be taken into account by the device.
3. The
external capacitor on NRST must be placed as close as possible to the device.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3.19
Analog switches booster
(1)
Table 76. Analog switches booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
V
DD
1.62
–
–
–
3.6
V
t
SU(BOOST)
Booster startup time
240
µs
Booster consumption for
1.62 V
≤
V
DD
≤
2.0 V
–
–
–
–
–
–
250
500
900
Booster consumption for
2.0 V
≤
V
DD
≤
2.7 V
I
DD(BOOST)
µA
Booster consumption for
2.7 V
≤
V
DD
≤
3.6 V
1. Guaranteed
by design.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.20
Analog-to-Digital converter characteristics
from tests performed under ambient temperature, f
frequency and V
supply voltage
DDA
Note:
It is recommended to perform a calibration after each power-up.
(1) (2) (3)
Table 77. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DDA
Analog supply voltage
–
1.62
2
–
–
3.6
V
V
V
V
DDA
≥
2 V
V
DDA
< 2 V
V
DDA
Positive reference
voltage
V
REF+
V
DDA
Negative reference
voltage
V
REF-
–
V
SSA
V
Range 1
0.14
–
–
–
–
–
–
–
–
–
–
64
f
ADC
ADC clock frequency
MHz
Range 2
0.14
16
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
–
–
–
–
–
–
–
–
4.26
4.92
5.81
7.11
3.36
4.00
4.57
7.11
Sampling rate
for FAST channels
f
s
Msps
Sampling rate
for SLOW channels
f
ADC
= 64 MHz
Resolution = 12 bits
–
–
–
4.26
MHz
External trigger
frequency
f
TRIG
Resolution = 12 bits
Differential mode
–
15
1/f
ADC
(V
REF+
REF-
) / 2
– 0.18
+
(V
REF+
+
REF-
) / 2
+ 0.18
(V
REF+
V
REF-
) / 2
+
V
V
V
V
Input common mode
CMIN
Conversion voltage
range(2)
(4)
V
AIN
–
–
–
–
0
–
–
–
V
REF+
V
External input
impedance
R
AIN
C
ADC
t
STAB
50
–
k
ꢀ
pF
Internal sample and hold
capacitor
–
5
1
Conversion
cycle
Power-up time
Calibration time
f
ADC
= 64 MHz
–
1.8125
116
µs
t
CAL
1 / f
ADC
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1) (2) (3)
Table 77. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
1.5
2
–
2.5
2.0
Trigger conversion
latency Regular and
injected channels
–
t
LATR
1/f
ADC
–
–
2.25
2.125
3.5
without conversion abort
–
–
2.5
3
–
Trigger conversion
latency Injected
channels aborting a
regular conversion
–
3.0
t
LATRINJ
1/f
ADC
–
–
–
3.25
3.125
10.0
640.5
–
f
ADC
= 64 MHz
–
0.039
2.5
–
µs
t
s
Sampling time
–
1/f
ADC
ADC voltage regulator
start-up time
–
–
–
–
20
t
ADCVREG_STUP
µs
µs
f
ADC
= 64 MHz
Resolution = 12 bits
0.234
1.019
T
o
tal conversion time
(including sampling time)
t
CONV
t
s
+ 12.5 cycles for successive
approximations = 15 to 653
Resolution = 12 bits
1/f
ADC
fs = 4.26 Msps
fs = 1 Msps
–
–
–
–
–
–
–
–
–
730
160
16
830
220
50
ADC consumption from
the V
DDA
supply
I
DDA
(ADC)
µA
fs = 10 ksps
fs = 4.26 Msps
130
30
160
40
ADC consumption from
I
DDV_S
(ADC) the
V
REF+
single ended
fs = 1 Msps
µA
µA
mode
fs = 10 ksps
fs = 4.26 Msps
fs = 1 Msps
fs = 10 ksps
0.6
250
60
2
310
70
ADC consumption from
I
DDV_D
(ADC) the
V
REF+
differential
mode
1.3
3
1. Guaranteed
by design
2. The
I/O analog switch voltage booster is enabled when V
DDA
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
< 2.4V). It is disable when V
DDA
≥
2.4 V.
V
3. SMPS
in bypass mode.
4.
V
REF+
can be internally connected to V
DDA
and V
REF-
can be internally connected to V
SSA
, depending on the package.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)(2)
Table 78. ADC sampling time
Fast channel
Slow channel
Resolution
(bits)
RAIN
(k
Ω
)
Minimum sampling
Sampling Minimum
sampling Sampling
time (ns)
cycles
time (ns)
cycles
0
0.05
0.1
0.2
0.5
1
33
37
6.5
6.5
57
62
6.5
6.5
42
6.5
67
6.5
51
6.5
76
6.5
78
6.5
104
151
526
994
1932
4744
9430
47
12.5
12.5
47.5
92.5
247.5
640.5
640.5
6.5
12
123
482
931
1830
4527
9021
27
12.5
47.5
92.5
247.5
640.5
640.5
2.5
5
10
20
50
100
0
0.05
0.1
0.2
0.5
1
30
2.5
51
6.5
34
6.5
55
6.5
41
6.5
62
6.5
64
6.5
85
6.5
10
100
395
763
1500
3709
7391
21
12.5
47.5
92.5
247.5
640.5
640.5
2.5
124
431
816
1584
3891
7734
37
12.5
47.5
92.5
247.5
640.5
640.5
2.5
5
10
20
50
100
0
0.05
0.1
0.2
0.5
1
24
2.5
40
6.5
27
2.5
43
6.5
32
6.5
49
6.5
50
6.5
67
6.5
8
78
6.5
97
6.5
5
308
595
1169
2891
5762
47.5
92.5
247.5
247.5
640.5
337
637
1237
3037
6038
24.5
47.5
92.5
247.5
640.5
10
20
50
100
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)(2)
Table 78. ADC sampling time
Fast channel
(continued)
Slow channel
Resolution
(bits)
RAIN
(k
Ω
)
Minimum sampling
Sampling Minimum
sampling Sampling
time (ns)
cycles
time (ns)
cycles
0
0.05
0.1
0.2
0.5
1
15
17
2.5
2.5
26
28
2.5
2.5
19
2.5
31
2.5
23
2.5
35
2.5
36
6.5
48
6.5
6
56
6.5
69
6.5
5
221
427
839
2074
4133
24.5
47.5
92.5
247.5
640.5
242
458
890
2184
4342
24.5
47.5
92.5
247.5
640.5
10
20
50
100
1. Guaranteed
by design.
2. V
DD
= 1.62 V, C
pcb
= 4.7 p
F
,
1
25 °C, booster enabled.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)(2)(3)
Table 79. ADC accuracy – Limited test conditions 1
Symbol
Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
4
5
5
Single
ended
T
o
tal
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
ET
unadjusted
error
3.5
3.5
1
4.5
4.5
2.5
2.5
2.5
2.5
4.5
4.5
3.5
3.5
1.5
1.5
1.2
1.2
2.5
2.5
2
Differential
Single
ended
1
EO
EG
Offset error
Gain error
1.5
1.5
2.5
2.5
2.5
2.5
1
Differential
Single
ended
LSB
Differential
Single
ended
Differential
linearity
error
1
ED
1
Differential
1
1.5
1.5
1
Single
ended
Integral
linearity
error
EL
Differential
1
2
10.4 10.5
10.4 10.5
10.8 10.9
10.8 10.9
64.4 65
64.4 65
66.8 67.4
66.8 67.4
–
Single
ended
Effective
number of
bits
–
ENOB
SINAD
SNR
bits
–
Differential
–
–
Single
ended
Signal-to-
noise and
distortion
ratio
–
–
Differential
–
dB
65
65
67
67
66
66
68
68
–
Single
ended
–
Signal-to-
noise ratio
–
Differential
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)(2)(3)
Table 79. ADC accuracy – Limited test conditions 1
(continued)
Symbol
Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
–
–
–
-74
-74
-79
-73
-73
-76
Single
ended
T
o
tal
harmonic
distortion
THD
dB
Differential
Slow channel (max speed)
–
-79
-76
1. Guaranteed
by design.
2. ADC
DC accuracy values are measured after internal calibration.
3. ADC
accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The
I/O analog switch voltage booster is enable when V
DDA
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA
< 2.4 V). It is disable when V
DDA
≥
2.4 V. No oversampling.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)(2)(3)
Table 80. ADC accuracy – Limited test conditions 2
Conditions
(4)
Fast channel (max speed)
Symbol Parameter
Min Typ Max Unit
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
4
6.5
6.5
5.5
5.5
4.5
5
Single
ended
T
o
tal
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
ET
EO
EG
ED
EL
unadjusted
error
3.5
3.5
1
Differential
Single
ended
1
Offset error
Gain error
1.5
1.5
2.5
2.5
2.5
2.5
1
3
Differential
3
6
Single
ended
6
LSB
3.5
3.5
1.5
1.5
1.2
1.2
3.5
3.5
3
Differential
Single
ended
Differential
linearity
error
1
1
Differential
1
1.5
1.5
1
Single
ended
Integral
linearity
error
Differential
1
2.5
–
10 10.5
10 10.5
10.7 10.9
10.7 10.9
Single
ended
Effective
ENOB number
of
bits
–
bits
–
Differential
–
62
62
65
65
–
Single
ended
Signal-to-
–
noise and
distortion
SINAD
66 67.4
66 67.4
–
ratio
Differential
–
dB
64
64
66
66
–
Single
ended
–
Signal-to-
SNR
noise ratio
66.5 68
66.5 68
–
Differential
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)(2)(3)
Table 80. ADC accuracy – Limited test conditions 2
(continued)
Symbol Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
–
–
–
-74
-74
-79
-65
-67
-70
Single
ended
T
o
tal
harmonic
distortion
THD
dB
Differential
Slow channel (max speed)
–
-79
-71
1. Guaranteed
by design.
2. ADC
DC accuracy values are measured after internal calibration.
3. ADC
accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The
I/O analog switch voltage booster is enable when V
DDA
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA
< 2.4 V). It is disable when V
DDA
≥
2.4 V. No oversampling.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)(2)(3)
Table 81. ADC accuracy – Limited test conditions 3
Symbol
Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5.5
4.5
4.5
4.5
2
7.5
6.5
7.5
5.5
5
Single
ended
T
o
tal
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
ET
unadjusted
error
Differential
Single
ended
2.5
2
5
EO
EG
Offset error
Gain error
3.5
3
Differential
2.5
4.5
3.5
3.5
3.5
1.2
1.2
1
7
Single
ended
6
LSB
4
Differential
5
1.5
1.5
1.2
1.2
3.5
3.5
2.5
2.5
–
Single
ended
Differential
linearity
error
ED
Differential
1
3
Single
ended
Integral
linearity
error
2.5
2
EL
Differential
2
10 10.4
10 10.4
10.6 10.7
10.6 10.7
Single
ended
Effective
number of
bits
–
ENOB
SINAD
SNR
bits
–
Differential
–
62
62
65
65
63
63
66
66
64
64
66
66
65
65
67
67
–
Single
ended
Signal-to-
noise and
distortion
ratio
–
–
Differential
–
dB
–
Single
ended
–
Signal-to-
noise ratio
–
Differential
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)(2)(3)
Table 81. ADC accuracy – Limited test conditions 3
(continued)
Symbol
Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
–
–
–
-69
-71
-72
-67
-67
-71
Single
ended
T
o
tal
harmonic
distortion
THD
dB
Differential
Slow channel (max speed)
–
-72
-71
1. Guaranteed
by design.
2. ADC
DC accuracy values are measured after internal calibration.
3. ADC
accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The
I/O analog switch voltage booster is enable when V
DDA
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA
< 2.4 V). It is disable when V
DDA
≥
2.4 V. No oversampling.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)(2)(3)
Table 82. ADC accuracy – Limited test conditions 4
Symbol
Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
4
5.4
5
Single
ended
T
o
tal
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
ET
unadjusted
error
4
5
Differential
3.5
2
4.5
4
Single
ended
2
4
EO
EG
Offset error
Gain error
2
3.5
3.5
4.5
4.5
4
Differential
2
4
Single
ended
4
LSB
3
Differential
3
4
1
1.5
1.5
1.2
1.2
3
Single
ended
Differential
linearity
error
1
ED
1
Differential
1
2.5
2.5
2
Single
ended
Integral
linearity
error
3
EL
2.5
2.5
–
Differential
2
10.2 10.5
10.2 10.5
10.6 10.7
10.6 10.7
Single
ended
Effective
number of
bits
–
ENOB
SINAD
SNR
bits
–
Differential
–
63
63
65
65
64
64
66
66
65
65
66
66
65
65
67
67
–
Single
ended
Signal-to-
noise and
distortion
ratio
–
–
Differential
–
dB
–
Single
ended
–
Signal-to-
noise ratio
–
Differential
–
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)(2)(3)
Table 82. ADC accuracy – Limited test conditions 4
(continued)
Symbol
Parameter
Conditions
(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
–
–
–
-71
-71
-73
-69
-69
-72
Single
ended
T
o
tal
harmonic
distortion
THD
dB
Differential
Slow channel (max speed)
–
-73
-72
1. Guaranteed
by design.
2. ADC
DC accuracy values are measured after internal calibration.
3. ADC
accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins that may potentially inject negative current.
4. The
I/O analog switch voltage booster is enabled when V
DDA
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA
< 2.4 V). It is disabled when V
DDA
≥
2.4 V. No oversampling.
Figure 29. ADC accuracy characteristics
E
G
(1) Example of an actual transfer curve
(2) Ideal transfer curve
(3) End point correlation line
4095
4094
4093
E
T
=
Total unadjusted error
: maximum deviation
between actual and ideal transfer curves
(2)
E
O
=
Offset error
: maximum deviation between the
first actual transition and the first ideal one
E
T
(3)
7
(1)
E
G
=
Gain error
: deviation between the last ideal
6
5
4
3
2
1
transition and the last actual one
E
L
E
D
E
D
=
Differential linearity error
: maximum
deviation between actual steps and the ideal ones
E
O
E
L
=
Integral linearity error
: maximum deviation
between any actual transition and the end point
correlation line
1 LSB ideal
6
V
REF+
/4096
1
2
3
4
5
4093 4094
4095 4096
7
MS54001V1
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Figure 30. Typical connection diagram using the ADC
V
DDA
V
T
Sample and hold ADC converter
(1)
R
AIN
R
ADC
AINx
12-bit
converter
(2)
(3)
C
parasitic
C
ADC
V
T
I
lkg
V
AIN
MS33900V5
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to
Table 72: I/O static characteristics
for the value of the pad capacitance). A high
C
General PCB design guidelines
(all packages except UFBGA129 and WLCSP100)
. The 10 nF capacitor needs to be
ceramic (good quality), placed as close as possible to the chip.
6.3.21
Voltage reference buffer characteristics
(1)
Table 83. VREFBUF characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
RS
= 0
2.4
2.8
–
–
–
–
3.6
3.6
2.4
2.8
Normal mode
V
RS
= 1
Analog supply
voltage
V
DDA
V
RS
= 0
V
RS
= 1
V
RS
= 0
V
RS
= 1
V
RS
= 0
V
RS
= 1
1.65
Degraded mode
(2)
Normal mode
1.65
V
2.046
(3)
2.498
(3)
V
DDA
-150 mV
V
DDA
-150 mV
2.048 2.049
(3)
2.5
2.502
(3)
V
REFBUF_
Voltage
reference output
OUT
–
–
V
DDA
Degraded mode
(2)
V
DDA
Trim step
resolution
TRIM
CL
–
–
–
–
–
±0.05
1
±0.1
1.5
%
Load capacitor
0.5
µF
Equivalent
series resistor
of C
load
esr
–
–
–
–
–
–
–
–
2
4
ꢀ
Static load
current
I
load
mA
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)
Table 83. VREFBUF characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I
load
= 500 µA
–
–
–
200
100
50
1000
500
I
line_reg
I
load_reg
Line regulation
2.8 V
≤
V
DDA
≤
3.6 V
ppm/V
I
load
= 4 mA
Load regulation
500
μ
A
≤
I
load
≤
4 mA
Normal mode
500
ppm/mA
T
coeff_
-40 °C < T
J
< +125 °C
–
–
–
–
+
vrefint
50
T
e
mperature
coefficient
T
Coeff
ppm/ °C
T
coeff_
0 °C < T
J
< +50 °C
+
vrefint
50
DC
40
25
–
60
40
–
Power supply
rejection
PSRR
t
START
dB
µs
100 kHz
–
CL = 0.5 µF
(4)
300
500
650
350
650
800
Start-up time
CL = 1.1 µF
(4)
CL = 1.5 µF
(4)
–
–
Control of
maximum DC
current drive on
VREFBUF_OUT
during start-up
phase
(5)
I
INRUSH
–
–
–
8
–
mA
µA
I
load
= 0 µA
–
–
–
16
18
35
25
30
50
VREFBUF
consumption
from V
DDA
I
DDA
(VREFBUF)
I
load
= 500 µA
I
load
= 4 mA
1. Guaranteed
by design, unless otherwise specified.
2. In
degraded mode, the voltage reference buffer cannot maintain accurately the output voltage that will follow (V
DDA
– drop
voltage).
3. Guaranteed
by test in production.
4. The
capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
5.
T
o
c
orrectly control the VREFBUF in-rush current during start-up phase and scaling change, the V
DDA
voltage must be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V
RS
= 0 and V
RS
= 1.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.22
Comparator characteristics
(1)
Table 84. COMP characteristics
Conditions
Symbol
V
DDA
Parameter
Min
Typ
Max Unit
Analog supply voltage
–
–
1.62
–
3.6
Comparator
input voltage range
V
IN
0
–
V
DDA
V
(2)
V
BG
Scaler input voltage
Scaler offset voltage
–
V
REFINT
V
SC
–
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
±5
200
0.8
100
–
±10
300
1
mV
nA
µA
µs
Scaler static consumption
from V
DDA
I
DDA
(SCALER)
t
START_SCALER
Scaler startup time
200
5
V
DDA
≥
2.7 V
High-speed
mode
V
V
V
DDA
< 2.7 V
DDA
≥
2.7 V
DDA
< 2.7 V
–
7
Comparator startup time
to reach propagation
delay specification
t
START
–
15
25
40
80
100
0.9
7
µs
ns
Medium mode
–
Ultra-low-power mode
–
V
DDA
≥
2.7 V
V
DDA
< 2.7 V
55
55
0.55
4
High-speed
mode
Propagation delay with
100 mV overdrive
(3)
t
D
Medium mode
µs
Ultra-low-power mode
Full common mode range
No hysteresis
V
offset
Comparator offset error
Comparator hysteresis
±5
0
±20
–
mV
Low hysteresis
8
–
V
hys
mV
nA
Medium hysteresis
High hysteresis
15
27
400
–
–
Static
600
Ultra-low-
power mode
With 50 kHz ±100 mV
overdrive square signal
–
–
–
–
–
1200
5
–
Static
7
Comparator consumption
Medium
from V
DDA
I
DDA
(COMP)
With 50 kHz ±100 mV
overdrive square signal
mode
6
–
100
–
µA
Static
70
75
High-speed
mode
With 50 kHz ±100 mV
overdrive square signal
1. Guaranteed
by design, unless otherwise specified.
3. Guaranteed
by characterization results.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
6.3.23
Temperature sensor characteristics
Table 85. TS characteristics
Parameter
Symbol
Min
Typ
Max
Unit
(1)
T
L
V
TS
linearity with temperature
–
±1
2.5
±2
2.7
°C
mV / °C
V
Avg_Slope
(2)
Average slope
2.3
V
30
Voltage at 30 °C (±5 °C)
(3)
0.742
–
0.76
0.785
t
START
Sensor buffer start-up time in continuous mode
(4)
8
15
µs
ADC sampling time when reading the temperature
–
70
–
120
–
µs
µs
t
START
t
S_temp
5
T
e
mperature sensor consumption from V
DD
, when
selected by ADC
I
–
4.7
7
µA
1. Guaranteed
by design.
2. Guaranteed
by characterization results.
3. Measured
at V
DDA
= 3.0 V ±10 m
V
.
T
he V
30
ADC conversion result is stored in the TS_CAL1 byte. Refer to
T
able 11:
4. Continuous
mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
6.3.24
V
monitoring characteristics
BAT
(1)
Table 86. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for V
BAT
Min
Typ
Max
Unit
R
Q
–
–
3 x 39
–
–
k
ꢀ
–
Ratio on V
BAT
measurement
Error on Q
3
–
Er
(2)
-10
12
10
–
%
µs
(2)
t
S_vbat
ADC sampling time when reading V
BAT
–
1. 1.55
< V
BAT
< 3.6
V
.
2. Guaranteed
by design.
Table 87. V
charging characteristics
BAT
Symbol
Parameter Conditions
Min
Typ
5
Max
Unit
Battery
charging
resistor
VBRS = 0
VBRS = 1
–
–
–
–
R
BC
k
ꢀ
1.5
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
6.3.25
6.3.26
SMPS step-down converter characteristics
The SMPS step-down converter characteristic are given at 4 MHz clock, with a 20 mA load
(unless otherwise specified), using a 10 µH inductor and a 4.7 µF capacitor.
LCD controller characteristics
The STM32WB55xx devices embed a built-in step-up converter to provide a constant LCD
reference voltage independently from the V
voltage. An external capacitor C
must be
DD
ext
connected to the VLCD pin to decouple this converter.
(1)
Table 88. LCD controller characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
LCD
V
LCD0
V
LCD1
V
LCD2
V
LCD3
V
LCD4
V
LCD5
V
LCD6
V
LCD7
LCD external voltage
–
–
–
–
–
–
–
–
–
–
3.6
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
2.62
2.76
2.89
3.04
3.19
3.32
3.46
3.62
–
–
–
–
–
–
–
–
V
Buffer OFF
(BUFEN=0 is LCD_CR register)
0.2
–
2
2
–
C
ext
V
LCD
external capacitance
μ
F
μ
A
Buffer ON
(BUFEN=1 is LCD_CR register)
1
–
–
–
–
–
–
–
Supply current from V
DD
at Buffer
OFF
3
V
DD
= 2.2 V
(BUFEN=0 is LCD_CR register)
(2)
I
LCD
Supply current from V
DD
at Buffer
OFF
1.5
0.5
0.6
0.8
1
–
V
DD
= 3.0 V
(BUFEN=0 is LCD_CR register)
Buffer OFF
(BUFFEN = 0, PON = 0)
–
Buffer ON
(BUFFEN = 1, 1/2 Bias)
–
Supply current
from V
LCD
(V
LCD
= 3 V)
I
VLCD
μ
A
Buffer ON
(BUFFEN = 1, 1/3 Bias)
–
Buffer ON
(BUFFEN = 1, 1/4 Bias)
–
R
HN
R
LN
T
o
tal High resistor value for Low drive resistive network
T
o
tal Low resistor value for High drive resistive network
–
–
5.5
–
–
M
ꢀ
k
ꢀ
240
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
(1)
Table 88. LCD controller characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
44
V
34
V
23
V
12
V
13
V
14
V
0
Segment/Common highest level voltage
Segment/Common 3/4 level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common 1/4 level voltage
Segment/Common lowest level voltage
–
–
–
–
–
–
–
V
LCD
3/4 V
LCD
2/3 V
LCD
1/2 V
LCD
1/3 V
LCD
1/4 V
LCD
0
–
–
–
–
–
–
–
V
1. Guaranteed
by design.
2. LCD
enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio = 64, all pixels active, no LCD connected.
6.3.27
Timer characteristics
The parameters given in the following tables are guaranteed by design. Refer to
Section 6.3.17
for details on the input/output alternate function characteristics (output
compare, input capture, external clock, PWM output).
(1)
Table 89. TIMx
characteristics
Symbol
t
res(TIM)
Parameter
Conditions
Min
Max
Unit
t
TIMxCLK
ns
–
1
–
Timer resolution time
f
TIMxCLK
= 64 MHz
15.625
–
f
TIMxCLK
/2
40
–
0
Timer external clock frequency
on CH1 to CH4
f
EXT
MHz
bit
f
TIMxCLK
= 64 MHz
0
TIM1, TIM16, TIM17
–
16
Res
TIM
Timer resolution
TIM2
–
32
–
f
TIMxCLK
= 64 MHz
–
1
65536
1024
t
TIMxCLK
µs
t
TIMxCLK
s
t
COUNTER
16-bit counter clock period
0.015625
–
–
65536 × 65536
67.10
Maximum possible count with
32-bit counter
t
MAX_COUNT
f
TIMxCLK
= 64 MHz
1. TIMx
,
is used as a general term where x stands for 1, 2, 16 or 17.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 90. IWDG min/max timeout period at 32 kHz (LSI1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0] = 0x000
Max timeout RL[11:0] = 0xFFF
Unit
/4
/8
0
0.125
0.250
0.500
1.0
512
1024
2048
1
/16
/32
/64
/128
/256
2
3
4
4096
8192
ms
2.0
5
4.0
16384
32768
6 or 7
8.0
1. The
exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC
period of uncertainty.
6.3.28
Clock recovery system (CRS)
The devices embed a special block for the automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range.
This automatic trimming is based on the external synchronization signal, which can be
derived from USB Sart Of Frame (SOF) signalization, from LSE oscillator, from an external
signal on CRS_SYNC pin or generated by user software.
For faster lock-in during startup it is also possible to combine automatic trimming with
manual trimming action.
6.3.29
Communication interfaces characteristics
I
2
C interface characteristics
2
The I2C interface meets the timings requirements of the I
C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): bit rate up to 100 kbit/s
Fast-mode (Fm): bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.
2
Table 91. Minimum I2CCLK frequency in all I
C modes
Symbol
Parameter
Condition
Min
Unit
Standard-mode
Fast-mode
–
2
9
Analog filter ON, DNF = 0
Analog filter OF
F
,
D
NF = 1
Analog filter ON, DNF = 0
Analog filter OF
F
,
D
NF = 1
I2CCLK
frequency
f
(I2CCLK)
9
MHz
19
16
Fast-mode Plus
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (see the reference manual).
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL
I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
is disabled, but is still present. The 20 mA output drive
DD
requirement in Fast-mode Plus is supported partially.
This limits the maximum load C
supported in Fast-mode Plus, given by these formulas:
load
t (SDA/SCL) = 0.8473 x R
x C
r p
load
R (min) = [V
– V
(max)] / I
(max)
p
DD
OL
OL
p
(1)
Table 92. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
t
AF
50
(2)
110
(3)
ns
1. Guaranteed
by design.
2. Spikes
with widths below t
AF(min)
are filtered.
3. Spikes
with widths above t
AF(max)
are not filtered
SPI characteristics
performed under the ambient temperature, f
frequency and supply voltage conditions
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5
ₓ
V
DD
(NSS, SCK, MOSI, MISO for SPI).
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 93. SPI characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Master mode
1.65 < V
DD
< 3.6 V
Voltage Range 1
32
Master transmitter mode
1.65 < V
DD
< 3.6 V
Voltage Range 1
32
32
Slave receiver mode
1.65 < V
DD
< 3.6 V
Voltage Range 1
f
SCK
1/t
c(SCK)
SPI clock frequency
–
–
MHz
Slave mode transmitter/full duplex
2.7 < V
DD
< 3.6 V
32
(2)
Voltage Range 1
Slave mode transmitter/full duplex
1.65 < V
DD
< 3.6 V
Voltage Range 1
Voltage Range 2
8
–
t
su(NSS)
NSS setup time
t
h(NSS)
NSS hold time
t
w(SCKH)
Slave mode, SPI prescaler = 2
Slave mode, SPI prescaler = 2
4xT
PCLK
2xT
PCLK
–
–
–
–
SCK high and low time
Master mode
T
PCLK
– 1.5
T
PCLK
T
PCLK
+ 1
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
Master mode
Slave mode
Master mode
Slave mode
1.5
1
–
–
–
–
–
–
–
–
Data input setup time
Data input hold time
5
–
ns
t
h(SI)
1
–
t
a(SO)
Data output access time
t
dis(SO)
Data output disable time
9
34
16
Slave mode
9
Slave mode 2.7 < V
DD
< 3.6 V
Voltage Range 1
–
–
–
14.5
15.5
19.5
15.5
24
Slave mode 1.65 < V
DD
< 3.6 V
Voltage Range 1
t
v(SO)
Data output valid time
Slave mode 1.65 < V
DD
< 3.6 V
Voltage Range 2
ns
26
t
v(MO)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
–
2.5
3
–
t
h(SO)
8
1
–
–
Data output hold time
t
h(MO)
–
1. Guaranteed
by characterization results.
2. Maximum
frequency in Slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
, which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having t
su(MI)
= 0 while Duty(SCK) = 50 %.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 31. SPI timing diagram – slave mode and CPHA = 0
NSS input
MISO
MSB OUT
BIT6 OUT
BIT1 IN
LSB OUT
OUTPUT
(SI)
MOSI
INPUT
LSB IN
MSB IN
(SI)
Figure 32. SPI timing diagram – slave mode and CPHA = 1
NSS input
t
SU(NSS)
t
h(NSS)
t
c(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(SO)
t
dis(SO)
t
v(SO)
t
a(SO)
MISO
MSB OUT
MSB IN
BIT6 OUT
LSB OUT
OUTPUT
t
h(SI)
t
su(SI)
MOSI
INPUT
LSB IN
BIT 1 IN
ai14135b
1. Measurement
points are set at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
Figure 33. SPI timing diagram – master mode
High
N
S
S
i
nput
t
c(SCK)
CPH
A
=
0
CPOL=0
CPH
A
=
0
CPOL=1
CPH
A
=
1
CPOL=0
CPH
A
=
1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
IN
P
UT
BIT6 IN
L
S
B IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BI
T
1 OUT
L
S
B OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement
points are set at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Quad-SPI characteristics
are derived from tests performed under the ambient temperature, f
frequency and V
AHB
DD
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 15 or 20 pF
Measurement points are set at CMOS levels: 0.5
ₓ
V
DD
characteristics.
(1)
Table 94. Quad-SPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.65 < V
DD
< 3.6
V
,
C
LOAD
= 20 pF
Voltage Range 1
–
–
40
1.65 < V
DD
< 3.6
V
,
C
LOAD
= 15 pF
Voltage Range 1
–
–
–
–
–
–
48
60
16
F
CK
Quad-SPI
clock frequency
MHz
1/t
(CK)
2.7 < V
DD
< 3.6
V
,
C
LOAD
= 15 pF
Voltage Range 1
1.65 < V
DD
< 3.6 V C
LOAD
= 20 pF
Voltage Range 2
t
w(CKH)
t
w(CKL)
t
(CK)
/2 – 0.5
–
–
t
(CK)
/2 + 1
Quad-SPI clock
high and low time
f
AHBCLK
= 48 MHz, presc=1
t
(CK)
/2 – 1
t
(CK)
/2 + 0.5
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
2
3.5
4.5
6
–
–
t
s(IN)
Data input setup time
Data input hold time
–
–
–
–
–
t
h(IN)
ns
–
–
1
1
–
1.5
1.5
–
t
v(OUT)
Data output valid time
t
h(OUT)
Data output hold time
–
0
0
–
–
1. Guaranteed
by characterization results.
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 95. Quad-SPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.65 < V
DD
< 3.6
V
,
C
LOAD
= 20 pF
Voltage Range 1
–
–
40
2.0 < V
DD
< 3.6
V
, C
LOAD
= 20 pF
Voltage Range 1
–
–
–
–
–
50
48
16
F
CK
Quad-SPI clock
frequency
MHz
1/t
(CK)
1.65 < V
DD
< 3.6
V
,
C
LOAD
= 15 pF
Voltage Range 1
1.65 < V
DD
< 3.6 V C
LOAD
= 20 pF
Voltage Range 2
–
t
w(CKH)
t
(CK)
/2
–
–
t
(CK)
/2 + 1
t
(CK)
/2
Quad-SPI clock
high and low time
f
AHBCLK
= 48 MHz, presc=0
t
w(CKL)
t
(CK)
/2 – 1
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
2.5
3.5
2.5
1.5
5.5
6.5
5
Data input setup
time on rising edge
t
sr(IN)
t
sf(IN)
t
hr(IN)
t
hf(IN)
–
–
–
–
–
–
Data input setup
time on falling edge
Data input hold
time on rising edge
Data input hold
time on falling edge
–
–
6
DHHC=0
Voltage Range 1
4
5.5
ns
Data output valid
time on rising edge
t
vr(OUT)
t
vf(OUT)
t
hr(OUT)
t
hf(OUT)
DHHC=1
–
t
(CK)
/2 + 1
t
(CK)
/2 + 1.5
Voltage Range 2
4.5
4
7
6
DHHC=0
Voltage Range 1
Data output valid
time on falling edge
DHHC=1
–
t
(CK)
/2 + 1
t
(CK)
/2 + 2
Voltage Range 2
6
–
–
–
–
–
–
7.5
DHHC=0
2
–
–
–
–
–
–
Voltage Range 1
Data output hold
time on rising edge
DHHC=1 t
(CK)
/2 + 0.5
3.5
Voltage Range 2
Voltage Range 1
Voltage Range 2
DHHC=0
3
Data output hold
time on falling edge
DHHC=1 t
(CK)
/2 + 0.5
5
1. Guaranteed
by characterization results.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 34. Quad-SPI timing diagram – SDR mode
t
r(CK)
t
(CK)
t
w(CKH)
t
w(CKL)
t
f(CK)
Clock
t
v(OUT)
t
h(OUT)
Data output
D0
D1
D2
t
s(IN)
t
h(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 35. Quad-SPI timing diagram – DDR mode
t
r(CLK)
t
(CLK)
t
w(CLKH)
t
w(CLKL)
t
f(CLK)
Clock
t
vf(OUT)
t
hr(OUT)
IO0
t
vr(OUT)
t
hf(OUT)
IO3
Data output
IO1
IO2
IO4
t
sr(IN
)
t
hr(IN)
IO5
t
sf(IN)
t
hf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
SAI characteristics
from tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
the following configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement are performed at CMOS levels: 0.5
ₓ
V
DD
characteristics (CK,SD,FS).
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
(1)
Table 96. SAI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
f
MCLK
SAI main clock output
–
–
50
Master transmitter
2.7 V
≤
V
DD
≤
3.6 V
Voltage Range 1
–
23.5
16
Master transmitter
1.65 V
≤
V
DD
≤
3.6 V
Voltage Range 1
–
–
–
Master receiver
Voltage Range 1
16
MHz
f
CK
SAI clock frequency
(2)
Slave transmitter
2.7 V
≤
V
DD
≤
3.6 V
26
20
Voltage Range 1
Slave transmitter
1.65 V
≤
V
DD
≤
3.6 V
Voltage Range 1
–
Slave receiver
Voltage Range 1
–
–
–
32
8
Voltage Range 2
Master mode
2.7 V
≤
V
DD
≤
3.6 V
21
t
v(FS)
FS valid time
Master mode
–
30
1.65 V
≤
V
DD
≤
3.6 V
t
h(FS)
t
su(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
10
1.5
2.5
1
–
–
–
–
–
–
t
h(FS)
Slave mode
t
su(SD_A_MR)
t
su(SD_B_SR)
t
h(SD_A_MR)
t
h(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
1.5
6.5
2.5
ns
–
Slave transmitter (after enable edge)
2.7 V
≤
V
DD
≤
3.6 V
–
19
t
v(SD_B_ST)
Data output valid time
Slave transmitter (after enable edge)
1.65 V
≤
V
DD
≤
3.6 V
–
10
–
25
–
t
h(SD_B_ST)
Data output hold time
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
2.7 V
≤
V
DD
≤
3.6 V
18.5
t
v(SD_A_MT)
Data output valid time
Master transmitter (after enable edge)
1.65 V
≤
V
DD
≤
3.6 V
–
25
–
t
h(SD_A_MT)
Data output hold time
Master transmitter (after enable edge)
10
1. Guaranteed
by characterization results.
2. APB
clock frequency must be at least twice SAI clock frequency.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 36. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
SAI_FS_X
t
h(FS)
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 37. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
DS11929 Rev 10
169
Electrical characteristics
STM32WB55xx STM32WB35xx
USB characteristics
The STM32WB55xx and STM32WB35xx USB interface is fully compliant with the USB
specification version 2.0, and is USB-IF certified (for Full-speed device operation).
(1)
Table 97. USB electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
V
DDUSB
USB transceiver operating voltage
–
3.0
(2)
–
3.6
85
V
USB crystal-less
T
crystal_less
–
–
-15
–
°
C
operation temperature
Embedded USB_DP pull-up value
during idle
R
PUI
900
1250 1600
Embedded USB_DP pull-up value
during reception
ꢀ
R
PUR
–
1400 2300 3200
28 36 44
(3)
Z
DRV
Output driver impedance
(4)
Driving high and low
1. T
A
= -40 to 125 °C unless otherwise specified.
2. The
STM32WB55xx and STM32WB35xx USB functionality is ensured down to 2.7 V, but the full USB
electrical characteristics are degraded in the 2.7 to 3.0 V voltage range.
3. Guaranteed
by design.
4. No
external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
JTAG/SWD interface characteristics
tests performed under the ambient temperature, f
frequency and supply voltage
configuration:
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5
ₓ
V
DD
Table 98. JTAG characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
2.7 < V
DD
< 3.6 V
–
–
–
29
1/t
c(TCK)
TCK clock frequency
MHz
1.65 < V
DD
< 3.6 V
–
21
t
isu(TMS)
t
ih(TMS)
t
isu(TDI)
t
ih(TDI)
TMS input setup time
TMS input hold time
TDI input setup time
TDI input hold time
–
2.5
2
–
–
–
–
–
–
1.5
2
–
–
–
–
–
ns
2.7 < V
DD
< 3.6 V
1.65 < V
DD
< 3.6 V
–
–
13.5
13.5
–
16.5
23
–
t
ov(TDO)
t
oh(TDO)
TDO output valid time
TDO output hold time
–
11
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Electrical characteristics
Table 99. SWD characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
2.7 < V
DD
< 3.6 V
–
–
–
–
55
35
–
1/t
c(SWCLK)
SWCLK clock frequency
MHz
1.65 < V
DD
< 3.6 V
t
isu(TMS)
t
ih(TMS)
SWDIO input setup time
SWDIO input hold time
–
2.5
2
–
–
–
–
2.7 < V
DD
< 3.6 V
1.65 < V
DD
< 3.6 V
–
–
16
16
–
18
28
–
ns
t
ov(TDO)
t
oh(TDO)
SWDIO output valid time
SWDIO output hold time
–
13
(CK, SD, WS).
DS11929 Rev 10
169
Package information
STM32WB55xx STM32WB35xx
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
ECOPACK is an ST trademark.
7.1
UFBGA129 package information
This UFBGA is a 129-ball, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array package.
Figure 38. UFBGA129 package outline
SEATING
PLANE
A4
A1 corner index area
B
A2
A
B
C
D
E
F
G
H J
K L M
N
b
1
2
e
3
4
5
6
7
8
E
E1
9
10
11
12
13
b (129 balls)
A
B
eee
C
M
M
C
f f f
F
e
F
A1
A
D1
D
ddd
C
BOTTOM VIEW
B09R_UFBGA129_ME_V2
1. Drawing
is not to scale.
2. –
The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metalized markings, or other feature of package body or integral heat slug.
– A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
Table 100. UFBGA129 mechanical data
millimeters
Typ
inches
(1)
Typ
Symbol
Min
Max
Min
Max
A
(2)
A1
–
–
0.60
0.11
–
–
–
0.024
–
–
–
–
0.004
A2
–
–
0.13
0.32
0.29
–
–
0.005
0.013
0.011
–
–
A4
–
b
(3)
0.24
0.34
0.009
0.013
170/1
93
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
Table 100. UFBGA129 mechanical data (continued)
millimeters
Typ
inches
(1)
Symbol
Min
Max
Min
Typ
Max
D
E
6.85
7.00
7.00
6.00
6.00
0.50
0.50
–
7.15
0.270
0.276
0.276
0.236
0.236
0.020
0.020
–
0.281
6.85
7.15
0.270
0.281
D1
E1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
e
–
–
F
–
–
ddd
eee
(4)
fff
(5)
0.08
0.15
0.05
0.003
0.006
0.002
–
–
–
–
1. Values
in inches are converted from mm and rounded to four decimal digits.
2. –
UFBGA stands for Ultra Thin Profile Fine Pitch Ball Grid Array.
– Ultra thin profile: 0.50 < A
≤
0.65mm / Fine pitch: e < 1.00mm pitch.
– The total profile height (Dim A) is measured from the seating plane to the top of the component
– The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ +
√
(A1²+A2²+A4² tolerance values).
3. The
typical balls diameters before mounting is 0.20 mm.
4. The
tolerance of position that controls the location of the pattern of balls with respect to datum A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The
tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.
Figure 39. UFBGA129 recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
Table 101. UFBGA129 recommended PCB design rules
Dimension Recommended
values
Pitch
0.5 mm
Dpad
0,360 mm
Dsm
0.460 mm typ. (depends on soldermask registration tolerance)
Stencil opening
Stencil thickness
0.360 mm
0.100 mm
Device marking for UFBGA129
Figure 40
gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 40. UFBGA129 marking example (package top view)
STM32WB
Product identification
(1)
55V
Additional
information
Y WW
Y
Pin 1 identifier
Date code
MS53511V1
1. Parts
marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
7.2
WLCSP100 package information
WLCSP100 is a 100-ball, 4.390 x 4.371 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 41. WLCSP100 outline
e1
A1
A1 BALL LOCATION
F
10
1
G
e
A
DETAIL A
e4
e2
E
E
K
K
e
e3
H
A
D
D
A2
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A3
A2
BUMP
FRONT VIEW
A1
SEATING PLANE
DETAIL A
ROTATED 90
A08S_WLCSP100_ME_V1
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
Table 102. WLCSP100 mechanical data
millimeters
Typ
inches
(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
A3
b
–
–
0.18
0.38
0.025
(2)
0.25
4.40
4.38
0.40
3.60
3.60
0.08
0.08
0.480
(3)
0.306
(3)
0.32
0.47
–
0.59
–
–
0.023
–
–
–
0.007
0.015
0.001
0.010
0.1728
0.1721
0.0157
0.1417
0.1417
0.0031
0.0033
0.0187
0.0119
0.0124
0.0185
–
–
–
–
–
–
–
–
–
–
0.22
0.28
0.009
0.0110
D
4.38
4.42
0.1715
0.1742
E
4.36
4.40
0.1707
0.1735
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
e1
e2
e3
e4
F
–
–
–
–
–
–
–
–
–
–
G
–
–
H
–
–
K
–
–
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.05
0.05
0.0039
0.0039
0.0039
0.0020
0.0020
–
–
–
–
–
–
–
–
1. Values
in inches are converted from mm and rounded to the third decimal place.
2. Nominal
dimension rounded to the third decimal place results from process capability.
3. Calculated
dimensions are rounded to third decimal place.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
Figure 42. WLCSP100 recommended footprint
Dpad
Dsm
A08S_WLCSP100_FP_V1
1. Dimensions
are expressed in millimeters.
Table 103. WLCSP100 recommended PCB design rules
Dimension Recommended
values
Pitch
0.4 mm
Dpad
0.225 mm
Dsm
0.290 mm typ. (depends on the soldermask registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
Device marking for WLCSP100
Figure 43
gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
Figure 43. WLCSP100 marking example (package top view)
Pin 1 identifier
WB55V
Product
identification
(1)
Y ww Y
Date code
MS53512V1
1. Parts
marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
7.3
VFQFPN68 package information
VFQFPN68 is a 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat package.
Figure 44. VFQFPN68 package outline
PIN 1 IDENTIFIER
LASER MARKING
ddd C
D
A
A1
68 67
A2
1
2
E
E
0.10 C
(2X)
SEATING
PLANE
C
TOP VIEW
D2
SIDE VIEW
L
E2
2
1
PIN 1 ID
C 0.30 X 45′
68 67
b
e
EXPOSED PAD AREA
B029_VFQFPN68_ME_V1
BOTTOM VIEW
1. VFQFPN
stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed
version. Very thin profile: 0.80 < A
≤
1.00 mm.
2. The
pin #1 identifier must be existed on the top surface of the package by using indentation mark or other
feature of package body. Exact shape and size of this feature is optional.
Table 104. VFQFPN68 mechanical data
millimeters
Typ
inches
(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.80
0
0.90
0.02
0.20
0.20
8.00
6.40
1.00
0.05
–
0.0315
0
0.0354
0.0008
0.0008
0.0079
0.3150
0.2520
0.0394
0.0020
–
–
–
0.15
7.85
6.30
0.25
8.15
6.50
0.0059
0.3091
0.2480
0.0098
0.3209
0.2559
D
D2
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
Table 104. VFQFPN68 mechanical data (continued)
millimeters
Typ
inches
(1)
Symbol
Min
Max
Min
Typ
Max
E
E2
e
7.85
6.30
–
8.00
6.40
0.40
0.50
–
8.15
6.50
–
0.3091
0.3150
0.2520
0.0157
0.0197
–
0.3209
0.2559
–
0.2480
–
L
0.40
–
0.60
0.08
0.0157
–
0.0236
0.0031
ddd
1. Values
in inches are converted from mm and rounded to four decimal digits.
Figure 45. VFQFPN68 recommended footprint
8.30
7.00
6.65
6.40
0.40
0.15
0.25
0.82
0.65
B029_VFQFPN68_FP_V2
1. Dimensions
are expressed in millimeters.
Device marking for VFQFPN68
Figure 45
gives an example of topside marking orientation versus pin 1 identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
Figure 46. VFQFPN68 marking example (package top view)
STM32WB55
Product
identification
(1)
R
Y
Pin 1 identifier
MS53514V1
1. Parts
marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
7.4
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 47. UFQFPN48 outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500×45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing
is not to scale.
2. All
leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There
is an exposed die pad on the underside of the UFQFPN package, it must be electrically connected to
the PCB ground.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
inches
(1)
Table 105. UFQFPN48 mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
–
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
–
0.600
0.050
7.100
7.100
5.700
5.700
0.500
–
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
–
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
–
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
–
E
D2
E2
L
T
b
0.200
–
0.300
–
0.0079
–
0.0118
–
e
ddd
–
0.080
–
0.0031
1. Values
in inches are converted from mm and rounded to four decimal digits.
Figure 48. UFQFPN48 recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions
are expressed in millimeters.
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
Device marking for UFQFPN48
location. The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 49. STM32WB55xx UFQFPN48 marking example (package top view)
STM32WB55
Product
identification
(1)
CGU6
Date code
Y
WW
Pin 1 identifier
Y
Revision code
MS51581V2
1. Parts
marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
Figure 50. STM32WB35xx UFQFPN48 marking example (package top view)
STM32WB35
Product
identification
(1)
CCU6
Date code
Y
WW
Pin 1 identifier
A
Revision code
MS53143V2
1. Parts
marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
7.5
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
The maximum chip-junction temperature, T
max, in degrees Celsius, can be calculated
J
using the equation:
T max
= T
max + (P
max x
Θ
)
J
A
D
JA
where:
T max
is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C / W,
JA
P max
is the sum of P
max and P
max (P
max = P
max + P
max),
INT I/O
D
INT
I/O
D
P
max is the product of I
and V
, expressed in Watt. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins:
I/O
P
max =
Σ
(V ×
I )
+
Σ
((V –
V )
× I
)
I/O
OL
OL
DD
OH
OH
taking into account the actual V
/ I
and V
/ I
of the I/Os at low and high level in the
OL OL
OH OH
application.
Note:
When the SMPS is used, a portion of the power consumption is dissipated into the external
inductor, therefore reducing the chip power dissipation. This portion depends mainly on the
inductor ESR characteristics.
Note:
Note:
As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the
chip power consumption.
RF characteristics (such as sensitivity, Tx power, consumption) are provided up to 85 °C.
Table 106. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
24.9
UFQFPN48 – 7 mm x 7 mm
Thermal resistance junction-ambient
47.0
35.8
41.5
13.0
36.1
N/A
VFQFPN68 – 8 mm x 8 mm
Θ
JA
°C/W
Thermal resistance junction-ambient
WLCSP100 – 0.4 mm pitch
Thermal resistance junction-ambient
UFBGA129 – 0.5 mm pitch
Thermal resistance junction-board
UFQFPN48 – 7 mm x 7 mm
Thermal resistance junction-board
VFQFPN68 – 8 mm x 8 mm
Θ
JB
°C/W
Thermal resistance junction-board
WLCSP100 – 0.4 mm pitch
Thermal resistance junction-board
16.2
UFBGA129 – 0.5 mm pitch
DS11929 Rev 10
185
Package information
STM32WB55xx STM32WB35xx
Table 106. Package thermal characteristics (continued)
Symbol
Parameter
Value
Unit
Thermal resistance junction-case
1.3
UFQFPN48 – 7 mm x 7 mm
Thermal resistance junction-case
13.7
N/A
VFQFPN68 – 8 mm x 8 mm
Θ
JC
°C/W
Thermal resistance junction-case
WLCSP100 – 0.4 mm pitch
Thermal resistance junction-case
34.9
UFBGA129 – 0.5 mm pitch
7.5.1
7.5.2
Reference document
JESD51-2 Integrated Circuits Thermal
T
e
st Method Environment Conditions – Natural
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the device at maximum dissipation, it is useful to
calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
max = 82 °C (measured according to JESD51-2),
A
I
max = 50 mA, V
= 3.5 V, maximum 20 I/Os used at the same time in output at
DD
DD
low level with I
= 8 mA, V
= 0.4 V and maximum 8 I/Os used at the same time in
OL
OL
output at low level with I
= 20 mA, V
= 1.3 V
OL
OL
P
P
max = 50 mA × 3.5 V = 175 mW
INT
max = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IO
This gives: P
max = 175 mW and P
max = 272 mW
IO
INT
P max
= 175 + 272 = 447 mW
D
J
–
For VFQFPN68, 47 °C / W
T max
= 82 °C + (47 °C / W × 447 mW) = 82 °C + 21 °C = 103 °C
J
J
In this case, parts must be ordered at least with the temperature range suffix 6.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Package information
Note:
With this given P
max user can find the T
max allowed for a given device temperature
D
A
range (order code suffix 7).
Suffix 7: T
max = T
max – (47 °C / W × 447 mW) = 125 °C – 21 °C = 103 °C
A
J
Example 2: High-temperature application
Using the same rules, it is possible to address applications running at high ambient
temperatures with a low dissipation, as long as junction temperature T
remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
max = 100 °C (measured according to JESD51-2),
A
I
max = 50 mA, V
= 3.5 V, maximum 20 I/Os used at the same time in output at
DD
DD
low level with I
= 8 mA, V
= 0.4 V
OL
OL
P
P
max = 50 mA × 3.5 V = 175 mW
INT
max = 20 × 8 mA × 0.4 V = 64 mW
IO
This gives: P
= 175 mW and P
max = 64 mW
IO
INTmax
P max
= 175 + 64 = 239 mW
D
Thus: P
max = 239 mW
D
J
–
For UFQFPN48, 24.9 °C / W
T max
= 100 °C + (24.9 °C / W × 239 mW) = 100 °C + 6 °C = 106 °C
J
This is above the range of the suffix 6 version parts (–40 < T
< 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8
), unless user reduces the power dissipation to be able to use suffix 6 parts.
DS11929 Rev 10
185
Ordering information
STM32WB55xx STM32WB35xx
8
Ordering information
Example:
STM32
WB
55
V
G
V
6 A
TR
Device family
®
STM32 = Arm
based 32-bit microcontroller
Product type
®
WB = Wireless Bluetooth
Device subfamily
55 = Die 5, full set of features
35 = Die 3, full set of features
(1)
Pin count
C = 48 pins
R = 68 pins
V = 100 or 129 pins
Flash memory size
C = 256 Kbytes
E = 512 Kbytes
Y
(2)
= 640 Kbytes
G = 1 Mbyte
Package
U = UFQFPN48 7 x 7 mm
V = VFQFPN68 8 x 8 mm
Y = WLCSP100 0.4 mm pitch
Q = UFBGA129 0.5 mm pitch
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
7 = Industrial temperature range, -40 to 105 °C (125 °C junction)
Identification code
A = Proprietary identification code
blank = Non-proprietary identification code
Packing
TR = tape and reel
xxx = programmed parts
1. STM32WB35xx
only available with 48-pin UFQFPN48 package, 256 or 512 Kbytes Flash
memory.
2. Only
STM32WB55V
Y
,
W
LCSP100 package, temperature range -40 to 85 °C (105 °C junction).
186/1
93
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Revision history
9
Revision history
Table 107. Document revision history
Changes
Date
Revision
25-Jul-2017
1
Initial release.
unit
,
Section 3.3.3: Embedded Flash memory
,
Section 3.4: Security and
safety
,
Section 3.6: RF subsystem
,
Section 3.6.1: RF front-end block
diagram
,
Section 3.6.2: BLE general description
,
Section 3.7.1: Power
supply distribution
,
Section 3.7.2: Power supply schemes
,
Section 3.7.4:
Power supply supervisor
,
Section 3.10: Clocks and startup
,
Section 3.14:
Analog to digital converter (ADC)
,
Section 3.19: True random number
generator (RNG)
,
Section 5: Memory mapping
,
Section 6.3.25: SMPS
step-down converter characteristics
and
Section 7.5.2: Selecting the
product temperature range
.
Updated
Table 2: STM32WB55xx devices features and peripheral
counts
,
T
a
ble 6: Power supply typical components
,
Table 7: Features
over all modes
,
Table 8: STM32WB55xx modes overview
,
Table 13:
Timer features
,
T
a
ble 15: Legend/abbreviations used in the pinout table
,
Table 16: STM32WB55xx pin and ball definitions
,
Table 17: Alternate
functions
,
Table 23: RF transmitter BLE characteristics
,
Table 26: RF
receiver BLE characteristics (1 Mbps)
and added footnote to it,
Table 28:
RF BLE power consumption for VDD = 3.3 V
,
Table 31: RF 802.15.4
power consumption for VDD = 3.3 V
,
Table 37: Typical current
consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V
,
Table 38: Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V
,
Table 40:
Current consumption in Low-power sleep modes, Flash memory in Power
down
,
Table 41: Current consumption in Stop 2 mode
,
T
a
ble 42: Current
consumption in Stop 1 mode
,
Table 43: Current consumption in Stop 0
mode
,
Table 44: Current consumption in Standby mode
,
T
a
ble 45:
Current consumption in Shutdown mode
,
Table 48: Peripheral current
consumption
,
T
a
ble 104: Package thermal characteristics
and
Table 97:
STM32WB55xx ordering information scheme
.
04-Apr-2018
2
Added
Table 47: Current under Reset condition
.
STM32WB55xx RF front-end block diagram
,
Figure 4: Power distribution
,
Figure 6: Power supply overview
,
Figure 7: Clock tree
,
Figure 8:
STM32WB55Cx UFQFPN48 pinout
(1)(2)
,
Figure 9: STM32WB55Rx
VFQFPN68 pinout
(1)(2)
,
Figure 10: STM32WB55Vx WLCSP100 ballout
(1)
and
Figure 14: Power supply scheme (all packages except UFBGA129)
.
DS11929 Rev 10
192
Revision history
STM32WB55xx STM32WB35xx
Table 107. Document revision history (continued)
Date
Revision
Changes
Changed document classification to Public.
Power supply schemes
,
Section 3.7.3: Linear voltage regulator
,
Section 3.10: Clocks and startup
,
Section 6.3.10: External clock source
characteristics
,
Section 6.3.20: Analog-to-Digital converter
characteristics
,
Section 6.3.29: Communication interfaces characteristics
,
Section 7.2: WLCSP100 package information
and
Section 7.5: Thermal
characteristics
.
Replaced V
DDIOx
with V
DD
throughout the whole document.
Updated
Table 5: Typical external components
, footnote
2
of
Table 7:
Features over all modes
,
Table 8: STM32WB55xx modes overview
and
its footnote
5
,
Table 12: Internal voltage reference calibration values
,
Table 16: STM32WB55xx pin and ball definitions
and its footnote
6
,
Table 17: Alternate functions
,
Table 20: Thermal characteristics
,
Table 21: Main performance at VDD = 3.3 V
,
Table 21: Main performance
at VDD = 3.3 V
,
T
a
ble 22: General operating conditions
,
Table 23: RF
transmitter BLE characteristics
and its footnote,
Table 26: RF receiver
BLE characteristics (1 Mbps)
,
Table 28: RF BLE power consumption for
VDD = 3.3 V
,
Table 29: RF transmitter 802.15.4 characteristics
and its
footnote
1
,
T
a
ble 30: RF receiver 802.15.4 characteristics
,
Table 31: RF
802.15.4 power consumption for VDD = 3.3 V
,
T
a
ble 34: Embedded
internal voltage reference
,
T
a
ble 35: Current consumption in Run and
Low-power run modes, code with data processing running from Flash,
ART enable (Cache ON Prefetch OFF), VDD = 3.3 V
,
Table 36: Current
consumption in Run and Low-power run modes, code with data
processing running from SRAM1, VDD = 3.3 V
,
Table 37: Typical current
consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V
,
Table 38: Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V
,
Table 39:
Current consumption in Sleep and Low-power sleep modes, Flash
memory ON
,
Table 40: Current consumption in Low-power sleep modes,
Flash memory in Power down
,
Table 41: Current consumption in Stop 2
mode
,
Table 42: Current consumption in Stop 1 mode
,
Table 43: Current
consumption in Stop 0 mode
,
Table 44: Current consumption in Standby
mode
,
Table 45: Current consumption in Shutdown mode
,
Table 46:
Current consumption in VBAT mode
,
Table 47: Current under Reset
condition
,
Table 48: Peripheral current consumption
,
Table 49: Low-
power mode wakeup timings
,
T
a
ble 50: Regulator modes transition times
,
Table 51: Wakeup time using LPUART
,
T
a
ble 53: HSE clock source
requirements
and added footnote to it,
Table 61: LSI2 oscillator
characteristics
,
T
a
ble 63: Flash memory characteristics
,
Table 65: EMS
characteristics
,
T
a
ble 67: ESD absolute maximum ratings
,
Table 69: I/O
current injection susceptibility
,
Table 70: I/O static characteristics
and its
footnotes,
T
a
ble 71: Output voltage characteristics
,
Table 72: I/O AC
characteristics
and its footnotes
1
and
2
,
Table 73: NRST pin
08-Oct-2018
3
characteristics
,
T
a
ble 77: ADC accuracy – Limited test conditions 1
,
Table 78: ADC accuracy – Limited test conditions 2
,
Table 79: ADC
accuracy – Limited test conditions 3
,
Table 80: ADC accuracy – Limited
test conditions 4
,
Table 82: COMP characteristics
,
Table 90: I2C analog
filter characteristics
,
Table 91: SPI characteristics
,
Table 92: Quad-SPI
characteristics in SDR mode
,
Table 93: Quad-SPI characteristics in DDR
mode
and
Table 94: SAI characteristics
.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Revision history
Table 107. Document revision history (continued)
Date
Revision
Changes
Updated
Figure 2: STM32WB55xx RF front-end block diagram
,
Figure 14: Power supply scheme (all packages except UFBGA129)
,
Figure 18: Typical energy detection (T = 27°C, VDD = 3.3 V)
and
Figure 25: I/O input characteristics
.
Added
Figure 5: Power-up/down sequence
,
Figure 17: Typical link quality
indicator code vs. Rx level
and
Figure 18: Typical energy detection (T =
27°C, VDD = 3.3 V)
.
3
08-Oct-2018
(cont’d) Added
Table 24: RF transmitter BLE characteristics (1 Mbps)
,
Table 25:
RF transmitter BLE characteristics (2 Mbps)
,
T
a
ble 27: RF receiver BLE
characteristics (2 Mbps)
,
Table 52: HSE crystal requirements
and
Table 89: Minimum I2CCLK frequency in all I2C modes
.
Removed former
Figure 22: I/O AC characteristics definition
(1)
and
Figure 27: SMPS efficiency – VDDSMPS = 3.6 V
.
Updated document title.
Product status moved to Production data.
Introduced BGA129 package, hence updated image on cover page,
Table 16: STM32WB55xx pin and ball definitions
and
Section 8: Ordering
information
, and added
Figure 11: STM32WB55Vx UFBGA129 ballout
(1)
and
Section 7.1: UFBGA129 package information
.
Updated
Features
,
Section 3.3.4: Embedded SRAM
,
Section 3.17:
T
o
uch
sensing controller (TSC)
and
Section 3.24: Low-power universal
asynchronous receiver transmitter (LPUART)
.
20-Feb-2019
4
Added
Section 6.3.28: Clock recovery system (CRS)
.
Added
Table 76: ADC sampling time
.
Removed former
Table 75: Maximum ADC RAIN
and
T
a
ble 84: SMPS
step-down converter characteristics
.
Updated captions of figures
8
,
9
and
10
.
Updated
Figure 43: VFQFPN68 recommended footprint
.
DS11929 Rev 10
192
Revision history
STM32WB55xx STM32WB35xx
Table 107. Document revision history (continued)
Date
Revision
Changes
Updated
Table 2: STM32WB55xx devices features and peripheral
counts
,
T
a
ble 8: STM32WB55xx modes overview
and its footnotes,
Table 21: Main performance at VDD = 3.3 V
,
Table 22: General operating
conditions
,
Table 23: RF transmitter BLE characteristics
,
Table 24: RF
transmitter BLE characteristics (1 Mbps)
,
Table 25: RF transmitter BLE
characteristics (2 Mbps)
,
Table 26: RF receiver BLE characteristics (1
Mbps)
,
Table 27: RF receiver BLE characteristics (2 Mbps)
,
T
a
ble 28: RF
BLE power consumption for VDD = 3.3 V
,
Table 29: RF transmitter
802.15.4 characteristics
,
Table 31: RF 802.15.4 power consumption for
VDD = 3.3 V
,
Table 35: Current consumption in Run and Low-power run
modes, code with data processing running from Flash, ART enable
(Cache ON Prefetch OFF), VDD = 3.3 V
,
Table 36: Current consumption
in Run and Low-power run modes, code with data processing running
from SRAM1, VDD = 3.3 V
,
Table 37: Typical current consumption in Run
and Low-power run modes, with different codes running from Flash, ART
enable (Cache ON Prefetch OFF), VDD= 3.3 V
,
Table 38: Typical current
consumption in Run and Low-power run modes, with different codes
4
20-Feb-2019
(cont’d)
running from SRAM1, VDD = 3.3 V
,
Table 39: Current consumption in
Sleep and Low-power sleep modes, Flash memory ON
,
Table 40: Current
consumption in Low-power sleep modes, Flash memory in Power down
,
Table 41: Current consumption in Stop 2 mode
,
Table 42: Current
consumption in Stop 1 mode
,
Table 43: Current consumption in Stop 0
mode
,
Table 44: Current consumption in Standby mode
,
T
a
ble 45:
Current consumption in Shutdown mode
,
Table 46: Current consumption
in VBAT mode
,
Table 47: Current under Reset condition
,
Table 48:
Peripheral current consumption
and its footnotes,
T
a
ble 49: Low-power
mode wakeup timings
,
T
a
ble 50: Regulator modes transition times
and its
footnote
1
,
T
a
ble 65: EMS characteristics
,
Table 66: EMI characteristics
,
Table 67: ESD absolute maximum ratings
,
T
a
ble 69: I/O current injection
susceptibility
,
Table 75: ADC characteristics
,
T
a
ble 77: ADC accuracy –
Limited test conditions 1
,
Table 78: ADC accuracy – Limited test
conditions 2
,
T
a
ble 79: ADC accuracy – Limited test conditions 3
,
Table 80: ADC accuracy – Limited test conditions 4
and
Table 104:
Package thermal characteristics
.
scheme
,
Section 6.2: Absolute maximum ratings
and
Section 7.2:
WLCSP100 package information
.
Updated
Table 6: Power supply typical components
,
Table 7: Features
over all modes
,
Table 11: Temperature sensor calibration values
,
Table 16: STM32WB55xx pin and ball definitions
,
Table 17: Alternate
functions
,
Table 21: Main performance at VDD = 3.3 V
,
T
a
ble 26: RF
receiver BLE characteristics (1 Mbps)
,
Table 34: Embedded internal
04-Oct-2019
5
voltage reference
,
T
a
ble 62: PLL, PLLSAI1 characteristics
and
Table 67:
ESD absolute maximum ratings
.
Updated
Figure 6: Power supply overview
and
Figure 33: Quad-SPI
timing diagram – DDR mode
.
Added
Figure 15: Power supply scheme (UFBGA129 package)
and
Figure 21: Low-speed external clock source AC timing diagram
.
Added
T
a
ble 56: Low-speed external user clock characteristics – Bypass
mode
.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
Revision history
Table 107. Document revision history (continued)
Date
Revision
Changes
consumption
,
Section 3.17:
T
o
uch sensing controller (TSC)
,
Section 7.1:
UFBGA129 package information
,
Section 7.2: WLCSP100 package
information
,
Section 7.3: VFQFPN68 package information
,
Section 7.4:
UFQFPN48 package information
,
Section 7.5: Thermal characteristics
and
Section 8: Ordering information
.
Added
JTAG/SWD interface characteristics
,
Device marking for
UFBGA129
,
Device marking for WLCSP100
and
Device marking for
VFQFPN68
.
Updated
Table 2: STM32WB55xx devices features and peripheral
counts
,
T
a
ble 7: Features over all modes
,
Table 16: STM32WB55xx pin
and ball definitions
,
Table 17: Alternate functions
,
T
a
ble 18: Voltage
characteristics
,
T
a
ble 22: General operating conditions
,
Table 26: RF
receiver BLE characteristics (1 Mbps)
,
Table 27: RF receiver BLE
characteristics (2 Mbps)
,
Table 30: RF receiver 802.15.4 characteristics
,
Table 47: Current under Reset condition
,
Table 61: LSI2 oscillator
characteristics
and
Table 104: Package thermal characteristics
.
19-Feb-2020
6
Added footnote
5
to
Table 15: Legend/abbreviations used in the pinout
table
.
Updated
Figure 2: STM32WB55xx RF front-end block diagram
,
Figure 6:
Power supply overview
,
Figure 7: Clock tree
,
Figure 11: STM32WB55Vx
UFBGA129 ballout
(1)
,
Figure 14: Power supply scheme (all packages
except UFBGA129)
,
Figure 36: UFBGA129 package outline
and
Figure 47: UFQFPN48 marking example (package top view)
.
Updated
Section 3.6.5: Typical RF application schematic
and
Section 6.3.10: External clock source characteristics
.
Updated
Figure 11: STM32WB55Vx UFBGA129 ballout
(1)
and
Figure 14:
Power supply scheme (all packages except UFBGA129)
.
10-Apr-2020
7
Minor text edits across the whole document.
Introduced STM32WB55V
Y
.
17-Jun-2020
8
DS11929 Rev 10
192
Revision history
STM32WB55xx STM32WB35xx
Table 107. Document revision history (continued)
Date
Revision
Changes
Added STM32WB35xx devices.
02-Jul-2020
9
scheme (UFBGA129 and WLCSP100 packages)
and added footnote to
23-Nov-2020
10
.
Minor text edits across the whole document.
DS11929 Rev 10
STM32WB55xx STM32WB35xx
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