STMicroelectronics-STP12NK30Z

STP12NK30Z  

N-CHANNEL 300V – 0.36

Ω

– 9A – TO-220  

Zener-Protected SuperMESH™Power MOSFET  

TYPE  

V

R

I

(1)  

D

Pw

(1)  

DSS  

DS(on)  

STP12NK30Z  

300 V  

< 0.4

Ω

 

9 A  

90 W  

■

■

■

■

■

■

■

TYPICAL R

 

(on) = 0.36

Ω

 

DS  

EXTREMELY HIGH dv/dt CAPABILITY  

IMPROVED ESD CAPABILITY  

100% AVALANCHE RATED  

3

2

1

GATE CHARGE MINIMIZED  

VERY LOW INTRINSIC CAPACITANCES  

VERY GOOD MANUFACTURING  

REPEATIBILITY  

TO-220  

DESCRIPTION  

The SuperMESH™ series is obtained through an  

extreme optimization of ST’s well established strip-  

based PowerMESH™ layout. In addition to pushing  

on-resistance significantly down, special care is tak-  

en to ensure a very good dv/dt capability for the  

most demanding applications. Such series comple-  

ments ST full range of high voltage MOSFE

T

s

i

n-  

cluding revolutionary MDmesh™ products.  

INTERNAL SCHEMATIC DIAGRAM  

APPLICATIONS  

■

LIGHTING  

■

IDEAL FOR OFF-LINE POWER SUPPLIES,  

ADAPTORS AND PFC  

■

HIGH CURRENT, HIGH SPEED SWITCHING  

ORDERING INFORMATION  

SALES TYPE  

MARKING  

PACKAGE  

P

A

CKAGING  

STP12NK30Z  

P12NK30Z  

TO-220  

TUBE  

December 2002  

1/8  

STP12NK30Z  

ABSOLUTE MAXIMUM RATINGS  

Symbol  

Parameter  

Value  

300  

Unit  

V

V

DS  

Drain-source Voltage (V

 

= 0)  

GS  

V

Drain-gate Voltage (R

 

= 20 k

Ω

)  

300  

V

DGR  

GS  

V

Gate- source Voltage  

± 30  

V

GS  

I

Drain Current (continuous) at T

 

= 25°C  

A

A

9

5.6  

D

C

Drain Current (continuous) at T

 

= 100°C  

C

I

(1)  

Drain Current (pulsed)  

36  

90  

A

DM  

P

Total Dissipation at T

 

= 25°C  

W

TOT  

C

Derating Factor  

0.72  

3000  

4.5  

W/°C  

V/ns  

V/ns  

V

Gate source ESD(HBM-C=100p

F

,

R

=1.5K

Ω)  

Peak Diode Recovery voltage slope  

Storage

T

e

mperature  

ESD(G-S)  

dv/dt (2)  

T

stg  

–55 to 150  

°C  

T

Max. Operating Junction

T

e

mperature  

j

THERMAL DATA  

Rthj-case  

Rthj-amb  

Thermal Resistance Junction-case  

Thermal Resistance Junction-ambient  

Max  

Max  

1.38  

62.5  

300  

°C/W  

°C/W  

°C  

T

Maximum Lead

T

emperature For Soldering Purpose  

l

Note: 1. Pulse

 

width limited by safe operating area  

2. I

 

< 9A, di/dt<300A/µs, V

 

<V ,

 

T <T  

JMAX  

SD  

DD  

(BR)DSS  

J

AVALANCHE CHARACTERISTICS  

Symbol  

Parameter  

Max Value  

Unit  

I

AR  

Avalanche Current, Repetitive or Not-Repetitive  

9

A

(pulse width limited by T

 

max)  

j

E

Single Pulse Avalanche Energy  

155  

mJ  

AS  

(starting T

 

= 25 °C, I

 

= I

 

, V

 

= 50 V)  

j

D

AR  

DD  

GATE-SOURCE ZENER DIODE  

Symbol  

BV  

Parameter  

Test Conditions  

Igs=± 1mA (Open Drain)  

Min.  

30  

T

y

p.  

Max.  

Unit  

Gate-Source Breakdown  

Voltage  

V

GSO  

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES  

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s  

ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be  

applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and  

cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the  

usage of external components.  

2/8  

STP12NK30Z  

ELECTRICAL CHARACTERISTICS

(TCASE =25°C UNLESS OTHERWISE SPECIFIED)  

ON/OFF  

Symbol  

Parameter  

Drain-source  

Test Conditions  

Min.  

T

y

p.  

Max.  

Unit  

V

I

= 1 mA, V

 

= 0  

300  

V

(BR)DSS  

D

GS  

Breakdown Voltage  

I

Zero Gate Voltage  

V

V

= Max Rating  

= Max Rating, T

 

= 125 °C  

1

50  

µA  

µA  

DSS  

DS  

DS  

Drain Current (V

 

= 0)  

GS  

C

I

Gate-body Leakage  

V

= ± 20V  

±10  

µA  

GSS  

GS  

Current (V

 

= 0)  

DS  

V

V

V

= V

 

, I

 

= 50µA  

Gate Threshold Voltage  

3

3.75  

0.36  

4.5  

0.4  

V

GS(th)  

DS  

GS  

GS  

D

R

Static Drain-source On  

Resistance  

= 10

V

, I

 

=

4

.5 A  

Ω

DS(on)  

D

DYNAMIC  

Symbol  

Parameter  

Test Conditions  

Min.  

T

y

p.  

Max.  

Unit  

g

(1)  

Forward Transconductance  

V

V

= 10 V

 

I =

 

4.5 A  

5.4  

S

fs  

DS  

, D  

C

C

C

Input Capacitance  

Output Capacitance  

Reverse Transfer  

Capacitance  

V

= 25V, f = 1 MHz, V

 

= 0  

670  

125  

28  

pF  

pF  

pF  

iss  

DS  

GS  

oss  

rss  

C

(3) Equivalent

 

Output  

Capacitance  

= 0V, V

 

= 0V to 440 V  

70  

pF  

oss eq.  

GS  

DS  

R

Gate Input Resistance  

f=1 MHz Gate DC Bias = 0  

T

e

st Signal Level = 20mV  

Open Drain  

3.6  

Ω

G

SWITCHING  

Symbol  

Parameter  

Test Conditions  

Min.  

T

y

p.  

Max.  

Unit  

t

Turn-on Delay Time  

Rise time  

Turn-off Delay Time  

Fall Time  

V

R

= 150

V

, I

 

= 4.5 A  

= 4.7

Ω

V =

 

10 V  

GS  

16  

20  

36  

10  

ns  

ns  

ns  

ns  

d(on)  

DD  

D

t

r

G

t

(Resistive Load see, Figure 3)  

d(off)  

t

f

Q

Q

Q

V

V

= 240

V

, I

 

= 9 A,  

= 10V  

35  

T

o

tal Gate Charge  

Gate-Source Charge  

Gate-Drain Charge  

25  

5.5  

13.4  

nC  

nC  

nC  

g

DD  

GS  

D

gs  

gd  

SOURCE DRAIN DIODE  

Symbol  

Parameter  

Test Conditions  

Min.  

T

y

p.  

Max.  

Unit  

I

9

36  

A

A

Source-drain Current  

Source-drain Current (pulsed)  

SD  

(2)  

I

SDM  

V

(1)  

I

= 9 A, V

 

= 0  

Forward On Voltage  

1.6  

V

SD  

SD  

GS  

t

I

= 9 A, di/dt = 100A/µs  

= 40

V

, T

 

=

1

50°C  

Reverse Recovery Time  

Reverse Recovery Charge  

Reverse Recovery Current  

165  

0.9  

1

1

.2  

ns  

µC  

A

rr  

SD  

Q

rr  

RRM  

V

DD  

j

I

(see test circuit, Figure 5)  

Note: 1. Pulsed:

 

Pulse duration = 300 µs, duty cycle 1.5 %.  

2. Pulse

 

width limited by safe operating area.  

3. C  

V

is defined as a constant equivalent capacitance giving the same charging time as C  

when V

 

increases from 0 to 80%  

oss DS  

oss eq.  

.

DSS  

3/8  

STP12NK30Z  

Safe Operating Area For TO-220  

Thermal Impedance For TO-220  

Output Characteristics  

Transfer Characteristics  

Transconductance  

Static Drain-source On Resistance  

4/8  

STP12NK30Z  

Gate Charge vs Gate-source Voltage  

Capacitance Variations  

Normalized Gate Thereshold Voltage vs Temp.  

Normalized On Resistance vs Temperature  

Source-drain Diode Forward Characteristics  

Normalized BVDSS vs Temperature  

5/8  

STP12NK30Z  

Fig. 1:

Unclamped Inductive Load Test Circuit  

Fig. 2:

Unclamped Inductive Waveform  

Fig. 3:

Switching Times Test Circuit For  

Fig. 4:

Gate Charge test Circuit  

Resistive Load  

Fig. 5:

Test Circuit For Inductive Load Switching  

And Diode Recovery Times  

6/8  

STP12NK30Z  

TO-220 MECHANICAL DATA  

mm  

inch  

TYP.  

DIM.  

MIN.  

4.40  

1.23  

2.40  

TYP.  

MAX.  

4.60  

1.32  

2.72  

MIN.  

0.173  

0.048  

0.094  

MAX.  

0.181  

0.051  

0.107  

A

C

D

D1  

E

1.27  

0.050  

0.49  

0.61  

1.14  

1.14  

4.95  

2.4  

0.70  

0.88  

1.70  

1.70  

5.15  

2.7  

0.019  

0.024  

0.044  

0.044  

0.194  

0.094  

0.393  

0.027  

0.034  

0.067  

0.067  

0.203  

0.106  

0.409  

F

F1  

F2  

G

G1  

H2  

L2  

L4  

L5  

L6  

L7  

L9  

DIA.  

10.0  

10.40  

16.4  

0.645  

13.0  

2.65  

15.25  

6.2  

14.0  

2.95  

15.75  

6.6  

0.511  

0.104  

0.600  

0.244  

0.137  

0.147  

0.551  

0.116  

0.620  

0.260  

0.154  

0.151  

3.5  

3.93  

3.85  

3.75  

L2  

Dia.  

L5  

L9  

L7  

L6  

L4  

P011C  

7/8  

STP12NK30Z  

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the  

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from  

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications  

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information  

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or  

systems without express written approval of STMicroelectronics.  

© The ST logo is a registered trademark of STMicroelectronics  

© 2002 STMicroelectronics – Printed in Italy – All Rights Reserved  

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8/8