STMicroelectronics-STP14NF10

Part #STMicroelectronics-STP14NF10
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STMicroelectronics-STP14NF10
STP14NF10  
N-channel 100 V – 0.115
Ω
– 15 A – TO-220  
low gate charge S
T
r
ipFET™ II Power MOSFET  
Features  
Type  
V

DSS

R

DS(on)

max  
100 V
 
< 0.13
Ω  
I

D  

STP14NF10  
15 A  
■
Exceptional dv/dt capability  
■
100% avalanche tested  
3
2
1
■
Application oriented characterization  
TO-220  
Application  
■
Switching applications  
Description  
This Power MOSFET series realized with  
Figure 1.  
Internal schematic diagram  
STMicroelectronics unique S
T
r
ipFET™ process  
has specifically been designed to minimize input  
capacitance and gate charge. It is therefore  
suitable as primary switch in advanced high-  
efficienc
y
,
h
igh-frequency isolated DC-DC  
converters for telecom and computer applications.  
It is also intended for any applications with low  
gate drive requirements.  
Table 1.  
Order code  
STP14NF10  
Device summary  
Marking  
Package  
TO-220  
Packaging  
P14NF10  
T
u
be  
April 2008  
Rev 4  
1/12  
12  

STP14NF10  
Electrical ratings  
1
Electrical ratings  
Table 2.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
V

DS  

V

GS  

I

D  

Drain-source voltage (V

GS

= 0)  
Gate- source voltage  
100  
20  
15  
10  
60  
60  
0.4  
9
V
V
Drain current (continuous) at T

C

= 25 °C  
Drain current (continuous) at T

C

= 100 °C  
Drain current (pulsed)  
A
I

D  

A
(1)  
I

DM  

P

tot  

A
T
o
tal dissipation at T

C

= 25 °C  
Derating factor  
W
W/°C  
V/ns  
mJ  
dv/dt

(2)  

Peak diode recovery voltage slope  
Single pulse avalanche energy  
Storage temperature  
(3)  
E

AS  

70  
T

stg  

T

j  

-55 to 175  
175  
°C  
°C  
Max. operating junction temperature  
1. Pulse
 
width limited by safe operating area.  
2. I

SD

≤
14A, di/dt
 
≤
300A/µs, V

DD

≤
V

(BR)DSS

, Tj
 
≤
T

JMAX  

3. Starting
 
T

j

= 25 °C, I

D

= 15A, V

DD

= 50V  
Table 3.  
Symbol  
Thermal data  
Parameter  
Value  
Unit  
R

thj-case  

R

thj-amb  

T

J  

Thermal resistance junction-case max  
2.5  
62.5  
300  
°C/W  
°C/W  
°C  
Thermal resistance junction-ambient max  
Maximum lead temperature for soldering purpose  
3/12  

Electrical characteristics  
STP14NF10  
2
Electrical characteristics  
(T  
=25 °C unless otherwise specified)  
CASE  
Table 4.  
Symbol  
On/off states  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
Drain-source  
V

(BR)DSS  

I

D

= 250 µA, V

GS

=0  
100  
V
breakdown voltage  
V

DS

= max ratings  
Zero gate voltage  
1
µA  
µA  
I

DSS  

V

DS

= max ratings,  
T

C

= 125 °C  
drain current (V

GS

= 0)  
10  
Gate-body leakage  
current (V

DS

= 0)  
I

GSS  

V

GS  

V

DS

= V

GS

, I

D

= 250 µA  

GS

= 10
V
,
I

D

= 7 A  
=
20 V  
100  
4
nA  
V
V

GS(th)  

R

DS(on)  

Gate threshold voltage  
2
3
Static drain-source on  
resistance  
V
0.115  
0.13  
Ω
Table 5.  
Symbol  
Dynamic  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
Forward  
transconductance  
(1)  
g

fs  

V

DS

= 15
V
,
I

D

= 7 A  
20  
S
Input capacitance  
Output capacitance  
C

iss  

C

oss  

C

rss  

460  
70  
pF  
pF  
pF  
V

DS

= 25
V
, f = 1
M
Hz,  
V

GS

= 0  
Reverse transfer  
capacitance  
30  
t

d(on)  

t

r  

t

d(off)  

t

f  

T
u
rn-on delay time  
Rise time  
16  
25  
32  
8
ns  
ns  
ns  
ns  
V

DD

= 50
V
,
I

D

= 7 A  
R

G

= 4.7
Ω
V

GS

= 10 V  
(see

)  
T
u
rn-off delay time  
Fall time  
Q

g  

Q

gs  

Q

gd  

T
o
tal gate charge  
Gate-source charge  
Gate-drain charge  
V

DD

= 80
V
,
I

D

= 12 A,  
V

GS

= 10 V  
15.5  
3.7  
21  
nC  
nC  
nC  
(see

)  
4.7  
1. Pulsed:
 
Pulse duration = 300 µs, duty cycle 1.5%.  
4/12  

STP14NF10  
Electrical characteristics  
Table 6.  
Symbol  
Source drain diode  
Parameter  
Test conditions  
Min.  
Typ.  
Max. Unit  
Source-drain current  
I

SD  

15  
60  
A
A
Source-drain current  
(pulsed)  
(1)  
I

SDM  

(2)  
V

SD  

Forward on voltage  
I

SD

= 14 A, V

GS

= 0  
1.5  
V
I

SD

= 14 A,  
t

rr  

Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
90  
230  
5
ns  
nC  
A
di/dt = 100 A/µs,  
V

DD

= 50
V
,
T

j

= 150 °C  
(see

)  
Q

rr  

I

RRM  

1. Pulse
 
width limited by safe operating area.  
2. Pulsed:
 
Pulse duration = 300 µs, duty cycle 1.5%  
5/12  

Electrical characteristics  
STP14NF10  
2.1  
Electrical characteristics (curves)  
Figure 2.
 
Safe operating area  
Figure 3.
 
Thermal impedance  
Figure 4.
 
Output characteristics  
Figure 5.
 
Transfer characteristics  
Figure 6.
 
Transconductance  
Figure 7.
 
Static drain-source on resistance  
6/12  

STP14NF10  
Electrical characteristics  
Figure 8.
 
Gate charge vs gate-source voltage
 
Figure 9.
 
Capacitance variations  
Figure 10.
 
Normalized gate threshold voltage
 
Figure 11.
 
Normalized on resistance vs  
vs temperature  
temperature  
Figure 12.
 
Source-drain diode forward  
characteristics  
Figure 13.
 
Normalized B  
vs temperature  
VDSS  
7/12  

Test circuits  
STP14NF10  
3
Test circuits  
Figure 14.
 
Switching times test circuit for  
resistive load  
Figure 15.
 
Gate charge test circuit  
Figure 16.
 
Test circuit for inductive load  
switching and diode recovery times  
Figure 17.
 
Unclamped Inductive load test  
circuit  
Figure 18.
 
Unclamped inductive waveform  
Figure 19.
 
Switching time waveform  
8/12  

STP14NF10  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECO
P
A
CK®  
packages. These packages have a lead-free second level interconnect. The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECO
P
ACK is an ST trademark.  
ECO
P
ACK specifications are available at:

9/12  

Package mechanical data  
STP14NF10  
TO-220 mechanical data  
mm  
inch  
Typ  
Dim  
Min  
Typ  
Max  
Min  
Max  
A
b
4.40  
0.61  
1.14  
0.4
8
 
15.25  
4.60  
0.
88  
1.70  
0.70  
15.75  
0.17
3  
0.024  
0.044  
0.01
9  
0.6  
0.1
8
1  
0.0
3
4  
0.066  
0.027  
0.62  
b
1  
c
D
D1  
E
1.27  
0.050  
10  
10.40  
2.70  
5.15  
1.
3
2  
6.60  
2.72  
14  
0.
393  
0.0
9
4  
0.1
9
4  
0.04
8  
0.244  
0.0
9
4  
0.511  
0.1
3
7  
0.40
9  
0.106  
0.202  
0.051  
0.256  
0.107  
0.551  
0.154  
e
2.40  
4.
9
5  
1.2
3  
6.20  
2.40  
1
3  
e1  
F
H1  
J1  
L
L1  
L20  
L
3
0  
∅
P  
Q
3
.50  
3
.
93  
16.40  
0.645  
2
8
.
9
0  
1.1
3
7  
3
.75  
3
.
8
5  
2.
9
5  
0.147  
0.104  
0.151  
0.116  
2.65  
10/12  

STP14NF10  
Revision history  
5
Revision history  
Table 7.  
Date  
Document revision history  
Revision  
Changes  
05-Feb-2004  
21-Jun-2004  
19-Jun-2006  
20-Mar-2008  
1
2
3
4
First version  
Preliminary version  
New template, no content change  
Removed packages: D²
P
A
K and TO-220FP  
11/12  

STP14NF10  
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12/12