STMicroelectronics-STP23N80K5

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STMicroelectronics-STP23N80K5
STP23N80K5  
N-channel 800 V, 0.23
Ω typ., 16 A MDmesh™ K5  
Power MOSFET in a TO-220 package  
Datasheet – production data  
Features  
Order code  
V

DS  

R

DS(on)

max.  
I

D  

P

TOT  

STP23N80K5 800
 
V  
0.28
Ω  
16 A
 
190 W  
Industry’s lowest R

DS(on)

x area  
Industry’s best figure of merit (FoM)  
Ultra low gate charge  
100% avalanche tested  
Zener-protected  
Applications  
Switching applications  
Figure 1: Internal schematic diagram  
Description  
This very high voltage N-channel Power  
MOSFET is designed using MDmesh™ K5  
technology based on an innovative proprietary  
vertical structure. The result is a dramatic  
reduction in on-resistance and ultra-low gate  
charge for applications requiring superior power  
density and high efficiency.  
Table 1: Device summary  
Order code  
Marking  
Package  
Packing  
STP23N80K5  
23N80K5  
TO-220  
Tube  
October 2015  
DocID028451 Rev 1  
1/13  
This is information on a product in full production.  

STP23N80K5  
Electrical ratings  
1
Electrical ratings  
Table 2: Absolute maximum ratings  
Symbol  
Parameter  
Value  
±30  
16  
Unit  
V

GS  

Gate-source voltage  
V
Drain current (continuous) at T

case

= 25 °C  
Drain current (continuous) at T

case

= 100 °C  
Drain current (pulsed)  
I

D  

A
10  
64  
A
P

TOT  

T

stg  

Total dissipation at T

case

= 25 °C  
Peak diode recovery voltage slope  
MOSFET dv/dt ruggedness  
190  
4.5  
50  
W
V/ns  
°C  
Storage temperature  
-55 to 150  
T

j  

Operating junction temperature  
Notes:  

(1)

Pulse width is limited by safe operating area.  
(2)  
I
≤ 16 A, di/dt=100 A/μs; V

DS

peak < V

(BR)DSS

, V

DD

= 80% V

(BR)DSS

.  
SD  
(3)  
V
≤ 640 V  
DS  
Table 3: Thermal data  
Parameter  
Symbol  
R

thj-case  

R

thj-amb  

Value  
0.66  
30  
Unit  
Thermal resistance junction-case  
Thermal resistance junction-ambient  
°C/W  
Table 4: Avalanche characteristics  
Parameter  
Symbol  
Value  
5
Unit  
A
Avalanche current, repetitive or not repetitive  
Single pulse avalanche energy  
400  
mJ  
Notes:  

(1)

Pulse width limited by T

jmax  

(2)

starting T

j

= 25 °C, I

D

= I

AR

, V

DD

= 50 V.  
.
DocID028451 Rev 1  
3/13  
 
 
 
 
 

Electrical characteristics  
STP23N80K5  
2
Electrical characteristics  
(T

case

= 25 °C unless otherwise specified)  
Table 5: Static  
Test conditions  
Symbol  
Parameter  
Min. Typ. Max. Unit  
Drain-source breakdown  
voltage  
V

(BR)DSS  

V

GS

= 0 V, I

D

= 1 mA  
800  
V
V

GS

= 0 V, V

DS

= 800 V  
1
Zero gate voltage drain  
current  
I

DSS  

µA  
V

GS

= 0 V, V

DS

= 800 V,  
T

case

= 125 °C  
50  
I

GSS  

Gate-body leakage current
 
V

DS

= 0 V, V

GS

= ±20 V  
±10  
5
µA  
V
V

GS(th)  

Gate threshold voltage  
V

DS

= V

GS

, I

D

= 100 µA  
3
4
Static drain-source on-  
resistance  
R

DS(on)  

V

GS

= 10 V, I

D

= 8 A  
0.23 0.28  
Ω
Table 6: Dynamic  
Test conditions  
Symbol  
C

iss  

Parameter  
Input capacitance  
Output capacitance  
Min. Typ. Max. Unit  
–
–
1000  
65  
–
–
C

oss  

V

DS

= 100 V, f = 1 MHz,  
V

GS

= 0 V  
pF  
pF  
Reverse transfer  
capacitance  
C

rss  

–
–
–
1.5  
165  
59  
–
–
–
Equivalent output  
capacitance  
C

O(tr

V

DS

= 0 to 640 V, V

GS

= 0 V  
Equivalent output  
capacitance  
C

O(er

V

DS

= 0 to 640 V, V

GS

= 0 V  
f = 1 MHz, I

D

= 0 A  
R

G  

Q

g  

Intrinsic gate resistance  
Total gate charge  
–
–
–
–
4.7  
33  
6
–
–
–
–
Ω
V

DD

= 640 V, I

D

= 16 A,  
V

GS

= 10 V (see

Q

gs  

Q

gd  

Gate-source charge  
Gate-drain charge  
nC  
25  
Notes:  

(1)

Time related is defined as a constant equivalent capacitance giving the same charging time as C

OSS

when V

DS  

increases from 0 to 80% V

DSS  

.

(2)

Energy related is defined as a constant equivalent capacitance giving the same stored energy as C

OSS

when  
V

DS

increases from 0 to 80% V

DSS  

Table 7: Switching times  
Symbol  
t

d(on)  

t

r  

Parameter  
Turn-on delay time  
Rise time  
Test conditions  
Min. Typ. Max. Unit  
V

DD

= 400 V, I

D

= 8 A  
–
–
–
14  
9
–
–
–
R

G

= 4.7
Ω, V

GS

= 10 V (see  
ns  
t

d(off)  

Turn-off delay time  
48  
t

f  

Fall time  
–
9
–
4/13  
DocID028451 Rev 1  
 
 

STP23N80K5  
Electrical characteristics  
Min. Typ. Max. Unit  
Table 8: Source-drain diode  
Test conditions  
Symbol  
I

SD  

Parameter  
Source-drain current  
–
–
16  
64  
A
A
Source-drain current  
(pulsed)  
t

rr  

Forward on voltage  
V

GS

= 0 V, I

SD

= 16 A  
–
–
–
1.5  
V
Reverse recovery time  
Reverse recovery charge  
I

SD

= 16 A, di/dt = 100 A/µs,  
V

DD

= 60 V (see

410  
7
ns  
µC  
Q

rr  

I

RRM  

Reverse recovery current  
–
34  
A
t

rr  

Reverse recovery time  
I

SD

= 16 A, di/dt = 100 A/µs,  
V

DD

= 60 V, T

j

= 150 °C (see  
–
–
650  
10  
ns  
Q

rr  

Reverse recovery charge  
µC  
I

RRM  

Reverse recovery current  
–
32  
A
Notes:  

(1)

Pulse width is limited by safe operating area.  

(2)

Pulse test: pulse duration = 300 µs, duty cycle 1.5%.  
Table 9: Gate-source Zener diode  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
±30  
V

(BR)GSO

Gate-source breakdown voltage  
I

GS

= ±1 mA, I

D

= 0 A  
–
–
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD  
performance of the device. The Zener voltage facilitates efficient and cost-effective device  
integrity protection, thus eliminating the need for additional external componentry.  
DocID028451 Rev 1  
5/13  
 
 

Electrical characteristics  
STP23N80K5  
2.1  
Electrical characteristics (curves)  
Figure 2: Safe operating area  
Figure 3: Thermal impedance  
K
δ=0.5  
0.2  
0.1  
10

-1  

0.05  
0.02  
Z
= K*R  
thj-c  
p
th  
δ= t
 
/
Ƭ  
0.01  
Single pulse  
t
p
Ƭ
10

-2  

10

-5  

10

-4  

10

-3  

10

-2  

10

-1  

t

P

(s)  
Figure 4: Output characteristics  
Figure 5: Transfer characteristics  
Figure 6: Gate charge vs gate-source voltage  
Figure 7: Static drain-source on-resistance  
6/13  
DocID028451 Rev 1  

STP23N80K5  
Electrical characteristics  
Figure 9: Normalized gate threshold voltage  
vs temperature  
Figure 8: Capacitance variations  
Figure 10: Normalized on-resistance vs  
temperature  
Figure 11: Normalized V(BR)DSS vs  
temperature  
Figure 12: Maximum avalanche energy vs temperature  
DocID028451 Rev 1  
7/13  

Test circuits  
STP23N80K5  
3
Test circuits  
Figure 13: Test circuit for resistive load  
switching times  
Figure 14: Test circuit for gate charge  
behavior  
Figure 15: Test circuit for inductive load  
switching and diode recovery times  
Figure 16: Unclamped inductive load test  
circuit  
Figure 18: Switching time waveform  
Figure 17: Unclamped inductive waveform  
8/13  
DocID028451 Rev 1  

STP23N80K5  
Package information  
4
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®  

specifications, grade definitions and product status are available at:

.  
ECOPACK

®

is an ST trademark.  
DocID028451 Rev 1  
9/13  

Package information  
STP23N80K5  
4.1  
TO-220 package information  
Figure 19: TO-220 type A package outline  
10/13  
DocID028451 Rev 1  

STP23N80K5  
Package information  
Table 10: TO-220 type A mechanical data  
mm  
Dim.  
Min.  
4.40  
0.61  
1.14  
0.48  
15.25  
Typ.  
Max.  
4.60  
0.88  
1.70  
0.70  
15.75  
A
b
b1  
c
D
D1  
E
1.27  
10  
10.40  
2.70  
5.15  
1.32  
6.60  
2.72  
14  
e
2.40  
4.95  
1.23  
6.20  
2.40  
13  
e1  
F
H1  
J1  
L
L1  
L20  
L30  
øP  
Q
3.50  
3.93  
16.40  
28.90  
3.75  
2.65  
3.85  
2.95  
DocID028451 Rev 1  
11/13  

Revision history  
STP23N80K5  
5
Revision history  
Table 11: Document revision history  
Revision  
Date  
Changes  
First release.  
06-Oct-2015  
1
12/13  
DocID028451 Rev 1  

STP23N80K5  
IMPORTANT NOTICE
–
PLEASE READ CAREFULLY  
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, and  
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der  
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design of Purchasers’ products.  
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2015 STMicroelectronics
–
All rights reserved  
DocID028451 Rev 1  
13/13