STMicroelectronics-STP5N105K5
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STP5N105K5
N-
channel 1050 V, 2.9 Ω typ., 3 A MDmesh™ K5
Power MOSFET in a TO-220 package
Datasheet – production data
Features
Order code
V
DS
R
DS(on)
max.
I
D
P
TOT
STP5N105K5 1050
V
3.5 Ω
3 A
85 W
Worldwide best FOM (figure of merit)
Ultra low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Figure 1: Internal schematic diagram
Description
D(2, TAB)
This N-channel Zener-protected Power MOSFET
is
designed using ST’s revolutionary avalanche
–
rugged very high voltage MDmesh™ K5
technology, based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance, and ultra-low gate
charge for applications which require superior
power density and high efficiency.
G(1)
Table 1: Device summary
Order code
Marking
Package
Packaging
STP5N105K5
5N105K5
TO-220
Tube
S(3)
AM01476v1
October 2014
DocID026703 Rev 3
1/14
This is information on a product in full production.
Contents
STP5N105K5
Contents
2/14
DocID026703 Rev 3
STP5N105K5
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
± 30
3
Unit
V
V
GS
I
D
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
A
I
D
2
A
12
85
1
A
P
TOT
I
AR
Total dissipation at T
C
= 25 °C
W
A
Max current during repetitive or single pulse avalanche
Single pulse avalanche energy
E
AS
85
mJ
(starting T
J
= 25 °C, I
D
=I
AS
, V
DD
= 50 V)
T
j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature
Storage temperature
4.5
50
V/ns
V/ns
– 55 to 150
°C
T
stg
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
≤ 3 A, di/dt ≤ 100 A/µs, V
DS(peak)
≤ V
(BR)DSS
≤ 840 V
SD
(3)
V
DS
Table 3: Thermal data
Parameter
Symbol
R
thj-case
R
thj-amb
Value
1.47
Unit
Thermal resistance junction-case max
Thermal resistance junction-amb max
°C/W
°C/W
62.5
DocID026703 Rev 3
3/14
Electrical characteristics
STP5N105K5
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified).
Table 4: On/off states
Test conditions
Symbol
Parameter
Min. Typ. Max. Unit
Drain-source breakdown
voltage
V
(BR)DSS
V
GS
= 0, I
D
= 1 mA
1050
V
V
GS
= 0, V
DS
= 1050 V
1
µA
µA
Zero gate voltage drain
current
I
DSS
V
GS
= 0, V
DS
= 1050 V,
Tc=125 °C
50
I
GSS
Gate body leakage current
Gate threshold voltage
V
DS
= 0, V
GS
= ± 20 V
V
DS
= V
GS
, I
D
= 100 µA
±10
5
µA
V
V
GS(th)
3
4
Static drain-source on-
resistance
R
DS(on)
V
GS
= 10 V, I
D
= 1.5 A
2.9
3.5
Ω
Table 5: Dynamic
Test conditions
Symbol
C
iss
Parameter
Input capacitance
Min. Typ. Max. Unit
–
–
–
210
16
–
–
–
pF
pF
pF
V
DS
=100 V, f=1 MHz,
V
GS
=0
C
oss
Output capacitance
C
rss
Reverse transfer capacitance
0.5
Equivalent capacitance time
related
–
–
26
10
–
–
pF
pF
V
GS
= 0, V
DS
= 0 to 840 V
f = 1MHz open drain
Equivalent capacitance
energy related
R
G
Q
g
Intrinsic gate resistance
Total gate charge
–
–
–
9
12.5
2
–
–
–
Ω
V
DD
= 840 V, I
D
= 3 A
V
GS
=10 V
nC
nC
Q
gs
Gate-source charge
Q
gd
Gate-drain charge
–
9.5
–
nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
oss
when V
DS
increases from 0 to 80% V
DSS
Table 6: Switching times
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Turn-on delay
time
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
15.5
8.5
31
–
–
–
–
ns
ns
ns
ns
V
DD
= 525V, I
D
= 1.5 A, R
G
=4.7 Ω,
V
GS
=10 V
Rise time
Turn-off delay
time
Fall time
24
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DocID026703 Rev 3
STP5N105K5
Symbol
Electrical characteristics
Min. Typ. Max. Unit
Table 7: Source drain diode
Test conditions
Parameter
Source-drain
current
I
SD
–
3
A
A
Source-drain
current (pulsed)
I
SDM
12
1.5
Forward on
voltage
t
rr
I
SD
= 3 A, V
GS
=0
–
–
–
–
–
–
–
V
Reverse recovery
time
400
2.3
12
ns
µC
A
I
SD
= 3 A, V
DD
= 60 V
di/dt = 100 A/µs,
Reverse recovery
charge
Q
rr
I
RRM
t
rr
Reverse recovery
current
Reverse recovery
time
I
SD
= 3 A,V
DD
= 60 V
di/dt=100 A/µs,
Tj=150 °C
560
3.1
11
ns
µC
A
Reverse recovery
charge
Q
rr
I
RRM
Reverse recovery
current
Notes:
(1)
Pulsed: pulse duration = 300µs, duty cycle 1.5%
Table 8: Gate-source Zener diode
Symbol
Parameter
Test conditions
Min
30
Typ.
Max.
Unit
V
(BR)GSO
Gate-source breakdown voltage
I
GS
= ± 1mA, I
D
=0
–
–
V
The built-in back-to-back Zener diodes have specifically been designed to enhance the
device’s ESD capability. In this respect the Zener voltage is appropriate to achieve an
efficient and cost-effective intervention to protect the device’s integrity. These integrated
Zener diodes thus avoid the usage of external components.
DocID026703 Rev 3
5/14
Electrical characteristics
STP5N105K5
2.1
Electrical characteristics (curves)
Figure 3: Thermal impedance
Figure 2: Safe operating area
GIPD0309201
4
1
1
36FSR
I
D
(A)
10
1
100µs
1ms
10ms
0.1
Tj=150°C
Tc=25°C
Single pulse
0.01
10
V
DS
(V)
1000
0.1
1
100
Figure 4: Output characteristics
Figure 5: Transfer characteristics
GIPG290820141204FSR
GIPG290820141334FSR
I
D
I
D
(A)
6
(A)
V
DS
=20V
5
4
3
2
V
G
S
=10, 11V
5
4
3
2
1
9V
8V
1
0
7V
6V
0
6
V
DS
(V)
9
7
8
V
G
S
(V)
5
10
0
5
10
15
20
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
GIPG290820141348FSR
V
GS
GIPG290820141400FSR
V
DS
(V)
R
DS(on)
(V)
(
Ω
)
V
DS
=840V
I
D
=3A
V
G
S
=10V
4
1200
10
8
V
DS
3.5
3
800
600
400
200
6
2.5
4
2
2
0
1.5
1
0
0
2
4
6
8
10
12
Q
g
(nC)
0
1
2
3
4
I
D
(A)
6/14
DocID026703 Rev 3
STP5N105K5
Electrical characteristics
Figure 9: Source-drain diode forward
Figure 8: Capacitance variations
C
(pF)
GIPG290820141409FSR
characteristics
GIPG290820141432FSR
(V)
1
V
SD
1000
100
10
T
J
=-50°C
Ciss
0.9
T
J
=25°C
0.8
0.7
Coss
Crss
1
T
J
=150°C
0.6
0.5
0.1
0.1
100
1
10
V
DS
(V)
0
0.5
1
1.5
2
I
SD
(A)
2.5
3
Figure 11: Normalized on-resistance vs
temperature
Figure 10: Normalized gate threshold
voltage vs temperature
AM18082v1
V
GS(th)
(norm)
I
D
=100 µ A
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
-100
-50
0
50
100
T
J
(°C)
150
Figure 12: Normalized V(BR)DSS vs
temperature
Figure 13: Maximum avalanche energy
GIPG290820141445FSR
E
AS
(mJ)
AM18083v1
V
(BR)DSS
(norm)
80
70
60
50
40
I
D
=1
m
A
1.1
1.05
1
30
20
0.95
0.9
10
0
0.85
0
120
20 40 60 80
100
140 T
J
(°C)
-100
-50
0
50
100
T
J
(°C)
DocID026703 Rev 3
7/14
Electrical characteristics
STP5N105K5
Figure 14: Output capacitance stored energy vs temperature
GIPG290820141419FSR
E
oss
(µJ)
4
2
0
200
400
600
800
V
DS
(V)
0
8/14
DocID026703 Rev 3
STP5N105K5
Test circuits
3
Test circuits
Figure 15: Switching times test circuit for
resistive load
Figure 16: Gate charge test circuit
Figure 17:
Test circuit for inductive load
switching and diode recovery times
Figure 18:
Unclamped inductive load test
circuit
Figure 19:
Unclamped inductive waveform
Figure 20:
Switching time waveform
DocID026703 Rev 3
9/14
Package mechanical
data
STP5N105K5
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
10/14
DocID026703 Rev 3
STP5N105K5
Package mechanical
data
4.1
TO-220 package mechanical data
Figure 21: TO-220 type A package outline
DocID026703 Rev 3
11/14
Package mechanical
data
STP5N105K5
Table 9: TO-220 type A mechanical data
mm
Dim.
Min.
Typ.
Max.
A
b
4.40
4.60
0.88
1.70
0.70
15.75
0.61
1.14
b1
c
0.48
D
15.25
D1
E
1.27
10
10.40
2.70
5.15
1.32
6.60
2.72
14
e
2.40
4.95
1.23
6.20
2.40
13
e1
F
H1
J1
L
L1
L20
L30
ÆP
Q
3.50
3.93
16.40
28.90
3.75
2.65
3.85
2.95
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DocID026703 Rev 3
STP5N105K5
Revision history
5
Revision history
Table 10: Document revision history
Changes
Date
Revision
17-Jul-2014
1
First release.
Document status promoted from preliminary to production data.
Minor text changes.
03-Sep-2014
15-Oct-2014
2
3
DocID026703 Rev 3
13/14
STP5N105K5
IMPORTANT NOTICE
–
PLEASE READ CAREFULLY
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, and
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der
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics
–
All rights reserved
14/14
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