STMicroelectronics-STQ2LN60K3-AP

Part #STMicroelectronics-STQ2LN60K3-AP
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STMicroelectronics-STQ2LN60K3-AP
STQ2LN60K3-AP  
N-
channel 600 V, 4 Ω typ., 0.6 A MDmesh™ K3  
Power MOSFET in a TO-92 package  
Datasheet – production data  
Features  
R

DS(on)  

max  
P

TOT  

Order code  
V

DS  

I

D  

2.5 W  
STQ2LN60K3-AP  
600 V  
4.5 Ω  
0.6 A  
3
100% avalanche tested  
Extremely high dv/dt capability  
Very low intrinsic capacitance  
Improved diode reverse recovery  
characteristics  
2
1
TO-92 ammopack  
Zener-protected  
Figure 1: Internal schematic diagram  
Applications  
D(2)  
Switching applications  
Description  
This MDmesh™ K3 Power MOSFET is the result  
of improvements applied to STMicroelectronics’  
MDmesh™ technology, combined with a new  
optimized vertical structure. This device boasts  
an extremely low on-resistance, superior dynamic  
performance and high avalanche capability,  
rendering it suitable for the most demanding  
applications.  
G(1)  
S(3)  
AM15572v1_no_tab  
Table 1: Device summary  
Order code  
Marking  
Package  
Packaging  
STQ2LN60K3-AP  
2LN60K3  
TO-92  
Ammopack  
February 2017  
DocID023499 Rev 3  
1/13  
This is information on a product in full production.  

STQ2LN60K3-AP  
Electrical ratings  
1
Electrical ratings  
Table 2: Absolute maximum ratings  
Symbol  
V

DS  

V

GS  

I

D  

Parameter  
Value  
600  
±30  
0.6  
Unit  
V
Drain-source voltage  
Gate-source voltage  
V
Drain current (continuous) at T

C

= 25 °C  
Drain current (continuous) at T

C

= 100 °C  
Drain current (pulsed)  
A
I

D  

0.38  
2.4  
A
I

DM  

A
P

TOT  

T

stg  

Total dissipation at T

C

= 25 °C  
Peak diode recovery voltage slope  
Storage temperature range  
2.5  
W
V/ns  
12  
-55 to 150  
°C  
T

j  

Operating junction temperature range  
Notes:  

(1)

Pulse width limited by safe operating area.  
(2)  
I
≤ 2 A, di/dt ≤ 400 A/µs, V

DS(peak)

< V

(BR)DSS  

SD  
Table 3: Thermal data  
Parameter  
Symbol  
R

thj-case  

R

thj-amb  

Value  
50  
Unit  
°C/W  
°C/W  
Thermal resistance junction-case  
Thermal resistance junction-ambient  
120  
Table 4: Avalanche characteristics  
Parameter  
Single pulse avalanche current  
(pulse width limited by T

jmax  

Symbol  
Value  
Unit  
I

AS  

2
A
)
Single pulse avalanche energy  
E

AS  

80  
mJ  
(starting T

J

=25 °C, I

D

=I

AR

, V

DD

=50 V)  
DocID023499 Rev 3  
3/13  
 
 

Electrical characteristics  
STQ2LN60K3-AP  
2
Electrical characteristics  
(T

CASE

= 25 °C unless otherwise specified)  
Table 5: On/off states  
Symbol  
Parameter  
Drain-source  
Test conditions  
I

D

= 1 mA, V

GS

= 0 V  
V

GS

= 0 V, V

DS

= 600 V  
Min. Typ. Max. Unit  
V

(BR)DSS  

600  
V
breakdown voltage  
1
Zero gate voltage drain  
current  
I

DSS  

µA  
V

GS

= 0 V, V

DS

= 600 V,  
T

C

= 125

50  
I

GSS  

Gate-body leakage current  
Gate threshold voltage  
V

DS

= 0 V, V

GS

= ±20 V  
V

DS

= V

GS

, I

D

= 50 µA  
±10  
4.5  
µA  
V
V

GS(th)  

3
3.75  
4
Static drain-source on-  
resistance  
R

DS(on)  

V

GS

= 10 V, I

D

= 1 A  
4.5  
Ω
Notes:  

(1)

Defined by design, not subject to production test.  
Table 6: Dynamic  
Test conditions  
Symbol  
C

iss  

Parameter  
Input capacitance  
Output capacitance  
Min. Typ. Max. Unit  
–
–
235  
22  
–
–
pF  
pF  
V

DS

= 50 V, f = 1 MHz,  
V

GS

= 0 V  
C

oss  

Reverse transfer  
capacitance  
C

rss  

–
–
–
3.5  
14  
10  
–
–
pF  
pF  
pF  
Eq. capacitance time  
related  
C

o(tr

V

GS

= 0 V, V

DS

= 0 to 480 V  
V

DD

= 480 V, I

D

= 1 A,  
Eq. capacitance energy  
related  
C

o(er

Q

g  

Total gate charge  
–
–
12  
–
–
nC  
nC  
V

GS

= 0 to 10 V  
Q

gs  

Gate-source charge  
1.8  
Q

gd  

R

G  

Gate-drain charge  
–
–
7.7  
7
–
–
nC  
Gate input resistance  
f=1 MHz, I

D

=0 A  
Ω
Notes:  
(1)  
C
oss eq.  
time related is defined as a constant equivalent capacitance giving the same charging time as C

oss

when  
V

DS

increases from 0 to 80% V

DSS  

(2)  
C
oss eq.  
energy related is defined as a constant equivalent capacitance giving the same stored energy as C

oss  

when V

DS

increases from 0 to 80% V

DSS  

4/13  
DocID023499 Rev 3  
 
 
 

STQ2LN60K3-AP  
Electrical characteristics  
Min. Typ. Max. Unit  
Table 7: Switching times  
Test conditions  
Symbol  
t

d(on)  

t

r  

Parameter  
Turn-on delay time  
Rise time  
V

DD

= 300 V, I

D

= 1 A,  
–
–
–
10  
8.5  
–
–
–
ns  
ns  
ns  
R

G

= 4.7 Ω, V

GS

= 10 V  
t

d(off)  

Turn-off delay time  
23.5  
t

f  

Fall time  
–
21  
–
ns  
Table 8: Source-drain diode  
Test conditions  
Symbol  
Parameter  
Min. Typ. Max. Unit  
Source-drain current  
–
–
0.6  
2.4  
1.5  
A
Source-drain current  
(pulsed)  
A
Forward on voltage  
I

SD

= 2 A, V

GS

= 0 V  
–
–
–
V
t

rr  

Reverse recovery time  
Reverse recovery charge  
I

SD

= 2 A, di/dt = 100 A/µs  
200  
800  
ns  
V

DD

= 60 V  
Q

rr  

nC  
I

RRM  

Reverse recovery current  
–
8
A
t

rr  

Reverse recovery time  
I

SD

= 2 A, di/dt = 100 A/µs  
–
–
230  
950  
ns  
V

DD

= 60 V, T

j

= 150 °C  
Q

rr  

Reverse recovery charge  
nC  
I

RRM  

Reverse recovery current  
–
8.5  
A
Notes:  

(1)

Pulse width limited by safe operating area.  

(2)

Pulsed: pulse duration = 300 µs, duty cycle 1.5%  
Table 9: Gate-source Zener diode  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
30  
V

(BR)GSO

Gate-source breakdown voltage  
I

GS

= ±1 mA, I

D

= 0 A  
–
–
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD  
performance of the device. The Zener voltage facilitates efficient and cost-effective device  
integrity protection,thus eliminating the need for additional external componentry.  
DocID023499 Rev 3  
5/13  
 
 

Electrical characteristics  
STQ2LN60K3-AP  
2.1  
Electrical characteristics (curves)  
Figure 2: Safe operating area  
Figure 3: Thermal impedance  
Figure 4: Output characteristics  
Figure 5: Transfer characteristics  
AM13054v1  
AM13055v1  
I
D  
I
D  
(A)  
(A)  
V
GS
=10V  
V
DS
=15V  
2.5  
2.0  
2.0  
1.5  
1.0  
6V  
1.5  
1.0  
0.5  
0
0.5  
0
5V  
2
8
V
GS
(V)  
8
V
DS
(V)  
0
4
6
0
2
4
6
Figure 6: Gate charge vs gate-source voltage  
Figure 7: Static drain-source on-resistance  
AM13057v1  
AM13056v1  
V
GS  
(V)  
R
DS(on)  
V
DS  
(V)  
(
W
)  
V
DD
=480V  
I
D
=2A  
V
GS
=10V  
12  
10  
8
4.2  
500  
400  
300  
200  
100  
V
DS  
4.0  
3.8  
3.6  
3.4  
6
4
2
0
3.2  
3.0  
0
1.0 1.2  
0.4 0.6
0.8  
0.2  
I
D
(A)  
10  
0
Q
g
(nC)  
0
5
6/13  
DocID023499 Rev 3  
 

STQ2LN60K3-AP  
Figure 8: Capacitance variations  
Electrical characteristics  
Figure 9: Source-drain diode forward characteristics  
AM13058v1  
AM13063v1  
C
(pF)  

V
SD

(V)  
T
J
=-50°C  
0.9  
T
J
=25°C  
0.8  
Ciss  
0.7  
100  
T
J
=150°C  
0.6  
0.5  
0.4  
0.3  
0.2  
10  
Coss  
Crss  
0.1  
0
1
0.1  
100  
0
1
10  
V
DS
(V)  
1
2
3
4
5
I
SD
(A)  
Figure 10: Normalized gate threshold voltage vs  
temperature  
Figure 11: Normalized on-resistance vs temperature  
AM13060v1  
AM13061v1  
V
GS(th)  
(norm)  
R
DS(on)  
(norm)  
I
D
=1A  
I
D
=50µA  
V
GS
=10V  
2.5  
1.10  
1.00  
0.90  
2.0  
1.5  
1.0  
0.80  
0.70  
0.5  
0
-75  
-75  
-25  
25  
75  
T
J
(°C)  
-25  
25  
75  
T
J
(°C)  
125  
125  
Figure 12: Normalized V

(BR)DSS

vs temperature  
Figure 13: Output capacitance stored energy  
AM13059v1  
AM13062v1  
E
oss  
(µJ)  
V
(BR)DSS  
(norm)  
I
D
=1mA  
1.10  
1.05  
1.5  
1
1.00  
0.5  
0
0.95  
0.90  
200  
400 500  
600 V
DS
(V)  
0
100  
300  
-75  
-25  
25  
75  
T
J
(°C)  
125  
DocID023499 Rev 3  
7/13  

Electrical characteristics  
STQ2LN60K3-AP  
Figure 14: Maximum avalanche energy vs temperature  
AM13064v1  
E
AS
(mJ)  
90  
I
D
=2 A  
V
DD
=50 V  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
20  
40  
60 80
 
100  
120  
140
T
J
(°C)  
8/13  
DocID023499 Rev 3  

STQ2LN60K3-AP  
Test circuits  
3
Test circuits  
Figure 15: Test circuit for resistive load  
switching times  
Figure 16: Test circuit for gate charge  
behavior  
Figure 17: Test circuit for inductive load  
switching and diode recovery times  
Figure 18: Unclamped inductive load test  
circuit  
Figure 19: Unclamped inductive waveform  
Figure 20: Switching time waveform  
DocID023499 Rev 3  
9/13  

Package information  
STQ2LN60K3-AP  
4
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®  

specifications, grade definitions and product status are available at:

.  
ECOPACK

®

is an ST trademark.  
4.1  
TO-92 ammopack package information  
Figure 21: TO-92 ammopack package outline  
T
A1  
T2  
T1  
H1  
delta H  
W2  
H
H3  
H0  
d
L
l1  
W
W0  
W1  
F1 F2  
F3  
D0  
t
P2  
P0  
0050910_Rev_22  
10/13  
DocID023499 Rev 3  

STQ2LN60K3-AP  
Package information  
Table 10: TO-92 ammopak mechanical data  
mm  
Dim.  
Min.  
Typ.  
Max.  
4.80  
3.80  
1.60  
2.30  
0.48  
12.90  
7.05  
2.94  
5.48  
2.00  
19.00  
6.50  
9.25  
0.50  
21.00  
18.20  
27.00  
2.00  
4.20  
0.90  
11.00  
A1  
T
T1  
T2  
d
0.45  
12.50  
5.65  
2.40  
4.98  
-2.00  
17.50  
5.50  
8.50  
0.47  
12.70  
6.35  
2.50  
5.08  
P0  
P2  
F1, F2  
F3  
delta H  
W
18.00  
6.00  
9.00  
W0  
W1  
W2  
H
18.50  
16.00  
25.00  
1.00  
H0  
H1  
H3  
D0  
t
15.50  
0.50  
3.80  
4.00  
L
I1  
3.00  
delta P  
-1.00  
1.00  
DocID023499 Rev 3  
11/13  

Revision history  
STQ2LN60K3-AP  
5
Revision history  
Table 11: Document revision history  
Changes  
Date  
Revision  
19-Jul-2012  
1
First release.  
Modified title, features and description on cover page  
Modified
Table 2: “Absolute maximum ratings”, Table 5: “On/off states”  
and
Table 9: “Gate-source Zener diode”  
24-Jan-2017  
01-Feb-2017  
2
3
Modified:
Figure 11: “Normalized on-resistance vs temperature”  
Updated
Section 4.1: “TO-92 ammopack package information”  
Minor text changes  
Minor text changes.  
12/13  
DocID023499 Rev 3  

STQ2LN60K3-AP  
IMPORTANT NOTICE
–
PLEASE READ CAREFULLY  
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications
, and  
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST  
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of or
der  
acknowledgement.  
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the  
design of Purchasers’ products.  
No license, express or implied, to any intellectual property right is granted by ST herein.  
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2017 STMicroelectronics
–
All rights reserved  
DocID023499 Rev 3  
13/13