STMicroelectronics-STS1NK60Z

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STMicroelectronics-STS1NK60Z
STS1NK60Z  
N-CHANNEL 600V – 13
Ω
– 0.25A – SO-8  
Zener-Protected SuperMESH™ Power MOSFET  
TYPE  
V
DSS  
R
I
D
Pw  
DS(on)  
STS1NK60Z  
600 V  
< 15
Ω  
0.25 A  
2 W  
TYPICAL R
 
(on) = 13
Ω  
DS  
EXTREMELY HIGH dv/dt CAPABILITY  
ESD IMPROVED CAPABILITY  
100% AVALANCHE TESTED  
NEW HIGH VOLTAGE BENCHMARK  
GATE CHARGE MINIMIZED  
SO-8  
DESCRIPTION  
The SuperMESH™ series is obtained through an  
extreme optimization of ST’s well established strip-  
based PowerMESH™ layout. In addition to pushing  
on-resistance significantly down, special care is tak-  
en to ensure a very good dv/dt capability for the  
most demanding applications. Such series comple-  
ments ST full range of high voltage MOSFE
T
s
i
n-  
cluding revolutionary MDmesh™ products.  
INTERNAL SCHEMATIC DIAGRAM  
APPLICATIONS  
AC ADAPTORS AND BATTERY CHARGERS  
SWITH MODE POWER SUPPLIES (SMPS)  
ORDERING INFORMATION  
SALES TYPE  
MARKING  
PACKAGE  
SO-8  
P
A
CKAGING  
STS1NK60Z  
S1NK60Z  
T
A
PE & REEL  
June 2003  
1/8  

STS1NK60Z  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
600  
600  
± 30  
0.25  
0.16  
1
Unit  
V
V
DS  
Drain-source Voltage (V
 
= 0)  
GS  
V
Drain-gate Voltage (R
 
= 20 k
Ω
)  
V
DGR  
GS  
V
Gate- source Voltage  
V
GS  
I
Drain Current (continuous) at T
 
= 25°C  
A
D
C
I
Drain Current (continuous) at T
 
= 100°C  
A
D
C
I
( )  
Drain Current (pulsed)  
A
DM  
P
TOT  
Total Dissipation at T
 
= 25°C  
2
W
C
Derating Factor  
0.016  
800  
4.5  
W/°C  
V
V
Gate source ESD(HBM-C=100p
F
,
R
=1.5K
Ω)  
Peak Diode Recovery voltage slope  
ESD(G-S)  
dv/dt (1)  
V/ns  
T
T
stg  
-55 to 150  
-55 to 150  
Operating Junction
T
e
mperature  
Storage
T
e
mperature  
°C  
°C  
j
( )
 
Pulse width limited by safe operating area  
(1) I
 
≤
0.3A, di/dt
≤
200A/µs, V
 
≤
V  
, T
 
≤
T  
j JMAX.  
SD  
DD  
(BR)DSS  
THERMAL DATA  
Rthj-amb  
Thermal Resistance Junction-ambient Max  
62.5  
°C/W  
GATE-SOURCE ZENER DIODE  
Symbol  
BV  
Parameter  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
Gate-Source Breakdown  
Voltage  
Igs=± 1mA (Open Drain)  
30  
V
GSO  
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES  
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s  
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be  
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and  
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the  
usage of external components.  
2/8  

STS1NK60Z  
ELECTRICAL CHARACTERISTICS
(T  
=25°C UNLESS OTHERWISE SPECIFIED)  
CASE  
ON/OFF  
Symbol  
Parameter  
Drain-source  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
V
I
= 1 mA, V
 
= 0  
600  
V
(BR)DSS  
D
GS  
Breakdown Voltage  
I
Zero Gate Voltage  
V
V
= Max Rating  
= Max Rating, T
 
= 125 °C  
1
50  
µA  
µA  
DSS  
DS  
DS  
Drain Current (V
 
= 0)  
GS  
C
I
Gate-body Leakage  
V
= ± 20V  
±10  
µA  
GSS  
GS  
Current (V
 
= 0)  
DS  
V
V
V
= V
 
, I
 
= 50 µA  
Gate Threshold Voltage  
3
3.75  
13  
4.5  
15  
V
GS(th)  
DS  
GS  
GS  
D
R
Static Drain-source On  
Resistance  
= 10
V
, I
 
=
0
.4 A  
Ω
DS(on)  
D
DYNAMIC  
Symbol  
Parameter  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
g
(1)  
Forward Transconductance  
V
V
= V
 
I =
 
0.4 A  
0.5  
S
fs  
DS  
, D  
C
C
C
Input Capacitance  
Output Capacitance  
Reverse Transfer  
Capacitance  
V
= 25V, f = 1 MHz, V
 
= 0  
94  
17.6  
2.8  
pF  
pF  
pF  
iss  
DS  
GS  
oss  
rss  
C
(3) Equivalent
 
Output  
Capacitance  
= 0V, V
 
= 0V to 480V  
11  
pF  
oss eq.  
GS  
DS  
SWITCHING ON  
Symbol  
Parameter  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
t
Turn-on Delay Time  
Rise Time  
V
R
= 300
V
, I
 
= 0.4 A  
= 4.7
Ω
V =
 
10 V  
GS  
5.5  
5
ns  
ns  
d(on)  
DD  
D
t
r
G
(Resistive Load see, Figure 3)  
Q
V
V
= 480
V
, I
 
= 0.8 A,  
= 10V  
6.9  
nC  
nC  
nC  
T
o
tal Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
4.9  
1
2.7  
g
DD  
GS  
D
Q
gs  
gd  
Q
SWITCHING OFF  
Symbol  
Parameter  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
t
Turn-off Delay Time  
Fall Time  
V
= 300
V
, I
 
=
0
.4A  
13  
28  
ns  
ns  
d(off)  
DD  
D
t
f
R =
 
4.7
Ω
V =
 
10 V  
G GS  
(Resistive Load see, Figure 3)  
t
V
R
=480V, I
 
= 0.8A,  
ns  
ns  
ns  
Off-voltage Rise Time  
Fall Time  
Cross-over Time  
28  
12.5  
48  
r(Voff)  
DD  
D
t
f
= 4.7
Ω,
V =
 
10V  
G
GS  
t
c
(Inductive Load see, Figure 5)  
SOURCE DRAIN DIODE  
Symbol  
Parameter  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
I
0.25  
1
A
A
Source-drain Current  
Source-drain Current (pulsed)  
SD  
(2)  
I
SDM  
V
(1)  
I
I
= 0.25A, V
 
= 0  
Forward On Voltage  
1.6  
V
SD  
SD  
SD  
GS  
t
= 0.8 A, di/dt = 100A/µs  
= 20
V
, T
 
=
1
50°C  
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Current  
140  
224  
3.2  
ns  
nC  
A
rr  
Q
V
DD  
rr  
RRM  
j
I
(see test circuit, Figure 5)  
Note: 1. Pulsed:
 
Pulse duration = 300 µs, duty cycle 1.5 %.  
2. Pulse
 
width limited by safe operating area.  
3. C  
V
is defined as a constant equivalent capacitance giving the same charging time as C  
when V
 
increases from 0 to 80%  
oss DS  
oss eq.  
.
DSS  
3/8  

STS1NK60Z  
Safe Operating Area  
Thermal Impedance  
Output Characteristics  
Transfer Characteristics  
Transconductance  
Static Drain-source On Resistance  
4/8  

STS1NK60Z  
Gate Charge vs Gate-source Voltage  
Capacitance Variations  
Normalized Gate Threshold Voltage vs Temp.  
Normalized On Resistance vs Temperature  
Source-drain Diode Forward Characteristics  
Normalized BVDSS vs Temperature  
5/8  

STS1NK60Z  
Fig. 1:
Unclamped Inductive Load Test Circuit  
Fig. 2:
Unclamped Inductive Waveform  
Fig. 3:
Switching Times Test Circuit For  
Fig. 4:
Gate Charge test Circuit  
Resistive Load  
Fig. 5:
Test Circuit For Inductive Load Switching  
And Diode Recovery Times  
6/8  

STS1NK60Z  
SO-8 MECHANICAL
 
DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.75  
0.25  
1.65  
0.85  
0.48  
0.25  
0.5  
MIN.  
MAX.  
0.068  
0.009  
0.064  
0.033  
0.018  
0.010  
0.019  
A
a1  
a2  
a3  
b
0.1  
0.003  
0.65  
0.35  
0.19  
0.25  
0.025  
0.013  
0.007  
0.010  
b1  
C
c1  
D
45 (typ.)  
4.8  
5.8  
5.0  
6.2  
0.188  
0.228  
0.196  
0.244  
E
e
1.27  
3.81  
0.050  
0.150  
e3  
F
3.8  
0.4  
4.0  
1.27  
0.6  
0.14  
0.157  
0.050  
0.023  
L
0.015  
M
S
8 (max.)  
0016023  
7/8  

STS1NK60Z  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from  
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications  
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information  
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or  
systems without express written approval of STMicroelectronics.  
© The ST logo is a registered trademark of STMicroelectronics  
© 2003 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
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8/8