STMicroelectronics-STW12NK90Z
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STW12NK90Z
N-channel 900
V
,
0
.72
Ω
, 11 A TO-247
Zener-protected SuperMESH™ Power MOSFET
Features
R
DS(on)
max
Order code
V
DSS
I
D
Pw
STW12NK90Z
900 V
< 0.88
Ω
11 A
230 W
■
Extremely high dv/dt capability
■
100% avalanche tested
3
2
■
Gate charge minimized
1
■
Very low intrinsic capacitance
■
Very good manufacturing repeatability
TO-247
Application
■
Switching applications
Figure 1.
Internal schematic diagram
Description
This device is made using the SuperMESH™
Power MOSFET technology that is obtained
through an extreme optimization of ST’s well
established strip-based PowerMESH™ layout. In
addition to pushing on-resistance significantly
down, special care is taken to ensure a very good
dv/dt capability for the most demanding
applications. Such series complements ST full
range of high voltage MOSFETs including
revolutionary MDmesh™ products.
Table 1.
Order code
STW12NK90Z
Device summary
Marking
Package
TO-247
Packaging
W12NK90Z
T
u
be
April 2011
Doc ID 9615 Rev 6
1/13
13
Contents
STW12NK90Z
Contents
Electrical ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
Doc ID 9615 Rev 6
STW12NK90Z
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
V
DS
V
GS
I
D
Drain-source voltage (V
GS
= 0)
Gate- source voltage
900
30
V
V
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
11
A
I
D
7
A
(1)
I
DM
P
tot
44
A
T
o
tal dissipation at T
C
= 25 °C
Derating Factor
230
1.85
6000
4.5
W
W/°C
V
V
ESD(G-S)
dv/dt
(2)
T
stg
Gate source ESD(HBM-C=100 p
F
,
R
=1.5 k
Ω
)
Peak diode recovery voltage slope
Storage temperature
V/ns
-55 to 150
°C
T
j
Max. operating junction temperature
1. Pulse
width limited by safe operating area.
2. I
SD
≤
11 A, di/dt
≤
200 A/µs, V
DD
≤
V
(BR)DSS
, T
j
≤
T
JMAX.
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
R
thj-case
R
thj-amb
T
J
Thermal resistance junction-case max
0.54
50
°C/W
°C/W
°C
Thermal resistance junction-ambient max
Maximum lead temperature for soldering purpose
300
Table 4.
Avalanche characteristics
Parameter
Symbol
Max value
Unit
Avalanche current, repetitive or not-repetitive
(pulse width limited by T
j
max)
I
AR
11
A
Single pulse avalanche energy
E
AS
500
mJ
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Doc ID 9615 Rev 6
3/13
Electrical characteristics
STW12NK90Z
2
Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 5.
Symbol
On/off states
Parameter
Test conditions
I
D
= 1 mA, V
GS
=0
Min. Typ. Max.
Unit
Drain-source
V
(BR)DSS
900
V
breakdown voltage
Zero gate voltage
V
DS
= max rating
1
µA
µA
I
DSS
drain current (V
GS
= 0)
V
DS
= max rating, T
C
= 125 °C
50
Gate-body leakage
current (V
DS
= 0)
I
GSS
V
GS
=
20 V
10
4.5
0.72 0.88
μ
A
V
V
GS(th)
R
DS(on)
Gate threshold voltage
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10
V
,
I
D
= 5.5 A
3
3.75
Static drain-source on
resistance
Ω
Table 6.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Forward
transconductance
(1)
g
fs
V
DS
= 15 V I
= 5.5 A
–
–
–
–
11
S
, D
Input capacitance
Output capacitance
C
iss
C
oss
C
rss
3500
280
58
pF
pF
pF
V
DS
= 25
V
, f = 1
M
Hz,
V
GS
= 0
Reverse transfer
capacitance
Equivalent output
capacitance
(2)
C
oss eq
V
GS
= 0, V
DS
= 0 to 800 V
117
pF
t
d(on)
t
r
t
d(off)
t
f
T
u
rn-on delay time
Rise time
31
20
88
55
ns
ns
ns
ns
V
DD
= 450
V
,
I
D
= 5 A
R
G
= 4.7
Ω
V
GS
= 10 V
T
u
rn-off delay time
Fall time
Q
g
Q
gs
Q
gd
T
o
tal gate charge
Gate-source charge
Gate-drain charge
V
DD
= 720
V
,
I
D
= 10 A,
V
GS
= 10
V
,
R
G
= 4.7
Ω
113
19
152
nC
nC
nC
–
60
1. Pulsed:
Pulse duration = 300 µs, duty cycle 1.5 %.
2. Coss
eq. is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
.
4/13
Doc ID 9615 Rev 6
STW12NK90Z
Electrical characteristics
Table 7.
Source drain diode
Parameter
Symbol
Test conditions
Min.
Typ.
Max. Unit
Source-drain current
I
SD
11
44
A
A
–
–
–
Source-drain current
(pulsed)
(1)
I
SDM
(2)
V
SD
Forward on voltage
I
SD
= 11 A, V
GS
= 0
1.6
V
t
rr
Reverse recovery time
I
SD
= 10 A,V
DD
= 50 V
728
7.8
ns
μ
C
A
Q
rr
Reverse recovery charge
di/dt = 100 A/µs,
I
RRM
21.6
t
rr
Reverse recovery time
I
SD
= 10 A, V
DD
= 50 V
964
11
ns
μ
C
A
Q
rr
Reverse recovery charge
di/dt = 100
A/µs,
–
I
RRM
23
1. Pulse
width limited by safe operating area.
2. Pulsed:
Pulse duration = 300 µs, duty cycle 1.5 %
Table 8.
Symbol
Gate-source Zener diode
Parameter
Test conditions
Igs= 1
mA (open drain)
Min.
Typ.
Max. Unit
Gate-source breakdown
voltage
BV
GSO
30
–
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capabilit
y
, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrit
y
.
T
hese integrated Zener diodes thus avoid the usage of external components.
Doc ID 9615 Rev 6
5/13
Electrical characteristics
STW12NK90Z
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
6/13
Doc ID 9615 Rev 6
STW12NK90Z
Electrical characteristics
Figure 8.
Gate charge vs gate-source voltage
Figure 9.
Capacitance variations
Figure 10.
Normalized gate threshold voltage
Figure 11.
Normalized on resistance vs
vs temperature
temperature
Figure 12.
Source-drain diode forward
characteristics
Figure 13.
Normalized breakdown voltage vs
temperature
Doc ID 9615 Rev 6
7/13
Test circuits
STW12NK90Z
3
Test circuits
Figure 14.
Switching times test circuit for
resistive load
Figure 15.
Gate charge test circuit
V
DD
12V
47k
Ω
1k
Ω
100nF
2200
3
.
3
μ
F
R
L
μ
F
I
G
=CON
S
T
V
DD
100
Ω
V
i
=20V=V
GMAX
D.U.
T
.
V
D
R
G
V
G
S
2200
μ
F
D.U.
T
.
V
G
2.7k
Ω
47k
Ω
P
W
1k
Ω
P
W
AM0146
8
v1
AM01469v1
Figure 16.
Test circuit for inductive load
switching and diode recovery times
Figure 17.
Unclamped Inductive load test
circuit
L
A
A
A
B
D
FA
S
T
DIODE
L=100
μ
H
V
D
G
2200
μ
F
D.U.
T
.
B
3
.
3
μ
F
V
DD
S
3
.
3
μ
F
1000
μ
F
B
V
DD
25
Ω
I
D
D
G
R
G
S
V
i
D.U.
T
.
P
w
AM01470v1
AM01471v1
Figure 18.
Unclamped inductive waveform
Figure 19.
Switching time waveform
t
on
td
on
t
off
td
off
V
(BR)D
SS
t
r
t
f
V
D
90
%
10
%
90
%
I
DM
10
%
V
D
S
I
D
0
0
V
DD
V
DD
90
%
V
G
S
10
%
AM01472v1
AM0147
3
v1
8/13
Doc ID 9615 Rev 6
STW12NK90Z
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECO
P
A
CK packages,
depending on their level of environmental compliance. ECO
P
A
CK
is an ST trademark.
Doc ID 9615 Rev 6
9/13
Package mechanical data
STW12NK90Z
Table 9.
Dim.
TO-247 mechanical data
mm
Min.
Typ.
Max.
A
A1
b
4.85
2.20
1.0
5.15
2.60
1.40
2.40
3.40
0.80
20.15
15.75
b1
b2
c
2.0
3.0
0.40
19.85
15.45
D
E
e
5.45
18.50
5.50
L
14.20
3.70
14.80
4.30
L1
L2
∅
P
∅
R
S
3.55
4.50
3.65
5.50
10/13
Doc ID 9615 Rev 6
STW12NK90Z
Figure 20.
TO-247 drawing
Package mechanical data
0075
3
25_F
Doc ID 9615 Rev 6
11/13
Revision history
STW12NK90Z
5
Revision history
Table 10.
Document revision history
Date
Revision
Changes
21-Jun-2004
17-Oct-2006
29-Apr-2011
4
5
6
Complete version
New template, no content change
12/13
Doc ID 9615 Rev 6
STW12NK90Z
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Doc ID 9615 Rev 6
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