STMicroelectronics-STW21N150K5

Part #STMicroelectronics-STW21N150K5
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STMicroelectronics-STW21N150K5
STW21N150K5  
N-
channel 1500 V, 0.7 Ω typ.,14 A MDmesh™ K5  
Power MOSFET in a TO-247 package  
Datasheet – production data  
Features  
Order code  
V

DS  

R

DS(on)

max.  
I

D  

P

TOT  

STW21N150K5  
1500 V  
0.9 Ω  
14 A  
446 W  
Industry’s lowest R

DS(on) *

area  
Industry’s best figure of merit (FoM)  
Ultra low gate charge  
100% avalanche tested  
Zener-protected  
3
2
1
TO-247  
Applications  
Switching applications  
Figure 1: Internal schematic diagram  
Description  
This very high voltage N-channel Power  
MOSFET is designed usin
g MDmesh™ K5  
technology based on an innovative proprietary  
vertical structure. The result is a dramatic  
reduction in on-resistance and ultra-low gate  
charge for applications requiring superior power  
density and high efficiency.  
Table 1: Device summary  
Order code  
Marking  
Package  
Packing  
STW21N150K5  
21N150K5  
TO-247  
Tube  
October 2015  
DocID026818 Rev 3  
1/12  
This is information on a product in full production.  

STW21N150K5  
Electrical ratings  
1
Electrical ratings  
Table 2: Absolute maximum ratings  
Symbol  
Parameter  
Value  
Unit  
V
V

GS  

I

D  

Gate-source voltage  
± 30  
14  
Drain current at T

C

= 25 °C  
Drain current at T

C

= 100 °C  
Drain current (pulsed)  
A
I

D  

8.7  
56  
A
A
P

TOT  

T

j  

Total dissipation at T

C

= 25 °C  
Peak diode recovery voltage slope  
MOSFET dv/dt ruggedness  
Operating junction temperature  
Storage temperature  
446  
4.5  
50  
W
V/ns  
V/ns  
– 55 to 150  
°C  
T

stg  

Notes:  

(1)

Pulse width limited by safe operating area  
(2)  
I
≤ 14 A, di/dt ≤ 100 A/µs, V

Peak

≤ V

(BR)DSS  

≤ 1200 V  
SD  
(3)  
V
DS  
Table 3: Thermal data  
Symbol  
R

thj-case  

R

thj-amb  

Parameter  
Thermal resistance junction-case  
Thermal resistance junction-amb  
Value  
0.28  
50  
Unit  
°C/W  
°C/W  
Table 4: Avalanche characteristics  
Symbol  
Parameter  
Value  
5
Unit  
A
Max current during repetitive or single pulse  
avalanche  
Single pulse avalanche energy  
1100  
mJ  
Notes:  

(1)

Pulse width limited by T

Jmax  

(2)

Starting T

J

= 25 °C, I

D

= I

AS

, V

DD

= 50 V  
DocID026818 Rev 3  
3/12  
 
 
 
 
 

Electrical characteristics  
STW21N150K5  
2
Electrical characteristics  
(T

CASE

= 25 °C unless otherwise specified)  
Table 5: Static  
Symbol  
Parameter  
Test conditions  
V

GS

= 0 V, I

D

= 1 mA  
V

GS

= 0 V, V

DS

= 1500 V  
Min.  
Typ.  
Max.  
Unit  
V
Drain-source breakdown  
voltage  
V

(BR)DSS  

1500  
1
µA  
µA  
Zero gate voltage drain  
current  
I

DSS  

V

GS

= 0 V, V

DS

= 1500 V,  
Tc = 125 °C  
50  
I

GSS  

Gate body leakage current
 
V

DS

= 0, V

GS

= ± 20 V  
±10  
5
µA  
V
V

GS(th)  

Gate threshold voltage  
V

DS

= V

GS

, I

D

= 100 µA  
3
4
Static drain-source on-  
resistance  
R

DS(on)  

V

GS

= 10 V, I

D

= 7 A  
0.7  
0.9  
Ω
Table 6: Dynamic  
Test conditions  
Symbol  
C

iss  

Parameter  
Input capacitance  
Output capacitance  
Min. Typ. Max. Unit  
–
–
3145  
172  
–
–
pF  
pF  
C

oss  

V

GS

= 0 V, V

DS

= 100 V,  
f = 1 MHz  
Reverse transfer  
capacitance  
C

rss  

–
–
–
1
–
–
–
pF  
pF  
pF  
Equivalent capacitance  
time related  
C

o(tr

161  
65  
V

DS

= 0 V to 1200 V, V

GS

= 0 V  
f = 1 MHz, I

D

= 0 A  
Equivalent capacitance  
energy related  
C

o(er

R

G  

Q

g  

Intrinsic gate resistance  
Total gate charge  
–
–
–
2.4  
89  
16  
–
–
–
Ω
V

DD

= 1200 V, I

D

= 7 A  
V

GS

= 10 V  
nC  
nC  
Q

gs  

Gate-source charge  
Q

gd  

Gate-drain charge  
–
59  
–
nC  
Notes:  

(1)

Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS  
increases from 0 to 80% VDSS  

(2)

Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when  
VDS increases from 0 to 80% VDSS  
Table 7: Switching times  
Symbol  
Parameter  
Turn-on delay time  
Rise time  
Test conditions  
Min. Typ. Max. Unit  
t

d(on)  

t

r  

t

d(off)  

t

f  

–
–
–
–
34  
14  
–
–
–
–
ns  
ns  
ns  
ns  
V

DD

= 750 V, I

D

= 3.5 A,  
R

G

= 4.7 Ω V

GS

= 10 V  
Turn-off delay time  
Fall time  
134  
26  
4/12  
DocID026818 Rev 3  
 
 

STW21N150K5  
Symbol  
Electrical characteristics  
Min. Typ. Max. Unit  
Table 8: Source drain diode  
Test conditions  
Parameter  
I

SD  

Source-drain current  
–
–
7
A
A
Source-drain current  
(pulsed)  
I

SDM  

28  
1.5  
t

rr  

Forward on voltage  
I

SD

= 7 A, V

GS

= 0 V  
–
–
–
V
Reverse recovery time  
Reverse recovery charge  
I

SD

= 7 A, V

DD

= 60 V  
di/dt = 100 A/µs,  
448  
ns  
µC  
Q

rr  

8.24  
I

RRM  

Reverse recovery current  
–
36.8  
A
t

rr  

Reverse recovery time  
I

SD

= 7 A,V

DD

= 60 V  
di/dt = 100 A/µs,  
Tj = 150 °C  
–
–
564  
ns  
Q

rr  

Reverse recovery charge  
9.48  
µC  
I

RRM  

Reverse recovery current  
–
33.6  
A
Notes:  

(1)

Pulsed: pulse duration = 300µs, duty cycle 1.5%  
Table 9: Gate-source Zener diode  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
30  
Gate-source breakdown  
voltage  
V

(BR)GSO  

I

GS

= ±1 mA, I

D

= 0 A  
–
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD  
performance of the device. The Zener voltage facilitates efficient and cost-effective device  
integrity protection, thus eliminating the need for additional external componentry.  
DocID026818 Rev 3  
5/12  
 

Electrical characteristics  
STW21N150K5  
2.1  
Electrical characteristics (curves)  
Figure 2: Safe operating area  
Figure 3: Thermal impedance  
Figure 4: Output characteristics  
Figure 5: Transfer characteristics  
Figure 6: Gate charge vs gate-source voltage  
Figure 7: Static drain-source on-resistance  
6/12  
DocID026818 Rev 3  

STW21N150K5  
Electrical characteristics  
Figure 9: Normalized gate threshold voltage  
vs temperature  
Figure 8: Capacitance variations  
Figure 10: Normalized on-resistance vs  
temperature  
Figure 11: Normalized V(BR)DSS vs  
temperature  
Figure 12: Maximum avalanche energy vs  
temperature  
Figure 13: Source-drain diode forward  
characteristics  
DocID026818 Rev 3  
7/12  

Test circuits  
STW21N150K5  
3
Test circuits  
Figure 15: Test circuit for gate charge  
Figure 14: Test circuit for resistive load  
switching times  
behavior  
Figure 16: Test circuit for inductive load  
switching and diode recovery times  
Figure 17: Unclamped inductive load test  
circuit  
Figure 19: Switching time waveform  
Figure 18: Unclamped inductive waveform  
8/12  
DocID026818 Rev 3  

STW21N150K5  
Package information  
4
Package information  
In order to meet environmental requirements, ST offers these devices in different grades of  
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

®  

specifications, grade definitions and product status are available at:

.  
ECOPACK

®

is an ST trademark.  
4.1  
TO-247 package information  
Figure 20: TO-247 package outline  
DocID026818 Rev 3  
9/12  

Package information  
STW21N150K5  
Table 10: TO-247 package mechanical data  
mm.  
Dim.  
Min.  
4.85  
2.20  
1.0  
Typ.  
Max.  
5.15  
2.60  
1.40  
2.40  
3.40  
0.80  
20.15  
15.75  
5.60  
14.80  
4.30  
A
A1  
b
b1  
b2  
c
2.0  
3.0  
0.40  
19.85  
15.45  
5.30  
14.20  
3.70  
D
E
e
5.45  
18.50  
5.50  
L
L1  
L2  
ØP  
ØR  
S
3.55  
4.50  
5.30  
3.65  
5.50  
5.70  
10/12  
DocID026818 Rev 3  

STW21N150K5  
Revision history  
5
Revision history  
Table 11: Document revision history  
Changes  
Date  
Revision  
26-Aug-2015  
1
First release.  
Text and formatting changes throughout document.  
Updated features on cover page.  
10-Sep-2015  
01-Oct-2015  
2
3
Updated sections
Electrical ratings
and
Electrical characteristics
.  
Added section
Electrical characteristics (curves)
.  
Updated section
TO-247 package information
.  
On cover page:  
– updated figure Internal schematic diagram  
In section Electrical characteristics:  
– updated and renamed table Static (was On/off states).  
DocID026818 Rev 3  
11/12  

STW21N150K5  
IMPORTANT NOTICE
–
PLEASE READ CAREFULLY  
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ges, corrections, enhancements, modifications, and  
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST  
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to ST’s terms and conditions of sale in place at the time of order  
acknowledgement.  
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the  
design of Purchasers’ p
roducts.  
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.  
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.  
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.  
© 2015 STMicroelectronics
–
All rights reserved  
12/12  
DocID026818 Rev 3