STMicroelectronics-STY145N65M5
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STY145N65M5
N-
channel 650 V, 0.012 Ω typ., 138 A MDmesh™
M5
Power MOSFET in a Max247 package
Datasheet – production data
Features
Order code
V
DS
@ T
Jmax
R
DS(on)
max.
710 V
0.015
Ω
I
D
STY145N65M5
138 A
•
•
•
•
Extremely low R
DS(on)
Low gate charge and input capacitance
Excellent switching performance
100% avalanche tested
3
2
1
Applications
Max247
•
Switching applications
Figure 1: Internal schematic diagram
Description
This device is an N-channel Power MOSFET
based on the MDmesh™ M5 innovative vertical
process technology combined with the well-
known PowerMESH™ horizontal layout. The
resulting product offers extremely low on-
resistance, making it particularly suitable for
applications requiring high power and superior
efficiency.
Table 1: Device summary
Order code
Marking
Package
Packaging
STY145N65M5
145N65M5
Max247
Tube
November 2015
DocID023718 Rev 3
1/12
This is information on a product in full production.
Contents
STY145N65M5
Contents
2/12
DocID023718 Rev 3
STY145N65M5
Electrical ratings
1
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
± 25
138
87
Unit
V
V
GS
I
D
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
A
I
D
A
552
625
A
P
TOT
I
AR
Total dissipation at T
C
= 25 °C
W
Avalanche current, repetitive or not repetitive (pulse width
12
A
limited by T
jmax
)
Single pulse avalanche energy (starting T
j
= 25 °C, I
D
= I
AR
V
DD
= 50 V)
,
E
AS
2420
mJ
T
stg
Peak diode recovery voltage slope
Storage temperature
15
– 55 to 150
150
V/ns
°C
T
j
Max. operating junction temperature
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
≤
138 A, di/dt
≤
400 A/µs; V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V.
SD
Table 3: Thermal data
Symbol
R
thj-case
R
thj-amb
Parameter
Value
0.2
Unit
Thermal resistance junction-case max
Thermal resistance junction-ambient max
°C/W
°C/W
30
DocID023718 Rev 3
3/12
Electrical characteristics
STY145N65M5
2
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4: On/off states
Symbol
Parameter
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 650 V
Min. Typ.
650
Max. Unit
Drain-source breakdown
voltage
V
(BR)DSS
V
10
µA
µA
Zero gate voltage drain
current
I
DSS
V
GS
= 0 V, V
DS
= 650 V,
T
C
= 125 °C
100
Gate-body leakage current
Gate threshold voltage
I
GSS
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
±100
5
nA
V
V
GS(th)
3
4
Static drain-source
on-resistance
R
DS(on)
V
GS
= 10 V, I
D
= 69 A
0.012 0.015
Ω
Table 5: Dynamic
Test conditions
Symbol
C
iss
Parameter
Input capacitance
Output capacitance
Min.
Typ.
18500
413
Max. Unit
–
–
–
–
pF
pF
C
oss
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
Reverse transfer
capacitance
C
rss
–
–
–
11
–
–
–
pF
pF
pF
Equivalent output
capacitance energy
related
415
V
GS
= 0, V
DS
= 0 to 520 V
Equivalent output
capacitance time related
1950
R
G
Q
g
Intrinsic gate resistance
Total gate charge
f = 1 MHz, open drain
V
DD
= 520 V, I
D
= 69 A,
–
–
–
–
0.7
414
114
164
–
–
–
–
Ω
nC
nC
nC
Q
gs
Q
gd
Gate-source charge
Gate-drain charge
Notes:
(1)
C
o(er)
is defined as a constant equivalent capacitance giving the same stored energy as C
oss
when V
DS
increases from 0 to 80% V
DSS
(2)
C
o(tr)
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases
from 0 to 80% V
DSS
4/12
DocID023718 Rev 3
STY145N65M5
Symbol
Electrical characteristics
Min. Typ. Max. Unit
Table 6: Switching times
Test conditions
Parameter
Voltage delay time
Voltage rise time
Current fall time
t
d(V)
t
r(V)
t
f(i)
V
DD
= 400 V, I
D
= 85 A
R
G
= 4.7
Ω, V
GS
= 10 V
–
–
–
255
11
–
–
–
ns
ns
ns
82
t
C(off)
Crossing time
–
88
–
ns
Table 7: Source drain diode
Test conditions
Symbol
Parameter
Min. Typ. Max. Unit
I
SD
Source-drain current
–
–
–
–
–
138
552
1.5
A
A
I
SDM
Source-drain current (pulsed)
Forward on voltage
V
SD
V
GS
= 0 V, I
SD
= 138 A
V
t
rr
Reverse recovery time
Reverse recovery charge
568
ns
µC
I
SD
= 138 A,
di/dt = 100 A/µs,
V
Q
rr
14.5
I
RRM
Reverse recovery current
–
51
A
t
rr
Reverse recovery time
–
–
728
ns
I
SD
= 138 A,
di/dt = 100 A/µs,
V
DD
= 100 V, T
j
= 150 °C
Q
rr
Reverse recovery charge
24.5
µC
I
RRM
Reverse recovery current
–
67
A
Notes:
(1)
Pulse width is limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID023718 Rev 3
5/12
Electrical characteristics
STY145N65M5
2.2
Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
AM09125v1
K
10
-1
10
-2
δ
=0.5
0.2
0.1
0.05
0.02
0.01
Zth=k Rthj-c
d=tp/t
Single pulse
tp
t
10
-2
10
-4
10
-1
10
-3
p
(s)
t
Figure 5: Transfer characteristics
Figure 4: Output characteristics
AM17902v1
AM17901v1
I
D
(A)
I
D
(A)
V
GS
=10V
9V
V
DS
=30V
300
300
8V
7V
250
200
150
100
50
250
200
150
100
50
0
6V
0
5
0
10
15
20
25
V
DS
(V)
2
5
6
7
8
V
GS
(V)
0
3
1
4
Figure 7: Static drain-source on-resistance
Figure 6: Gate charge vs gate-source voltage
6/12
DocID023718 Rev 3
STY145N65M5
Electrical characteristics
Figure 9: Normalized gate threshold voltage
Figure 8: Capacitance variations
vs temperature
AM08899v1
AM15553v1
V
GS(th)
C
(norm)
(pF)
1.10
100000
I =
250µA
D
V
= V
DS
GS
Ciss
10000
1000
100
1.00
0.90
Coss
Crss
f=1 MHz
0.80
0.70
10
1
0.1
100
1
10
V
DS
(V)
-50
-25
25 50 75
T
J
(°C)
0
100
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
AM10399v1
AM08900v1
V
(BR)DSS
R
DS(on)
(norm)
(norm)
1.08
2.1
1.7
I
D
= 1mA
I
D
= 69A
V
GS
= 10V
1.06
1.04
1.02
1.00
1.3
0.9
0.98
0.96
0.94
0.92
0.5
-50
-25
0
25 50 75
T
J
(°C)
-50
-25
100
0
25 50 75
T
J
(°C)
100
Figure 12: Output capacitance stored energy
Figure 13: Switching losses vs gate
resistance
AM15555v1
E
(µJ)
Eon
V
DD
=400 V
GS
=10 V
9000
8000
7000
6000
5000
4000
3000
2000
1000
V
I
D
=85 A
Eoff
0
20
30
40
10
R
G
(W)
0
The previous figure E
on
includes reverse recovery of a SiC diode.
DocID023718 Rev 3
7/12
Test circuits
STY145N65M5
3
Test circuits
Figure 14: Test circuit for resistive load
switching times
Figure 15: Test circuit for gate charge
behavior
Figure 16: Test circuit for inductive load
switching and diode recovery times
Figure 17: Unclamped inductive load test
circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
Concept waveform for Indu
ctive Load Turn-off
Id
90%Vds
90%Id
Tdelay -off
Vgs
90%Vgs
10%Vds
on
Vgs(I(t ))
10%Id
Vds
Trise
Tfall
Tcross -over
AM05540v2_for_M5
8/12
DocID023718 Rev 3
STY145N65M5
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
ECOPACK
®
is an ST trademark.
4.1
Max247 package information
Figure 20: Max247 package outline
0094330
_
R
ev_D
DocID023718 Rev 3
9/12
Package information
STY145N65M5
Table 8: Max247 package mechanical data
mm
Dim.
Min.
4.70
2.20
1.00
2.00
3.00
0.40
19.70
5.35
15.30
14.20
3.70
Typ.
Max.
5.30
2.60
1.40
2.40
3.40
0.80
20.30
5.55
15.90
15.20
4.30
A
A1
b
–
–
–
–
–
–
–
–
–
–
–
b1
b2
c
D
e
E
L
L1
10/12
DocID023718 Rev 3
STY145N65M5
Revision history
5
Revision history
Table 9: Document revision history
Changes
Date
Revision
25-Sep-2012
1
First release.
Modified: I
AR
and E
AS
values
17-Jan-2013
13-Nov-2015
2
3
Modified: typical values on Table 5, 6 and 7
Updated title, features and description on cover page.
Document status promoted from preliminary to production data.
Minor text changes.
DocID023718 Rev 3
11/12
STY145N65M5
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
12/12
DocID023718 Rev 3
