STMicroelectronics-STY60NM60

Part #STMicroelectronics-STY60NM60
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STMicroelectronics-STY60NM60
STY60NM60  
N-CHANNEL 600V – 0.050
Ω
– 60A Max247  
Zener-Protected MDmesh™Power MOSFET  
TYPE  
V
DSS  
R
I
D
DS(on)  
STY60NM60  
600V  
< 0.055
Ω  
60 A  
TYPICAL R
 
(on) = 0.050
Ω  
DS  
HIGH dv/dt AND AVALANCHE CAPABILITIES  
IMPROVED ESD CAPABILITY  
LOW INPUT CAPACITANCE AND GATE  
CHARGE  
3
2
1
LOW GATE INPUT RESISTANCE  
TIGHT PROCESS CONTROL  
INDUSTRY’S LOWEST ON-RESISTANCE  
Max247  
DESCRIPTION  
The MDmesh™ is a new revolutionary MOSFET  
technology that associates the Multiple Drain pro-  
cess with the Company’s PowerMESH™ horizontal  
layout. The resulting product has an outstanding low  
on-resistance, impressively high dv/dt and excellent  
avalanche characteristics. The adoption of the  
Company’s proprietary strip technique yields overall  
dynamic performance that is significantly better than  
that of similar competition’s products.  
INTERNAL SCHEMATIC DIAGRAM  
APPLICATIONS  
The MDmesh™ family is very suitable for increasing  
power density of high voltage converters allowing  
system miniaturization and higher efficiencies.  
ORDERING INFORMATION  
SALES TYPE  
MARKING  
PACKAGE  
Max247  
P
A
CKAGING  
STY60NM60  
Y60NM60  
TUBE  
July 2003  
1/8  

STY60NM60  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
600  
Unit  
V
V
DS  
Drain-source Voltage (V
 
= 0)  
GS  
V
Drain-gate Voltage (R
 
= 20 k
Ω
)  
600  
V
DGR  
GS  
V
Gate- source Voltage  
±30  
V
GS  
I
Drain Current (continuous) at T
 
= 25°C  
60  
A
D
C
I
Drain Current (continuous) at T
 
= 100°C  
37.8  
240  
A
D
C
I
( )  
Drain Current (pulsed)  
A
DM  
P
TOT  
Total Dissipation at T
 
= 25°C  
560  
W
C
V
Gate source ESD(HBM-C=100p
F
,
R
=15K
Ω)  
Derating Factor  
6
KV  
W/°C  
V/ns  
°C  
°C  
ESD(G-S)  
4.5  
dv/dt (1)  
Peak Diode Recovery voltage slope  
Storage
T
e
mperature  
15  
T
stg  
–65 to 150  
150  
T
Max. Operating Junction
T
e
mperature  
j
(•)Pulse width limited by safe operating area  
(1) I
 
≤
60A, di/dt
≤
400 A/µs, V
 
≤
V  
, T
 
≤
T  
j JMAX.  
SD  
DD  
(BR)DSS  
THERMAL DATA  
Rthj-case  
Rthj-amb  
Thermal Resistance Junction-case  
Thermal Resistance Junction-ambient  
Max  
Max  
0.22  
30  
°C/W  
°C/W  
°C  
T
Maximum Lead
T
emperature For Soldering Purpose  
300  
l
AVALANCHE CHARACTERISTICS  
Symbol  
Parameter  
Max Value  
Unit  
I
AR  
Avalanche Current, Repetitive or Not-Repetitive  
30  
A
(pulse width limited by T
 
max)  
j
E
Single Pulse Avalanche Energy  
1.4  
J
AS  
(starting T
 
= 25 °C, I
 
= I
 
, V
 
= 35 V)  
j
D
AR  
DD  
GATE-SOURCE ZENER DIODE  
Symbol  
BV  
Parameter  
Test Conditions  
Igs=± 1mA (Open Drain)  
Min.  
T
y
p.  
Max.  
Unit  
Gate-Source Breakdown  
Voltage  
30  
V
GSO  
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES  
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s  
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be  
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and  
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the  
usage of external components.  
2/8  

STY60NM60  
ELECTRICAL CHARACTERISTICS
(T  
= 25 °C UNLESS OTHERWISE SPECIFIED)  
CASE  
ON/OFF  
Symbol  
Parameter  
Drain-source  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
V
I
= 250 µA, V
 
= 0  
600  
V
(BR)DSS  
D
GS  
Breakdown Voltage  
I
Zero Gate Voltage  
V
V
V
= Max Rating  
DS  
10  
µA  
µA  
µA  
DSS  
Drain Current (V
 
= 0)  
GS  
= Max Rating, T
 
= 125°C  
100  
±10  
DS  
GS  
C
I
Gate-body Leakage  
= ± 20V  
GSS  
Current (V
 
= 0)  
DS  
V
V
V
= V
 
, I
 
= 250 µA  
5
V
Gate Threshold Voltage  
3
4
GS(th)  
DS  
GS  
GS  
D
R
Static Drain-source On  
Resistance  
= 10 V, I
 
= 30 A  
0.050  
0.055  
Ω
DS(on)  
D
DYNAMIC  
Symbol  
Parameter  
Test Conditions  
Min.  
T
y
p.  
Max.  
Unit  
g
(1)  
Forward Transconductance  
V
= I  
x R  
DS(on)max,  
35  
S
fs  
DS  
D(on)  
I
= 30 A  
D
C
Input Capacitance  
Output Capacitance  
Reverse Transfer  
Capacitance  
V
= 25
V
, f = 1
M
Hz, V
 
= 0  
7300  
2000  
40  
pF  
pF  
pF  
iss  
DS  
GS  
C
oss  
C
rss  
R
Gate Input Resistance  
f=1 MHz Gate DC Bias = 0  
T
e
st Signal Level = 20mV  
Open Drain  
1.8  
Ω
G
SWITCHING ON  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
t
Turn-on Delay Time  
Rise Time  
V
R
= 300
V
, I
 
= 30 A  
= 4.7
Ω
V =
 
10 V  
GS  
55  
95  
ns  
ns  
d(on)  
DD  
D
t
r
G
(see test circuit, Figure 3)  
Q
T
o
tal Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
V
V
= 470
V
, I
 
= 60 A,  
= 10 V  
178  
44.5  
95  
266  
nC  
nC  
nC  
g
DD  
GS  
D
Q
gs  
gd  
Q
SWITCHING OFF  
Symbol  
Parameter  
Test Conditions  
Min.  
Min.  
Typ.  
Max.  
Unit  
t
Off-voltage Rise Time  
Fall Time  
Cross-over Time  
V
DD  
= 400 V, I
 
= 60 A,  
130  
76  
105  
ns  
ns  
ns  
r(Voff)  
D
t
f
R =
 
4.7
Ω,
V =
 
10 V  
G GS  
(see test circuit, Figure 5)  
t
c
SOURCE DRAIN DIODE  
Symbol  
Parameter  
Test Conditions  
Typ.  
Max.  
Unit  
I
Source-drain Current  
Source-drain Current (pulsed)  
60  
240  
A
A
SD  
(2)  
I
SDM  
V
(1)  
I
I
= 60 A, V
 
= 0  
Forward On Voltage  
1.5  
V
SD  
SD  
SD  
GS  
t
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Current  
= 60 A, di/dt = 100 A/µs,  
= 30 V, T
 
= 150°C  
600  
14  
48  
ns  
µC  
A
rr  
Q
V
DD  
rr  
RRM  
j
I
(see test circuit, Figure 5)  
Note: 1. Pulsed:
 
Pulse duration = 300 µs, duty cycle 1.5 %.  
2. Pulse
 
width limited by safe operating area.  
3/8  

STY60NM60  
Safe Operating Area  
Thermal Impedance  
Output Characteristics  
Transfer Characteristics  
Transconductance  
Static Drain-source On Resistance  
4/8  

STY60NM60  
Gate Charge vs Gate-source Voltage  
Capacitance Variations  
Normalized Gate Threshold Voltage vs Temp.  
Normalized On Resistance vs Temperature  
Source-drain Diode Forward Characteristics  
Normalized BVDSS vs Temperature  
5/8  

STY60NM60  
Fig. 1:
Unclamped Inductive Load Test Circuit  
Fig. 2:
Unclamped Inductive Waveform  
Fig. 3:
Switching Times Test Circuit For  
Fig. 4:
Gate Charge test Circuit  
Resistive Load  
Fig. 5:
Test Circuit For Inductive Load Switching  
And Diode Recovery Times  
6/8  

STY60NM60  
Max247 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
4.70  
2.20  
1.00  
2.00  
3.00  
0.40  
19.70  
5.35  
15.30  
14.20  
3.70  
TYP.  
MAX.  
5.30  
2.60  
1.40  
2.40  
3.40  
0.80  
20.30  
5.55  
15.90  
15.20  
4.30  
MIN.  
MAX.  
A
A1  
b
b1  
b2  
c
D
e
E
L
L1  
P025Q  
7/8  

STY60NM60  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from  
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications  
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information  
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or  
systems without express written approval of STMicroelectronics.  
© The ST logo is a registered trademark of STMicroelectronics  
© 2003 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
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Singapore – Spain – Sweden – Switzerland – United Kingdom – United States.  
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