STMicroelectronics-TDA7786
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TDA7786
TDA7786M
ELITE automotive tuners for AM/FM car-radio
Datasheet
–
production data
Description
The TDA7786x (ELITE) tuner is an optimized high-
performance AM/FM tuner IC family for car-radio
applications, suitable also
(in combination with an
external baseband decoder) for HD Radio™
reception.
‘!0’03ꢀꢀꢁꢂꢁ
Its members integrate mixers and IF amplifiers for
AM, FM and WX, fully integrated VCO and PLL
synthesizer, IF- processing including adaptive
bandwidth control, stereo decoder, RDS decoder,
and digital interfaces for external HD Radio™
decoding on a single IC.
LQFP64
Features
AM/FM IBOC base band filtering is available in
parallel to standard analog reception.
AEC-Q100 qualified
FM, AM and weather band reception
Fully integrated VCO for world tuning
High performance PLL for fast RDS system
Integrated AM LNA and PIN diodes
The utilization of digital signal processing results
in numerous advantages: very low number of
external components, very small space
occupation and easy application, very high
selectivity due to digital filters, high customization
possibility through software control, automatic
alignment and a powerful DSP for custom
processing.
Automatic self alignment for FM front-end pre-
selection filter and image rejection
Integrated IF filters with high selectivity,
dynamic range and adaptive bandwidth control
Two versions of the device cover different
application/performance requirements:
Drift-free Digital-IF signal processing with high
performance
TDA7786:
entry-level, high-performance tuner;
RDS demodulation with group and block
TDA7786M:
tuner with enhanced behavior in
case of FM multipath, thanks to the proprietary
MuSICA algorithm.
synchronization
High performance stereo decoder with noise-
blanker
Both versions are HW- and SW-compatible.
Digital interface for HD Radio™ reception with
digital audio blending
Table 1. Device summary
2
I C
bus-controlled
Order code
Package
Packing
2
I S
input/output digital audio interfaces
TDA7786
LQFP64
Tray
Single 5 V supply
LQFP64 package
(10x10x1.4mm)
TDA7786M
MuSICA (multipath noise reduction) algorithm
available for premium version of the device
October 2016
DocID026122 Rev 5
1/54
This is information on a product in full production.
Contents
TDA7786, TDA7786M
Contents
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Pin description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
FM – mixers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
FM – AGC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
AM – LNA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
AM – AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
AM – Mixers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
IF A/D converters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Audio D/A converters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
VCO .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Tuner PLL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 Crystal
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.12 Digital
high speed IO interface pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.13 Multipath
reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.14 HD
Radio™ connectivity
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.15 I
2
S – serial audio interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
2.16 Audio
sample rate converter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
2.17 Serial
control interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.17.1 Serial
interface / boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
2.17.2 I
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.18 Digital-down-converter
(DDC) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Electrical specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
2/54
DocID026122 Rev 5
TDA7786, TDA7786M
Contents
Phase locked loop
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Tuning DAC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2
I
C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Front-end registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FM IF-processing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
Soft mute
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
High cut control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Stereo decoder
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
AM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
Channel selection filter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Soft mute
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
High cut control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DocID026122 Rev 5
3/54
3
List of tables
TDA7786, TDA7786M
List of tables
Device summar
y
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SAI_BB timing values (normal mode
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
7
Audio I
S configuration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I
S interface timing (receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
I
S interface timing (transmitter
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
0
Phase locked loop
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Tuning DAC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IF ADC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Audio DAC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I
C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AM LW overall system performanc
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
9
AM SW overall system performance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
WX overall system performanc
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
0
Adjacent channel mute – continuous se
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
6
High cut control – continuous set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
De-emphasis filter – continuous set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Stereo decoder – continuous se
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
8
High cut control – continuous set
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4/54
DocID026122 Rev 5
TDA7786, TDA7786M
List of figures
List of figures
Crystal oscillator block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SAI_BB waveforms (normal mode)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I
S interface timing (receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2
I
S interface timing (transmitter
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
0
2
I
S interface 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
Figure 10.
I
S interface 32/24/20/16-bi
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1
Figure 11.
I
C “write” sequenc
e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
Figure 12.
I
C “read” sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
2
Figure 13.
Digital-down-converter simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14.
Cumulative transfer function at output of IBOC_FM filter . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.
Cumulative transfer function at output of IBOC_AM filter . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16.
Cumulative digital-down-converter transfer function for FM . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17.
Cumulative digital-down-converter transfer function for AM . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18.
I
C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19.
FM input set-u
p
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5
Figure 20.
AM MW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21.
AM LW input set-up
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22.
AM SW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23.
WX input set-up
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24.
FM wide-band applicatio
n
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
0
Figure 25.
LQFP64 (10x10x1.4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID026122 Rev 5
5/54
5
1
Block diagram and pin description
1.1
Block diagram
Figure 1. Functional block diagram
“LEND CONTROL
FROM DECODER
ꢉ”AND
TO )”/# DECODER
)ꢈ1 “ASE
)”/#
INTERF ꢄ
.#/
!’#
$!#
2$3
“LEND
&-
!$#
!$#
35-
$30ꢁ
!-
ꢀ 6
)ꢇ#
-%-
$30ꢊ
&2%&
ꢀ .
!’#
0,,
32#
)ꢇ3
34%2%/
$!#
6#/
0,,
3UPPLY
/3#
ꢂꢃꢄꢅꢆ -(Z
!UDIO /UT
)NꢈOUT $IGITAL
AUDIO
‘!0’03ꢀꢃꢄꢅꢆ
TDA7786, TDA7786M
Block diagram and pin description
1.2
Pin description
Figure 2. Pin connection (top view)
ꢃꢅ ꢃꢂ ꢃꢇ ꢃꢊ ꢃꢁ ꢋꢍ ꢋꢆ ꢋꢌ ꢋꢃ ꢋꢋ ꢋꢅ ꢋꢂ ꢋꢇ ꢋꢊ ꢋꢁ ꢅꢍ
ꢊ
ꢇ
ꢂ
ꢅ
ꢋ
ꢃ
ꢌ
ꢆ
ꢍ
&-0).$26
&-0).$DEC
&–)8DEC
&–)8ꢇIN
&–)8ꢊIN
‘.$ꢉ2&
4#!-
ꢅꢆ
ꢅꢌ
ꢅꢃ
ꢅꢋ
ꢅꢅ
ꢅꢂ
ꢅꢇ
ꢅꢊ
ꢅꢁ
ꢂꢍ
ꢂꢆ
ꢂꢌ
ꢂꢃ
ꢂꢋ
ꢂꢅ
ꢂꢂ
4
E
ST
6$$ #/2% ꢊ6ꢇ
‘.$ ꢊ6ꢇ
“,%.$ꢈ!3
3!)?””?1
3!)?””?)
3!)?””?7#,+
3!)?””?”#,+
3!)?!5$)/?$)
3!)?!5$)/?$/
3!)?!5$)/?7#,+
3!)?!5$)/?”#,+
‘.$ ꢂ6ꢂ
6##ꢉ2&
#+?3%,
‘.$ 6#/
,&REF
ꢊꢁ
ꢊꢊ
ꢊꢇ
ꢊꢂ
ꢊꢅ
,&ꢊ
6## 6#/
4#!-ꢇ
6$$ ꢂ6ꢂ
0).$DEC
0).$IN
3#,
ꢊꢋ
ꢊꢃ
3$!
ꢊꢌ ꢊꢆ ꢊꢍ ꢇꢁ ꢇꢊ ꢇꢇ ꢇꢂ ꢇꢅ ꢇꢋ ꢇꢃ ꢇꢌ ꢇꢆ ꢇꢍ ꢂꢁ ꢂꢊ ꢂꢇ
‘!0’03ꢀꢃꢄꢇꢀ
Table 2. Pin description
Pin
Pin name
I/O
Function
Description
Equivalent circuit
1
FMPINDRV
Out
FM PIN diode driver output
‘!0’03ꢀꢀꢈꢀꢉ
Integrated FM PINdiode
decoupling
2
FMPINDdec
In
FM
‘!0’03ꢀꢀꢈꢀꢄ
3
4
FMMIXdec
FMMIXin2
–
FM RF signal ground
FM mixer input 2
In
5
6
FMMIXin1
GNDRF
In
–
FM mixer input 1
RF power ground
‘!0’03ꢀꢀꢈꢀꢆ
–
–
DocID026122 Rev 5
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53
Block diagram and pin description
TDA7786, TDA7786M
Equivalent circuit
Table 2. Pin description (continued)
Pin
Pin name
I/O
Function
Description
7
8
TCAM
–
–
–
AM AGC time constant
RF 5 V supply
ꢌ
ꢊꢅ
‘!0’03ꢀꢀꢈꢂꢀ
VCCRF
In
–
Master/Slave clock operation
select
9
CK_SEL
In
–
‘!0’03ꢀꢀꢈꢂꢂ
10 GNDVCO
11 LFref
–
–
VCO ground
–
–
–
–
Loop filter reference
Loop filter output
VCO 5V supply
12 LF1
–
13 VCCVCO
In
VCO
14 TCAM2
–
–
AM AGC 2
nd
order time constant
ꢌ
ꢊꢅ
‘!0’03ꢀꢀꢈꢂꢀ
AM AGC internal PIN diode
decoupling
15 PINDdec
‘!0’03ꢀꢀꢈꢂꢁ
AM pin diode
16 PINDin
17 GNDLNA
18 LNAin
–
–
AM AGC internal PIN diode input
AM LNA ground
‘!0’03ꢀꢀꢈꢂꢃ
–
In
AM LNA input
‘!0’03ꢀꢀꢈꢂꢈ
AM LNA
19 LNAdec
–
AM LNA decoupling
‘!0’03ꢀꢀꢈꢂꢅ
20 LNAout
21 LNAin2
Out
–
AM LNA output
–
–
AM LNA input 2
nd
stage
8/54
DocID026122 Rev 5
TDA7786, TDA7786M
Block diagram and pin description
Table 2. Pin description (continued)
Pin
Pin name
I/O
Function
Description
Equivalent circuit
22 LNAout2
23 LNAdec2
–
AM LNA output 2
nd
stage
‘!0’03ꢀꢀꢈꢂꢇ
AM LNA
–
AM LNA decoupling 2
nd
stage
‘!0’03ꢀꢀꢈꢂꢉ
24 AMMIXin1
25 AMMIXin2
In
In
AM mixer input 1
AM mixer input 2
AM mixer
inputs
‘!0’03ꢀꢀꢈꢀꢆ
Internal inter-IC communication
bus ground
26 GNDSLINK
–
–
27 Vdig
In
In
Front-end digital 5 V supply
–
–
28 VCCreg1V2
29 REG1V2
Internal 1.2 V regulator 5 V supply
Internal 1.2 V regulator output
Out
Supply,
ground and
reset
30 Vreg3v3
Out
Internal 3.3 V regulator output
‘!0’03ꢀꢀꢈꢂꢆ
Reset (low active)
31 RSTN
32 RDSINT
33 SDA
In
Pull-up 50 k
Ω
to 3.3 V IO supply
‘!0’03ꢀꢀꢈꢂꢄ
RDS interrupt output
Out
–
Pull-down 50 k
Ω
to ground
I
2
C bus data
In/Out
Pull-up 50 k
Ω
to 3.3 V IO supply
‘!0’03ꢀꢀꢈꢃꢀ
I
2
C interface
I
2
C bus clock
34 SCL
In
Pull-up 50 k
Ω
to 3.3 V IO supply
‘!0’03ꢀꢀꢈꢂꢄ
35 VDD3V3
36 GND3V3
In
–
–
–
IO ring (3.3 V) supply
IO ring (3.3 V) supply
–
–
DocID026122 Rev 5
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53
Block diagram and pin description
TDA7786, TDA7786M
Equivalent circuit
Table 2. Pin description (continued)
Pin
Pin name
I/O
Function
Description
SAI clk
37 SAI_AUDIO_BCLK In/Out
38 SAI_AUDIO_WCLK
In/Out
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
Audio SAI word-select
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
Audio SAI data output
39 SAI_AUDIO_DO
40 SAI_AUDIO_DO
41 SAI_BB_BCLK
42 SA_BB_WCLK
43 SAI_BB_I
Out
In
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
Audio SAI data-input
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
SAI Base-Band clock
HD Radio™
connectivity/
Audio output
I2S interface
In/Out
In/Out
Out
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
‘!0’03ꢀꢀꢈꢃꢀ
SAI Base-Band word-select
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
SAI Base-Band I data
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
SAI Base-Band Q data
44 SAI_BB_Q
Out
Pull-down 50 k
Ω
to ground,
SINE_3V3_LIN pad
HD blend input
45 BLEND/AS
In
Pull-down 50 k
Ω
to ground
‘!0’03ꢀꢀꢈꢂꢄ
46 GND1V2
–
–
–
DSP core ground
–
47 VDD
core 1V2
In
DSP core 1.2 V supply
–
T
e
st Mode
48
T
e
st
In
–
Pull-down 50 k
Ω
to ground
‘!0’03ꢀꢀꢈꢂꢄ
49 VDDPLL1V2
50 VDDIO1V2
In
In
–
–
Digital PLL 1.2 V supply
–
Internal inter-IC communication
1.2 V supply
–
–
Front-end reference frequency and
regulator 5 V supply
51 VCC-REF
In
–
10/54
DocID026122 Rev 5
TDA7786, TDA7786M
Block diagram and pin description
Table 2. Pin description (continued)
Pin
Pin name
I/O
Function
Description
Equivalent circuit
52 OSCin
In
Crystal oscillator input
–
Oscillator
53 OSCout
Out
–
Crystal oscillator output
‘!0’03ꢀꢀꢈꢃꢂ
Front-end reference frequency and
regulator ground
54 GND-REF
55 Vrefdec
–
–
–
–
3.3 V Bias generation decoupling
‘!0’03ꢀꢀꢈꢃꢃ
56 GND-ADC_DAC
57 DACoutL
–
IFADC and audio DAC ground
Audio output left
–
Out
DAC
58 DACoutR
Out
Audio output right
‘!0’03ꢀꢀꢈꢃꢁ
59 VCC-ADC_DAC
60 VCC-PLL
In
In
–
IFADC and audio DAC 5 V supply
Tuning PLL 5 V supply
–
–
–
61 GND-PLL
Tuning PLL ground
PLL
62 PLLtest
Out
PLL
T
e
st output
‘!0’03ꢀꢀꢈꢃꢈ
63 TCFM
–
–
–
FM AGC time constant
Tuning voltage output
‘!0’03ꢀꢀꢈꢃꢁ
64 TVDAC
Out
–
DocID026122 Rev 5
11/54
53
Function description
TDA7786, TDA7786M
2
Function description
2.1
FM – mixers
The FM Image Rejection mixer has two single ended inputs, selectable through software.
They are designed to achieve best performance both in case of a passive tuned
preselection and of a passive fixed band-pass preselection without tuning for lower cost
applications.
The input frequency is down-converted to very low IF with high image rejection.
The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is
performed automatically on-chip.
2.2
FM – AGC
The programmable RFAGC senses the mixer input to avoid overload.
When the RFAGC threshold is reached, the PIN diode output is activated in order to
attenuate the incoming RF signal
The PIN diode driver is able to drive external PIN diodes with up to 15 mA current.
The time constant of the FM AGC is defined by the combination of an external capacitor and
internal currents. There are two programmable attack and decay time constants.
2.3
2.4
AM – LNA
The integrated AM LNA feature is integrated with low-noise and high IIP2 and IIP3. The gain
of the LNA is controlled by the AGC. The maximum gain is set with an external resistor,
typically 26 dB with 470
Ω
.
AM – AGC
The programmable AM RFAGC senses the mixer inputs and controls the internal PIN
diodes and LNA gains.
Firstly the LNA gain is reduced by about 10 dB, and then the PIN diodes are activated to
further attenuate the signal.
nd
The time constant of the 2
order AM AGC LPF is defined by both external components
and programmable internal currents.
2.5
AM – Mixers
The image rejection mixer has two AM inputs selectable via software. It easily supports low-
cost applications for extended frequency bands like short-waves.
The input frequency is converted to low IF with high image rejection.
12/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
2.6
IF A/D converters
A high performance IQ-IFADC converts the IF signal to the digital domain for subsequent
digital signal processing.
Two fully differential, continuous-time Sigma-Delta (
Σ∆
) IF-ADCs are used for both the ‘I’
path and the ‘Q’ path. For each IFADC, two fully differential input nodes are fed with an input
signal having a bandwidth up to 325 kHz. This fully differential design provides good
suppression of even-order harmonics. For complex filtering, the input signals of the ‘I’ path
and the ‘Q’ path have a 90 degree phase shift. The IFADC sampling frequency is 36.48
MHz.
2.7
2.8
Audio D/A converters
A CD-quality (>100dB DR) stereo DAC provides the left/right audio signals after IF
processing and stereo-decoding by the DS
P
.
I
n presence of an external HD Radio™
decoder the DAC delivers the high quality audio resulting from the decoding of the
HD Radio™ transmissions.
VCO
The VCO is fully integrated without any external tuning component. It covers all the FM
frequency bands including EU, US, Japan, East-Europe, Weather-Band and the AM bands
including LW, MW and SW. Its center frequency is approximately 2.7 GHz.
2.9
PLL
2.9.1
Tuner PLL
The very high-speed tuning PLL is able to settle within about 100 µs for fast RDS
applications. The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.
2.10
Crystal oscillator
The device works with a 36.48 MHz fundamental tone crystal. The oscillator block diagram
chip oscillator input and output pins of the chip. The internal load capacitance together with
pin and pad capacitance is optimized for fundamental tone crystal units at 36.48 MHz. It is
not recommended to put any additional external load capacitors. By suitably configuring pin
#9 (CK_SEL), the device can be operated as either a clock master or a clock slave. If pin 9
is left open or tied to GND, the device is configured as clock master (typical operation
mode). In case the device is configured as clock slave, pin 9 needs to be connected to 5 V.
Then the crystal oscillator is switched off and the device expects a crystal equivalent signal
on the OSCout/OSCin pins.
DocID026122 Rev 5
13/54
53
Function description
TDA7786, TDA7786M
Figure 3. Crystal oscillator block diagram
!,#
#LOCK
BUFFER
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‘!0’03ꢀꢀꢈꢃꢇ
2.11
DSP and digital hardware accelerators
The TDA7786x embeds two DSP cores for high computational power and achievable
customization. The DSP cores, in combination with the hardware accelerators, take care of
all the tuner digital signal processing. The main program is fixed in ROM. Control
parameters are copied to RAM and are accessible and modifiable there, thus allowing a
parametric performance optimization. The operations performed by the DSP cores and HW
accelerators are:
digital down-conversion of IF
bandwidth selection with variable controlled bandwidth
FM and AM noise blanking
FM/AM demodulation with soft-mute, high-cut, weak signal processing and quality
detection
FM stereo decoding with stereo-blend
RDS demodulation including error correction and block synchronization with generation
of an RDS interrupt for the main µP
Autonomous control of RDS-AF tests
Self-alignment of pre-selection tuning
14/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
2.12
Digital high speed IO interface pins
The IC has several IOs tasked for connectivity to an external HD Radio™ decoder and/or to
2
I S audio sources and destinations (pins 37 to 44).
These pins are driven by a special buffer that has been developed to reduce disturbance
originating from activity on the digital lines. This bidirectional buffer is based on a TTL
Schmitt trigger receiver and a slew-rate controlled driver with programmable cut-off
frequency and current capability.
Typical configurations of these IOs for both analog and digital-HD reception are indicated in
with a 10 MHz cut-off frequency:
Table 3. Suggested GPIO direction and driving capability
Driving capability
Use case:
Use case:
Pin
HD reception
digital audio out
10 pF
5 pF
37
38
39
40
41
42
43
44
IN
OUT
X
X
X
X
IN
OUT
OUT
IN
OUT
IN
–
OUT
OUT
OUT
OUT
X
–
X
–
X
X
–
In case a different GPIO configuration is used, it is recommended to connect the TDA7786x
to an externally regulated 3.3 V source.
2.13
Multipath reduction
The TDA7786 is equipped with a basic FM multipath noise reduction system in addition to
the traditional weak signal processing. The algorithm, called DANCE, assures an improved
performance in presence of in-band interference (such as in case of multipath).
The premium version of the ELITE family, the TDA7786M is equipped with a superior
algorithm, called MuSICA, to further enhance the reception quality even in presence of
strong multipath.
DocID026122 Rev 5
15/54
53
Function description
TDA7786, TDA7786M
2.14
HD Radio™ connectivity
The ELITE complies with HD Radio™ interface specifications as per Ibiquity’s
‘RX_SSS_1108 HD Radio™ power efficient RF-IF and peripheral processing (power RIPP)
specification’, thus providing an external HD Radio™ decoder with I/Q base-band signals
Figure 4. HD Radio™ system architecture example
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The complex baseband signal of an IBOC transmission is sent to the external decoder using
the dedicated digital output interface SAI_BB. The SAI_BB supports the modes shown in
16/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
Figure 5. SAI_BB waveforms (normal mode)
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‘!0’03ꢀꢀꢈꢃꢆ
Table 4. SAI_BB timing values (normal mode)
Rate
Symbol
Parameter
Unit
Fpll
PLL clock
332.8
650
345.6
675
451.584
882
466.944
912
245.76
48
MHz
KHz
Fws
Fbclk
Fbclk
Word strobe
(332.8/512) (345.6/512)
(451.582/512) (466.944/512)) (245.76/5120)
10.4
10.8
14.112
14.592
0.768
Bit clock in
SPLIT mode
MHz
MHz
(332.8/32)
(345.6/32)
(451.584/32)
(466.944/32)
(245.76/320)
20.8
21.6
28.224
29.184
1.536
Bit clock in
MUX mode
(332.8/16)
(345.6/16)
(451.584/16)
(466.944/16)
(245.76/160)
20.8
21.6
28.224
29.184
1.536
Bit clock in
AFE mode
Fbclk
Ts
MHz
ns
(332.8/16)
(345.6/16)
(451.584/16)
(466.944/16)
(245.76/160)
Data setup
time (min)
5
5
5
5
5
5
5
5
5
5
Data hold time
(min)
Th
ns
DocID026122 Rev 5
17/54
53
Function description
TDA7786, TDA7786M
Figure 6. SAI_BB waveforms (burst mode)
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Table 5. SAI_BB timing values (burst mode)
Rate
Symbol
Parameter
Unit
Fpll
PLL clock
332.8
345.6
675
451.584
882
466.944
912
245.76
48
MHz
650
Fws
Fbclk
Fbclk
Word strobe
KHz
MHz
MHz
(332.8/512)
(345.6/512) (451.582/512) (466.944/512)) (245.76/5120)
332.8/n
345.6/n
451.584/n
(n=16/32)
466.944/n
(n=16/32)
245.76/n
Bit clock in
SPLIT mode
(n=16/32)
(n=16/32)
(n=160/320)
332.8/n
345.6/n
451.584/n
(n=8/16)
466.944/n
(n=8/16)
245.76/n
Bit clock in
MUX mode
(n=8/16)
(n=8/16)
(n=80/160)
332.8/n
345.6/n
451.584/n
(n=8/16)
466.944/n
(n=8/16)
245.76/n
Bit clock in
AFE mode
Fbclk
Ts
MHz
ns
(n=8/16)
(n=8/16)
(n=80/160)
Data setup
time (min)
5
5
5
5
5
5
5
5
5
5
Data hold
time (min)
Th
ns
18/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
2.15
I
2
S – serial audio interface
The audio SAI serves as stereo input/output audio bus interface (e.g. to an external audio
2
processor, or from an external HD decoder) using the I
S protocol. The latter calls for a bit
clock line, a word select line and data lines; the SAI interface on the TDA7786x has one
input data line and one output data line.
The audio SAI lines are: SAI_AUDIO_CLK (pin 37, bit clock line), SAI_AUDIO_WCLK (pin
38, word select (frame) clock line), SAI_AUDIO_DO (pin 39, data output line),
SAI_AUDIO_DI (pin 40, data input line). In master mode SAI_AUDIO_BCLK and
SAI_AUDIO_WCLK are outputs, in slave mode these pins are inputs.
The input and output data lines are operated at the same sampling frequency.
The bit clock has one pulse for each discrete bit of data on the data lines. The bit clock
operates at a frequency which is a multiple of the sample rate, and is equal to the sampling
frequency times the number of bits per word times two.
2
Table 6. Audio I S configuration overview
1×2 In
SAI
and
16/32
16/24
4
I
2
S
M/S
32-48
32-48
12.288 MHz
1×2 Out
2
Figure 7. I
S interface timing (receiver)
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Note:
The polarity of the signals and the data bit-shift direction can be selected by configuration
bits.
DocID026122 Rev 5
19/54
53
Function description
Symbol
TDA7786, TDA7786M
Min. Typ. Max. Unit
2
Table 7. I S interface timing (receiver)
Parameter Condition
t
CLK
t
CLKH
t
CLKL
t
WSS
t
WSH
t
WSD
t
DS
Minimum Clock Cycle (CLK)
Minimum bit clock high time
Minimum bit clock low time
Word-select setup time
Word-select hold time
Word-select delay
–
–
–
50
25
25
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
slave mode
slave mode
3
master mode
4
Data setup time
–
–
5
t
DH
Data_hold time
5
2
Figure 8. I S interface timing (transmitter)
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The polarity of the signals and the data shift direction can be selected by configuration bits.
2
Table 8. I
S interface timing (transmitter)
Symbol
Parameter
Condition
Min. Typ. Max. Unit
t
CLK
Minimum Clock Cycle (CLK)
–
–
–
50
25
25
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
t
CLKH
Minimum bit clock high time
t
CLKL
Minimum bit clock low time
t
WSS
Word-select setup time
t
WSH
Word-select hold time
t
WSD
Word-select delay
slave mode
slave mode
master mode
–
5
5
t
DD
Data delay
5
The audio SAI can be configured via software to be operating either in master or in slave
shows the default setting of SAI for the 16-bit mode. Different settings of clock polarity, word
2
clock polarity, transmission mode (I
S mode) and data direction (either MSB or LSB first
transmission) are possible, and they can be changed through software. Supported
20/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
2
Figure 9. I
S interface 16-bit
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Figure 10. I
S interface 32/24/20/16-bit
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‘!0’03ꢀꢀꢈꢁꢈ
2.16
Audio sample rate converter
The TDA7786x is equipped with internal sample rate converters (SRC) that can be
configured to modify the sampling frequency of outgoing and incoming digital audio both in
the master and in the slave SAI mode (the native audio sampling frequency of the
TDA7786x is 45.6 kHz).
The SRC is able to automatically detect the input and output sampling rates and includes a
sample clock jitter rejection function which can be enabled separately. The input signal
word-width is 20 bits, while the output signal word width can be selected as 20 bits or 16
bits. In order to properly assist in the conversion, the SRC is coupled to self-adjusting low-
pass filters.
DocID026122 Rev 5
21/54
53
Function description
TDA7786, TDA7786M
2.17
Serial control interface
2
The device is controlled via I C.
Through serial bus the processing parameters can be modified and the signal quality
parameters and the RDS information can be read out.
The operation of the device is handled mainly through high level commands sent by the car-
radio microprocessor through the serial interface, which allows simplification of the
operations carried out in the microprocessor itself. The high level commands include among
others:
change frequency (which allows to avoid computing the PLL divider factors)
change band;
start seek (the seek operation can be carried out by the TDA7786x in a completely
autonomous fashion);
RDS seek/search (jumps to AF and quality measurements are automatically
sequenced).
2.17.1
Serial interface / boot mode
The device possesses two different I2C addresses: 0xC2/C3 and 0xC8/C9. The
configuration is chosen by applying the proper voltage at the exit from reset to the pins
transitions from low to high (when RSTN is low, the IC is in reset mode).
The voltage level forced to the boot pins must be released to start the system operation a
suitable time after the RSTN line has gone high. The list of configurations is shown in the
following table:
Table 9. 64-pin package boot mode configuration
SAI_AUDIO_DO
RDS INT
pin 32
BUS mode
pin 39
0
0
0
1
I
2
C Address = 0xC2
I
2
C Address = 0xC8
The status of these pins during the reset phase can be set to:
High: through external <10 k
Ω
resistors tied to 3.3V
Low: by not forcing any voltage on them from outside, as 50 k
Ω
internal pull-down
resistors are present inside the device.
2
To
m
ake sure the I
C address is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and further keep it
low for an additional time Treset.
22/54
DocID026122 Rev 5
TDA7786, TDA7786M
2
Function description
2.17.2
I C
bus protocol
2
The I
C communication requires two signals: clock (SCL) and data (SDA – bidirectional).
The protocol requires an acknowledge signal after any 8-bit transmission.
A “write” communication example is shown in the figure below, for an unspecified number of
data bytes (see the relevant technical documentation for frame structure description):
2
Figure 11. I
C “write” sequence
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CLKꢆ
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CLKꢊ
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The sequence consists of the following phases:
1. STAR
T
:
S
DA line transitioning from H to L with SCL fixed H. This indicates that a new
transmission is starting;
2. DATA
LATCHING: on the rising SCL edge. The SDA line can vary only when SCL is
low (otherwise its transitions are interpreted as either a START or a STOP transition);
3. ACKNOWLEDGE:
on the 9th SCL pulse the microprocessor keeps the SDA line H, and
the TDA7786x pulls it down in case the communication has been successful. Lack of
the acknowledge pulse generation from the TDA7786x indicates a communication
failure; the chip-address byte must be sent at the beginning of the transmission. The
value can be 0xC2 or 0xC8 (according to the mode chosen at start-up) for “write”; as
many data bytes as needed can follow the address before the communication is
terminated. See the next section for details on the frame format;
4. STOP:
SDA line transitioning from L to H with SCL H. This signifies the end of the
transmission.
Dashed lines represent transmissions from the TDA7786x to the microprocessor. A
communication example is shown in the figure below, for an unspecified number of data
bytes (see later on for frame structure description):
2
Figure 12. I
C “read” sequence
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K
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K
ꢆ
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K
ꢍ
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K
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K
ꢇ
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K
ꢆ
CL
K
ꢍ
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ADDRESS
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34/0
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DocID026122 Rev 5
23/54
53
Function description
TDA7786, TDA7786M
The “read” sequence is similar to the “write” and it has the same constraints for start, stop,
data-latching and the following differences:
the chip address must always be sent by the microprocessor to the TDA7786x; the
address must be 0xC3 (if C2 had been selected at boot) or 0xC9 (if 0xC8 had been
selected at boot);
the header is transmitted after the chip address (the same happens for “write”) before
data are transferred from the TDA7786x to the microprocessor. See the relevant
technical documentation for details on the frame format;
when data are transmitted from the TDA7786x to the µ
P
,
t
he latter keeps the SDA line
H;
the acknowledge pulse is generated by the µP for those data bytes that are sent by the
th
TDA7786x to the µ
P
.
F
ailure of the µP to generate an ACK pulse on the 9
CLK pulse
has the same effect on the TDA7786x as a STO
P
.
The maximum clock speed is 500 kbit/s.
Warning: When
the TDA7786x is not powered on, the internal ESD
2
protection diodes act as a pull-down keeping the I C lines
2
voltage below 2 V. This implies that the I C bus connected to
the TDA7786x may not be used to drive other devices when
the TDA7786x is powered off.
24/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
2.18
Digital-down-converter (DDC)
The complex digital mixer in the DDC performs mixing of the IF signal to zero I
F
.
T
he
internal sample rate for FM/AM processing is 456 kS/s and the sample rate for FM/AM IBOC
is 912 kS/s. AM IBOC require additional filtering implemented in software.
Figure 13. Digital-down-converter simplified block diagram
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Figure 14. Cumulative transfer function at output of IBOC_FM filter
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Table 10. Overall filter characteristics for IBOC_FM filter
Item
Value
Unit
Pass-band edge
Stop-band edge
282
325
kHz
kHz
dB
In-band ripple (0 kHz to 282 kHz)
Anti-alias band range
<0.002
[-500 +500]
100
kHz
dB
Anti-alias Attenuation
DocID026122 Rev 5
25/54
53
Function description
TDA7786, TDA7786M
Figure 15. Cumulative transfer function at output of IBOC_AM filter
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Table 11. Overall filter characteristics at output of IBOC_AM filter
|Item
Value
Unit
Pass-band edge
Stop-band edge
In-band ripple
15
25
kHz
kHz
dB
<0.34
>100
Anti-alias Attenuation
dB
Figure 16. Cumulative digital-down-converter transfer function for FM
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ꢁ
ꢉꢊꢁ
ꢉꢇꢁ
ꢉꢂꢁ
ꢉꢅꢁ
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ꢇꢅꢁ
&
R
EQUENCY ꢎK(Zꢏ
‘!0’03ꢀꢀꢈꢁꢄ
26/54
DocID026122 Rev 5
TDA7786, TDA7786M
Function description
Table 12. Overall filter characteristics for FM (not including DISS filter)
|Item
Value
Unit
Pass-band edge
45.8
228
kHz
kHz
dB
Stop-band edge
In-band ripple
<0.003
>100
Anti-alias Attenuation
dB
Figure 17. Cumulative digital-down-converter transfer function for AM
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ꢉꢇꢁ
ꢉꢂꢁ
ꢉꢅꢁ
ꢉꢋꢁ
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ꢉꢊꢁꢁ
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Table 13. Overall filter characteristics for AM
|Item
Value
Unit
Pass-band edge
Stop-band edge
In-band ripple
20
300
kHz
kHz
dB
<0.051
>100
Anti-alias Attenuation
dB
DocID026122 Rev 5
27/54
53
Electrical specifications
TDA7786, TDA7786M
3
Electrical specifications
3.1
Absolute maximum ratings
Table 14. Absolute maximum ratings
Test condition
Symbol
Parameter
Min
Typ
Max
Units
V
CC
T
stg
Abs. supply voltage
Storage temperature
–
–
-0.5
-55
–
5.5
V
–
150
°C
Human Body model
>|±2000|
>|±400|
>|±750|
ESD absolute minimum
withstand voltage
V
ESD
Charged device model
V
Charged device mode, corner pins
Max. input at any pin
(latch-up characteristic)
–
I
INMAX
±100
mA
Note:
For all pins 37-44, when set as input, injecting current cannot exceed 20 mA as it would lead
to voltage at the pin above the abs max.
3.2
Thermal data
Table 15. Thermal data
Symbol
R
th
Parameter
Test condition
Value
Units
LQFP64 10×10,
JEDEC
2s1p
PCB
Thermal resistance
55
°C/W
3.3
General key parameters
Table 16. General key parameters
Test condition
Symbol
Parameter
Min
Typ
Max
Units
V
CC
I
CC
5 V supply voltage
4.7
–
5
175
–
5.2
225
85
V
see note
(1)
supply current @ 5 V
Ambient temperature range
mA
°C
T
amb
–
-40
Operating junction
temperature
T
j
–
–
–
–
150
5.2
1.3
°C
V
V
VCCREG12
VCCREG12 supply voltage
see note
(2)
2.3
1.14
when supplied externally
see note
(3)
Digital core 1.2 V supply
voltage
V
1V2
1.2
V
V
1V2
= 1.2V
see note
(3)
Digital core 1.2 V supply
current
I
1V2
–
55
–
80
mA
V
when supplied externally
see note
(4)
V
3V3
Digital IO 3.3 V supply voltage
3.0
3.6
28/54
DocID026122 Rev 5
TDA7786, TDA7786M
Electrical specifications
Table 16. General key parameters (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Units
Maximum current specified
Digital IO 3.3 V supply current
only in case generated from
Internal supply only
I
3V3
–
–
10
mA
1. FM
functional test from antenna mixer input to audio output.
2. In
the typical application supplied from 5 V with a 27
Ω
series resistor.
T
e
st condition: maximum current load for minimum value, unloaded for maximum value.
3. When
the 1.2 V supply is applied externally, and not using the internal 1.2 V regulator.
T
e
st condition: FM functional test from antenna mixer input to audio output.
4. When
the 3.3 V supply is applied externally, and not using the internal 3.3 V regulator.
3.4
Electrical characteristics
V
= 4.7 V to 5.25 V; T
= -40 °C to +85 °C; unless otherwise specified.
CC
amb
3.4.1
FM – section
Table 17. FM – section
Test condition
Symbol
FM IMR Mixer
Parameter
Min
Typ
Max Units
RF gain 0
33
36
37
39
–
35
38
37
RF gain 1
(1)
40
dB
41
Voltage gain (mix in -> s.e. test
output)
RF Gain
RF gain 2
39
RF gain 3
41
43
Rsource=1.25 k
Ω
, noiseless
Rsource=0
2.3
2.1
1.9
1.6
2.9
Vnoise low
gain
Input noise voltage (RF gain 0)
Input noise voltage (RF gain 3)
nV/
Hz
2.6
–
Rsource=1.25 k
Ω
, noiseless
Rsource=0
–
2.4
Vnoise high
gain
nV/
Hz
2.0
–
RF gain 0, up to Vin/tone = 92 dBµV
124
RF gain 3, up to Vin/tone = 86 dBµV
119
127
122
IIP3
3
rd
order intercept point
–
dBµV
dBµV
FM AGC
min setting, reg8<14> =1
85.4
89
88.4
92
91.4
95
RFAGC threshold, referred to
mixer input;
max setting, reg8<14>=1
min setting, reg8<14>=0
88.4
92
91.4
95
94.4
98
RF level
RFAGC-Thr
max setting, reg8<14>=0
Threshold steps
–
1.3
-1.5
–
1.8
–
2.3
1.5
–
dB
dB
Threshold error
@ T
amb
–
Threshold temperature drift
0.016
dB/K
DocID026122 Rev 5
29/54
53
Electrical specifications
TDA7786, TDA7786M
Table 17. FM – section (continued)
Test condition
Symbol
Parameter
IFAGC threshold
Min
Typ
Max Units
min setting
max setting
–
120
126
1.5
-1.5
–
122
124
130
2.5
1.5
–
dBµV
dBµV
dB
128
IFAGC-Thr Threshold
steps
Threshold error
2
@ T
amb
–
0.016
20
200
2
dB
Threshold temperature drift
–
dB/K
Slow attack
Fast attack
Slow decay
Fast decay
10
100
1
30
300
5
I attack
Time
constant
µA
I decay
10
-15
3
20
–
30
–
(2)
–
–
PIN diode source current
@ T
amb
mA
µA
PIN diode sink current
–
–
20
PIN diode source current in
constant current mode
–
@ T
amb
-0.9
–
–
mA
1. The
gain is internally 6 dB higher than what measured at the test output. This is due to the differential to single-ended
conversion used for the test output.
2. The
current is generated by a PTAT (proportional to absolute temperature) source, and has therefore a temperature
dependency described by:
∆
I/Io =
∆
T/
T
o
, with Io being the current at ambient temperature (25 °C) and
T
o
t
he ambient
temperature (25 °C) expressed in Kelvin, that is 298K.
3.4.2
AM – section
Table 18. AM – section
Test condition
Symbol
AM IMR Mixer
Parameter
Min
Typ
Max
Units
normal
reduced
–
20
17
20
22
19
30
24
21
45
Voltage gain (mix in -> s.e.
test output)
(1)
Gain
dB
Rin
Input resistance
k
Mix 1, 2
Vnoise
Input noise voltage
–
7.5
9
–
nV/
Hz
R
source
= 1 k
Ω
, noise-less
Mix1, 2
IIP3
IIP2
3
rd
order intercept point
nd
order intercept point
128
132
dBµV
up to Vin/tone = 90 dBµV
Mix1, 2
2
152
80
158
–
–
–
dBµV
dB
up to Vin/tone = 90 dBµV
LO hsupp
LO harmonic suppression
–
AM LNA
Max gain, R
ext
= 470
Ω
24
8
28
12
32
16
Gain
Voltage gain
dB
Min gain (AGC controlled)
R
in
C
in
Input resistance
–
–
600
–
950
20
1300
–
k
Ω
input capacitance
pF
30/54
DocID026122 Rev 5
TDA7786, TDA7786M
Electrical specifications
Table 18. AM – section (continued)
Test condition
Symbol
Parameter
Input noise voltage
rd
order intercept point
2
rd
order intercept point
Min
Typ
Max
Units
V
noise
IIP3
–
–
0.7
120
127
1.0
nV/
Hz
dBµV
3
@ maximum LNA gain
@ maximum LNA gain
116
121
–
–
IIP2
dBµV
AM PIN diode
Full attenuation,
Csource = 80 p
F
, f = 1
M
Hz
IIP2
2
rd
order intercept point
134
140
–
dBµV
Res
Cin
Minimum resistance
Input capacitance
–
–
–
5
2
15
–
Ω
High ohmic
pF
AM AGC
Mix 1,2 min setting
80
92.6
1.3
-2.5
-3
83
95.6
1.8
–
86
98.6
2.3
2.5
3
Referred to mixer input;
RF level
AGC-Thr
dBµV
Mix 1,2 max setting
Thr-steps Threshold
steps
–
dB
dB
dB
mA
µA
–
–
–
–
Threshold error
@
T
amb
Threshold temperature drift
PIN diode source current
PIN diode sink current
–
–
@ T
amb
See note
(2)
-10
15
–
–
–
30
45
PIN diode source current in
constant current mode
–
-1
–
–
mA
1. The
gain is internally 6 dB higher than what measured at the test output. This is due to the differential to single-ended
conversion used for the test output.
2. The
current is generated by a PTAT (proportional to absolute temperature) source, and has therefore a temperature
dependency described by:
∆
I/Io =
∆
T/
T
o
, with Io being the current at ambient temperature (25 °C) and
T
o
t
he ambient
temperature (25 °C) expressed in Kelvin, that is 298K.
3.4.3
VCO
Table 19. VCO
Test condition
Symbol
Parameter
Min
Typ
Max
Units
Minimum VCO oscillation
frequency
(1)
fvco,
min
fvco,
max
–
–
–
2.34
GHz
Maximum VCO oscillation
frequency
(2)
3.025
–
–
–
GHz
dBc/Hz
Hz
Locked VCO;
values referred @ 100MHz
@ 100 Hz
@ 1 kHz
@ 10 kHz
PN
Phase noise of LO
–
–
-105
-115
-115
FM reception, deemphasis
50 µs, f
audio
=20 Hz…20 kHz
dev
deviation error (RMS)
5
8
1. Limited
by application Firmware to 2.1 GHz.
2. Limited
by application Firmware to 3.1 GHz.
DocID026122 Rev 5
31/54
53
Electrical specifications
TDA7786, TDA7786M
3.4.4
Phase locked loop
Table 20. Phase locked loop
Test condition
Symbol
Parameter
Settling time FM
Min
Typ
Max
Units
T
settle
∆
f < 10 kHz
–
–
–
100
5
140
µs
kHz
Hz
FM step
AM step
FM Frequency step
AM frequency step
–
–
–
–
500
3.4.5
Tuning DAC
Table 21. Tuning DAC
Test condition
Symbol
Parameter
Min
Typ
Max
Units
R
es
V
outmin
V
outmax
R
out
Resolution
8 bit
14
–
18
22
0.75
–
mV
V
Min output voltage
Max output voltage
Output impedance
Diff. Nonlinearity
Conversion time
–
0.6
–
VCC-0.25 VCC-0.15
V
–
1.5
2.5
–
3.5
0.5
–
k
Ω
LSB
µs
DNL
–
–
–
T
conv
Without capacitive load
20
3.4.6
IF ADC
Table 22. IF ADC
Test condition
Symbol
Parameter
Min
Typ
Max
Units
DR
FM
Dynamic range in FM
BW = ±100 kHz
87
1.7
105
6.3
82
90
–
dB
Input noise referred to mixer
input
vnoise
FM
DR
AM
RF gain 2
0.94
108
3.2
85
–
–
–
–
–
–
–
nV/
Hz
dB
Dynamic range in AM
BW = ±3 kHz
normal gain
BW = ±200 kHz
RF gain 2
Input noise referred to mixer
input
vnoise
AM
DR
FM-HD
Vnoise
FM-HD
DR
AM-HD
vnoise
AM-HD
nV/
Hz
dB
Dynamic range in FM-IBOC
Input noise referred to mixer
input
2.3
97
1.2
100
2.9
nV/
Hz
dB
Dynamic range in AM-IBOC
BW = ±15 kHz
normal gain
Input noise referred to mixer
input
5.6
nV/
Hz
32/54
DocID026122 Rev 5
TDA7786, TDA7786M
Electrical specifications
3.4.7
Audio DAC
Table 23. Audio DAC
Test condition
Symbol
Parameter
Min
Typ
Max
Units
V
out
BW
Max. output voltage
Pass-band
Full scale
1.2
1.4
20
–
–
Vrms
KHz
Ω
0.01dB attenuation
–
Rout
Output resistance
–
100
150
14
200
30
multipath Output
noise
–
–
–
µVrms
%
D
Distortion
-6 dBFS
0.03
0.05
3.4.8
IO interface pins
Table 24. IO interface pins
Test condition
Symbol
Parameter
Min
Typ
Max
Units
–
–
–
–
–
High level output voltage
Low level output voltage
Input voltage range
Unloaded
2.9
–
3.2
–
V
V
V
V
V
Unloaded
0.1
0.3
3.5
–
–
–
–
0
–
–
–
High level input voltage
Low level input voltage
2.0
–
0.8
Minimum time during which
pin RSTN must be low so as
to reset the device
T
reset
Reset time
10
–
–
–
µs
Minimum time during which
the voltage applied at pins 32
Boot mode configuration latch
and 39 must be driven in
T
latch
10
–
µs
time
order to latch the correct
control serial bus address
configuration
DocID026122 Rev 5
33/54
53
Electrical specifications
2
TDA7786, TDA7786M
3.4.9
I C
interface
2
The I
C protocol serial bus communication parameters of the following table are defined as
2
Table 25. I C interface
Symbol
f
SCL
t
AA
Parameter
Test condition
Min
Typ
Max
Units
SCL Clock frequency
–
–
–
–
–
500
–
kHz
µs
SCL low to SDA data valid
0.3
Time the bus must be kept
free before a new
transmission
t
buf
–
1.3
–
–
µs
t
HD-STA
t
LOW
START condition hold time
Clock low period
–
–
–
–
–
–
–
–
–
–
0.6
1.3
0.6
0.1
0
–
–
–
–
–
–
–
–
–
–
–
–
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
t
HIGH
t
SU-SDA
t
HD-DAT
t
SU-DAT
t
R
Clock high period
–
START condition setup time
Data input hold time
Data input setup time
SDA & SCL rise time
SDA & SCL full time
Stop condition setup time
Data out time
–
0.9
–
0.1
–
0.3
0.3
–
t
F
–
t
SU-STOP
t
DH
0.6
–
0.3
2
Figure 18. I
C bus timing diagram
T
T
T
T
2
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2
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34/54
DocID026122 Rev 5
TDA7786, TDA7786M
Electrical specifications
3.5
Overall system performance
3.5.1
FM overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms (Antenna terminal voltage with 75
Ω
dummy
load).
Figure 19. FM input set-up
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6
R
F
‘!0’03ꢀꢀꢈꢈꢂ
Input level referred to 75
Ω
antenna dummy output. F
= 98.1 MHz, V
= 60 dBµV, mono
rf
rf
modulation, f
= 40 kHz, f
=1 kHz audio. De-emphasis = 50 µs. Wide-band, not-tuned
dev
audio
pre-selection application, unless otherwise specified.
Table 26. FM overall system performance
Parameter
Test condition
Min
Typ
Max
Units
(can be modified by the user)
Tuning range FM Eu
Tuning step FM Eu
Tuning range FM US
Tuning step FM US
Tuning range FM Jp
Tuning step FM Jp
Tuning range FM EEu
87.5
–
100
–
108
MHz
kHz
(automatic FE alignment
available)
(can be modified by the user)
–
87.5
–
–
107.9
–
(can be modified by the user)
MHz
kHz
(automatic FE alignment
available)
(can be modified by the user)
(can be modified by the user)
200
–
76
–
90
–
MHz
kHz
(automatic FE alignment
available)
(can be modified by the user)
100
–
(can be modified by the user)
65
74
MHz
(automatic FE alignment not
available)
Tuning step FM EEu
Sensitivity
(can be modified by the user)
S/N = 26 dB
–
–
100
-6
–
kHz
-3
dBµV
@ 10 dBµV, no high-cut,
DISS BW = #4
S/N
49
77
82
67
52
80
85
70
–
–
–
–
dB
dB
dB
dB
@ 60 dBµV, mono
@ 60 dBµ
V
,
Deviation = 75 kHz, mono
Ultimate S/N
@ 60 dBµV, stereo
DocID026122 Rev 5
35/54
53
Electrical specifications
TDA7786, TDA7786M
Table 26. FM overall system performance (continued)
Parameter
Test condition
Deviation= 75 kHz
Min
Typ
Max
Units
Distortion
–
0.05
166
0.1
–
%
Max deviation
THD=3%
150
kHz
∆
F =100 kHz, SINAD=30 dB
Desired 40 dBµ
V
,
dev = 40 kHz, 400 Hz
undesired Dev=40 kHz,
1 kHz
Adjacent channel Selectivity
(D/U ratio)
20
30
–
dB
∆
F = 200 kHz, SINAD=30 dB
Desired 40 dBµ
V
,
dev = 40 kHz, 400 Hz
undesired Dev=40 kHz,
1 kHz
Alternate Channel Selectivity
(D/U ratio)
52
75
62
80
–
–
dB
dB
Desired = 40 dBµV
SINAD = 30 dB
Max. Strong Signal Interferer
(D/U ratio)
Undesired
F = 1MHz
Desired = 40 dBµV, dev =
40 kHz, 400 Hz,
SINAD = 30 dB
Undesired1 = ± 400 kHz,
dev = 40 kHz, 1 kHz
101
105
106
110
–
–
dBµV
dBµV
Undesired2 = ± 800 kHz, no
mod
3 signal performance
(“wide-band”) application
Desired = 40 dBµV,
dev = 40 kHz, 400 Hz,
SINAD = 30 dB
Undesired1 = ±1 MHz,
dev = 40 kHz, 1 kHz
Undesired2 =±2MHz, no mod
AM suppression
m= 30 %
60
70
–
dB
–
-0.41
-0.35
(equiva
lent to
37
(equiv
alent
to 43
@40 dBµV
Logarithmic field strength
indicator
-0.38
read “FM_Smeter_log”
dBµV)
dBµV)
36/54
DocID026122 Rev 5
TDA7786, TDA7786M
Electrical specifications
3.5.2
AM MW overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms
Figure 20. AM MW input set-up
ꢂꢁ
:
ꢊꢋ P&
ꢋꢁ
:
0#”
5.$%2
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6
R
F
‘!0’03ꢀꢀꢈꢈꢃ
Level referred to SG EMF output before antenna dummy; dummy antenna load as shown
above F
= 999 kHz (1000 kHz for US), V
=74 dBµV, mod = 30 %, f
=400 Hz, unless
rf
rf
audio
otherwise specified.
Table 27. AM MW overall system performance
Parameter
Test condition
Min
Typ
Max
Units
Tuning range MW Eu/Jp
Tuning step MW Eu/Jp
Tuning range MW US
Tuning step MW US
Sensitivity
(can be modified by the user)
(can be modified by the user)
(can be modified by the user)
(can be modified by the user)
S/N = 20 dB
531
–
1629
kHz
kHz
kHz
kHz
dBµV
dB
–
530
–
9
–
–
1710
10
25
72
–
28
–
–
Ultimate S/N
@ 80 dBµV
67
Ref.=74 dBµV
(1)
AGC
F
.
O.M.
64
0.1
47
–
0.2
–
dB
%
-10dB drop point
Distortion
M=80%
–
∆
F = 9 kHz, SINAD = 26 dB
undesired M = 30 % 1 kHz
Adjacent channel selectivity
44
dB
∆
F = 18 kHz, SINAD = 26 dB
undesired M = 30 % 1 kHz
Alternate channel selectivity
48
8
51
12
–
–
dB
dB
∆
F = ±40 kHz
Strong signal interferer (1)
SNR
desired = 40 dBµV
undesired = 110 dBµV,
m = 30 % 1 kHz
∆
F = ±40 kHz
Strong signal interferer (1)
suppression
desired = 40 dBµV
–
–
10
15
dB
dB
undesired = 110 dBµV,
m = 30 % 1 kHz
∆
F = ±40 kHz
desired = 80 dBµV
Strong signal interferer (1)
cross-modulation
undesired = 110 dBµV,
m = 30 % 1 kHz
1
4
maximum SNR of undesired
channel
DocID026122 Rev 5
37/54
53
Electrical specifications
TDA7786, TDA7786M
Table 27. AM MW overall system performance (continued)
Parameter
Test condition
Min
Typ
Max
Units
∆
F = ±400 kHz
Strong signal interferer (2)
SNR
desired = 40 dBµV
5
11
–
dB
undesired = 110 dBµV,
m = 30 %, 1 kHz
∆
F = ±400 kHz
Strong signal interferer (2)
suppression
desired = 40 dBµV
–
–
15
18
dB
dB
undesired = 110 dBµV,
m = 30 %, 1 kHz
∆
F = ±400 kHz
desired = 80 dBµV
Strong signal interferer (2)
cross-modulation
undesired = 110 dBµV,
m = 30 %, 1 kHz
1
4
maximum SNR of undesired
channel
Desired = 40 dBµV
SINAD = 26dB, blocking<6dB
Max. strong signal interferer
Image rejection
90
98
80
–
dB
µV
Undesired
∆
F = 400 kHz,
m = 30 % (crossmod.
T
e
st)
–
60
–
dB
-0.47
-0.41
(equiva
lent to
57
(equiv
alent
to 63
Logarithmic field strength
indicator
@60 dBµV read
“AM_SMeter_log”
-0.44
–
dBµV
dBµV)
1. Programmable
by software parameters.
38/54
DocID026122 Rev 5
TDA7786, TDA7786M
Electrical specifications
3.5.3
AM LW overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms
Figure 21. AM LW input set-up
ꢂꢁ
:
ꢊꢋ P&
ꢋꢁ
:
0#”
5.$%2
4%34
ꢃꢋ P&
6
R
F
‘!0’03ꢀꢀꢈꢈꢁ
Level referred to SG EMF output before antenna dummy; dummy antenna load as shown
above F
=216 kHz, V
=74 dBµV, mod = 30 %, f
= 400 Hz, unless otherwise specified.
rf
rf
audio
Table 28. AM LW overall system performance
Parameter
Test condition
Min
Typ
Max
Units
Tuning range LW
Tuning step LW
Sensitivity
(can be modified by the user)
(can be modified by the user)
S/N = 20 dB
144
–
288
kHz
kHz
dBµV
dB
–
–
1
–
34
–
30
70
Ultimate S/N
@ 80 dBµV
63
Ref. = 74 dBµV
-10dB drop point
(1)
AGC
F
.
O.M.
64
–
dB
Distortion
M= 80 %
–
–
0.1
80
0.2
–
%
Image rejection
60
dB
1. Programmable
by software parameters.
3.5.4
AM SW overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms
Figure 22. AM SW input set-up
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Level referred to SG EMF output before antenna dummy; dummy antenna load as shown
above; F
= 6000 kHz, V
=74 dBµV, mod = 30 %, f
= 400 Hz, unless otherwise
rf
rf
audio
specified.
DocID026122 Rev 5
39/54
53
Electrical specifications
TDA7786, TDA7786M
Table 29. AM SW overall system performance
Parameter
Test condition
Min
Typ
Max
Units
Tuning range SW
Tuning step SW
Sensitivity
(can be modified by the user)
2300
–
30000
kHz
kHz
dBµV
dB
(can be modified by the user)
S/N = 20 dB
–
–
1
–
32
–
26
70
Ultimate S/N
@ 80 dBµV
63
Ref.=74 dBµV
(1)
AGC
F
.
O.M.
58
–
dB
-10 dB drop point
Distortion
M = 80%
–
–
0.1
80
0.2
–
%
Image rejection
60
dB
1. Programmable
by software parameters.
3.5.5
WX overall system performance
Antenna level equivalence: 0 dBµV = 1 µVrms (Antenna terminal voltage with 75
dummy
load).
Figure 23. WX input set-up
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Input level referred to 75
dummy antenna output; antenna dummy as shown above.
F =
162.475 MHz, V
= 60 dBµV, mono modulation, f
= 3 kHz, f
= 400 Hz audio.
rf
rf
dev
audio
De-emphasis = 75 µs. Application WX using mixer input 2.Unless otherwise specified.
Table 30. WX overall system performance
Parameter
Sensitivity
Test condition
S/N = 26 dB
Min
Typ
Max
Units
–
70
–
-6
81
0.8
–
-3
–
dBµV
dB
Ultimate S/N
Distortion
@ 60 dBµV
Deviation= 4.5 kHz
THD = 3%
1
–
%
Max deviation
5
kHz
∆
F = 25 kHz, SINAD = 30dB
desired 40 dBµV,
dev = 2.0 kHz, 400 Hz
undesired Dev = 2.0 kHz,
1 kHz
Adjacent channel Selectivity
Alternate Channel Selectivity
60
60
70
70
–
–
dB
dB
∆
F = 50 kHz, SINAD = 30dB
desired 40 dBµV,
dev = 2.0 kHz, 400 Hz
undesired Dev = 2.0 kHz,
1 kHz
40/54
DocID026122 Rev 5
TDA7786, TDA7786M
Front-end registers
4
Front-end registers
All the parameters in this section refer to the programmability of the FE part of the device
(registers). The part of the registers that are not described here have either fixed values or
values written by the tuner drivers, and are described in the proper technical documentation.
Table 31. Register 0x00
Register number
Register definition
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
AM mixer input selector
0
1
1 Input
#1
0 Input
#2
AM PIN diode
0
1
Internal
External
AM AGC mode
0
1
LNA and PIN diode
PIN diode only
AM AGC time constant
Slow (125 ms with 1 µF)
Medium (25ms with 1 µF)
Fast (5ms with 1 µF)
AM AGC thresholds @ mixin
90.2 dBµV @ mixin
92.0 dBµV @ mixin
93.8 dBµV @ mixin
95.6 dBµV @ mixin
88.4 dBµV @ mixin
86.6 dBµV @ mixin
84.8 dBµV @ mixin
83 dBµV @ mixin
AM AGC attack time constant
Normal
0
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Fast
DocID026122 Rev 5
41/54
53
Front-end registers
TDA7786, TDA7786M
Register definition
Table 32. Register 0x01
Register number
MSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
LSB
8
7
6
5
4
3
2
1 0
FM mixer RF-gain
35 dB
0
0
1
1
0
1
0
1
38 dB
39 dB
41 dB
FM mixer input
Input #1 (single-ended)
Input #2 (single-ended)
Input #1/2 (differential)
FM AGC output mode
Normal
0
1
1
1
0
1
0
0
1
0
1
1
Constant 15mA
Constant 1mA
42/54
DocID026122 Rev 5
TDA7786, TDA7786M
Front-end registers
Table 33. Register 0x02
Register Number
MSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
LSB
1
Register Definition
8
7
6
5
4
3
2
0
FM RF AGCThresholds@ mixin
0
0
1
1
0
0
1
1
0 88.4
dBµV
1 90.2
dBµV
0 92.0
dBµV
1 93.8
dBµV
0 91.4
dBµV
1 93.2
dBµV
0 95.0
dBµV
1 96.8
dBµV
Reg 0x008<14> = 1
Reg 0x008<14> = 0
FM IFAGC threshold@IFADCin
0
0
1
1
0
1
0
1
122 dBµV
124 dBµV
126 dBµV
128 dBµV
FMAGC attack time constant
0
1
slow
fast
FMAGC decay time constant
0
1
slow
fast
FM DAC
0
1
off
on
FM DAC VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
… … … … … … … …
…
255
1
1
1
1
1
1 1 1
DocID026122 Rev 5
43/54
53
Front-end registers
TDA7786, TDA7786M
Register Definition
Table 34. Register 0x05
Register Number
MSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
LSB
1
8
7
6
5
4
3
2
0
GPODATA
0 low
1 high
Table 35. Register 0x08
Register number
MSB
LSB
Register definition
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8 7 6 5 4 3 2 1 0
FMAGC gain select
0
1
FM AGC thresholds high
FM AGC thresholds down
44/54
DocID026122 Rev 5
TDA7786, TDA7786M
Weak signal processing
5
Weak signal processing
All the parameters in this section refer to the programmability of the DSP part of the device.
The typical values are those set by default parameters (start-up without parametric change
from main microprocessor); the max and the min values refer to the programmability range.
The values are referred to the typical application (‘wide-band’ in FM). Wherever the possible
values are a discrete set, all the possible programmable values are displayed.
5.1
FM IF-processing
5.1.1
Dynamic channel selection filter (DISS)
Table 36. Dynamic channel selection filter (DISS) – discrete set
Symbol
Parameter
IF filter #10
Test condition
Min
Typ
Max
Units
–
–
–
–
±150
±120
±100
±85
±75
±65
±60
±55
±45
±35
±25
–
–
–
–
–
–
–
–
–
–
–
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
IF filter #9
IF filter #8
IF filter #7
IF filter #6
DISS BW
IF filter #5
IF filter #4
response: – 3dB
IF filter #3
IF filter #2
–
–
–
IF filter #1
IF filter #0
5.1.2
Soft mute
Table 37. Soft mute – continuous set
Parameter Test
condition
audio atten = 1 dB
Symbol
Min
Typ
Max
Units
SMsp
Start point vs. field strength
read “FM_SoftMute”
0
6
20
10
dBµV
no adjacent channel present
audio atten = SMd + 1 dB
read “FM_SoftMute”
SMep
End point vs. field strength
Depth
-6
-6
dBµV
no adjacent channel present
SMd
-30
0.1
-15
0
dB
Hz
Field strength LPF cut-off
frequency for soft mute activation
SMtauatt
100
4000
Field strength LPF cut-off
frequency for soft mute release
SMtaurel
0.1
1
4000
Hz
DocID026122 Rev 5
45/54
53
Weak signal processing
TDA7786, TDA7786M
5.1.3
Adjacent channel mute
Table 38. Adjacent channel mute – continuous set
Symbol
ACMd
Parameter
Test condition
Min
Typ
Max
Units
Depth
–
SMd
0
0
dB
5.1.4
Stereo blend
Table 39. Stereo blend – continuous set
Symbol
Parameter
Test condition
Min
Typ
Max
Units
field strength = 80 dBµ
V
,
p
ilot
deviation = 6.75 kHz
MaxSep
Maximum stereo separation
Start point vs. field strength
0
40
50
dB
separation = MaxSep – 1 dB
no multipath present
SBFSsp
SBFSep
20
20
50
30
60
60
dBµV
dBµV
separation = 1 dB
End point vs. field strength
Field strength-related
no multipath present
V
rf
step-like variation from
20 dBµV to 80 dBµV
SBFStM2S transition
time from mono to
stereo
0.001
0.001
3
20
20
s
s
Field strength-related
SBFStS2M transition
time from stereo to
mono
V
rf
step-like variation from
80 dBµV to 20 dBµV
0.5
separation = MaxSep – 1 dB
equivalent 19 kHz AM
modulation depth;
SBMPsp Start
point vs. multipath
SBMPep End
point vs. multipath
5
5
10
30
80
80
%
%
field strength = 80 dBµV
separation = 1 dB
equivalent 19 kHz AM
modulation depth;
field strength = 80 dBµV
Multipath-related transition
SBMPtM2S
V
rf
step-like variation from
20 dBµV to 80 dBµV
0.001
0.001
1
20
20
s
s
time from mono to stereo
Multipath-related transition
SBMPtS2M
V
rf
step-like variation from
80 dBµV to 20 dBµV
0.001
time from stereo to mono
Threshold on pilot tone
Pil ThrM2S
Pilot detector stereo threshold
deviation for mono-stereo
transition
0.8
–
2.74
0.01
–
–
kHz
kHz
Difference in Pil. det.
Pilot detector threshold
hysteresis
deviation threshold for stereo
to mono transition compared
to PilThrM2S
Pil ThrHyst
46/54
DocID026122 Rev 5
TDA7786, TDA7786M
Weak signal processing
5.1.5
High cut control
Table 40. High cut control – continuous set
Symbol
Parameter
Test condition
Min
Typ
Max
Units
minimum RF level for widest
HC filter (filter # 7)
HCFSsp
HCFSep
Start point vs. field strength
0
50
50
dBµV
no multipath present
maximum RF level for
narrowest HC filter (filter # 0)
End point vs. field strength
Field strength-related
0
30
40
dBµV
no multipath present
V
rf
step-like variation from
60 dBµV to 10 dBµV
(1)
HCFStW2N transition
time from wide to
narrow band
–
Field strength-related
HCFStN2W transition
time from narrow to
wide band
V
rf
step-like variation from
0 dBµV to 60 dBµV
(1)
14
10
100
s
minimum RF level for widest
HC filter (filter # 7)
HCMPsp Start
point vs. multipath
HCMPep End
point vs. multipath
equivalent 19 kHz AM
modulation depth;
5
150
(2)
%
%
field strength = 80 dBµV
maximum RF level for
narrowest HC filter (filter # 0)
equivalent 19 kHz AM
modulation depth;
5
30
150
(2)
field strength = 80 dBµV
Multipath-related transition
HCMPtN2W time
from narrow to wide
band
V
rf
step-like variation from
20 dBµV to 80 dBµV
0.001
0.001
0.001
0.001
14
20
20
18
s
s
Multipath-related transition
HCMPtW2N
V
rf
step-like variation from
80 dBµV to 20 dBµV
time from wide to narrow
Filter #7, -3 dB response
frequency, input signal with
pre-emphasis
Maximum cut-off frequency of
HCmaxBW
HCmin
BW
kHz
high cut filter bank
Filter #0, -3 dB response
frequency, input signal with
pre-emphasis
Minimum cut-off frequency of
HCminBW
HCma
xBW
0.1
–
3
kHz
–
high cut filter bank
HCnumFilt Number
of discrete HC filters
–
8
(3)
–
1. Depends
only on field strength filter time constant.
2. Means
that 100% equivalent 19 kHz AM modulation depth will not achieve full band narrowing.
3. Intermediate
filters (#6 – #1) cut-off frequencies exponentially spaced between HCmaxBW and HCminBW.
DocID026122 Rev 5
47/54
53
Weak signal processing
TDA7786, TDA7786M
Table 41. De-emphasis filter – continuous set
Symbol
Parameter
Test condition
Min
Typ
Max
Units
De-emphasis time constant 1
De-emphasis time constant 2
–
–
–
–
50
75
–
–
DEtc
µs
5.1.6
Stereo decoder
Table 42. Stereo decoder – continuous set
Symbol
Parameter
Test condition
Min
Typ
Max
Units
PilSup
Pilot signal suppression
Pilot 9%, 19 kHz, ref = 40 kHz
f = 38 kHz
–
–
–
–
60
70
70
80
–
–
–
–
dB
dB
dB
dB
SubcSup Subcarrier
suppression
f = 57 kHz
f = 76 kHz
5.2
AM IF-processing
5.2.1
Channel selection filter
Table 43. Channel selection filter
Test condition
Symbol
Parameter
Min
Typ
Max
Units
CSF BW
Channel selection filter BW
response: – 3dB
–
±3.7
–
kHz
5.2.2
Soft mute
Table 44. Soft mute – continuous set
Test condition
Symbol
Parameter
Min
Typ
Max
Units
audio atten = 1 dB
SMsp
Start point vs. field strength
End point vs. field strength
read “FM_SoftMute”
0
25
40
dBµV
no adjacent channel present
audio atten = SMd + 1 dB
read “FM_SoftMute”
SMep
SMd
0
0
30
dBµV
no adjacent channel present
Depth
–
-40
-24
0.1
0
dB
s
Transition time for field
SMtauatt strength-dependent
soft mute
activation
–
0.001
10
Transition time for field
SMtaurel strength-dependent
soft mute
release
–
0.001
3
10
s
48/54
DocID026122 Rev 5
TDA7786, TDA7786M
Weak signal processing
5.2.3
High cut control
Table 45. High cut control – continuous set
Symbol
Parameter
Test condition
Min
Typ
Max
Units
minimum RF level for widest
HC filter (filter # 7)
HCFSsp
HCFSep
Start point vs. field strength
0
40
50
dBµV
no multipath present
maximum RF level for
narrowest HC filter (filter # 0)
End point vs. field strength
Field strength-related
0
30
0.2
10
14
50
20
20
18
dBµV
s
no multipath present
V
rf
step-like variation from
60 dBµV to 10 dBµV
HCFStW2N transition
time from wide to
narrow band
0.001
0.001
Field strength-related
HCFStN2W transition
time from narrow to
wide band
V
rf
step-like variation from
0 dBµV to 60 dBµV
s
Filter #7, -3 dB response
frequency, input signal with
pre-emphasis
Maximum cut-off frequency of
HCmaxBW
HCmin
BW
kHz
high cut filter bank
Filter #0, -3 dB response
frequency, input signal with
pre-emphasis
Minimum cut-off frequency of
HCminBW
HCma
xBW
1
–
3
8
kHz
–
high cut filter bank
HCnumFilt Number
of discrete HC filters
–
–
DocID026122 Rev 5
49/54
53
6
Basic
application schematic
Figure 24. FM wide-band application
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TDA7786, TDA7786M
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages,
depending on their level of environmental compliance. ECOPACK
®
ECOPACK is
an ST trademark.
7.1
LQFP64 (10x10x1.4 mm) package information
Figure 25. LQFP64 (10x10x1.4 mm) package outline
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DocID026122 Rev 5
51/54
53
Package information
TDA7786, TDA7786M
Table 46. LQFP64 (10x10x1.4 mm) package mechanical data
Dimensions
Ref
Millimeters
Typ.
Inches
(1)
Typ.
Min.
Max.
Min.
Max.
A
A1
A2
b
–
0.05
1.350
0.17
0.09
11.80
9.80
–
–
1.60
0.15
1.45
0.27
0.20
12.20
10.20
–
–
–
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
–
–
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
–
–
1.40
0.22
–
0.0551
0.0087
–
c
D
12.00
10.00
7.50
12.00
10.00
7.50
0.50
0.60
1.00
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
0.0236
0.0394
D1
D3
E
11.80
9.80
–
12.20
10.20
–
0.4646
0.3858
–
0.4803
0.4016
–
E1
E3
e
–
–
–
–
L
0.45
–
0.75
–
0.0177
–
0.0295
–
L1
K
0° (min.), 3.5° (typ.) 7° (max.)
0.08
ccc
–
–
–
–
0.0031
1. Values
in inches are converted from mm and rounded to 4 decimal digits.
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Revision history
8
Revision history
Table 47. Document revision history
Changes
Date
Revision
24-Mar-2014
1
Initial release.
29-May-2014
2
Document status promoted from preliminary data to production data.
27
Ω
.
23-Feb-2016
3
Updated:
to 27
Ω
);
Updated:
– Title in cover page;
27-May-2016
4
Removed section 2.14 Antenna switching.
The publication scope change from internal to public document, no
content change.
05-Oct-2016
5
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