Tagore-Technology-TA9410E
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TA9410E
Preliminary
TA9410E
–
25W CW, 50V, 20 – 3000MHz GaN Power Transistor
1.0 Features
●
Small signal gain @ 1000MHz: 20dB
●
Gain at P3dB @ 1000MHz: 17dB
●
P3dB @ 1000MHz: 44dBm
●
PAE @ P3dB @ 1000MHz: 57%
●
50V Typical operation
● Operating frequency:
20MHz to 3.0GHz
Figure 1.1 Device Image
(8 Pin 6×5×0.8mm QFN Package)
2.0 Applications
●
Private mobile radio handsets
●
Public safety radios
●
Cellular infrastructure
●
Military radios
RoHS/REACH/Halogen Free
Compliance
3.0 Description
The TA9410E is a broadband GaN power transistor capable
of delivering 25W CW from 20MHz to 3.0GHz frequency band.
The input and output can be matched for best power and
efficiency for the desired band.
The TA9410E is packaged in a compact, low cost Quad Flat
No lead (QFN) 5x6x0.8mm, 8 leads plastic package.
Figure 3.1 Function Block Diagram
(Top View)
4.0 Ordering Information
Table 4.1 Ordering Information
Base Part
Reel
Diameter
Reel
Width
Orderable
Part Number
Package Type
Form
Qty
Number
8 Pin 5×6×0.8mm
QFN
TA9410E
Tape and Reel
1000
13” (330mm)
18mm
TA9410EMTRPBF
Tuned Evaluation Board, 20 – 525MHz
Tuned Evaluation Board, 20 – 1000MHz
TA9410E-EVB-A
TA9410E-EVB-B
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TA9410E
Preliminary
5.0 Pin Description
Table 5.1 Pin Definition
Pin Number
Pin Name
NC
V
GG
& RF
IN
V
DD
& RF
OUT
Paddle/Slug
Description
1, 4, 5, 8
2, 3
No internal connection, Can be grounded
Gate voltage and RF input
Drain voltage and RF output
Ground
6, 7
9
[1]
Note:
[1] The backside ground slug of the device must be grounded directly to the ground plane through
multiple vias to ensure proper operation.
Adequate heatsinking required.
6.0 Absolute Maximum Ratings
Table 6.1 Absolute Maximum Ratings
@T
A
=+25°C Unless Otherwise Specified
Parameter
Symbol
Value
Unit
Electrical Ratings
Breakdown voltage
Gate voltage
V
DS
V
GS
I
DS
+150
-10 to +2.0
3.0
V
V
Drain current
A
Gate current
I
GS
5.2
mA
W
Power dissipation CW
P
diss
RF
IN
T
st
28
RF input power CW, 20-1000MHz
Storage Temperature Range
Operating Temperature Range
Maximum Junction Temperature
29
dBm
°C
°C
°C
-55 to +150
-40 to +85
+225
T
op
T
J
Thermal Ratings
Thermal Resistance (junction-to-case)
–
Bottom side
R
θJC
5.0
°C/W
°C
Soldering Temperature
T
SOLD
260
ESD Ratings
Human Body Model (HBM)
Level 1A
Level C1
250 to <500
250 to <500
V
V
Charged Device Model (CDM)
Moisture Rating
Moisture Sensitivity Level
MSL
1
–
Attention:
Maximum ratings are absolute ratings. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Exceeding one or a combination of the absolute maximum ratings
may cause permanent and irreversible damage to the device and/or to surrounding circuit.
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TA9410E
Preliminary
7.0 RF Electrical Specifications
Table 7.1 Electrical Specifications
@T
A
=+25°C Unless Otherwise Specified;
Parameter
Small Signal Gain
Large Signal Gain
P3dB
Condition
Minimum Typical Maximum
Unit
1000MHz
20
17
44
57
50
dB
dB
dBm
%
P
OUT
= 44dBm, 1000MHz
1000MHz
Power Added Efficiency (PAE)
Drain Voltage
P
OUT
= 44dBm
V
All phase, P
OUT
= 44dBm,
1000MHz
Ruggedness
VSWR 10:1
Note:
Data taken from 20 – 1000MHz broadband reference design (EVB), V
D
=+50V; I
DQ
=50mA, CW
8.0 Recommended Operating Conditions
Table 8.1 Recommended Operating Conditions
Parameter
Symbol
Minimum Typical Maximum
Unit
Drain Voltage
V
DD
+50
-2.75
50
V
V
Gate Voltage
V
GG
-3.3
-2.1
Drain Bias Current
Drain Current
Power Dissipation CW
[1]
Operating Temperature Range
Note:
[1] @TC = +85
°C
I
DQ
mA
mA
W
I
DS,
Pout = 44dBm, 1000MHz
P
diss,
Pout = 44dBm, 1000MHz
880
20
25
-40
+25
+85
°C
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TA9410E
Preliminary
9.0 Typical Characteristics
9.1 20 – 1000MHz EVB (Vdd = 50V, Idq = 50mA, CW)
Figure 9.1 Small Signal SParameters (T
A
=+25°C)
Figure 9.2 Gain and PAE vs P
OUT
(T
A
=+25°C)
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TA9410E
Preliminary
Figure 9.2 IRL and Pdiss vs P
OUT
(T
A
=+25°C)
Figure 9.3 Gain and PAE vs P
OUT
over temperature at 20MHz
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TA9410E
Preliminary
Figure 9.4 Gain and PAE vs P
OUT
over temperature at 525MHz
Figure 9.5 Gain and PAE vs P
OUT
over temperature at 1000MHz
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TA9410E
Preliminary
Figure 9.6 IMD3 vs P
OUT
(Vdd=50V, Idq = 50mA, 1MHz tone spacing)
Figure 9.7 IMD5 vs P
OUT
(Vdd=50V, Idq = 50mA, 1MHz tone spacing)
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TA9410E
Preliminary
Figure 9.8 IMD3 vs P
OUT
(Vdd=50V, Idq = 75mA, 1MHz tone spacing)
Figure 9.10 IMD5 vs P
OUT
(Vdd=50V, Idq = 75mA, 1MHz tone spacing)
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TA9410E
Preliminary
9.2 20
–
525MHz EVB (Vdd = 50V, Idq = 50mA, CW)
Figure 9.11 Small Signal SParameters (T
A
=+25°C)
Figure 9.12 Gain and PAE vs P
OUT
(T
A
=+25°C)
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TA9410E
Preliminary
Figure 9.13 IRL and Pdiss vs P
OUT
(T
A
=+25°C)
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TA9410E
Preliminary
10.0 Bias and Sequencing
Table 10.1 Bias and Sequencing
Turn ON Device
Turn OFF Device
1. Set V
G
to -5V
1. Turn RF power off
2. Set V
D
to +50V
3. Adjust V
G
to reach required I
DQ
current
4. Apply RF power
2. Turn off V
D
3. Turn off V
G
11.0 Evaluation Boards
11.1 20 – 1000MHz EVB
Vgg
Vdd
+50V
C24
-ve
..
7.5V ZENER
4.7uF
C21
D11
C14
0.1uF
..
0.1uF
R12
24.9ohms
L21
1.3uH
C11
R11
L23
C23
L11
L12
3.3nH
6.9nH
6.8nH
4.7nF
C12
3.6ohms
C22 4.7nF
2.2pF
Q1
C13
.. 8.2pF
.. 4.7pF
Figure 11.1 Schematic of the 20 – 1000MHz EVB
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TA9410E
Preliminary
Note : Pins 4 and 5 can be grounded
Figure 11.2 Board Layout of the 20 – 1000MHz EVB
Table 11.1 BOM of the 20 – 1000MHz EVB
Component ID
C11, C23
C12
Value
4.7nF, 100V
4.7pF
Manufacturer
Murata
Recommended Part Number
GCD188R72A472KA01
600S4R7BT250XT
0603HP-6N8XJLC
0603HP-3N3XJLC
600S8R2CT250XT
GRM31C5C2A104JA01
4310LC-132KEC
ATC
L11
6.8nH
Coilcraft
L12
3.3nH
Coilcraft
C13
8.2pF
ATC
C14, C21
L21
0.1uF, 100V
1.3uH
Murata
Coilcraft
C24
4.7uf, 100V
6.9nH
Murata
GCM32DC72A475KE02
0807SQ-6N9JLC
L23
Coilcraft
C22
2.2pF
ATC
600S2R2BT250XT
ERJ-P06J3R6V
R11
3.6Ω, 0.5W
24.9Ω, 0.75W
7.5 V Zener
Panasonic
Vishay
R12
CRCW121024R9FKEAHP
SZMMSZ5236BT 1G
TA9410E
D11
On Semiconductor
Tagore Technology
Q1
PCB
Rogers RO4350B, 20 mils, 2 oz copper
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TA9410E
Preliminary
11.2 20 – 525MHz EVB
Vgg
-ve
Vdd
C24
+50V
..
7.5V ZENER
4.7uF
C21
D11
C14
0.1uF
..
0.1uF
L21
1.3uH
R12
24.9ohms
C11
L11
R11
L23
C23
L12
10nH
6.8nH
3.3nH
4.7nF
C12
3.6ohms
C22 4.7nF
2.0pF
Q1
C13
.. 8.2pF
.. 4.7pF
Figure 11.3 Schematic of the 20 – 525MHz EVB
Note : Pins 4 and 5 can be grounded
Figure 11.4 Board Layout of the 20 – 525MHz EVB
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TA9410E
Preliminary
Table 11.2 BOM of the 20 – 525MHz EVB
Component ID
C11, C23
C12
Value
4.7nF, 100V
4.7pF
Manufacturer
Murata
Recommended Part Number
GCD188R72A472KA01
600S4R7BT250XT
0603HP-6N8XJLC
0603HP-3N3XJLC
600S8R2CT250XT
GRM31C5C2A104JA01
4310LC-132KEC
ATC
L11
6.8nH
Coilcraft
L12
3.3nH
Coilcraft
C13
8.2pF
ATC
C14, C21
L21
0.1uF, 100V
1.3uH
Murata
Coilcraft
C24
4.7uf, 100V
10nH
Murata
GCM32DC72A475KE02
0807SQ-10NJLC
L23
Coilcraft
C22
2.0pF
ATC
600S2R0BT250XT
ERJ-P06J3R6V
R11
3.6Ω, 0.5W
24.9Ω, 0.75W
7.5 V Zener
Panasonic
Vishay
R12
CRCW121024R9FKEAHP
SZMMSZ5236BT 1G
TA9410E
D11
On Semiconductor
Tagore Technology
Q1
PCB
Rogers RO4350B, 20 mils, 2 oz copper
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TA9410E
Preliminary
12.0 Device Package Information
Figure 12.1 Device Package Drawing
(All dimensions are in mm)
Table 12.1 Device Package Dimensions
Dimension
(mm)
Value
(mm)
Tolerance
(mm)
Dimension
(mm)
Value
(mm)
Tolerance
(mm)
±0.05
A
A1
b
0.80
0.203
±0.05
±0.02
E
E1
F
5.00 BSC
4.00
±0.05
0.40
+0.05/-0.07
±0.05
0.395
0.60
±0.05
D
6.00 BSC
3.40
L
±0.05
D1
e
±0.05
K
0.70
±0.05
1.27 BSC
±0.05
Note:
Lead finish: Pure Sn without underlayer; Thickness: 7.5μm ~ 20μm (Typical 10μm ~ 12μm)
Attention:
soldering related guidelines.
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TA9410E
Preliminary
13.0 PCB Land Design
Guidelines:
[1] 2-layer PCB is recommended.
[2] Via diameter is recommended to be 0.3mm to prevent solder wicking inside the vias
[3] Thermal vias shall only be placed on the center pad
[4] The maximum via number for the center pad is 7(X)×8(Y)=56
Figure 13.1 PCB Land Pattern
(Dimensions are in mm)
Non-Solder Mask Defined
(Preferred)
Solder Mask Defined
Figure 13.2 Solder Mask Pattern
(Dimensions are in mm)
Figure 13.3 Thermal Via Pattern
(Recommended Values: S≥0.15
mm
; Y≥0.20
mm; d=0.3mm; Plating Thickness
t=25μm or 50μm)
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TA9410E
Preliminary
14.0 PCB Stencil Design
Guidelines:
[1] Laser-cut, stainless steel stencil is recommended with electro-polished trapezoidal walls to improve
the paste release.
[2] Stencil thickness is recommended to be 125
μm
.
Figure 14.1 Stencil Openings
(Dimensions are in mm)
Figure 14.2 Stencil Openings Shall not Cover Via Areas If Possible
(Dimensions are in mm)
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TA9410E
Preliminary
15.0 Tape and Reel Information
Figure 15.1 Tape and Reel Drawing
Table 15.1 Tape and Reel Dimensions
Dimension
(mm)
Value
(mm)
Tolerance
(mm)
Dimension
(mm)
Value
(mm)
Tolerance
(mm)
±0.10
A0
B0
D0
D1
E
6.35
5.35
1.50
1.50
1.75
5.50
±0.10
±0.10
K0
P0
P1
P2
T
1.10
4.00
8.00
2.00
0.30
12.00
±0.10
+0.10/-0.00
+0.10/-0.00
±0.10
±0.10
±0.05
±0.05
F
±0.05
W
±0.30
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TA9410E
Preliminary
Edition Revision 1.0 – 2021-03-18
Published by
Tagore Technology Inc.
5 East College Drive, Suite 200
Arlington Heights, IL 60004, USA
©2020 All Rights Reserved
Legal Disclaimer
The information provided in this document shall in no event be regarded as a guarantee of conditions or
characteristics. Tagore Technology assumes no responsibility for the consequences of the use of this
information, nor for any infringement of patents or of other rights of third parties which may result from
the use of this information. No license is granted by implication or otherwise under any patent or patent
rights of Tagore Technology. The specifications mentioned in this document are subject to cha
n
g
e
without notice.
Information
For further information on technology, delivery terms and conditions and prices, please contact Tagore
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