Texas-Instruments-AFEDRI8201PFBT
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AFEDRI8201
SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
IF ADC Front End for AM/FM and HD Radios
F
D
EATURES
DESCRIPTION
The AFEDRI8201 implements the receive channel analog
functions required for intermediate-frequency (IF)
sampled AM/FM and HD digital radio receivers. It is
designed to be used with TI’s DRIx50 digital baseband
processor. The AFEDRI8201 is programmed by the
DRIx50 for use in AM/FM and HD radio. The AFEDRI8201
oversamples the radio tuner IF output at speeds of up to
80MHz to reduce noise and improve dynamic range. The
radio tuner output IF is typically 10.7MHz for AM or FM as
well as 450kHz or 455kHz for AM, as desired. The
AFEDRI8201 then mixes, filters, and decimates the signal
to provide baseband I and Q output signals to the digital
baseband processor. The AFEDRI8201 also includes a
general-purpose 12-bit control digital-to-analog converter
(DAC) to provide a gain control signal or other analog
feedback to the tuner.
Interfaces To Texas Instruments DRIx50 HD
Radio Baseband Processors
D
12-Bit, 80MSPS ADC Reduces Noise and
Improves Sensitivity
D
Typical SNR of 102dB in 3kHz Bandwidth
D
Programmable Input Range For Optimum
Tuner Dynamic Range
D
Integrated Digital Downconverter (DDC)
− Quadrature
Mixer, NCO, CIC Decimation
Filter, And FIR Filters
D
D
D
Mixer: 32-Bit Frequency and Phase
Decimation Ratio: 32 to 4096
User-Programmable FIR Filters with 16-Bit
Coefficients
D
12-Bit Auxiliary DAC
The DRIx50 digital baseband device writes control register
data as well as decimation filter coefficients to the
AFEDRI8201 through the industry-standard SPI control
interface. The baseband output signals are transported to
the DRIx50 through a general-purpose, high-speed serial
interface (TI’s Buffered Serial Ports, McBSP).
D
Code Composer Module for Easy Software
Generation
SPI
Control Interface
D
A
D
PPLICATIONS
This unit uses 3.3V analog and 1.8V digital power
supplies. Typical power dissipation is 490mW. The digital
I/O lines can be powered by a 3.3V supply.
AM/FM and HD Radio Receivers
IF Receive Channels
Software Radios
D
D
D
Narrowband Receivers
DOUT0
IFP
12
−
B
it
Pipeline
ADC
Quadrature
Mixer
CIC Filter
N
FIR Filter 1
2
FIR Filter 2A
2
DOUT1
DFSO
DCLK
DIN
IFM
NCO
FIR Filter 2B
2
Auxiliary
DAC
AUX
DFSI
Voltage
Reference
Clock
Interface
Timing
Generator
SPI Control
Interface
REFM VCM REFP VGB
MCLK MCLKB PWD SYNC
RESET
SCK MOSI
MISO CS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
T
e
xas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.
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Copyright
2003−2005,
T
e
xas Instruments Incorporated
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
(1)
ORDERING INFORMATION
SPECIFIED
TEMPER
A
T
URE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE-LEAD
AFEDRI8201PFBT
T
a
pe and Reel, 250
AFEDRI8201
TQFP-48
PFB
−40
°
C to +85
°
C
DRI8201
AFEDRI8201PFBR
T
a
pe
and Reel, 2000
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website
This integrated circuit can be damaged by ESD.
T
e
xas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
AFEDRI8201
−0.5 to 4.0
UNIT
V
AVDD
DVDD
IOVDD
−0.5 to 2.3
V
Supply Voltage Range
−0.5 to 3.6
V
Voltage between AGND and DGND
Voltage between AVDD and DVDD
−0.3 to 0.5
V
−3.3 to 3.3
V
(2)
Digital inputs
−0.3 to DVDD + 0.3
−0.3 to DVDD + 0.3
−40 to +85
V
Digital data output
Operating free-air temperature range, T
V
°
C
°
C
A
Storage temperature range
−55 to +125
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified
is not implied.
Measured with respect to DGND.
(2)
RECOMMENDED OPERATING CONDITIONS
MIN
−40
TYP
MAX
+85
UNIT
°
C
V
Operating free-air temperature range, T
A
Analog supply voltage range, AVDD
Digital supply voltage range, DVDD
Output driver supply voltage range, IOVDD
Input common-mode voltage
3.15
1.71
3.15
3.3
1.8
3.3
3.45
1.89
3.45
V
Supplies and
References
V
V
CM
2
V
Differential input voltage
V
PP
Sample rate, f
5
0.4
2
80
MHz
V
S
Differential input mode voltage input swing
Single-ended mode high-level input voltage, V
3.3
V
Clock Inputs:
IHC
MCLK and MCLKB
Single-ended mode low-level input voltage, V
0.8
V
ILC
Clock pulse width high, t
5.625
5.625
6.25
6.25
ns
ns
W(H)
Clock pulse width low, t
W(L)
2
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
AUXILIARY DAC CHARACTERISTICS
All specifications at +25
°
C, AVDD = +3.3V, and DVDD = +1.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
12
MAX
UNIT
bits
Resolution
Input code 0x000
Input code 0xFFF
0.0
2.75
1
V
Output voltage range
V
Output impedance
Settling time
k
Ω
to 0.1% FSR
10
µ
s
Offset
1
5
% of FSR
% of FSR
LSB
LSB
dB
Gain error
DC
performance
Differential nonlinearity, DNL
Integral nonlinearity, INL
Power-supply rejection ratio, PSRR
Ensured monotonic
0.5
2
After correcting for gain and offset errors
Input code 0x400,
A
VDD = 3.15VDC to 3.45VDC
60
RECEIVE CHANNEL CHARACTERISTICS
All specifications at +25
°
C, f
= 80MSPS, AVDD = +3.3V, DVDD = +1.8V, IOVDD = +3.3V, Gain = 1, Decimation Ratio = 80, Internal Digital
S
Filter Bandwidth = 284kHz, and Input Signal = 10.7MHz, unless otherwise noted.
PARAMETER
DC Accuracy
CONDITIONS
MIN
TYP
MAX
UNIT
Input impedance
Differential nonlinearity, DNL
Integral nonlinearity, INL
Offset error
6.25
0.0122
0.012
3
k
Ω
−0.0244
−0.0244
+0.0244
+0.0244
%FSR
%FSR
mV
Gain error
1
%FS
Gain = 1
1.0
V
Gain = 1.14
Gain = 1.33
Gain = 1.6
Gain = 2.0
Gain = 2.67
Gain = 4.0
0.875
0.75
0.625
0.5
V
V
V
Full-scale input level (peak differential)
V
0.375
0.25
2
V
V
Gain change settling time
Power-supply rejection ratio, PSRR
References
Number of samples to achieve rated accuracy
AVDD = 3.15VDC to 3.45VDC
Samples
dB
70
Negative reference, VREFN
Positive reference, VREFP
Common-mode voltage, VCM
AC Performance
1.1
2.1
1.25
2.25
1.8
1.4
2.4
V
V
V
Input 455kHz, −1dBFS
76
86
75
74
102
2
dBc
dBc
dB
dB
dB
ns
Spurious-free dynamic range, SFDR
Signal-to-noise ratio, SNR
Input 10.7MHz, −1dBFS
76
70
Input 455kHz, −1dBFS
Input 10.7MHz, −1dBFS
In 3kHz bandwidth, −1dBFS, 10.7MHz, 20kHz from fundamental
Aperture delay
Aperture uncertainty
0.2
ps
Power Supply
Analog supply voltage, AVDD
Digital supply voltage, DVDD
Output driver supply voltage, IOVDD
3.15
1.71
3.15
3.3
1.8
3.3
490
20
3.45
1.89
3.45
570
V
V
V
Normal operation
Power-down
mW
mW
mA
mA
mA
Power dissipation
Digital I/O supply current
Digital supply current
Analog supply current
7
72
103
3
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
PIN ASSIGNMENTS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
AVDD
AGND
IFP
36 SYNC
35 RESET
3
34
33
32
31
30
29
28
DOUT1
DOUT0
DCLK
DFSO
DIN
4
IFM
AGND
VCM
5
6
AFEDRI8201
AVDD
VREFN
VREFP
AVDD
AGND
VBG
7
8
DFSI
9
SCK
10
11
12
27 MISO
26 MOSI
25 CS
13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTIONS
NAME
IFP
PIN
TYPE
Input
FUNCTION
3
Positive IF input
Negative IF input
IFM
4
Input
VCM
6
Output
Output
Output
Output
Output
Input
Common-mode voltage output
Negative reference voltage output
Positive reference Voltage output
Bandgap voltage output
VREFN
VREFP
VBG
8
9
12
14
18
19
25
26
27
28
29
30
31
32
33
34
35
36
37
AUX
Auxiliary DAC output
MCLK
MCLKB
CS
Master clock input
Input
Complementary master clock input
SPI chip select (active low)
SPI serial Input
Input
MOSI
MISO
SCK
Input
Output
Input
SPI serial output
SPI serial clock
DFSI
Input
Data interface input frame sync
Data interface input data
Data interface output frame sync
Data interface clock output
Data interface filter 0 output data
Data interface filter 1 output data
DIN
Input
DFSO
DCLK
DOUT0
DOUT1
RESET
SYNC
PWD
Output
Output
Output
Output
Input
Global reset (active low). Resets all registers to zero, except for FIR filters.
Input
External sync
Input
Power-down: PWD = 1; normal operation: PWD = 0
Analog supply (3.3V)
Analog ground
AVDD
AGND
DVDD
DGND
IOVDD
IOGND
NC
1, 7, 10, 13, 20, 45, 46, 48
Supply
Ground
Supply
Ground
Supply
Ground
—
2, 5, 11, 15, 17, 43, 44, 47
22, 41
21, 42
24, 39
23, 38, 40
16
Digital supply (1.5V to 1.8V)
Digital ground
Digital I/O supply (3.3V)
Digital I/O ground
Not connected
4
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
DIGITAL INTERFACE SPECIFICATIONS
All specifications at +25
°
C, AVDD = 3.3V, DVDD = 1.8V, IOVDD = 3.3V, and maximum 20pF load, unless otherwise noted.
PARAMETER
CONDITIONS
= 1.6V to 3.6V
IH
MIN
−10
TYP
MAX
10
UNITS
High-level input current, I
V
µ
A
µ
A
V
IH
Low-level input current, I
V
= 0V to 0.4V
−10
10
IL
IL
High-level output voltage, V
I
= −50
µ
A
= 50
µ
A
0.8
×
IOVDD
OH
OH
Low-level output voltage, V
High-level input voltage, V
I
0.2
×
IOVDD
0.25
×
IOVDD
V
OL
OL
0.7
×
IOVDD
V
IH
Low-level input voltage, V
V
IL
DATA INTERFACE TIMING
DCLK
DFSO
DOUT0
IA[15]
IA[14]
IA[13]
IA[12]
DOUT1
IB[15]
IB[14]
IB[13]
IB[12]
t
d1
t
d2
t
d3
Figure 1. Output Data Interface TIming
PARAMETER
CONDITIONS
MIN
−0.4
−0.2
−0.2
TYP
MAX
3.2
UNITS
ns
DCLK to DFSO delay, t
d1
DCLK to DOUT0 delay, t
2.5
ns
d2
d3
DCLK to DOUT1 delay, t
2.5
ns
DCLK
DFSI
DIN
D[15]
D[14]
D[13]
D[12]
t
su1
t
su2
t
h1
t
h2
Figure 2. Input Data Interface TIming
PARAMETER
CONDITIONS
MIN
1.2
0.4
1.0
0.4
TYP
MAX
UNITS
ns
DFSI to DCLK setup time, t
su1
DFSI to DCLK hold time, t
DIN to DCLK setup time, t
ns
h1
ns
su2
DIN to DCLK hold time, t
ns
h2
5
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
CONTROL INTERFACE TIMING
SCK
CS
MOSI
MISO
t
T
t
L
t
su3
t
h3
t
I
t
d4
Figure 3. Control Interface Timing
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
Maximum SCK frequency
1
CS leading time, t
Trailing CS to leading SCK
Trailing SCK to leading CS
Leading CS to trailing CS
5.0
5.0
5.0
5.0
1.0
1.0
L
CS trailing time, t
ns
T
CS idle time, t
ns
I
MOSI to SCK setup time, t
ns
su3
MOSI to SCK hold time, t
ns
h3
SCK to MISO delay time, t
8
ns
d4
6
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
DETAILED DESCRIPTION
The AFEDRI8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC) with programmable input
range, digital downconverter (DDC), and user programmable digital filters with 16-bit coefficients. It is designed to sample
narrowband (up to 2.5MHz) IF signals and digitally mix, filter, and decimate the signals to baseband. The ADC integrates a
programmable gain sample-and-hold amplifier that is variable over gains of 1x to 4x to change the full-scale input voltage range
of the device from 1.0V peak to 0.25V peak. When the gain is changed, two sample periods may be needed for the output of
the ADC to settle to the correct value.
The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2). The mixer
frequency and initial phase are independently programmed by 32-bit control words. The quadrature mixer generates I and Q
signals, each of which are decimated by the CIC filter. The CIC is a 5th-order Comb filter with a decimation factor that is
programmable over a range of 8 to 1024. Each of the FIR filters adds an additional decimation factor of 2, for a total range of
32 to 4096.
The I and Q signals generated by the quadrature mixer are then passed on to the first FIR filter (FIR1). This decimate-by-two
FIR filter can implement even, odd, halfband, and arbitrary impulse responses. The length of the filter response is dependent
on the decimation factor of the CIC filter and the FIR filter response type, up to a maximum of 62 taps. Coefficients for multiple
filter responses may be stored in the coefficient memory (up to 64 unique coefficients may be stored); responses can be changed
by changing a control register to point the filter to a different section of coefficient memory.
Following FIR1 are two parallel decimate-by-two FIR filters (FIR2A and FIR2B). These filters are similar to FIR1, but have twice
the data and coefficient memory and can therefore realize longer filter responses. The responses of the FIR2A and FIR2B can
be different from each other (with some limitations). In addition, FIR2A and FIR2B can be optionally interleaved to form a single
extra-long FIR filter that can realize up to 251 taps.
Control register information, as well as decimation filter coefficients, are written to the AFEDRI8201 through the industry-standard
SPI control interface. The baseband output signals are transported through a high-speed serial interface that is compatible with
the TI C5x/C6x DSP buffered serial ports (McBSP).
The AFEDRI8201 also contains a 12-bit auxiliary digital-to-analog converter (DAC) which can be used for a number of purposes,
including tuner automatic gain control or frequency control. Input data for the DAC may be sent either from the DSP through
the serial data port or from a microcontroller through the SPI control interface.
7
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
CONTROL INTERFACE
The AFEDRI8201 uses an SPI slave interface to read and write control data. Control data consists of eleven 16-bit control
registers, as shown in
T
a
ble 1, and three memory banks (see
T
a
ble 2). The control registers are used to program all chip
parameters. The memory banks store 16-bit FIR filter coefficient data.
To read and write to control registers and memory banks, data is transferred by a 16-bit instruction followed by 16 bits of data.
Memory bank read and write operations also support block transfer. Memory bank block transfer consists of a 16-bit instruction
followed by multiple 16-bit data words.
Table 1. Control Registers
REGISTER ADDRESS
DESCRIPTION
0
1
Data interface parameters DI
V
,
M
ODE
NCO frequency (bits 0−15)
2
NCO frequency (bits 16−31)
3
NCO Initial Phase (bits 0−15)
4
NCO Initial Phase (bits 16−31)
5
CIC Filter Decimation Rate: DEC_RATE
CIC Filter Parameters: SCALE, SHIFT
First FIR Filter Parameters: BASE_ADDR, NCOEF
F
,
M
ODE
Second FIR A Filter Parameters: BASE_ADDR, NCOEF
F
,
M
ODE
Second FIR B Filter Parameters: BASE_ADDR, NCOEF
F
,
M
ODE
Setup for the Second FIR
6
7
8
9
10
11
12
Auxiliary DAC: DAC_DATA
ADC Parameters: GAIN, PWD
Table 2. Memory Banks
MEMORY BANK ADDRESS
DESCRIPTION
SIZE
DATA MEMORY
62 Samples
00
01
10
FIR Filter 1 Coefficients
FIR Filter 2A Coefficients
FIR Filter 2B Coefficients
64 Coefficients
128 Coefficients
128 Coefficients
126 Samples
126 Samples
The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select (CS), a serial data input
(MOSI—Master Out, Slave In), and a serial data output (MISO—Master In, Slave Out). Data is transferred in groups of 32
bits. The first 16 bits are the instruction, which indicate:
(1) if data is to be written or to be read;
(2) if the data target is a control register or a memory bank; and
(3) the address of the data target.
The second 16 bits are the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle.
8
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A single data word write cycle is shown in Figure 4. The cycle is initiated by the high-to-low transition of the CS line. 32
SCK pulses clock the instruction and the data into the MOSI line. Instructions and data are clocked in MSB first. The first
16 bits are the instruction; the second 16 bits are the data word. There are two possible single data word write cycle
instructions: register write and memory write. The formats for these instructions are shown in Figure 5 and Figure 6.
SCK
CS
MSB
LSB
MOSI
MISO
Instruction
Data
Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory
1
0
0
REG_ADDR
10
Don’t Care
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
Figure 5. Register Write Instruction Format
1
0
1
Don’t Care
11
MEM
MEM_ADDR
15
14
13
12
10
9
8
7
6
5
4
3
2
1
0
Figure 6. Memory Write Instruction Format
In case RESET is applied, either wait at least three SCK clocks before applying CS, or execute a dummy read operation
(either from a register or memory) in order to initialize the SPI interface correctly. The only information required for a register
write is the 5-bit register address (REG_ADDR). For a memory write, the 2-bit memory select (MEM) and the 8-bit memory
address (MEM_ADDR) are required (see
T
a
ble 2).
Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle this data
word is written to the appropriate register or memory location in the AFE.
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The read cycle is illustrated in Figure 7. It is similar to the write cycle, except that instead of the data word being clocked
into MOSI during the second half of the cycle, the data word is clocked out of MISO. The two data read instructions are
similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9.
SCK
CS
MSB
LSB
MOSI
MISO
MSB
LSB
Instruction
Data
Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory
0
1
0
REG_ADDR
10
Don’t Care
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
Figure 8. Register Read Instruction Format
0
1
1
Don’t Care
11
MEM
MEM_ADDR
15
14
13
12
10
9
8
7
6
5
4
3
2
1
0
Figure 9. Memory Read Instruction Format
Block transfers are supported for memory reading and writing. Multiple data words are transmitted following the memory
read or write instruction for a block transfer. The data words are sequentially read from or written to RAM sequentially
starting at the address contained in the instruction. The sequential RAM access terminates when the CS line goes high.
Figure 10 shows a memory block read cycle. In the illustration, three successive memory locations are read starting at
address N. The memory block write cycle is similar, except of course data is clocked into MOSI.
SCK
CS
MSB
LSB
MSB
LSB
MISO
Instruction
Data (N)
Data (N + 1)
Data (N + 2)
Figure 10. Block Memory Read Cycle Control Interface
In all cases, the control interface is reset when CS goes high. If the final SCK is not received before CS goes high, then
the cycle will end prematurely. For a read cycle, transfer of data will terminate; for a write cycle, no data will be written to
register or memory.
10
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DATA INTERFACE
The data interface consists of six signals:
1. serial
data clock DCLKO;
2. output
frame sync DFSO;
3. output
data line DOUT0;
4. output
data line DOUT1;
5. input
frame sync DFSI; and
6. input
data line DIN.
The decimation filter outputs from the DDC (either IA and QA, or IA, QA, IB, and QB) are multiplexed onto the data outputs.
The control DAC data is shifted into the data input. Control Register 0 programs the functionality of the data interface, as
seen in Figure 11.
0
0
0
0
0
Don’t Care
9
DIV
MODE
0
Register Address
15
14
13
12
11
10
8
7
6
5
4
3
2
1
Figure 11. Data Interface Control Register
Two parameters, DIV and MODE, control the data interface and are programmed by register 0. The first parameter is DIV. The
serial data clock, DCLKO, is derived from MCLK in a manner controlled by DIV such that the frequency of DCLKO is:
f
MCLK
2
DIV
f
DCLKO
+
(1)
where DIV ranges from 0 to 3.
As an example, if MCLK is 80MHz, DCLK0 can be either 80MHz, 40MHz, 20MHz, or 10MHz. DCLK0, of course, must be
fast enough to clock out the I and Q data words generated by the on-chip DDC and filters.
The second parameter is MODE. When MODE is 0, all four DDC outputs are time multiplexed onto DOUT0, as shown in
Figure 12. When MODE is 1, IA and QA outputs are multiplexed onto DOUT0 while IB and QB outputs are multiplexed onto
DOUT1, see Figure 13. If only one set of I/Q outputs is used, MODE 1 is recommended so that data is output through
DOUT0.
DCLKO
DFSO
MSB
LSB
DOUT0
IA
QA
IB
QB
DOUT1
DFSI
MSB
LSB
DIN
DAC
Figure 12. Data Interface Timing for MODE = 0
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DCLKO
DFSO
MSB
LSB
LSB
DOUT0
IA
IB
QA
QB
MSB
DOUT1
DFSI
MSB
LSB
DIN
DAC
Figure 13. Data Interface Timing for MODE = 1
When the data interface receives new outputs from the decimation filters, an output cycle is started by asserting DFSO
for one DCLKO period. On successive leading edges of DCLKO, the filter output data is shifted out MSB first on DOUT0
(and DOUT1 for MODE = 1), as shown in the timing diagrams. The spacing of the DFSO pulses depends on two settings:
the overall decimation ratio R of the DDC and the factor DI
V
.
T
he number of bits which need to be transmitted in one frame,
NBITS, is 64 for MODE = 0 and 32 for MODE = 1. In order to have enough DCLKO cycles between DFSO pulses, the
following relationship must be true:
R
w
NBITS
2
DIV
(2)
or
R
ǒ
Ǔ
DIV
v
log
2
NBITS
(3)
For example, assume the overall decimation ratio, R, for the DDC is 80. For MODE = 0, the largest allowable value for DIV
is 0. In other words, if MCLK is 80MHz, for R = 80, DCLKO must be 80MHz so that all of the 64 data bits may be clocked
out before the next I and Q data words must be clocked out.
For MODE = 1, since only 32 bits need to be clocked out during one cycle, DCLKO can be reduced to 40MHz (which means
that DIV may be increased to 1, cutting the frequency of DCLKO in half).
DFSI and DIN are used to send control DAC data to the AFEDRI8201. DCLKO supplied by the AFEDRI8201 is used as
the serial clock. An input cycle is initiated by holding DFSI high through one rising edge of DCLKO. On the successive 16
leading edges of DCLKO the input data word is read in serially, MSB first. The lower 12 bits of the data word are sent to
the DAC as the unsigned DAC input.
Note that the input data does not need to bear any timing relationship to the output data, except that both data streams are
synchronous with DCLKO.
QUADRATURE MIXER/NCO
The NCO frequency and initial phase are set by the 32-bit unsigned variables FREQ and PHASE. Each of these variables
is set via a pair of control registers; see Figure 14. The I and Q outputs of the mixer are given by:
(
)
I
+
ADC
sin 2
p
ft
)
f
(4)
(5)
and
(
)
Q
+
ADC
cos 2
p
ft
)
f
where ADC is the output of the IF analog-to-digital converter, f is the NCO frequency given by:
FREQ
f
+
f
MCLK
2
32
(6)
(7)
and
φ
is the NCO phase offset (in radians) given by:
PHASE
f
+
2
p
2
32
12
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LSB
MSB
15
0
0
0
0
1
FREQ[15:0]
Register Address
14
14
14
14
13
13
13
13
12
12
12
12
11
11
11
11
10
10
10
10
9
9
9
9
8
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
0
0
0
1
0
FREQ[31:16]
Register Address
15
15
15
8
7
0
0
0
1
1
PHASE[15:0]
Register Address
8
7
0
0
1
0
0
PHASE[31:16]
Register Address
8
7
Figure 14. Mixer Control Registers
The SYNC pin can be used to externally control the phase of the mixer. While the SYNC pin is high, the phase accumulator
is held to a constant value PHASE, essentially holding t to zero in the I and Q equations. When the SYNC pin is brought
low, the phase accumulator is incremented by the value FREQ once per MCLK cycle.
Note that the mixer can be bypassed by setting FREQ and PHASE to 0 and using only the Q (real) output.
CIC FILTER
The first stage of decimation filtering is provided by a 5th-order CIC filter. The operation of the CIC filter is controlled by
the unsigned variable DEC_RATE, SCALE, and SHIFT which are mapped into control registers as illustrated in Figure 15.
The valid range for DEC_RATE is from 8 to 1024.
0
0
1
0
1
Don’t Care
13
DEC_RATE
5
Register Address
15
15
14
12
12
11
11
10
10
9
8
8
7
7
6
6
4
4
3
3
2
2
1
1
0
0
0
0
1
1
0
Don’t Care
14 13
SCALE
SHIFT
Register Address
9
5
Figure 15. CIC Filter Control Registers
The inherent dc gain of the CIC filter is DEC_RATE
5
. The control variables SHIFT and SCALE are used to reduce this very
high gain before the signal is output to the next stage of decimation filter. The combined effect of DEC_RATE, SHIF
T
,
a
nd
SCALE produces an overall dc gain for the CIC filter of:
Scale
ń
32
5
Gain
+
DEC_RATE
ǒ
Ǔ
2
shift
(8)
In general, SHIFT and SCALE should be chosen to make GAIN as close to 1 as possible. For example, if DEC_RATE is
20, setting SHIFT to 22 and scale to 41 will result in a GAIN of 0.9775.
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FIRST FIR FILTER
The block following the CIC filter is a decimate-by-two FIR filter with programmable coefficients. MODE sets the type of
filter response—ODD (MODE = 00: symmetric impulse response, odd number of taps), EVEN (MODE = 01: symmetric
impulse response, even number of taps), HALFBAND (MODE = 10), and ARBITRARY (MODE = 11: non-symmetric
impulse response).
The 16-bit wide filter coefficients are stored in memory bank 0. Up to 64 coefficients can be stored in this memory.
Depending on the types of filters desired and the number of taps, coefficients for multiple filter responses may be stored
in the memory bank. The filter response may be changed simply by updating the control register with new values for MODE,
NCOEFF, and BASE_ADDR, as shown in Figure 16.
0
0
1
1
1
Don’t Care
15 14
BASE_ADDR
11
1
0
NCOEFF
MODE
Register Address
13
12
9
8
7
6
5
4
3
2
1
0
Figure 16. First FIR Filter Control Register
NCOEFF defines the number of unique filter coefficients which make up the filter response. BASE_ADDR defines the
memory location where the first filter coefficient is stored. The actual filter length is a function of MODE and NCOEFF:
Filter length = 2(NCOEFF − 1) + 1 for ODD
Filter length = 2NCOEFF for EVEN
Filter length = 4(NCOEFF − 1) + 1 for HALFBAND
Filter length = NCOEFF for ARBITRARY
The maximum filter length which can be realized is limited by two factors. First, the number of clock cycles between
successive filter outputs limits the number of coefficients which can be processed to:
NCOEFF
v
2
DEC_RATE
*
4
(9)
where DEC_RATE is the decimation ration of the CIC filter. Second, the size of the data memory (which stores incoming
data samples) limits filter length to 62 taps.
A filter response is defined by a set of NCOEFF 16-bit filter coefficients stored in memory bank 0 (MEM = 0) starting at
address BASE_ADDR. MODE determines how the coefficients are applied to the samples stored in data memory.
Figure 17 is an example illustrating how the filter coefficients are applied to stored input samples in the various filter modes
with NCOEFF = 6. Because NCOEFF = 6 in this example, six computation cycles are required to calculate the filter output
regardless of the filter mode. The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending
memory address in the coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being
applied to the input data is highlighted.
The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending memory address in the
coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being applied to the input data is
highlighted.
The four groupings on the right in Figure 17 represent the four filter modes: EVEN, ODD, HALFBAND, and ARBITRAR
Y
.
In each column, the locations in data memory that are operated on at each computation cycle is shown. The leftmost data
sample in each group is the newest sample, the rightmost sample is the oldest. The chart illustrates the order in which
computation on data occurs.
T
o
u
se the chart, select the filter mode of interest, then move down the chart through the six
computation cycles to understand the sequence of calculations.
14
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COMPUTATION COEFFICIENT
CYCLE
BANK
FILTER PROCESSING
ODD
EVEN
HALFBAND
ARBITRARY
1
2
3
4
5
6
Figure 17. Application of Filter Coefficients in Different Filter Modes
15
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For example, using the ODD mode in the first cycle of MCLK, the filter coefficient at BASE_ADDR is applied to two values
in data memory, the most recent at address N and the oldest at address N+10. In the next cycle of MCLK the coefficient
at BASE_ADDR+1 is applied to the data values at N+1 and N+9, and so on until the last coefficient at BASE_ADDR+5
is reached. Because this is an odd filter, the final coefficient is applied only to the data value at address N+5. The full cycle
is shown in
T
a
ble 3.
Table 3. ODD Mode Calculation Example with Six Filter Coefficients
CYCLE
FILTER COEFFICIENT ADDRESS
BASE_ADDR
APPLIED TO DATA ADDRESS
N and N+10
1
2
3
4
5
6
BASE_ADDR+1
N+1 and
N+9
N+2 and
N+8
N+3 and
N+7
N+4 and
N+6
N+5
BASE_ADDR+2
BASE_ADDR+3
BASE_ADDR+4
BASE_ADDR+5
Figure 17 clearly illustrates that the overall filter length is different in different filter modes even if NCOEFF is unchanged.
For NCOEFF = 6, filter length ranges from 6 taps for ARBITRARY mode to 19 taps for HALFBAND mode.
The dc gain of the FIR filter depends on the coefficient values and the filter mode.
For ODD mode and for HALFBAND mode, the dc gain is given by:
NCOEFF
*
1
15
ǒ
2
Ǔ
GAIN
+
ǒ
Ǔ
ń
h
NCOEFF
)
2h
n
*
1
S
n
+
1
(10)
where h
n
is the
nth
of NCOEFF filter coefficients stored in memory.
For EVEN mode the dc gain is:
NCOEFF
15
ǒ
2
Ǔ
GAIN
+
ǒ
Ǔ
2h
n
*
1
ń
S
n
+
1
(11)
(12)
while for ARBITRARY mode the gain is:
NCOEFF
15
ǒ
2
Ǔ
GAIN
+
ǒ
Ǔ
h
n
*
1
ń
S
n
+
1
16
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SECOND FIR FILTER
The second FIR filter, shown in Figure 18, is similar to the first FIR filter with four notable exceptions.
1. The
depth of the coefficient and data memories are doubled to 128. This allows for filters up to 126 taps to be
realized without running out of data memory. It also allows longer sets of filter coefficients to be stored in
coefficient memory. Note that BASE_ADDR and NCOEFF are each one bit wider in the control register.
2. Because
of the additional decimation by two from the first FIR filter, twice as many MCLK cycles are available
to process coefficients, increasing the maximum allowable value of NCOEFF to:
NCOEFF
v
4
DEC_RATE
*
4
3. In
the first FIR filter, the total of all the filter tap weights must add up to 2
− 1 in order to achieve unity gain through
(13)
15
the filter. With longer filters (and thus smaller coefficients), frequency response errors may be introduced
because of coefficient truncation. A shift parameter has been added to the second FIR filter to alleviate this
15+SHIFT
problem. The total of all filter tap weights must add up to 2
− 1 to achieve unity gain through FIR2A or
FIR2B. Note that shift values for FIR2A and FIR2B can be set separately.
4. A
second coefficient memory and computational unit is added to allow the simultaneous implementation of two
filters with differing responses acting on the same input data stream. Coefficients for filter A are stored in memory
bank 1 (MEM = 1) and coefficients for filter B are stored in memory bank 2 (MEM = 2).
Note that while the coefficient values for filter A and filter B can be different, the two filters share the same values for MODE,
NCOEFF, and BASE_ADDR.
0
1
0
0
0
BASE_ADDR_A
NCOEFF_A
5
MODE_A
Register Address
15
15
15
14
14
14
13
12
11
10
10
10
9
9
9
8
8
7
7
7
6
6
4
4
4
3
3
3
2
2
1
0
0
1
0
0
1
BASE_ADDR_B
NCOEFF_B
5
MODE_B
Register Address
13
12
11
1
0
0
0
1
0
1
0
Don’t Care
12
M2X
8
SHIFT_B
SHIFT_A
Register Address
13
11
6
5
2
1
Figure 18. Second FIR Filter Control Register
EXTENDED-LENGTH FILTER MODE
If FIR2A or FIR2B cannot provide enough filter taps to achieve the desired frequency response, setting control bit M2X to
‘1’ will put the two filters into an interleaved mode, which will double the length of filter which can be realized. The limitations
are:
1. only
odd symmetrical filters may be realized;
2. the
filter length M must be such that (M + 1)/4 is an integer; and
3. only
one filter can be realized (in M2X mode the A and B outputs are identical: IB = IA and QB = QA).
In addition to setting the M2X bit to ‘1’, FIR2A must be set to EVEN mode and FIR2B must be set to ODD mode. NCOEFF_A
and NCOEFF_B are both set to (M+1)/4. SHIFT_A and SHIFT_B should be identical. There are no restrictions on
BASE_ADDR_A or BASE_ADDR_B.
The M-tap filter will have (M+1)/2 unique coefficients. The first, third, fifth, etc. coefficients are loaded into the FIR2A
coefficient memory; the second, fourth, sixth, etc. are loaded into the FIR2B memory. The center coefficient of the filter will
end up as the last coefficient loaded into FIR2B.
17
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SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
AUXILIARY DAC
In normal operation the auxiliary DAC values are sent over the data interface through input pin DIN and framed by DFSI.
The auxiliary DAC control register, shown in Figure 19, allows the DAC value to be set through the control interface as an
alternative. A new DAC value through either interface will cause the DAC output to change, regardless of which interface
set the previous DAC value. Please note, however, that unpredictable results will occur if both interfaces write to the DAC
at the same time.
0
1
0
1
1
Don’t Care
14 13
DAC_DATA
Register Address
15
12
11
10
9
8
7
6
5
4
3
2
1
0
Figure 19. Auxiliary DAC Control Register
PGA AND POWER-DOWN
The gain of PGA and the power-down mode can be set in register 12. The gain setting of the PGA is shown in
T
a
ble 4.
Table 4. PGA Gain Setting
3-BIT CODE
(B4, B3, AND B2)
PGA GAIN RANGE
1.00
1.14
1.33
1.60
2.00
2.67
4.00
000
100
010
110
001
101
0
1
1
Bit 0
PWD = 0 for normal operation.
PWD = 1 for power-down.
Don’t
Care
0
1
1
0
0
Don’t Care
10
GAIN
PWD
0
Register Address
15
14
13
12
11
9
8
7
6
5
4
3
2
1
Figure 20. PGA and PWD Register
18
SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005
AFEDRI8201 Revision History
DATE
REV
PAGE
SECTION
DESCRIPTION
6
Control Interface Timing
Changed
Maximum SCK Frequency
from 10MHz to 1MHz.
Changed “16 bit” to “16-bit” (added hyphen) in last sentence of 2nd paragraph.
Changed “16 bits is” to “16 bits are” in last paragraph.
8
9
Control Interface
8/25/05
F
Changed 1st sentence of 4th paragraph to include additional info on initializing
the SPI interface correctly.
13
16
Quadrature Mixer/NCO
Control Interface
Changed “mixer” to “the mixer” in 1st sentence of 1st paragraph.
Changed “mode” to “modes” in 1st sentence of 2nd paragraph.
:
NOTE Page
numbers for previous revisions may differ from page numbers in the current version.
19
PACKAGE OPTION ADDENDUM
30-Jan-2007
PACKAGING INFORMATION
Orderable Device
AFEDRI8201PFBR
AFEDRI8201PFBRG4
AFEDRI8201PFBT
AFEDRI8201PFBTG4
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Qty
Type
Drawing
TQFP
PFB
48
48
48
48
2000 Green
(RoHS &
CU NIPDAU
Level-2-260C-1 YEAR
no Sb/Br)
TQFP
TQFP
TQFP
PFB
PFB
PFB
2000 Green
(RoHS &
CU NIPDAU
Level-2-260C-1 YEAR
no Sb/Br)
250 Green
(RoHS &
CU NIPDAU
Level-2-260C-1 YEAR
no Sb/Br)
250 Green
(RoHS &
CU NIPDAU
Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. — The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
M
E
CHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0
°
–
7
°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
407317
6
/B
1
0/96
NOTES: A. All
linear dimensions are in millimeters.
B. This
drawing is subject to change without notice.
C. Falls
within JEDEC MS-026
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
IMPORTANT NOTICE
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