Texas-Instruments-CC1100-RTR1
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CC1100
CC1100
Low-Power Sub- 1 GHz RF Transceiver
Applications
•
Ultra low-power wireless applications
operating in the 315/433/868/915 MHz
ISM/SRD bands
•
Wireless alarm and security systems
•
Industrial monitoring and control
•
Wireless sensor networks
•
AMR – Automatic Meter Reading
•
Home and building automation
Product Description
The main operating parameters and the 64-
byte transmit/receive FIFOs of
CC1100
can be
controlled via an SPI interface. In a typical
system, the
CC1100
will be used together with a
microcontroller and a few additional passive
components.
The
CC1100
is a low-cost sub- 1 GHz
transceiver designed for very low-power
wireless applications. The circuit is mainly
intended for the ISM (Industrial, Scientific and
Medical) and SRD (Short Range Device)
frequency bands at 315, 433, 868, and 915
MHz, but can easily be programmed for
operation at other frequencies in the 300-348
MHz, 400-464 MHz and 800-928 MHz bands.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data up to 500 kBaud.
1
2
3
4
5
15
14
13
12
11
CC1100
CC1100
provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication, and wake-on-radio.
This product shall not be used in any of the following products or systems without prior express written permission
from Texas Instruments:
(i)
implantable cardiac rhythm management systems, including without limitation pacemakers,
defibrillators and cardiac resynchronization devices,
(ii)
(iii)
external cardiac rhythm management systems that communicate directly with one or more
implantable medical devices; or
other devices used to monitor or treat cardiac function, including without limitation pressure
sensors, biochemical sensors and neurostimulators.
Please contact lpw-medical-approval@list.ti.com if your
application might fall within the category described above.
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CC1100
Key Features
•
•
Programmable Preamble Quality Indicator
(PQI) for improved protection against
false sync word detection in random noise
Support for automatic Clear Channel
Assessment (CCA) before transmitting
(for listen-before-talk systems)
Support for per-package Link Quality
Indication (LQI)
Optional automatic whitening and de-
whitening of data
RF Performance
•
•
•
•
•
•
High sensitivity (–111 dBm at 1.2 kBaud,
868 MHz, 1% packet error rate)
Low current consumption (14.4 mA in RX,
1.2 kBaud, 868 MHz)
Programmable output power up to +10
dBm for all supported frequencies
Excellent receiver selectivity and blocking
performance
Programmable data rate from 1.2 to 500
kBaud
Frequency bands: 300-348 MHz, 400-464
MHz and 800-928 MHz
•
•
Low-Power Features
•
•
400nA SLEEP mode current consumption
Fast startup time: 240us from sleep to RX
or TX mode (measured on EM reference
Analog Features
•
•
Wake-on-radio functionality for automatic
low-power RX polling
Separate 64-byte RX and TX data FIFOs
(enables burst mode data transmission)
•
2-FSK, GFSK, and MSK supported as
well as OOK and flexible ASK shaping
Suitable for frequency hopping systems
•
due to
a
fast settling frequency
synthesizer: 90us settling time
General
•
•
Automatic Frequency Compensation
(AFC) can be used to align the frequency
synthesizer to the received centre
frequency
•
Few external components: Completely on-
chip frequency synthesizer, no external
filters or RF switch needed
Integrated analog temperature sensor
•
•
•
Green package: RoHS compliant and no
antimony or bromine
Small size (QLP 4×4 mm package, 20
pins)
Suited for systems targeting compliance
with EN 300 220 (Europe) and FCC CFR
Part 15 (US).
Digital Features
•
Flexible support for packet oriented
systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling
Efficient SPI interface: All registers can be
programmed with one “burst” transfer
Digital RSSI output
Programmable channel filter bandwidth
Programmable Carrier Sense (CS)
indicator
•
Support
for
asynchronous
and
synchronous serial receive/transmit mode
for backwards compatibility with existing
radio communication protocols
•
•
•
•
SWRS038D
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CC1100
Abbreviations
Abbreviations used in this data sheet are described below.
ACP
ADC
AFC
Adjacent Channel Power
MSK
N/A
Minimum Shift Keying
Not Applicable
Analog to Digital Converter
Automatic Frequency Compensation
NRZ
Non Return to Zero (Coding)
AGC
AMR
ASK
Automatic Gain Control
Automatic Meter Reading
Amplitude Shift Keying
OOK
PA
PCB
On-Off Keying
Power Amplifier
Printed Circuit Board
BER
BT
Bit Error Rate
PD
Power Down
Bandwidth-Time product
Clear Channel Assessment
Code of Federal Regulations
Cyclic Redundancy Check
Carrier Sense
PER
PLL
Packet Error Rate
CCA
CFR
CRC
CS
Phase Locked Loop
Power-On Reset
POR
PQI
Preamble Quality Indicator
Preamble Quality Threshold
PQT
PTAT
QLP
QPSK
RC
CW
Continuous Wave (Unmodulated Carrier)
Direct Current
Proportional To Absolute Temperature
Quad Leadless Package
Quadrature Phase Shift Keying
Resistor-Capacitor
DC
DVGA
ESR
FCC
FEC
FIFO
FHSS
2-FSK
GFSK
IF
Digital Variable Gain Amplifier
Equivalent Series Resistance
Federal Communications Commission
Forward Error Correction
First-In-First-Out
RF
Radio Frequency
RSSI
RX
Received Signal Strength Indicator
Receive, Receive Mode
Surface Aqustic Wave
Surface Mount Device
Signal to Noise Ratio
Frequency Hopping Spread Spectrum
Binary Frequency Shift Keying
Gaussian shaped Frequency Shift Keying
Intermediate Frequency
In-Phase/Quadrature
SAW
SMD
SNR
SPI
Serial Peripheral Interface
Short Range Devices
To Be Defined
I/Q
SRD
TBD
T/R
ISM
LC
Industrial, Scientific, Medical
Inductor-Capacitor
Transmit/Receive
LNA
LO
Low Noise Amplifier
TX
Transmit, Transmit Mode
Ultra High frequency
Local Oscillator
UHF
VCO
WOR
XOSC
XTAL
LSB
LQI
Least Significant Bit
Voltage Controlled Oscillator
Wake on Radio, Low power polling
Crystal Oscillator
Link Quality Indicator
MCU
MSB
Microcontroller Unit
Most Significant Bit
Crystal
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CC1100
Table Of Contents
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CC1100
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CC1100
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Page 6 of 92
CC1100
1
Absolute Maximum Ratings
exceeding one or more of the limiting values may cause permanent damage to the device.
Caution!
ESD
sensitive
device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
Parameter
Min
Max
3.9
Units
Condition
Supply voltage
–0.3
V
V
All supply pins must have the same voltage
Voltage on any digital pin
–0.3
VDD+0.3
max 3.9
2.0
Voltage on the pins RF_P, RF_N,
and DCOUPL
–0.3
V
Voltage ramp-up rate
Input RF level
120
+10
150
kV/µs
dBm
°
C
Storage temperature range
Solder reflow temperature
ESD
–50
260
According to IPC/JEDEC J-STD-020C
°
C
<500
V
According to JEDEC STD 22, method A114,
Human Body Model
Table 1: Absolute Maximum Ratings
2
Operating Conditions
Parameter
Min
-40
1.8
Max
85
Unit
°
C
Condition
Operating temperature
Operating supply voltage
3.6
V
All supply pins must have the same voltage
Table 2: Operating Conditions
3
General Characteristics
Parameter
Min
300
400
800
1.2
1.2
26
Typ
Max
348
464
928
500
250
500
Unit
MHz
Condition/Note
Frequency range
MHz
MHz
Data rate
kBaud
kBaud
kBaud
2-FSK
GFSK, OOK, and ASK
(Shaped) MSK (also known as differential offset
QPSK)
Optional Manchester encoding (the data rate in kbps
will be half the baud rate)
Table 3: General Characteristics
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CC1100
4
Electrical Specifications
4.1 Current
Consumption
Tc = 25
°
C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference designs
Reduced current settings (
MDMCFG2.DEM_DCFILT_OFF=1
) gives a slightly
lower current consumption at the cost of a
Parameter
Min Typ Max Unit Condition
Current consumption in power
down modes
400
900
95
nA Voltage
regulator to digital part off, register values retained
(SLEEP state). All GDO pins programmed to 0x2F (HW to 0)
nA Voltage
regulator to digital part off, register values retained, low-
power RC oscillator running (SLEEP state with WOR enabled
Voltage regulator to digital part off, register values retained,
µ
A
µ
A
µ
A
160
9.8
Voltage regulator to digital part on, all other modules in power
down (XOFF state)
Current consumption
Automatic RX polling once each second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate,
PLL calibration every 4
th
wakeup. Average current with signal in
34.2
1.5
Same as above, but with signal in channel
above
carrier sense
level, 1.95 ms RX timeout, and no preamble/sync word found.
µ
A
µ
A
Automatic RX polling every 15
th
second, using low-power RC
oscillator, with 460kHz filter bandwidth and 250 kBaud data rate,
PLL calibration every 4
th
wakeup. Average current with signal in
39.3
1.6
Same as above, but with signal in channel
above
carrier sense
level, 29.3 ms RX timeout, and no preamble/sync word found.
µ
A
mA Only
voltage regulator to digital part and crystal oscillator running
(IDLE state)
8.2
mA Only
the frequency synthesizer is running (FSTXON state). This
currents consumption is also representative for the other
intermediate states when going from IDLE to RX or TX, including
the calibration state.
Current consumption,
315MHz
15.1
13.9
14.9
14.1
15.9
14.5
mA Receive
mode, 1.2 kBaud, reduced current, input at sensitivity
limit
mA Receive
mode, 1.2 kBaud, reduced current, input well above
sensitivity limit
mA Receive
mode, 38.4 kBaud, reduced current, input at sensitivity
limit
mA Receive
mode,38.4 kBaud, reduced current, input well above
sensitivity limit
mA Receive
mode, 250 kBaud, reduced current, input at sensitivity
limit
mA Receive
mode, 250 kBaud, reduced current, input well above
sensitivity limit
27.0
14.8
12.3
mA Transmit
mode, +10 dBm output power
mA Transmit
mode, 0 dBm output power
mA Transmit
mode, –6 dBm output power
SWRS038D
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CC1100
Parameter
Min Typ Max Unit Condition
Current consumption,
433MHz
15.5
14.5
15.4
14.4
16.5
15.2
mA Receive
mode, 1.2
kBaud , reduced current, input at sensitivity
limit
mA Receive
mode, 1.2
kBaud , reduced current, input well above
sensitivity limit
mA Receive
mode, 38.4
kBaud , reduced current, input at sensitivity
limit
mA Receive
mode, 38.4
kBaud , reduced current, input well above
sensitivity limit
mA Receive
mode, 250
kBaud , reduced current, input at sensitivity
limit
mA Receive
mode, 250
kBaud , reduced current, input well above
sensitivity limit
28.9
15.5
13.1
15.4
mA Transmit
mode, +10 dBm output power
mA Transmit
mode, 0 dBm output power
mA Transmit
mode, –6 dBm output power
Current consumption,
868/915MHz
mA Receive
mode, 1.2
kBaud , reduced current, input at sensitivity
limit
14.4
15.2
14.4
16.4
15.1
mA Receive
mode, 1.2
kBaud , reduced current, input well above
sensitivity limit
mA Receive
mode, 38.4
kBaud , reduced current, input at sensitivity
limit
mA Receive
mode,38.4 kBaud
, reduced current, input well above
sensitivity limit
mA Receive
mode, 250
kBaud , reduced current, input at sensitivity
limit
mA Receive
mode, 250
kBaud , reduced current, input well above
sensitivity limit
31.1
16.9
13.5
mA Transmit
mode, +10 dBm output power
mA Transmit
mode, 0 dBm output power
mA Transmit
mode, –6 dBm output power
Table 4: Electrical Specifications
4.2 RF
Receive Section
Tc = 25
°
C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference designs
Parameter
Min
Typ
Max
Unit
Condition/Note
Digital channel filter
bandwidth
58
812
kHz
User programmable. The bandwidth limits are proportional to
crystal frequency (given values assume a 26.0 MHz crystal).
(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)
Receiver sensitivity
-111
dBm
Sensitivity can be traded for current consumption by setting
consumption is then reduced from
17.1 mA to 15.1 mA at
sensitivity limit. The sensitivity is typically reduced to -109 dBm
315 MHz, 500 kBaud data rate, sensitivity optimized,
MDMCFG2.DEM_DCFILT_OFF=0
(
MDMCFG2.DEM_DCFILT_OFF
=1
cannot be used for data rates > 250 kBaud)
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
-88
dBm
SWRS038D
Page 9 of 92
CC1100
Parameter
(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth
Min
Typ
Max
Unit
Condition/Note
Receiver sensitivity
–110
dBm
Sensitivity can be traded for current consumption by setting
consumption is then reduced from
17.4 mA to 15.5 mA at
sensitivity limit. The sensitivity is typically reduced to -108 dBm
(2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)
Receiver sensitivity
–103
dBm
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity
–94
dBm
433 MHz, 500 kBaud data rate, sensitivity optimized,
MDMCFG2.DEM_DCFILT_OFF=
0
(
MDMCFG2.DEM_DCFILT_OFF
=1
cannot be used for data rates > 250 kBaud)
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity
–88
dBm
(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)
Receiver sensitivity
–111
dBm
Sensitivity can be traded for current consumption by setting
consumption is then reduced from
17.7 mA to 15.4 mA at
sensitivity limit. The sensitivity is typically reduced to -109 dBm
Saturation
–15
33
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit. 100 kHz
channel spacing
Alternate channel
rejection
33
dB
Desired channel 3 dB above the sensitivity limit. 100 kHz
channel spacing
See Figure 25 fo
r plot of selectivity versus frequency offset
IF frequency 152 kHz
Image channel
rejection,
868MHz
30
dB
Desired channel 3 dB above the sensitivity limit.
868 MHz, 38.4 kBaud data rate
(2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)
Receiver sensitivity
Saturation
–103
–16
20
dBm
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit. 200 kHz
channel spacing
Alternate channel
rejection
28
dB
Desired channel 3 dB above the sensitivity limit. 200 kHz
channel spacing
See Figure 26 fo
r plot of selectivity versus frequency offset
IF frequency 152 kHz
Image channel
rejection,
868MHz
23
dB
Desired channel 3 dB above the sensitivity limit.
SWRS038D
Page 10 of 92
CC1100
Parameter
Min
Typ
Max
Unit
Condition/Note
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver
–93
dBm
Sensitivity can be traded for current consumption by setting
sensitivity
is then reduced from 18.8 mA to 1
6.4 mA at sensitivity limit. The
sensitivity is typically reduced to -91 dBm
Saturation
–16
24
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit. 750 kHz channel
spacing
Alternate channel
rejection
37
dB
Desired channel 3 dB above the sensitivity limit. 750 kHz channel
spacing
See Figure 27 fo
r plot of selectivity versus frequency offset
IF frequency 254 kHz
Image channel
rejection,
868MHz
14
dB
Desired channel 3 dB above the sensitivity limit.
868 MHz, 500
kBaud data rate, sensitivity optimized,
MDMCFG2.DEM_DCFILT_OFF=0
(
MDMCFG2.DEM_DCFILT_OFF
=1
cannot be used for data rates > 250
kBaud )
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver
–88
dBm
sensitivity
(OOK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver
-86
dBm
sensitivity
(2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)
Receiver
sensitivity
–111
dBm
Sensitivity can be traded for current consumption by setting
is then reduced from 17.7 mA to 1
5.4 mA at sensitivity limit. The
sensitivity is typically reduced to -109 dBm
(2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)
Receiver
–104
dBm
sensitivity
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver
sensitivity
–93
dBm
Sensitivity can be traded for current consumption by setting
is then reduced from 18.8 mA to 1
6.4 mA at sensitivity limit. The
sensitivity is typically reduced to -92 dBm
915 MHz, 500
kBaud data rate, sensitivity optimized,
MDMCFG2.DEM_DCFILT_OFF=0
(
MDMCFG2.DEM_DCFILT_OFF
=1
cannot be used for data rates > 250
kBaud )
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver
–87
dBm
sensitivity
SWRS038D
Page 11 of 92
CC1100
Parameter
Blocking
Min
Typ
-53
-51
-43
-43
Max
Unit Condition/Note
Blocking at ±2 MHz offset,
1.2 kBaud, 868 MHz
dBm Desired
channel 3dB above the sensitivity limit. Compliant
with ETSI EN 300 220 class 2 receiver requirement.
Blocking at ±2 MHz offset,
500 kBaud, 868 MHz
dBm Desired
channel 3dB above the sensitivity limit. Compliant
with ETSI EN 300 220 class 2 receiver requirement.
Blocking at ±10 MHz offset,
1.2 kBaud, 868 MHz
dBm Desired
channel 3dB above the sensitivity limit. Compliant
with ETSI EN 300 220 class 2 receiver requirement.
Blocking at ±10 MHz offset,
500 kBaud, 868 MHz
dBm Desired
channel 3dB above the sensitivity limit. Compliant
with ETSI EN 300 220 class 2 receiver requirement.
General
Spurious emissions
-68
-66
9
–57
–47
dBm 25
MHz – 1 GHz
(Maximum figure is the ETSI EN 300 220 limit)
dBm Above
1 GHz
(Maximum figure is the ETSI EN 300 220 limit)
RX latency
bit
Serial operation. Time from start of reception until data is
available on the receiver data output pin is equal to 9 bit.
Table 5: RF Receive Section
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Page 12 of 92
CC1100
4.3 RF
Transmit Section
Tc = 25
°
C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using the CC1100EM reference
Parameter
Min
Typ
Max
Unit Condition/Note
Differential impedance as seen from the RF-port (RF_P and
Differential load
impedance
RF_N) towards
the antenna. Follow the CC1100EM reference
315 MHz
122 + j31
116 + j41
86.5 + j43
+10
Ω
433 MHz
868/915 MHz
Output power,
highest setting
dBm Output
power is programmable, and full range is available in all
frequency bands
(Output power may be restricted by regulatory limits. See also
Delivered to a 50
Ω
single-ended load via CC1100EM reference
Output power,
lowest setting
-30
dBm Output
power is programmable, and full range is available in all
frequency bands.
Delivered to a 50
Ω
single-ended load via CC1100EM reference
Harmonics,
radiated
CW, 10 dBm output power
2
3
nd
Harm, 433 MHz
rd
Harm, 433 MHz
-50
-40
dBm The
antennas used during the radiated measurements (SMAFF-
433 from R.W.Badland and Nearson S331 868/915) plays a part
in attenuating the harmonics
2
3
nd
Harm, 868 MHz
rd
Harm, 868 MHz
-34
-45
Harmonics,
conducted
Measured with 10 dBm CW, TX frequency at 315.00 MHz,
433.00 MHz, 868.00 MHz, or 915.00 MHz
315 MHz
< -33
< -38
dBm Frequencies
below 960 MHz
Frequencies above 960 MHz
433 MHz
< -51
< -34
Frequencies below 1 GHz
Frequencies above 1 GHz
868 MHz
915 MHz
< -32
< -30
SWRS038D
Page 13 of 92
CC1100
Spurious emissions,
conducted
Measured with 10 dBm CW, TX frequency at 315.00 MHz,
433.00 MHz, 868.00 MHz or 915.00 MHz
Harmonics not
included
315 MHz
< -58
< -53
dBm Frequencies
below 960 MHz
Frequencies above 960 MHz
433 MHz
< -50
< -54
< -56
Frequencies below 1 GHz
Frequencies above 1 GHz
Frequencies within
47-74, 87.5-118, 174-230, 470-862 MHz
868 MHz
< -50
< -51
< -53
Frequencies below 1 GHz
Frequencies above 1 GHz
Frequencies within
47-74, 87.5-118, 174-230, 470-862 MHz.
The peak conducted spurious emission is -53dBm @ 699 MHz,
which is in an EN300220 restricted band limited to -54dBm. All
radiated spurious emissions are within the limits of ETSI.
Frequencies below 960 MHz
Frequencies above 960 MHz
915 MHz
< -51
< -51
General
TX latency
8
bit
Serial operation. Time from sampling the data on the transmitter
data input DIO pin until it is observed on the RF output ports.
Table 6: RF Transmit Section
4.4 Crystal
Oscillator
Tc = 25
°
C @ VDD = 3.0 V if nothing else is stated.
Parameter
Min
Typ
26
Max
Unit Condition/Note
Crystal frequency
Tolerance
26
27
MHz
±40
ppm This
is the total tolerance including a) initial tolerance, b)
crystal loading,
c) aging, and d) temperature dependence.
The acceptable crystal tolerance depends on RF frequency
and channel spacing / bandwidth.
ESR
100
Ω
Start-up time
150
µs
using crystal AT-41CD2 from NDK.
This parameter is to a large degree crystal dependent.
Table 7: Crystal Oscillator Parameters
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CC1100
4.5 Low
Power RC Oscillator
Tc = 25
°
C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1100EM reference des
igns ([5]
Parameter
Min
Typ
Max
Unit
kHz
Condition/Note
Calibrated frequency
34.7
34.7
36
Calibrated RC Oscillator frequency is XTAL
frequency divided by 750
Frequency accuracy after
calibration
±1
%
Temperature coefficient
Supply voltage coefficient
Initial calibration time
+0.5
+3
2
Frequency drift when temperature changes after
calibration
% /
°
C
% / V
ms
Frequency drift when supply voltage changes after
calibration
When the RC Oscillator is enabled, calibration is
continuously done in the background as long as
the crystal oscillator is running.
Table 8: RC Oscillator Parameters
4.6 Frequency
Synthesizer Characteristics
Tc = 25
°
C @ VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1100EM reference
designs ([5] and [
6])
.
Min figures are given using a 27 MHz crystal. Typ and max are given using a 26 MHz crystal.
Parameter
Min
397
Typ
Max
412
Unit
Hz
Condition/Note
Programmed frequency
resolution
F
XOSC
/
26-27 MHz crystal.
2
16
The resolution (in Hz) is equal for all frequency
bands.
Synthesizer frequency
tolerance
±40
ppm
Given by crystal used. Required accuracy
(including temperature and aging) depends on
frequency band and channel bandwidth /
spacing.
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
PLL turn-on / hop time
–89
–89
–90
–98
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
µ
s
@ 50 kHz offset from carrier
@ 100 kHz offset from carrier
@ 200 kHz offset from carrier
@ 500 kHz offset from carrier
@ 1 MHz offset from carrier
@ 2 MHz offset from carrier
@ 5 MHz offset from carrier
@ 10 MHz offset from carrier
–107
–113
–119
–129
88.4
85.1
88.4
Time from leaving the IDLE state until arriving in
the RX, FSTXON or TX state, when not
performing calibration.
Crystal oscillator running.
PLL RX/TX settling time
PLL TX/RX settling time
PLL calibration time
9.3
20.7
694
9.6
21.5
721
9.6
21.5
721
Settling time for the 1·IF frequency step from RX
to TX
µ
s
µ
s
µ
s
Settling time for the 1·IF frequency step from TX
to RX
Calibration can be initiated manually or
automatically before entering or after leaving
RX/TX.
Table 9: Frequency Synthesizer Parameters
SWRS038D
Page 15 of 92
CC1100
4.7 Analog
Temperature Sensor
sensor in the IDLE state.
Parameter
Min
Typ
Max
Unit
Condition/Note
0.651
0.747
0.847
0.945
2.45
0
V
V
V
V
Output voltage at –40
°
C
Output voltage at 0
°
C
Output voltage at +40
°
C
Output voltage at +80
°
C
Temperature coefficient
mV/
°
C Fitted
from –20
°
C to +80
°
C
Error in calculated
temperature, calibrated
-2
*
2
*
°
C
From –20
°
C to +80
°
C when using 2.45 mV /
°
C,
after 1-point calibration at room temperature
*
The indicated minimum and maximum error with 1-
point calibration is based on simulated values for
typical process parameters
Current consumption
0.3
mA
increase when enabled
Table 10: Analog Temperature Sensor Parameters
4.8 DC
Characteristics
Tc = 25
°
C if nothing else stated.
Digital Inputs/Outputs
Logic “0” input voltage
Logic “1” input voltage
Logic “0” output voltage
Logic “1” output voltage
Logic “0” input current
Logic “1” input current
Min
Max
0.7
Unit
V
Condition
0
VDD-0.7
0
VDD
0.5
V
V
For up to 4 mA output current
For up to 4 mA output current
Input equals 0V
VDD-0.3
N/A
VDD
–50
50
V
nA
nA
N/A
Input equals VDD
Table 11: DC Characteristics
4.9 Power-On
Reset
functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until
Parameter
Min Typ Max Unit Condition/Note
Power-up ramp-up time.
Power off time
5
ms
ms
From 0V until reaching 1.8V
1
Minimum time between power-on and power-off
Table 12: Power-On Reset Requirements
SWRS038D
Page 16 of 92
CC1100
5
Pin Configuration
20 19 18 17 16
SCLK 1
SO (GDO1) 2
GDO2 3
15 AVDD
14 AVDD
13 RF_N
12 RF_P
11 AVDD
DVDD 4
DCOUPL 5
GND
Exposed die
attach pad
6
7
8
9 10
Figure 1: Pinout Top View
Note: The exposed die attach pad
must
be connected to a solid ground plane as this is the main
ground connection for the chip.
Pin #
Pin Name
Pin type
Description
1
2
SCLK
Digital Input
Digital Output
Serial configuration interface, clock input
Serial configuration interface, data output.
Optional general output pin when CSn is high
Digital output pin for general use:
SO (GDO1)
3
GDO2
Digital Output
•
•
•
•
•
Test signals
FIFO status signals
Clear Channel Indicator
Clock output, down-divided from XOSC
Serial output RX data
4
5
DVDD
Power (Digital)
Power (Digital)
1.8 – 3.6 V digital power supply for digital I/O’s and for the digital core
voltage regulator
DCOUPL
1.6 – 2.0 V digital power supply output for decoupling.
NOTE: This pin is intended for use with the
CC1100
only. It can not be used
to provide supply voltage to other devices.
6
GDO0
Digital I/O
Digital output pin for general use:
(ATEST)
•
•
•
•
•
•
Test signals
FIFO status signals
Clear Channel Indicator
Clock output, down-divided from XOSC
Serial output RX data
Serial input TX data
Also used as analog test I/O for prototype/production testing
Serial configuration interface, chip select
Crystal oscillator pin 1, or external clock input
1.8 – 3.6 V analog power supply connection
Crystal oscillator pin 2
7
CSn
Digital Input
Analog I/O
8
XOSC_Q1
AVDD
9
Power (Analog)
Analog I/O
10
XOSC_Q2
SWRS038D
Page 17 of 92
CC1100
Pin #
Pin Name
Pin type
Description
11
12
AVDD
RF_P
Power (Analog)
RF I/O
1.8 -3.6
V analog power supply connection
Positive RF input signal to LNA in receive mode
Positive RF output signal from PA in transmit mode
Negative RF input signal to LNA in receive mode
Negative RF output signal from PA in transmit mode
1.8 – 3.6 V analog power supply connection
1.8 – 3.6 V analog power supply connection
Analog ground connection
13
RF_N
RF I/O
14
15
16
17
18
19
20
AVDD
AVDD
GND
Power (Analog)
Power (Analog)
Ground (Analog)
Analog I/O
RBIAS
DGUARD
GND
External bias resistor for reference current
Power supply connection for digital noise isolation
Ground connection for digital noise isolation
Serial configuration interface, data input
Power (Digital)
Ground (Digital)
Digital Input
SI
Table 13: Pinout Overview
6
Circuit Description
RADIO CONTROL
ADC
LNA
SCLK
ADC
SO (GDO1)
SI
RF_P
RF_N
FREQ
SYNTH
0
CSn
90
GDO0 (ATEST)
GDO2
PA
RC OSC
BIAS
XOSC
RBIAS
XOSC_Q1 XOSC_Q2
Figure 2:
CC1100
Simplified Block Diagram
frequency synthesizer includes a completely
on-chip LC VCO and a 90 degree phase
shifter for generating the I and Q LO signals to
the down-conversion mixers in receive mode.
A simplified block diagram of
CC1100
is shown
CC1100
features a low-IF receiver. The
received RF signal is amplified by the low-
noise amplifier (LNA) and down-converted in
quadrature (I and Q) to the intermediate
frequency (IF). At IF, the I/Q signals are
digitised by the ADCs. Automatic gain control
(AGC), fine channel filtering and demodulation
bit/packet synchronization are performed
digitally.
A crystal is to be connected to XOSC_Q1 and
XOSC_Q2. The crystal oscillator generates the
reference frequency for the synthesizer, as
well as clocks for the ADC and the digital part.
A 4-wire SPI serial interface is used for
configuration and data buffer access.
The digital baseband includes support for
channel configuration, packet handling, and
data buffering.
The transmitter part of
CC1100
is based on
direct synthesis of the RF frequency. The
SWRS038D
Page 18 of 92
CC1100
7
Application Circuit
Only a few external components are required
for using the
CC1100
. The recommended
Figure 4. The externa
l components are
The balun and LC filter component values and
their placement are important to keep the
performance
optimized.
It
is
highly
recommended to follow the CC1100EM
Crystal
Bias Resistor
The crystal oscillator uses an external crystal
with two loading capacitors (C81 and C101).
The bias resistor R171 is used to set an
accurate bias current.
Additional Filtering
Balun and RF Matching
Additional external components (e.g. an RF
SAW filter) may be used in order to improve
the performance in specific applications.
The components between the RF_N/RF_P
pins and the point where the two signals are
joined together (C131, C121, L121 and L131
L121, L131, C121, L122, C131, C122 and
L132 for the 868/915 MHz reference design
RF signal on
CC1100
to a single-ended RF
signal. C124 is needed for DC blocking.
Together with an appropriate LC network, the
balun components also transform the
impedance to match a 50
Ω
antenna (or
cable). Suggested values for 315 MHz, 433
Power Supply Decoupling
The power supply must be properly decoupled
close to the supply pins. Note that decoupling
capacitors are not shown in the application
circuit. The placement and the size of the
decoupling capacitors are very important to
achieve the optimum performance. The
should be followed closely.
Component
C51
Description
Decoupling capacitor for on-chip voltage regulator to digital part
C81/C101
C121/C131
C122
RF balun/matching capacitors
RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching
capacitor (868/915 MHz).
C123
C124
RF LC filter/matching capacitor
RF balun DC blocking capacitor
C125
RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna)
RF balun/matching inductors (inexpensive multi-layer type)
L121/L131
L122
RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor
(868/915 MHz).
(inexpensive multi-layer type)
L123
L124
L132
R171
XTAL
RF LC filter/matching filter inductor (inexpensive multi-layer type)
RF LC filter/matching filter inductor (inexpensive multi-layer type)
RF balun/matching inductor.
(inexpensive multi-layer type)
Resistor for internal bias current reference.
Table 14: Overview of External Components (excluding supply decoupling capacitors)
SWRS038D
Page 19 of 92
CC1100
1.8V-3.6V power supply
R171
SI
Antenna
(50 Ohm)
SCLK
1 SCLK
AVDD 15
C131
L131
SO
2 SO
(GDO1)
AVDD 14
RF_N 13
RF_P 12
AVDD 11
(GDO1)
GDO2
(optional)
C125
C123
CC1100
3 GDO2
DIE ATTACH PAD:
4 DVDD
L122
L123
C122
C121
5 DCOUPL
L121
C124
C51
GDO0
(optional)
CSn
XTAL
C81
C101
Figure 3: Typical Application and Evaluation Circuit 315/433 MHz
(excluding supply
decoupling capacitors)
1.8V-3.6V power supply
R171
SI
Antenna
(50 Ohm)
C131
L132
SCLK
1 SCLK
AVDD 15
AVDD 14
RF_N 13
SO
L131
L121
2 SO (GDO1)
3 GDO2
(GDO1)
GDO2
(optional)
C125
L123 L124
C121
4 DVDD
DIE ATTACH PAD:
RF_P 12
C122
5 DCOUPL
AVDD 11
C123
L122
C124
C51
GDO0
(optional)
CSn
XTAL
C81
C101
Figure 4: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply
decoupling capacitors)
SWRS038D
Page 20 of 92
CC1100
Component
Value at 315MHz
Value at 433MHz
Value at
Manufacturer
868/915MHz
C51
C81
100 nF ± 10%, 0402 X5R
27 pF ± 5%, 0402 NP0
27 pF ± 5%, 0402 NP0
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
C101
C121
6.8 pF ± 0.5 pF,
0402 NP0
3.9 pF ± 0.25 pF,
0402 NP0
1.0 pF ± 0.25
pF, 0402 NP0
C122
C123
C124
C125
C131
L121
L122
L123
L124
L131
L132
12 pF ± 5%, 0402
NP0
8.2 pF ± 0.5 pF,
0402 NP0
1.5 pF ± 0.25
pF, 0402 NP0
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
Murata LQG15HS series
6.8 pF ± 0.5 pF,
0402 NP0
5.6 pF ± 0.5 pF,
0402 NP0
3.3 pF ± 0.25
pF, 0402 NP0
220 pF ± 5%,
0402 NP0
220 pF ± 5%,
0402 NP0
100 pF ± 5%,
0402 NP0
220 pF ± 5%,
0402 NP0
220 pF ± 5%,
0402 NP0
100 pF ± 5%,
0402 NP0
6.8 pF ± 0.5 pF,
0402 NP0
3.9 pF ± 0.25 pF,
0402 NP0
1.5 pF ± 0.25
pF, 0402 NP0
33 nH ± 5%, 0402
monolithic
27 nH ± 5%, 0402
monolithic
12 nH ± 5%,
0402 monolithic
18 nH ± 5%, 0402
monolithic
22 nH ± 5%, 0402
monolithic
18 nH ± 5%,
0402 monolithic
33 nH ± 5%, 0402
monolithic
27 nH ± 5%, 0402
monolithic
12 nH ± 5%,
0402 monolithic
12 nH ± 5%,
0402 monolithic
33 nH ± 5%, 0402
monolithic
27 nH ± 5%, 0402
monolithic
12 nH ± 5%,
0402 monolithic
18 nH ± 5%,
0402 monolithic
R171
XTAL
56 k
Ω
± 1%, 0402
Koa RK73 series
NDK, AT-41CD2
26.0 MHz surface mount crystal
Table 15: Bill Of Materials for the Application Circuit
SWRS038D
Page 21 of 92
CC1100
8
Configuration Overview
CC1100
can be configured to achieve optimum
performance for many different applications.
Configuration is done using the SPI interface.
The following key parameters can be
programmed:
•
Forward Error Correction (FEC) with
interleaving
Data Whitening
•
•
Wake-On-Radio (WOR)
•
•
•
•
•
•
•
•
•
Power-down / power up mode
Crystal oscillator power-up / power-down
Receive / transmit mode
RF channel selection
Data rate
Modulation format
RX channel filter bandwidth
RF output power
Data buffering with separate 64-byte
receive and transmit FIFOs
Packet radio hardware support
Details of each configuration register can be
Figure 5
shows a simplified state diagram that
explains the main
CC1100
states, together with
typical usage and current consumption. For
detailed information on controlling the
CC1100
state machine, and a complete state diagram,
•
SWRS038D
Page 22 of 92
CC1100
Sleep
Lowest power mode. Most
SPWD or wake-on-radio (WOR)
register values are retained.
Current consumption typ
400 nA, or typ 900 nA when
wake-on-radio (WOR) is
enabled.
SIDLE
Default state when the radio is not
receiving or transmitting. Typ.
current consumption: 1.6 mA.
CSn = 0
IDLE
SXOFF
CSn = 0
SCAL
Used for calibrating frequency
synthesizer upfront (entering
receive or transmit mode can
then be done quicker).
Transitional state. Typ. current
consumption: 8.2 mA.
All register values are
retained. Typ. current
consumption; 0.16 mA.
Manual freq.
synth. calibration
Crystal
oscillator off
SRX or STX or SFSTXON or wake-on-radio (WOR)
Frequency
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state. Typ. current consumption: 8.2 mA.
synthesizer startup,
optional calibration,
settling
SFSTXON
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the STX
command strobe.Typ. current
consumption: 8.2 mA.
Frequency
synthesizer on
STX
SRX or wake-on-radio (WOR)
STX
TXOFF_MODE = 01
SFSTXON or RXOFF_MODE = 01
Typ. current consumption:
13.5 mA at -6 dBm output,
16.9 mA at 0 dBm output,
30.7 mA at +10 dBm output.
Typ. current
consumption:
from 14.4 mA (strong
input signal) to 15.4mA
(weak input signal).
STX or RXOFF_MODE=10
SRX or TXOFF_MODE = 11
Transmit mode
Receive mode
TXOFF_MODE = 00
RXOFF_MODE = 00
Optional transitional state. Typ.
current consumption: 8.2mA.
In FIFO-based modes,
In FIFO-based modes,
transmission is turned off and
this state entered if the TX
FIFO becomes empty in the
middle of a packet. Typ.
reception is turned off and this
state entered if the RX FIFO
overflows. Typ. current
TX FIFO
underflow
Optional freq.
synth. calibration
RX FIFO
overflow
consumption: 1.6 mA.
current consumption: 1.6 mA.
SFTX
SFRX
IDLE
Figure 5: Simplified State Diagram, with Typical Current Consumption at 1.2 kBaud Data Rate
SWRS038D
Page 23 of 92
CC1100
9
Configuration Software
CC1100
can be configured using the SmartRF
®
software is highly recommended for obtaining
optimum register settings, and for evaluating
performance and functionality. A screenshot of
the SmartRF
®
Studio user interface for
CC1100
After chip reset, all the registers have default
The optimum register setting might differ from
the default value. After a reset all registers that
shall be different from the default value
therefore needs to be programmed through
the SPI
interface.
10 4-wire
Serial Configuration and Data Interface
The CSn pin must be kept low during transfers
on the SPI bus. If CSn goes high during the
transfer of a header byte or during read/write
CC1100
is configured via a simple 4-wire SPI-
compatible interface (SI, SO, SCLK and CSn)
where
CC1100
is the slave. This interface is
also used to read and write buffered data. All
transfers on the SPI interface are done most
significant bit first.
from/to a register,
the transfer will be
cancelled. The timing for the address and data
All transactions on the SPI interface start with
a header byte
containing a R/W;¯ bit, a burst
access bit (B), and a 6-bit address (A
5
– A
0
).
When CSn is pulled low, the MCU must wait
until
CC1100
SO pin goes low before starting to
transfer the header byte. This indicates that
the crystal is running. Unless the chip was in
SWRS038D
Page 24 of 92
CC1100
the SLEEP or XOFF states, the SO pin will
always go low immediately after taking CSn
low.
Figure 7: Configuration Registers Write and Read Operations
Parameter
Description
Min
Max
Units
f
SCLK
SCLK frequency
100 ns delay inserted between address byte and data byte (single access), or
between address and data, and between each data byte (burst access).
–
10
MHz
SCLK frequency, single access
–
–
9
No delay between address and data byte
SCLK frequency, burst access
No delay between address and data byte, or between data bytes
6.5
t
sp,pd
t
sp
CSn low to positive edge on SCLK, in power-down mode
150
20
50
50
–
–
µ
s
ns
ns
ns
ns
ns
ns
CSn low to positive edge on SCLK, in active mode
–
t
ch
Clock high
–
t
cl
Clock low
–
t
rise
t
fall
t
sd
Clock rise time
Clock fall time
5
5
–
–
Setup data (negative SCLK edge) to
Single access
55
positive edge on SCLK
(t
sd
applies between address and data bytes, and between
data bytes)
Burst access
76
–
t
hd
t
ns
Hold data after positive edge on SCLK
Negative edge on SCLK to CSn high.
20
20
–
–
ns
ns
Table 16: SPI Interface Timing Requirements
depends on the start-up time of the crystal being used. The 150 us in
Table 16 is the
crystal oscillator
NDK.
SWRS038D
Page 25 of 92
CC1100
10.1 Chip
Status Byte
when the chip is in receive mode. Likewise, TX
is active when the chip is transmitting.
When the header byte, data byte, or command
strobe is sent on the SPI interface, the chip
status byte is sent by the
CC1100
on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
before the first positive edge of SCLK. The
running.
The last four bits (3:0) in the status byte con-
operations (the R/W;¯ bit in the header byte is
reading from the RX FIFO. For write
contains the number of bytes that can be
This value reflects the state of the chip. The
XOSC and power to the digital core is on in
the IDLE state, but all other modules are in
power down. The frequency and channel
configuration should only be updated when the
chip is in this state. The RX state will be active
written
to
the
TX
FIFO.
When
FIFO_BYTES_AVAILABLE=15
, 15 or more
bytes are available/free.
Table 17 give
s a status byte summary.
Bits
Name
Description
7
CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when
using the SPI interface.
6:4
STATE[2:0]
Indicates the current main state machine mode
Value State
Description
000
IDLE
IDLE state
(Also reported for some transitional states
instead of SETTLING or CALIBRATE)
001
010
011
100
RX
Receive mode
Transmit mode
Fast TX ready
TX
FSTXON
CALIBRATE
Frequency synthesizer calibration is
running
101
110
SETTLING
PLL is settling
RXFIFO_OVERFLOW
RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with
SFRX
111
TXFIFO_UNDERFLOW
TX FIFO has underflowed. Acknowledge
with
SFTX
3:0
FIFO_BYTES_AVAILABLE[3:0]
The number of bytes available in the RX FIFO or free bytes in the TX FIFO
Table 17: Status Byte Summary
10.2 Register
Access
the status byte is sent on the SO pin each time
a header byte or data byte is transmitted on
the SI pin. When reading from registers, the
status byte is sent on the SO pin each time a
header byte is transmitted on the SI pin.
The configuration registers on the
CC1100
are
located on SPI addresses from 0x00 to 0x2E.
registers. It is highly recommended to use
SmartRF
®
Studio [7] to gene
rate optimum
register settings. The detailed description of
registers can be both written to and read. The
R/W;¯ bit controls if the register should be
written to or read. When writing to registers,
Registers with consecutive addresses can be
accessed in an efficient way by setting the
burst bit (B) in the header byte. The address
bits (A
5
– A
0
) set the start address in an
internal address counter. This counter is
incremented by one each new byte (every 8
clock pulses). The burst access is either a
SWRS038D
Page 26 of 92
CC1100
read or a write access and must be terminated
by setting CSn high.
For register addresses in the range 0x30-
0x3D, the burst bit is used to select between
status registers, burst bit is one, and command
Because of this, burst access is not available
for status registers and they must be accesses
one at a time. The status registers can only be
read.
10.5 FIFO
Access
The 64-byte TX FIFO and the 64-byte RX
FIFO are accessed through the 0x3F address.
When the R/W;¯ bit is zero, the TX FIFO is
accessed, and the RX FIFO is accessed when
the R/W;¯ bit is one.
10.3 SPI
Read
When reading register fields over the SPI
interface while the register fields are updated
The TX FIFO is write-only, while the RX FIFO
is read-only.
a small, but finite,
The burst bit is used to determine if the FIFO
access is a single byte access or a burst
access. The single byte access method
expects a header byte with the burst bit set to
zero and one data byte. After the data byte a
new header byte is expected; hence, CSn can
remain low. The burst access method expects
one header byte and then consecutive data
bytes until terminating the access by setting
CSn high.
probability that a single read from the register
is being corrupt. As an example, the
being corrupt, assuming the maximum data
rate is used, is approximately 80 ppm. Refer to
10.4 Command
Strobes
Command Strobes may be viewed as single
byte instructions to
CC1100
. By addressing a
command strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 13
The following header bytes access the FIFOs:
•
•
•
•
0x3F: Single byte access to TX FIFO
0x7F: Burst access to TX FIFO
0xBF: Single byte access to RX FIFO
0xFF: Burst access to RX FIFO
The command strobe registers are accessed
by transferring a single header byte (no data is
being transferred). That is, only the R/W;¯ bit,
the burst access bit (set to 0), and the six
address bits (in the range 0x30 through 0x3D)
are written. The R/W;¯ bit can be either one or
When writing to the TX FIFO, the status byte
byte can be used to detect TX FIFO underflow
while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
free
before
writing the byte in progress to the
TX FIFO. When the last byte that fits in the TX
FIFO is transmitted on SI, the status byte
received concurrently on SO will indicate that
one byte is free in the TX FIFO.
zero
and
will
determine
how
the
byte should be interpreted.
When writing command strobes, the status
byte is sent on the SO pin.
The TX FIFO may be flushed by issuing a
command strobe will flush the RX FIFO. A
issued in the IDLE, TXFIFO_UNDERLOW, or
RXFIFO_OVERFLOW states. Both FIFOs are
flushed when going to the SLEEP state.
A command strobe may be followed by any
other SPI access without pulling CSn high.
one will have to waith for SO to go low again
before the next header byte can be issued as
executed immediately, with the exception of
executed when CSn goes high.
Figure 9 gives
a brief overview of different
register access types possible.
SWRS038D
Page 27 of 92
CC1100
10.6 PATABLE
Access
written and read from the lowest setting (0) to
the highest (7), one byte at a time. An index
counter is used to control the access to the
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the
highest value is reached the counter restarts
at zero.
The 0x3E address is used to access the
power control settings. The SPI expects up to
eight data bytes after receiving the address.
power ramp-up and ramp-down can be
achieved, as well as ASK modulation shaping
for reduced bandwidth. Note that both the ASK
modulation shaping and the PA ramping is
limited to output powers up to -1 dBm, and the
PATABLE
settings allowed are 0x00 and 0x30
to 0x3F. See SmartRF
®
Studio [7] for
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The R/W;¯ bit controls whether the
access is a read or a write access.
recommended shaping
sequences.
/
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
output power programming.
the PA control settings to use for each of the
eight PA power values (selected by the 3-bit
when entering the SLEEP state, except for the
first byte (index 0).
Figure 9: Register Access Types
11 Microcontroller
Interface and Pin Configuration
(GDO1) that can output internal status
In a typical system,
CC1100
will interface to a
microcontroller. This microcontroller must be
able to:
information useful for control software. These
pins can be used to generate interrupts on the
on the signals that can be programmed.
GDO1 is shared with the SO pin in the SPI
interface. The default setting for GDO1
/
SO is
3-state output. By selecting any other of the
programming options, the GDO1
/
SO pin will
become a generic pin. When CSn is low, the
pin will always function as a normal SO pin.
•
Program
CC1100
into different modes
•
Read and write buffered data
•
Read back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLK and CSn).
11.1 Configuration
Interface
In the synchronous and asynchronous serial
modes, the GDO0 pin is used as a serial TX
data input pin while in transmit mode.
The microcontroller uses four I/O pins for the
SPI configuration interface (SI, SO, SCLK and
The GDO0 pin can also be used for an on-chip
analog temperature sensor. By measuring the
voltage on the GDO0 pin with an external
ADC, the temperature can be calculated.
Specifications for the temperature sensor are
11.2 General
Control and Status Pins
The
CC1100
has two dedicated configurable
pins (GDO0 and GDO2) and one shared pin
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CC1100
latched and a command strobe is generated
internally according to the pin configuration. It
is only possible to change state with this
functionality. That means that for instance RX
will not be restarted if SI and SCLK are set to
RX and CSn toggles. When CSn is low the SI
and SCLK has normal SPI functionality.
temperature sensor output is only available
when the frequency synthesizer is enabled
(e.g. the MANCAL, FSTXON, RX, and TX
states). It
is necessary to write 0xBF to the
sensor in the IDLE state. Before leaving the
restored to its default value (0x7F).
All pin control command strobes are executed
delayed until CSn goes high.
11.3 Optional
Radio Control Feature
The
CC1100
has an optional way of controlling
the radio, by reusing SI, SCLK, and CSn from
the SPI interface. This feature allows for a
simple three-pin control of the major states of
the radio: SLEEP, IDLE, RX, and TX.
CSn SCLK SI
Function
1
↓
↓
↓
↓
X
0
0
1
1
X
Chip unaffected by SCLK/
SI
0
1
This optional functionality is enabled with the
0
1
State changes are commanded as follows
:
When CSn is high the SI and SCLK is set to
SPI
mode
SPI
SPI mode (wakes up into
0
mode IDLE
if in SLEEP/XOFF)
Table 18: Optional Pin Control Coding
12 Data
Rate Programming
The data rate used when transmitting, or the
data rate expected in receive is programmed
by
the
an
d
the
The data rate is given by the formula below.
As the formula shows, the programmed data
rate depends on the crystal frequency.
The data rate can be set from 1.2 kBaud to
500 kBaud with the minimum step size of:
Min Data
Rate
[kBaud]
Typical Data
Rate
[kBaud]
Max Data
Rate
[kBaud]
Data rate
Step Size
[kBaud]
(
256
+
DRATE
_
M
)
⋅
2
DRATE
_
E
R
DATA
=
⋅
f
XOSC
2
28
0.8
3.17
6.35
12.7
25.4
50.8
101.6
203.1
406.3
1.2 / 2.4
4.8
3.17
6.35
12.7
25.4
50.8
101.6
203.1
406.3
500
0.0062
0.0124
0.0248
0.0496
0.0992
0.1984
0.3967
0.7935
1.5869
9.6
The following approach can be used to find
suitable values for a given data rate:
19.6
38.4
76.8
153.6
250
R
DATA
⋅
2
20
⎢
⎥
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
DRATE
_
E
=
log
⎢
2
f
XOSC
⎢
⎣
⎥
⎦
R
DATA
⋅
2
28
f
XOSC
⋅
2
DRATE
_
E
DRATE
_
M
=
−
256
500
Table 19: Data Rate Step Size
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CC1100
13 Receiver
Channel Filter Bandwidth
In order to meet different channel width
requirements, the receiver channel filter is
control the receiver channel filter bandwidth,
which scales with the crystal oscillator
frequency. The following formula gives the
relation between the register settings and the
channel filter bandwidth:
For best performance, the channel filter
bandwidth should be selected so that the
signal bandwidth occupies at most 80% of the
channel filter bandwidth. The channel centre
tolerance due to crystal accuracy should also
be subtracted from the signal bandwidth. The
following example illustrates this:
With the channel filter bandwidth set to
500 kHz, the signal should stay within 80% of
500 kHz, which is 400 kHz. Assuming
915 MHz frequency and ±20 ppm frequency
uncertainty for both the transmitting device and
the receiving device, the total frequency
uncertainty is ±40 ppm of 915MHz, which is
±37 kHz. If the whole transmitted signal
bandwidth is to be received within 400kHz, the
transmitted signal bandwidth should be
maximum 400kHz – 2·37 kHz, which is
326 kHz.
f
XOSC
BW
channel
=
8
⋅
(4
+
CHANBW
_
M
)
·
2
CHANB
W
_
E
The
CC1100
supports the following channel
filter bandwidths:
MDMCFG4.CHANBW_E
MDMCFG4.
CHANBW_M
00
01
10
11
102
81
00
01
10
11
812
650
541
464
406
325
270
232
203
162
135
116
68
58
Table 20: Channel Filter Bandwidths [kHz]
(Assuming a 26MHz crystal)
14 Demodulator,
Symbol Synchronizer, and Data Decision
CC1100
contains an advanced and highly
configurable demodulator. Channel filtering
and frequency offset compensation is
performed digitally. To generate the RSSI level
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
the offset compensator will freeze until carrier
sense asserts. This may be useful when the
radio is in RX for long periods with no traffic,
since the algorithm may drift to the boundaries
when trying to track noise.
The tracking loop has two gain factors, which
affects the settling time and noise sensitivity of
gain before the sync word is detected, and
the sync word has been found.
14.1 Frequency
Offset Compensation
When using 2-FSK, GFSK, or MSK
modulation, the demodulator will compensate
for the offset between the transmitter and
receiver frequency, within certain limits, by
estimating the centre of the received data.
Note that frequency offset compensation is not
supported for ASK or OOK modulation.
14.2 Bit
Synchronization
synthesizer is
according to the estimated frequency offset.
the
frequency
adjusted
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
continuously to adjust for error in the incoming
symbol rate.
automatically
The tracking range of the algorithm is
selectable as fractions of the channel
configuration register.
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CC1100
14.3 Byte
Synchronization
correlation threshold can be set to 15/16,
16/16, or 30/32 bits match. The sync word can
be further qualified using the preamble quality
indicator mechanism described below and/or a
carrier sense condition. The sync word is
registers.
Byte synchronization is achieved by
a
continuous sync word search. The sync word
is a 16 bit configurable field (can be repeated
to get a 32 bit) that is automatically inserted at
the start of the packet by the modulator in
transmit mode. The demodulator uses this
field to find the byte boundaries in the stream
of bits. The sync word will also function as a
system identifier, since only packets with the
correct predefined sync word will be received if
the sync word detection in RX is enabled in
sync word detector correlates against the
user-configured 16 or 32 bit sync word. The
In order to make false detections of sync
words less likely,
a
mechanism called
preamble quality indication (PQI) can be used
to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
order for a detected sync word to be accepted.
15 Packet
Handling Hardware Support
The
CC1100
has built-in hardware support for
•
Packet length check (length byte checked
packet oriented radio protocols.
against
length).
a
programmable maximum
In transmit mode, the packet handler can be
configured to add the following elements to the
packet stored in the TX FIFO:
•
•
•
De-whitening
De-interleaving and decoding
and Table 22)
with RSSI value, Link
Quality Indication, and CRC status can be
appended in the RX FIFO.
•
•
A programmable number of preamble
bytes
A two byte synchronization (sync) word.
Can be duplicated to give a 4-byte sync
word (recommended). It is not possible to
only insert preamble or only insert a sync
word.
•
Bit Field
Name
Description
7:0 RSSI
RSSI value
•
A CRC checksum computed over the
data field.
Table 21: Received Packet Status Byte 1
(first byte appended after the data)
•
•
The recommended setting is 4-byte
preamble and 4-byte sync word, except
for 500 kBaud data rate where the
recommended preamble length is 8 bytes.
Bit Field
Name
CRC_OK
Description
7
1: CRC for received data OK
(or CRC disabled)
•
•
0: CRC error in received data
Indicating the link quality
In addition, the following can be
implemented on the data field and the
optional 2-byte CRC checksum:
6:0 LQI
Table 22: Received Packet Status Byte 2
(second byte appended after the data)
•
•
Whitening of the data with a PN9
sequence.
Forward error correction by the use of
interleaving and coding of the data
(convolutional coding).
•
•
•
Note that register fields that control the
packet handling features should only be
altered when
CC1100
is in the IDLE state.
•
In receive mode, the packet handling support
will de-construct the data packet by
implementing the following (if enabled):
15.1 Data
Whitening
From a radio perspective, the ideal over the air
data are random and DC free. This results in
the smoothest power distribution over the
occupied bandwidth. This also gives the
regulation loops in the receiver uniform
operation conditions (no data dependencies).
•
•
•
•
Preamble detection.
Sync word detection.
CRC computation and CRC check.
One byte address check.
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CC1100
Real world data often contain long sequences
of zeros and ones. Performance can then be
improved by whitening the data before
transmitting, and de-whitening the data in the
receiver. With
CC1100
, this can be done
XOR-ed with a 9-bit pseudo-random (PN9)
sequence before being transmitted, as shown
in Figure 10.
At the receiver end, the data are
XOR-ed with the same pseudo-random
sequence. This way, the whitening is reversed,
and the original data appear in the receiver.
The PN9 sequence is initialized to all 1’s.
automatically
by
setting
PKTCTRL0.WHITE_DATA=1
. All data, except
the preamble and the sync word, are then
Figure 10: Data Whitening in TX Mode
15.2 Packet
Format
•
•
•
•
•
Optional length byte
Optional address byte
Payload
The format of the data packet can be
configured and consists of the following items
Optional 2 byte CRC
•
•
Preamble
Synchronization word
Optional data whitening
Optionally FEC encoded/decoded
Optional CRC-16 calculation
Legend:
Inserted automatically in TX,
processed and removed in RX.
Optional user-provided fields processed in TX,
processed but not removed in RX.
Preamble bits
(1010…1010)
Data field
Unprocessed user data (apart from FEC
and/or whitening)
8
8
8 x
n
bits
16/32 bits
8 x n bits
16 bits
bits bits
Figure 11: Packet Format
The preamble pattern is an alternating
sequence of ones and zeros (10101010…).
The minimum length of the preamble is
programmable. When enabling TX, the
modulator will start transmitting the preamble.
When the programmed number of preamble
bytes has been transmitted, the modulator will
send the sync word and then data from the TX
FIFO if data is available. If the TX FIFO is
empty, the modulator will continue to send
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CC1100
preamble bytes until the first byte is written to
the TX FIFO. The modulator will then send the
sync word and then the data bytes. The
number of preamble bytes is programmed with
the possibility to have a different length field
configuration than supported for variable
length packets (in variable packet length mode
the length byte is the first byte after the sync
word). At the start of reception, the packet
length is set to a large value. The MCU reads
out enough bytes to interpret the length field in
according to this value. The end of packet will
occur when the byte counter in the packet
the MCU must be able to program the correct
length, before the internal counter reaches the
packet length.
The synchronization word is a two-byte value
sync word provides byte synchronization of the
incoming packet. A one-byte synch word can
preamble pattern. It is also possible to emulate
a
32
bit
sync
word
by
using
word will then be repeated twice.
CC1100
supports both constant packet length
protocols and variable length protocols.
Variable or fixed packet length mode can be
used for packets up to 255 bytes. For longer
packets, infinite packet length mode must be
used.
15.2.2 Packet
Length > 255
Also the packet automation control register,
PKTCTRL0,
can be reprogrammed during TX
and RX. This opens the possibility to transmit
and receive packets that are longer than 256
bytes and still be able to use the packet
handling hardware support. At the start of the
packet, the infinite packet length mode
set to mod(length, 256)
.
On the RX side the
MCU reads out enough bytes to interpret the
register to mod(length, 256)
.
When less than
256 bytes remains of the packet the MCU
disables infinite packet length mode and
activates fixed packet length mode. When the
value, the transmission or reception ends (the
radio enters the state determined by
CRC appending/checking can also be used
Fixed packet length mode is selected by
register.
In
variable
packet
length
mode,
length is configured by the first byte after the
sync word. The packet length is defined as the
payload data, excluding the length byte and
used to set the maximum packet length
allowed in RX. Any packet received with a
will be discarded.
packet length is set to infinite and transmission
and reception will continue until turned off
manually. As described in the next section, this
can be used to support packet formats with
different length configuration than natively
supported by
CC1100
. One should make sure
that TX mode is not turned off during the
transmission of the first half of any byte. Refer
When for example a 600-byte packet is to be
transmitted, the MCU should do the following
•
•
mod(600, 256) = 88.
Note that the minimum packet length
supported (excluding the optional length byte
and CRC) is one byte of payload data.
•
Transmit at least 345 bytes (600 – 255), for
example by filling the 64-byte TX FIFO six
times (384 bytes transmitted).
15.2.1 Arbitrary
Length Field Configuration
•
•
reprogrammed during receive and transmit. In
combination with fixed packet length mode
The transmission ends when the packet
counter reaches 88. A total of 600 bytes
are transmitted.
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CC1100
Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again
0,1,……….,88,………………..255,0,……..,88,………………,255,0,……..,88,………………,255,0,…………………..
600 bytes transmitted and
received
Fixed packet length
enabled when less than
256 bytes remains of
packet
Infinite packet length enabled
Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88
Figure 12: Packet Length > 255
15.3 Packet
Filtering in Receive Mode
FIFO if the CRC check fails. After auto flushing
the RX FIFO, the next state depends on the
CC1100
supports three different types of
packet-filtering; address filtering, maximum
length filtering, and CRC filtering.
When using the auto flush function, the
maximum packet length is 63 bytes in variable
packet length mode and 64 bytes in fixed
packet length mode. Note that the maximum
allowed packet length is reduced by two bytes
15.3.1 Address
Filtering
value than zero enables the packet address
filter. The packet handler engine will compare
the destination address byte in the packet with
register and the 0x00 broadcast address when
PKTCTRL1.ADR_CHK=10
or both 0x00 and
when
enabled, to make room in the RX FIFO for the
two status bytes appended at the end of the
packet. Since the entire RX FIFO is flushed
when the CRC check fails, the previously
received packet must be read out of the FIFO
before receiving the current packet. The MCU
must not read from the current packet until the
CRC has been checked as OK.
0xFF
broadcast
addresses
when
PKTCTRL1.ADR_CHK=11
. If the received
address matches a valid address, the packet is
received and written into the RX FIFO. If the
address match fails, the packet is discarded
and receive mode restarted (regardless of the
15.4 Packet
Handling in Transmit Mode
If the received address matches a valid
address when using infinite packet length
mode
and
address filtering is enabled, 0xFF
will be written into the RX FIFO followed by the
address byte and then the payload data.
The payload that is to be transmitted must be
written into the TX FIFO. The first byte written
must be the length byte when variable packet
length is enabled. The length byte has a value
equal to the payload of the packet (including
the optional address byte). If address
recognition is enabled on the receiver, the
second byte written to the TX FIFO must be
the address byte. If fixed packet length is
enabled, then the first byte written to the TX
FIFO should be the address (if the receiver
uses address recognition).
15.3.2 Maximum
Length Filtering
In
variable
packet
length
mode,
the
used to set the maximum allowed packet
length. If the received length byte has a larger
value than this, the packet is discarded and
receive mode restarted (regardless of the
The modulator will first send the programmed
number of preamble bytes. If data is available
in the TX FIFO, the modulator will send the
two-byte (optionally 4-byte) sync word and
then the payload in the TX FIFO. If CRC is
enabled, the checksum is calculated over all
the data pulled from the TX FIFO and the
result is sent as two extra bytes following the
payload data. If the TX FIFO runs empty
before the complete packet has been
15.3.3 CRC
Filtering
The filtering of a packet when CRC check fails
is
enabled
by
setting
PKTCTRL1.CRC_AUTOFLUSH=1
. The CRC
auto flush function will flush the
entire
RX
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CC1100
transmitted,
the
radio
will
enter
when a packet has been received/transmitted.
Additionally, for packets longer than 64 bytes
the RX FIFO needs to be read while in RX and
the TX FIFO needs to be refilled while in TX.
This means that the MCU needs to know the
number of bytes that can be read from or
written to the RX FIFO and TX FIFO
respectively. There are two possible solutions
to get the necessary status information:
TXFIFO_UNDERFLOW state. The only way to
exit this state is by issuing an SFTX strobe.
Writing to the TX FIFO after it has underflowed
will not restart TX mode.
If whitening is enabled, everything following
the sync words will be whitened. This is done
before the optional FEC/Interleaver stage.
Whitening
is
enabled
by
setting
a) Interrupt Driven Solution
In both RX and TX one can use one of the
GDO pins to give an interrupt when a sync
word has been received/transmitted and/or
If FEC/Interleaving is enabled, everything
following the sync words will be scrambled by
the interleaver and FEC encoded before being
modulated. FEC is enabled by setting
when
a
complete packet has been
received/transmitted
are
associated with
IOCFGx.GDOx_CFG=0x01
) and two that are
2
configurations
for
that
RX
the
are
FIFO
and
15.5 Packet
Handling in Receive Mode
re
gister
the
In receive mode, the demodulator and packet
handler will search for a valid preamble and
the sync word. When found, the demodulator
has obtained both bit and byte synchronism
and will receive the first payload byte.
associated
with
the
TX
FIFO
and
IOCFGx.GDOx_CFG=0x03
) that can be used
as interrupt sources to provide information on
how many bytes are in the RX FIFO and TX
If FEC/Interleaving is enabled, the FEC
decoder will start to decode the first payload
byte. The interleaver will de-scramble the bits
before any other processing is done to the
data.
b) SPI Polling
If whitening is enabled, the data will be de-
whitened at this stage.
given rate to get information about the current
GDO2 and GDO0 values respectively. The
polled at a given rate to get information about
the number of bytes in the RX FIFO and TX
FIFO respectively. Alternatively, the number of
bytes in the RX FIFO and TX FIFO can be
read from the chip status byte returned on the
MISO line each time a header byte, data byte,
or command strobe is sent on the SPI bus.
When variable packet length mode is enabled,
the first byte is the length byte. The packet
handler stores this value as the packet length
and receives the number of bytes indicated by
the length byte. If fixed packet length mode is
used, the packet handler will accept the
programmed number of bytes.
Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is
enabled, the packet handler computes CRC
and matches it with the appended CRC
checksum.
It is recommended to employ an interrupt
driven solution as high rate SPI polling will
reduce the RX sensitivity. Furthermore, as
is a small, but finite, probability that a single
the case when reading the chip status byte.
At the end of the payload, the packet handler
will optionally write two extra packet status
CRC status, link quality indication, and RSSI
value.
15.6 Packet
Handling in Firmware
When implementing a packet oriented radio
protocol in firmware, the MCU needs to know
SWRS038D
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CC1100
16 Modulation
Formats
16.2 Minimum
Shift Keying
CC1100
supports amplitude, frequency, and
phase shift modulation formats. The desired
(preamble, sync word, and payload) will be
MSK modulated.
modulation
format
is
set
in
the
MDMCFG2.MOD_FORMAT
register.
Optionally, the data stream can be Manchester
coded by the modulator and decoded by the
demodulator. This option is enabled by setting
MDMCFG2.MANCHESTER_EN=1
. Manchester
encoding is not supported at the same time as
using the FEC/Interleaver option.
Phase shifts are performed with a constant
transition time.
The fraction of a symbol period used to
change the phase can be modified with the
equivalent to changing the shaping of the
symbol.
16.1 Frequency
Shift Keying
The MSK modulation format implemented in
CC1100
inverts the sync word and data
compared to e.g. signal generators.
2-FSK can optionally be shaped by
Gaussian filter with BT = 1, producing a GFSK
modulated signal.
a
The frequency deviation is programmed with
exponent/mantissa form, and the resultant
deviation is given by:
16.3 Amplitude
Modulation
CC1100
supports two different forms of
amplitude modulation: On-Off Keying (OOK)
and Amplitude Shift Keying (ASK).
OOK modulation simply turns on or off the PA
to modulate 1 and 0 respectively.
f
xosc
2
17
f
dev
=
⋅
(8
+
DEVIATION
_
M
)
⋅
2
DEVIATION
_
E
The ASK variant supported by the
CC1100
allows programming of the modulation depth
(the difference between 1 and 0), and shaping
of the pulse amplitude. Pulse shaping will
produce a more bandwidth constrained output
spectrum. Note that the pulse shaping feature
on the
CC1100
does only support output power
up to about -1dBm. The
PATABL
E
settings that
can be used for pulse shaping are 0x00 and
0x30 to 0x3F.
Format
Symbol
Coding
2-FSK/GFSK
‘0’
‘1’
– Deviation
+ Deviation
Table 23: Symbol Encoding for 2-FSK/GFSK
Modulation
1
Identical to offset QPSK with half-sine
shaping (data coding may differ)
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CC1100
17 Received
Signal Qualifiers and Link Quality Information
A “Preamble Quality Reached” signal can be
IOCFGx.GDOx_CFG=8
. It is also possible to
determine if preamble quality is reached by
PKTSTATUS
register. This signal / bit asserts
when the received signal exceeds the PQT.
CC1100
has several qualifiers that can be used
to increase the likelihood that a valid sync
word is detected.
17.1 Sync
Word Qualifier
If sync word detection in RX is enabled in
filling the RX FIFO and perform the packet
valid sync word has been detected. The sync
17.3 RSSI
The RSSI value is an estimate of the signal
power level in the chosen channel. This value
is based on the current gain setting in the RX
chain and the measured signal level in the
channel.
word
qualifier
mode
is
set
by
MDMCFG2.SYNC_MODE
and is summarized in
Table 24. Ca
rrier sense is described in Section
In RX mode, the RSSI value can be read
continuously from the RSSI status register until
the demodulator detects a sync word (when
sync word detection is enabled). At that point
the RSSI readout value is frozen until the next
time the chip enters the RX state. The RSSI
value is in dBm with ½dB resolution. The RSSI
update rate, f
RSSI
, depends on the receiver
filter bandwidth (BW
channel
defined in Section
Sync Word Qualifier Mode
000
001
010
011
100
No preamble/sync
15/16 sync word bits detected
16/16 sync word bits detected
30/32 sync word bits detected
No preamble/sync, carrier sense
above threshold
101
110
111
15/16 + carrier sense above threshold
16/16 + carrier sense above threshold
30/32 + carrier sense above threshold
2
⋅
BW
channel
f
RSSI
=
8
⋅
2
FILTER
_
LENGTH
Table 24: Sync Word Qualifier Mode
last RSSI value of the packet is automatically
added to the first byte appended after the
payload.
17.2 Preamble
Quality Threshold (PQT)
The Preamble Quality Threshold (PQT) sync-
word qualifier adds the requirement that the
received sync word must be preceded with a
The RSSI value read from the RSSI status
register is a 2’s complement number. The
following procedure can be used to convert the
RSSI reading to an absolute power level
(RSSI_dBm).
preamble with
a
quality above the
programmed threshold.
Another use of the preamble quality threshold
is as a qualifier for the optional RX termination
1) Read
the RSSI status register
2) Convert
the reading from a hexadecimal
number to a decimal number (RSSI_dec)
The preamble quality estimator increases an
internal counter by one each time a bit is
received that is different from the previous bit,
and decreases the counter by 8 each time a
bit is received that is the same as the last bit.
The threshold is configured with the register
this counter is used to gate sync word
detection. By setting the value to zero, the
preamble quality qualifier of the synch word is
disabled.
3) If
RSSI_dec
≥
128 then RSSI_dBm =
(RSSI_dec – 256)/2 – RSSI_offset
4) Else
if RSSI_dec < 128 then RSSI_dBm =
(RSSI_dec)/2 – RSSI_offset
Table 25 gives typica
l values for the
RSSI_offset.
RSSI reading as a function of input power
level for different data rates.
SWRS038D
Page 37 of 92
CC1100
Data rate [kBaud]
RSSI_offset [dB], 433 MHz
RSSI_offset [dB], 868 MHz
1.2
38.4
250
500
75
75
79
79
74
74
78
77
Table 25: Typical RSSI_offset Values
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input Power [dBm]
1.2 kBuad
38.4 kBaud
250 kBaud
500 kBaud
Figure 13: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input Power [dBm]
1.2 kBaud
250 kBaud
500 kBaud
38.4 kBuad
Figure 14: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz
SWRS038D
Page 38 of 92
CC1100
17.4 Carrier
Sense (CS)
setting.
Carrier Sense (CS) is used as a sync word
qualifier and for CCA and can be asserted
based on two conditions, which can be
individually adjusted:
readout values at the CS threshold at 2.4
kBaud and 250 kBaud data rate respectively.
used.
•
CS is asserted when the RSSI is above a
programmable absolute threshold, and de-
asserted when RSSI is below the same
threshold (with hysteresis).
For other data rates the user must generate
similar tables to find the CS absolute
threshold.
•
CS is asserted when the RSSI has
increased with a programmable number of
dB from one RSSI sample to the next, and
de-asserted when RSSI has decreased
with the same number of dB. This setting
is not dependent on the absolute signal
level and is thus useful to detect signals in
environments with time varying noise floor.
MAX_DVGA_GAIN[1:0]
00
-97.5
-94
01
-91.5
-88
10
11
-79.5
-76
000
001
010
011
100
101
110
111
-85.5
-82.5
-78.5
-76.5
-73.5
-72
-90.5
-88
-84.5
-82.5
-80
-72.5
-70.5
-68
Carrier Sense can be used as a sync word
qualifier that requires the signal level to be
higher than the threshold for a sync word
search to be performed. The signal can also
-85.5
-84
-78
-66
-82
-76
-70
-64
-79
-73.5
-67
-61
Other uses of Carrier Sense include the TX-if-
and the optional fast RX termination (see
Table 26: Typical RSSI Value in dBm at CS
CS can be used to avoid interference from
other RF sources in the ISM bands.
MAX_DVGA_GAIN[1:0]
00
01
-84.5
-82
10
-78.5
-76
-72
-70
-68
-66
-64
-62
11
-72.5
-70
-66
-64
-62
-60
-58
-56
17.4.1 CS
Absolute Threshold
000
001
010
011
100
101
110
111
-90.5
-88
The absolute threshold related to the RSSI
value depends on the following register fields:
-84.5
-82.5
-80.5
-78
-78.5
-76.5
-74.5
-72
•
•
•
•
•
-76.5
-74.5
-70
-68
Table 27: Typical RSSI Value in dBm at CS
absolute threshold can be adjusted ±7 dB in
steps
of
1
dB
using
between blocker tolerance/selectivity and
sensitivity. The value sets the desired signal
level in the channel into the demodulator.
Increasing this value reduces the headroom
for blockers, and therefore close-in selectivity.
It is strongly recommended to use SmartRF
®
If the threshold is set high, i.e. only strong
signals are wanted, the threshold should be
adjusted upwards by first reducing the
and
then
the
power consumption in
the receiver front end,
since the highest gain settings are avoided.
SWRS038D
Page 39 of 92
CC1100
17.4.2 CS
Relative Threshold
feature is called TX-if-CCA. Four CCA
requirements can be programmed:
The relative threshold detects sudden changes
in the measured signal level. This setting is not
dependent on the absolute signal level and is
thus useful to detect signals in environments
with a time varying noise floor. The register
is used to enable/disable relative CS, and to
select threshold of 6 dB, 10 dB, or 14 dB RSSI
change.
•
•
•
•
Always (CCA disabled, always goes to TX)
If RSSI is below threshold
Unless currently receiving a packet
Both the above (RSSI below threshold and
not currently receiving a packet)
17.6 Link
Quality Indicator (LQI)
17.5 Clear
Channel Assessment (CCA)
The Link Quality Indicator is a metric of the
current quality of the received signal. If
value is automatically added to the last byte
appended after the payload. The value can
LQI gives an estimate of how easily a received
signal can be demodulated by accumulating
the magnitude of the error between ideal
constellations and the received signal over the
64 symbols immediately following the sync
The Clear Channel Assessment (CCA) is used
to indicate if the current channel is free or
busy. The current CCA state is viewable on
any of the GDO pins by setting
when determining CCA.
given while
CC1100
is in the RX state, the TX or
FSTXON state is only entered if the clear
channel requirements are fulfilled. The chip will
otherwise remain in RX (if the channel
becomes available, the radio will not enter TX
or FSTXON state before a new strobe
command is sent on the SPI interface). This
word. LQI is best used as
a
relative
measurement of the link quality (a high value
indicates a better link than what a low value
does), since the value is dependent on the
modulation format.
18 Forward
Error Correction with Interleaving
18.1 Forward
Error Correction (FEC)
a given length, to be transmitted successfully.
Finally, in realistic ISM radio environments,
transient and time-varying phenomena will
produce occasional errors even in otherwise
good reception conditions. FEC will mask such
errors and, combined with interleaving of the
coded data, even correct relatively long
periods of faulty reception (burst errors).
CC1100
has built in support for Forward Error
Correction (FEC). To enable this option, set
in
fixed
packet
length
mode
employed on the data field and CRC word in
order to reduce the gross bit error rate when
The FEC scheme adopted for
CC1100
is
convolutional coding, in which
n
bits are
generated based on
k
input bits and the
m
most recent input bits, forming a code stream
able to withstand a certain number of bit errors
between each coding state (the
m
-bit window).
operating
near
the
sensitivity
limit.
Redundancy is added to the transmitted data
in such a way that the receiver can restore the
original data in the presence of some bit
errors.
The use of FEC allows correct reception at a
lower SNR, thus extending communication
range if the receiver bandwidth remains
constant. Alternatively, for a given SNR, using
FEC decreases the bit error rate (BER). As the
packet error rate (PER) is related to BER by:
The convolutional coder is a rate 1/2 code with
a constraint length of m = 4. The coder codes
one input bit and produces two output bits;
hence, the effective data rate is halved. I.e. to
transmit at the same effective datarate when
using FEC, it is necessary to use twice as high
over-the-air datarate. This will require a higher
receiver bandwidth, and thus reduce
sensitivity. In other words the improved
PER
=
1
−
(
1
−
BER
)
packet
_
length
a lower BER can be used to allow longer
packets, or a higher percentage of packets of
SWRS038D
Page 40 of 92
CC1100
reception by using FEC and the degraded
sensitivity from a higher receiver bandwidth
will be counteracting factors.
receiver, the received symbols are written into
the columns of the matrix, whereas the data
passed onto the convolutional decoder is read
from the rows of the matrix.
When FEC and interleaving is used at least
one extra byte is required for trellis
termination. In addition, the amount of data
transmitted over the air must be a multiple of
the size of the interleaver buffer (two bytes).
The packet control hardware therefore
automatically inserts one or two extra bytes at
the end of the packet, so that the total length
of the data to be interleaved is an even
number. Note that these extra bytes are
invisible to the user, as they are removed
before the received packet enters the RX
FIFO.
18.2 Interleaving
Data received through radio channels will
often experience burst errors due to
interference and time-varying signal strengths.
In order to increase the robustness to errors
divning multiple bits, interleaving is used
when FEC is enabled. After de-interleaving, a
continuous div of errors in the received
stream will become single errors spread apart.
CC1100
employs matrix interleaving, which is
interleaving and de-interleaving buffers are 4 x
4 matrices. In the transmitter, the data bits
from the rate ½ convolutional coder are written
into the rows of the matrix, whereas the bit
sequence to be transmitted is read from the
columns of the matrix. Conversely, in the
When FEC and interleaving is used the
minimum data payload is 2 bytes.
Interleaver
Write buffer
Interleaver
Read buffer
Packet
Engine
FEC
Encoder
Modulator
Interleaver
Write buffer
Interleaver
Read buffer
FEC
Decoder
Packet
Engine
Demodulator
Figure 15: General Principle of Matrix Interleaving
SWRS038D
Page 41 of 92
CC1100
19 Radio
Control
SIDLE
SPWD
| SWOR
SLEEP
0
CAL_COMPLETE
MANCAL
3,4,5
IDLE
1
CSn = 0
| WOR
SXOFF
SCAL
CSn = 0
XOFF
2
SRX
| STX | SFSTXON | WOR
FS_WAKEUP
6,7
FS_AUTOCAL = 01
&
SRX
| STX | SFSTXON | WOR
FS_AUTOCAL = 00 | 10 | 11
&
CALIBRATE
8
SRX
| STX | SFSTXON | WOR
CAL_COMPLETE
SETTLING
9,10,11
SFSTXON
FSTXON
18
STX
SRX
| WOR
SRX
TXOFF_MODE=01
STX
SFSTXON
|
RXOFF_MODE = 01
RXTX_SETTLING
21
STX
|
RXOFF_MODE = 10
( STX
| SFSTXON
) & CCA
|
RXOFF_MODE = 01 | 10
TX
19,20
RX
13,14,15
TXOFF_MODE = 10
RXOFF_MODE = 11
SRX
| TXOFF_MODE
= 11
TXRX_SETTLING
16
RXOFF_MODE = 00
&
FS_AUTOCAL = 10 | 11
TXOFF_MODE = 00
&
FS_AUTOCAL = 10 | 11
TXFIFO_UNDERFLOW
RXFIFO_OVERFLOW
CALIBRATE
12
TXOFF_MODE = 00
RXOFF_MODE = 00
&
FS_AUTOCAL = 00 | 01
&
FS_AUTOCAL = 00 | 01
TX_UNDERFLOW
22
RX_OVERFLOW
17
SFTX
SFRX
IDLE
1
Figure 16: Complete Radio Control State Diagram
19.1 Power-On
Start-Up Sequence
CC1100
has a built-in state machine that is
used to switch between different operational
states (modes). The change of state is done
either by using command strobes or by
internal events such as TX FIFO underflow.
When the power supply is turned on, the
system must be reset. This is achieved by one
of the two sequences described below, i.e.
automatic power-on reset (POR) or manual
reset.
A simplified state diagram, together with
typical usage and current consumption, is
16. The nu
mbers refer to the state number
This register is primarily for test purposes.
After the automatic power-on reset or manual
reset it is also recommended to change the
signal that is output on the GDO0 pin. The
default setting is to output a clock signal with a
frequency of CLK_XOSC/192, but to optimize
SWRS038D
Page 42 of 92
CC1100
XOSC and voltage regulator switched on
40 us
performance in TX and RX an alternative GDO
setting should be selected from the settings
CSn
SO
19.1.1 Automatic
POR
A power-on reset circuit is included in the
CC1100
. The minimum requirements stated in
Table 12 m
ust be followed for the power-on
reset to fu
nction properly. The internal power-
XOSC Stable
SRES
SI
When the
CC1100
reset is completed the chip
will be in the IDLE state and the crystal
oscillator will be running. If the chip has had
sufficient time for the crystal oscillator to
stabilize after the power-on-reset the SO pin
will go low immediately after taking CSn low. If
CSn is taken low before reset is completed the
SO pin will first go high, indicating that the
crystal oscillator is not stabilized, before going
Note that the above reset procedure is only
required just after the power supply is first
turned on. If the user wants to reset the
CC1100
after this, it is only necessary to issue an
SRES
command strobe.
19.2 Crystal
Control
The crystal oscillator (XOSC) is either
automatically controlled or always on, if
MCSM0.XOSC_FORCE_O
N
is set.
In the automatic mode, the XOSC will be
strobes are issued; the state machine then
goes to XOFF or SLEEP respectively. This
can only be done from the IDLE state. The
XOSC will be turned off when CSn is released
(goes high). The XOSC will be automatically
turned on again when CSn goes low. The
state machine will then go to the IDLE state.
The SO pin on the SPI interface must be
pulled low before the SPI interface is ready to
Figure 17: Power-On Reset
19.1.2 Manual
Reset
The other global reset possibility on
CC1100
this strobe, all internal registers and states are
set to the default, IDLE state. The manual
If the XOSC is forced on, the crystal will
always stay on even in the SLEEP state.
Crystal oscillator start-up time depends on
crystal ESR and load capacitances. The
electrical specification for the crystal oscillator
•
Set SCLK
= 1 and SI
= 0, to avoid
potential problems with pin control mode
•
•
Strobe CSn low / high.
Hold CSn high for at least 40µs relative to
pulling CSn low
19.3 Voltage
Regulator Control
The voltage regulator to the digital core is
controlled by the radio controller. When the
chip enters the SLEEP state, which is the state
with the lowest current consumption, the
voltage regulator is disabled. This occurs after
strobe has been sent on the SPI interface. The
chip is now in the SLEEP state. Setting CSn
•
Pull CSn low and wait for SO to go low
•
•
When SO goes low again, reset is
complete and the chip is in the IDLE state.
SWRS038D
Page 43 of 92
CC1100
low again will turn on the regulator and crystal
oscillator and make the chip enter the IDLE
state.
state will change as indicated by the
destinations are the same as for RX.
When wake on radio is enabled, the WOR
module will control the voltage regulator as
The MCU can manually change the state from
RX to TX and vice versa by using the
command strobes. If the radio controller is
used, the current transmission will be ended
and the transition to RX will be done.
19.4 Active
Modes
CC1100
has two active modes: receive and
transmit. These modes are activated directly
command strobes, or automatically by Wake
on Radio.
if-CCA function will be used. If the channel is
not clear, the chip will remain in RX. The
cont
rols
the
The frequency synthesizer must be calibrated
regularly.
CC1100
has one manual calibration
automatic calibration options, controlled by the
conditions for clear channel assessment. See
used to force the radio controller to go to the
IDLE state.
•
•
•
Calibrate when going from IDLE to either
RX or TX (or FSTXON)
19.5 Wake
On Radio (WOR)
Calibrate when going from either RX or TX
to IDLE automatically
The optional Wake on Radio (WOR)
functionality enables
CC1100
to periodically
wake up from SLEEP and listen for incoming
packets without MCU interaction.
Calibrate every fourth time when going
from either RX or TX to IDLE automatically
When the WOR strobe command is sent on
the SPI interface, the
CC1100
will go to the
SLEEP state when CSn is released. The RC
oscillator must be enabled before the WOR
strobe can be used, as it is the clock source
for the WOR timer. The on-chip timer will set
CC1100
into IDLE state and then RX state. After
a programmable time in RX, the chip will go
back to the SLEEP state, unless a packet is
details on how the timeout works.
If the radio goes from TX or RX to IDLE by
performed. The calibration takes a constant
timing details).
When RX is activated, the chip will remain in
receive mode until a packet is successfully
received or the RX termination timer expires
false sync word is detected can be reduced by
using PQT, CS, maximum sync word length,
and sync word qualifier mode as described in
received the radio controller will then go to the
setting. The possible destinations are:
Set the
CC1100
into the IDLE state to exit WOR
mode.
CC1100
can be set up to signal the MCU that a
packet has been received by using the GDO
pins. If
a
packet is received, the
will determine the
•
•
IDLE
behaviour at the end of the received packet.
When the MCU has read the packet, it can put
from the IDLE state. The FIFO will loose its
contents in the SLEEP state.
FSTXON: Frequency synthesizer on and
ready at the TX frequency. Activate TX
•
•
TX: Start sending preamble
The WOR timer has two events, Event 0 and
Event 1. In the SLEEP state with WOR
activated, reaching Event 0 will turn on the
digital regulator and start the crystal oscillator.
Event 1 follows Event 0 after a programmed
timeout.
RX: Start search for a new packet
Similarly, when TX is active the chip will
remain in the TX state until the current packet
has been successfully transmitted. Then the
SWRS038D
Page 44 of 92
CC1100
The time between two consecutive Event 0 is
programmed with a mantissa value given by
oscillator is locked to the main crystal
frequency divided by 750.
In applications where the radio wakes up very
often, typically several times every second, it
is possible to do the RC oscillator calibration
and
an
exponent
value
set
by
once
and
then
turn
off
calibration
750
t
Even
t
0
=
⋅
EVEN
T
0
⋅
2
5
⋅
WOR
_
RES
consumption. This requires that RC oscillator
calibration values are read from registers
respectively. If the RC oscillator calibration is
turned off it will have to be manually turned on
again if temperature and supply voltage
changes.
f
XOSC
The Event 1 timeout is programmed with
timing relationship between Event 0 timeout
and Event 1 timeout.
details.
19.6 Timing
The radio controller controls most of the timing
in
CC1100
, such as synthesizer calibration, PLL
lock time, and RX/TX turnaround times. Timing
from IDLE to RX and IDLE to TX is constant,
dependent on the auto calibration setting.
RX/TX and TX/RX turnaround times are
constant. The calibration time is constant
crystal clock cycles for key state transitions.
Figure 19: Event 0 and Event 1 Relationship
The time from the
CC1100
enters SLEEP state
until the next Event0 is programmed to appear
(t
SLEEP
in Figure 19)
should be larger than
11.08 ms when using a 26 MHz crystal and
10.67 ms when a 27 MHz crystal is used. If
t
SLEEP
is less than 11.08 (10.67) ms there is a
chance that the consecutive Event 0 will occur
Power on time and XOSC start-up times are
Note that in a frequency hopping spread
spectrum or a multi-channel protocol the
calibration time can be reduced from 721 µs to
approximately 150 µs. This is explained in
750
seconds
⋅
128
f
XOSC
in detail the theory of operation and the
different registers involved when using WOR,
as well as highlighting important aspects when
using WOR mode.
Description
XOSC
Periods
26 MHz
Crystal
IDLE to RX, no calibration
IDLE to RX, with calibration
2298
88.4
µ
s
809
µ
s
88.4
µ
s
~21037
2298
19.5.1 RC
Oscillator and Timing
IDLE to TX/FSTXON, no
calibration
The frequency of the low-power RC oscillator
used for the WOR functionality varies with
temperature and supply voltage. In order to
keep the frequency as accurate as possible,
the RC oscillator will be calibrated whenever
possible, which is when the XOSC is running
and the chip is not in the SLEEP state. When
the power and XOSC is enabled, the clock
used by the WOR timer is a divided XOSC
clock. When the chip goes to the sleep state,
the RC oscillator will use the last valid
calibration result. The frequency of the RC
IDLE to TX/FSTXON, with
calibration
~21037
809
µ
s
TX to RX switch
560
21.5
µ
s
9.6
µ
s
0.1
µ
s
721
µ
s
721
µ
s
RX to TX switch
250
RX or TX to IDLE, no calibration
RX or TX to IDLE, with calibration
Manual calibration
2
~18739
~18739
Table 28: State Transition Timing
SWRS038D
Page 45 of 92
CC1100
19.7 RX
Termination Timer
For ASK/OOK modulation, lack of carrier
sense is only considered valid after eight
CC1100
has optional functions for automatic
termination of RX after a programmable time.
The main use for this functionality is wake-on-
radio (WOR), but it may be useful for other
applications. The termination timer starts when
in RX state. The timeout is programmable with
expires, the radio controller will check the
condition for staying in RX; if the condition is
not met, RX will terminate.
symbol
periods.
Thus,
the
in ASK/OOK mode when the distance between
“1” symbols is 8 or less.
If RX terminates due to no carrier sense when
or if no sync word was found when using the
will always go back to IDLE if WOR is disabled
and back to SLEEP if WOR is enabled.
determines the state to go to when RX ends.
This means that the chip will not automatically
go back to SLEEP once a sync word has been
received. It is therefore recommended to
always wake up the microcontroller on sync
word detection when using WOR mode. This
can be done by selecting output signal 6 (see
programmable GDO output pins, and
programming the microcontroller to wake up
on an edge-triggered interrupt from this GDO
pin.
The programmable conditions are:
•
receive if sync word has been found
Contin
ue
•
receive if sync word has been found or
preamble quality is above threshold (PQT)
Contin
ue
If the system can expect the transmission to
have started when enabling the receiver, the
The radio controller will then terminate RX if
the first valid carrier sense sample indicates
no carrier (RSSI below threshold). See Section
20 Data
FIFO
received data byte is written to the RX FIFO at
the exact same time as the last byte in the RX
FIFO is read over the SPI interface, the RX
FIFO pointer is not properly updated and the
last read byte is duplicated. To avoid this
problem one should never empty the RX FIFO
before the last byte of the packet is received.
The
CC1100
contains two 64 byte FIFOs, one
for received data and one for data to be
transmitted. The SPI interface is used to read
from the RX FIFO and write to the TX FIFO.
access. The FIFO controller will detect
overflow in the RX FIFO and underflow in the
TX FIFO.
When writing to the TX FIFO it is the
responsibility of the MCU to avoid TX FIFO
overflow. A TX FIFO overflow will result in an
error in the TX FIFO content.
For packet lengths less than 64 bytes it is
recommended to wait until the complete
packet has been received before reading it out
of the RX FIFO.
Likewise, when reading the RX FIFO the MCU
must avoid reading the RX FIFO past its empty
value, since an RX FIFO underflow will result
in an error in the data read out of the RX FIFO.
If the packet length is larger than 64 bytes the
MCU must determine how many bytes can be
read
from
the
RX
FIFO
software routine can be used:
The chip status byte that is available on the
SO pin while transferring the SPI header
contains the fill grade of the RX FIFO if the
access is a read operation and the fill grade of
the TX FIFO if the access is a write operation.
on this.
1.
Read
repeatedly at a rate guaranteed to be at
least twice that of which RF bytes are
received until the same value is returned
twice; store value in
n
.
2. If
n
< # of bytes remaining in packet, read
n
-1 bytes from the RX FIFO.
The number of bytes in the RX FIFO and TX
FIFO can be read from the status registers
SWRS038D
Page 46 of 92
CC1100
FIFO_THR
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
3. Repeat
steps 1 and 2 until
n
= # of bytes
Bytes in TX FIFO
Bytes in RX FIFO
remaining in packet.
61
57
53
49
45
41
37
33
29
25
21
17
13
9
4
8
4. Read
the remaining bytes from the RX
FIFO.
12
16
20
24
28
32
36
40
44
48
52
56
60
64
to program threshold points in the FIFOs.
the corresponding thresholds for the RX and
TX FIFOs. The threshold value is coded in
opposite directions for the RX FIFO and TX
FIFO. This gives equal margin to the overflow
and underflow conditions when the threshold
is reached.
A signal will assert when the number of bytes
in the FIFO is equal to or higher than the
programmed threshold. This signal can be
5
1
Corresponding FIFO Thresholds
Figure 21 sh
ows the number of bytes in both
Figure 20 sh
ows the signal as the respective
FIFO is filled above the threshold, and then
drained below.
Overflow
margin
FIFO_THR=13
NUM_RXBYTES
53 54 55 56 57 56 55 54 53
GDO
NUM_TXBYTES
6
7
8
9
10
9
8
7
6
56 bytes
GDO
FIFO_THR=13
Underflow
8 bytes
margin
RXFIFO
TXFIFO
Figure 21: Example of FIFOs at Threshold
SWRS038D
Page 47 of 92
CC1100
21 Frequency
Programming
The base or start frequency is set by the 24 bit
be set to the centre of the lowest channel
frequency that is to be used.
The frequency programming in
CC1100
is
designed to minimize the programming
needed in a channel-oriented system.
To set up a system with channel numbers, the
desired channel spacing is programmed with
the
The desired channel number is programmed
with the 8-bit channel number register,
channel offset. The resultant carrier frequency
is given by:
spacing registers are mantissa and exponent
respectively.
f
XOSC
2
16
f
carrier
=
⋅
(
FREQ
+
CHAN
⋅
(
(
256
+
CHANSPC
_
M
)
⋅
2
CHANSPC
_
E
−
2
))
automatically calculates the optimum
channel spacing and channel filter bandwidth.
With a 26 MHz crystal the maximum channel
spacing is 405 kHz. To get e.g. 1 MHz channel
spacing one solution is to use 333 kHz
channel spacing and select each third channel
If any frequency programming register is
altered when the frequency synthesizer is
running, the synthesizer may give an
undesired response. Hence, the frequency
programming should only be updated when
the radio is in the IDLE state.
The preferred IF frequency is programmed
frequency is given by:
f
XOSC
f
IF
=
⋅
FREQ
_
IF
2
10
22 VCO
The VCO is completely integrated on-chip.
command strobe is activated in the IDLE
mode.
Note that the calibration values are maintained
in SLEEP mode, so the calibration is still valid
after waking up from SLEEP mode (unless
supply voltage or temperature has changed
significantly).
22.1 VCO
and PLL Self-Calibration
The VCO characteristics will vary with
temperature and supply voltage changes, as
well as the desired operating frequency. In
order to ensure reliable operation,
CC1100
includes frequency synthesizer self-calibration
circuitry. This calibration should be done
regularly, and must be performed after turning
on power and before using a new frequency
(or channel). The number of XOSC cycles for
completing the PLL calibration is given in
To check that the PLL is in lock the user can
and use the lock detector output available on
the GDOx pin as an interrupt for the MCU (x =
0,1, or 2). A positive transition on the GDOx
pin means that the PLL is in lock. As an
alternative the user can read register FSCAL1.
The PLL is in lock if the register content is
different from 0x3F. Refer also to the
CC1100
source code could include a check so that the
PLL is re-calibrated until PLL lock is achieved
if the PLL does not lock the first time.
The calibration can be initiated automatically
or manually. The synthesizer can be
automatically calibrated each time the
synthesizer is turned on, or each time the
synthesizer is turned off automatically. This is
register setting. In manual mode, the
calibration is initiated when the
SCAL
SWRS038D
Page 48 of 92
CC1100
23 Voltage
Regulators
Setting the CSn pin low turns on the voltage
regulator to the digital core and starts the
crystal oscillator. The SO pin on the SPI
interface must go low before the first positive
CC1100
contains several on-chip linear voltage
regulators, which generate the supply voltage
needed by low-voltage modules. These
voltage regulators are invisible to the user, and
can be viewed as integral parts of the various
modules. The user must however make sure
that the absolute maximum ratings and
are not exceeded. The voltage regulator for
the digital core requires one external
decoupling capacitor.
If the chip is programmed to enter power-down
turned off after CSn goes high. The power and
crystal oscillator will be turned on again when
CSn goes low.
The voltage regulator output should only be
used for driving the
CC1100
.
24 Output
Power Programming
The RF output power level from the device
has two levels of programmability, as
illustrated in Figure 22.
Firstly, the special
PATABLE
register can hold up to eight user
selected output power settings. Secondly, the
PATABLE
entry to use. This two-level
functionality provides flexible PA power ramp
up and ramp down at the start and end of
transmission, as well as ASK modulation
shaping. All the PA power settings in the
If OOK modulation is used, the logic 0 and
logic 1 power levels shall be programmed to
index 0 and 1 respectively.
settings for various output levels and
frequency bands. Using PA settings from 0x61
to 0x6F is not recommended. See Section
details.
Table 31
contains output power and current
burst mode if you want to write to other entries
from index
0
up to the
The power ramping at the start and at the end
of a packet can be turned off by setting
program the desired output power to index 0 in
to zero and then
for the first byte (index 0) is lost when entering
the SLEEP state.
315 MHz
Current
433 MHz
Current
868 MHz
Current
915 MHz
Current
Output
Power
[dBm]
Setting Consumption, Setting Consumption, Setting Consumption, Setting Consumption,
Typ. [mA]
Typ. [mA]
Typ. [mA]
Typ. [mA]
-30
-20
-15
-10
-5
0x04
0x17
0x1D
0x26
0x57
0x60
0x85
0xCB
0xC2
10.6
0x04
0x17
0x1C
0x26
0x57
0x60
0x85
0xC8
0xC0
11.5
0x03
0x0D
0x1C
0x34
0x57
0x8E
0x85
0xCC
0xC3
11.9
0x11
0x0D
0x1C
0x26
0x57
0x8E
0x83
0xC9
0xC0
11.8
11.1
12.1
12.4
12.3
11.8
12.7
13.0
13.0
13.0
14.0
14.5
14.3
12.9
13.7
14.1
13.9
0
14.8
15.6
16.9
16.7
5
18.1
19.1
20.0
19.9
7
22.1
24.2
25.8
25.8
10
27.1
29.2
31.1
32.3
SWRS038D
Page 49 of 92
CC1100
315 MHz
433 MHz
868 MHz
915 MHz
Output Current
Default Output Current
Output Current
Output Current
Power
Setting [dBm]
Power
Consumption, Power
Consumption, Power
Typ. [mA]
[dBm]
Consumption, Power
Typ. [mA]
[dBm]
Consumption,
Typ. [mA]
Typ. [mA]
[dBm]
0xC6 8.7
24.5
7.9
25.2 8.9
28.3 7.9
26.8
25 Shaping
and PA Ramping
With ASK modulation, up to eight power
settings are used for shaping. The modulator
contains a counter that counts up when
transmitting a one and down when transmitting
a zero. The counter counts at a rate equal to 8
times the symbol rate. The counter saturates
This counter value is used as an index for a
lookup in the power table. Thus, in order to
should be 7 when ASK is active. The shaping
of the ASK signal is dependent on the
Note that the ASK shaping feature is only
supported for output power levels up to -1
dBm and only values in the range 0x30–0x3F,
together with 0x00 can be used. The same is
the case when implementing PA ramping for
some
examples
of
ASK
shaping.
PATABLE(7)[7:0]
PATABLE(6)[7:0]
PATABLE(5)[7:0]
PATABLE(4)[7:0]
PATABLE(3)[7:0]
PATABLE(2)[7:0]
PATABLE(1)[7:0]
PATABLE(0)[7:0]
The PA uses this
setting.
Settings 0 to PA_POWER are
used during ramp-up at start of
transmission and ramp-down at
end of transmission, and for
ASK/OOK modulation.
Index into PATABLE(7:0)
The SmartRF® Studio software
should be used to obtain optimum
PATABLE settings for various
output powers.
e.g 6
PA_POWER[2:0]
in FREND0 register
Output Power
PATABLE[7]
PATABLE[6]
PATABLE[5]
PATABLE[4]
PATABLE[3]
PATABLE[2]
PATABLE[1]
PATABLE[0]
Time
Bit Sequence
1
0
0
1
0
1
1
0
FREND0.PA_POWER = 3
FREND0.PA_POWER = 7
Figure 23: Shaping of ASK Signal
SWRS038D
Page 50 of 92
CC1100
Output Power [dBm]
PATABLE Setting
0x00
315 MHz
-62.0
-41.7
-21.8
-16.2
-12.8
-10.5
-8.6
433 MHz
-62.0
-39.0
-21.7
-16.1
-12.7
-10.4
-8.5
868 MHz
-57.1
-33.6
-21.2
-16.0
-12.7
-10.5
-8.7
915 MHz
-56.0
-33.1
-21.0
-15.8
-12.5
-10.3
-8.5
0x30
0x31
0x32
0x33
0x34
0x35
0x36
-7.2
-7.1
-7.4
-7.2
0x37
-5.9
-5.8
-6.2
-6.0
0x38
-4.8
-4.9
-5.3
-5.1
0x39
-3.9
-4.0
-4.5
-4.3
0x3A
-3.2
-3.3
-3.8
-3.7
0x3B
-2.5
-2.7
-3.3
-3.1
0x3C
0x3D
0x3E
-2.1
-2.3
-2.8
-2.7
-1.7
-1.9
-2.5
-2.3
-1.3
-1.6
-2.1
-2.0
0x3F
-1.1
-1.3
-1.9
-1.7
Table 32: PATABLE Settings used together with ASK Shaping and PA Ramping
Assume working in the 433 MHz and using
FSK. The
desired output power is -10 dBm.
Figure 24
shows how the PATABLE should
look like in the two cases where no ramping is
used (A) and when PA ramping is being
implemented (B). In case A, the PATABLE
PATABLE[7] = 0x00
PATABLE[6] = 0x00
PATABLE[5] = 0x00
PATABLE[4] = 0x00
PATABLE[3] = 0x00
PATABLE[2] = 0x00
PATABLE[1] = 0x00
PATABLE[0] = 0x26
PATABLE[7] = 0x00
PATABLE[6] = 0x00
PATABLE[5] = 0x34
PATABLE[4] = 0x33
PATABLE[3] = 0x32
PATABLE[2] = 0x31
PATABLE[1] = 0x30
PATABLE[0] = 0x00
FREND0.PA_POWER = 0
FREND0.PA_POWER = 5
A: Output Power = -10 dBm,
No PA Ramping
B: Output Power = -10 dBm,
PA Ramping
Figure 24: PA Ramping
SWRS038D
Page 51 of 92
CC1100
26 Selectivity
Figure 25 to Figure 27 sho
w the typical selectivity performance (adjacent and alternate rejection).
50.0
40.0
30.0
20.0
10.0
0.0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.4
0.5
-10.0
Frequency off
s
e
t
[
MHz]
Figure 25: Typical Selectivity at 1.2 kBaud Data Rate, 868 MHz, 2-FSK, 5.2 kHz Deviation. IF
Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz
40.0
30.0
20.0
10.0
0.0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.4
0.5
-10.0
-20.0
Frequency off
s
e
t
[
MHz]
Figure 26: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, 2-FSK, 20 kHz Deviation. IF
Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz
SWRS038D
Page 52 of 92
CC1100
50.0
40.0
30.0
20.0
10.0
0.0
-2.3
1.5
-1.0
-0.8
0.0
0.8
1.0
1.5
2.3
-10.0
-20.0
Frequency off
s
e
t
[
MHz]
Figure 27: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, MSK, IF Frequency is 254 kHz
and the Digital Channel Filter Bandwidth is 540 kHz
27 Crystal
Oscillator
A crystal in the frequency range 26-27 MHz
must be connected between the XOSC_Q1
and XOSC_Q2 pins. The oscillator is designed
for parallel mode operation of the crystal. In
addition, loading capacitors (C81 and C101)
for the crystal are required. The loading
capacitor values depend on the total load
capacitance, C
L
, specified for the crystal. The
total load capacitance seen between the
crystal terminals should equal C
L
for the
crystal to oscillate at the specified frequency.
28. Typi
cal component values for different
values of C
L
are given in Table 33.
The crystal oscillator is amplitude regulated.
This means that a high current is used to start
up the oscillations. When the amplitude builds
up, the current is reduced to what is necessary
to maintain approximately 0.4 Vpp signal
swing. This ensures a fast start-up, and keeps
the drive level to a minimum. The ESR of the
crystal should be within the specification in
order to ensure a reliable start-up (see Section
1
C
L
=
+
C
parasitic
1
1
+
C
81
C
101
The initial tolerance, temperature drift, aging
and load pulling should be carefully specified
in order to meet the required frequency
accuracy in a certain application.
The parasitic capacitance is constituted by pin
input capacitance and PCB stray capacitance.
Total parasitic capacitance is typically 2.5 pF.
XOSC_Q1
XOSC_Q2
XTAL
C81
C101
Figure 28: Crystal Oscillator Circuit
Component
C81
C
L
= 10 pF
C
L
= 13 pF
22 pF
C
L
= 16 pF
27 pF
15 pF
15 pF
C101
22 pF
27 pF
Table 33: Crystal Oscillator Component Values
SWRS038D
Page 53 of 92
CC1100
27.1 Reference
Signal
XOSC_Q1 input. The sine wave must be
connected to XOSC_Q1 using
a
serial
The chip can alternatively be operated with a
reference signal from 26 to 27 MHz instead of
a crystal. This input clock can either be a full-
swing digital signal (0 V to VDD) or a sine
wave of maximum 1 V peak-peak amplitude.
The reference signal must be connected to the
capacitor. When using a full-swing digital
signal this capacitor can be omitted. The
XOSC_Q2 line must be left un-connected. C81
and C101 can be omitted when using a
reference signal.
28 External
RF Match
The
passive
matching/filtering
network
The balanced RF input and output of
CC1100
share two common pins and are designed for
a simple, low-cost matching and balun network
on the printed circuit board. The receive- and
transmit switching at the
CC1100
front-end is
controlled by a dedicated on-chip function,
eliminating the need for an external RX/TX-
switch.
connected to
CC1100
should have the following
differential impedance as seen from the RF-
port (RF_P and RF_N) towards the antenna:
Z
out 315 MHz
= 122 + j31
Ω
Z
out 433 MHz
= 116 + j41
Ω
Z
out 868/915 MHz
= 86.5 + j43
Ω
A few passive external components combined
with the internal RX/TX switch/termination
circuitry ensures match in both RX and TX
mode.
To ensure optimal matching of the
CC1100
differential output it is recommended to follow
closely as possible. Gerber files for the
reference designs are available for download
from the TI website.
Although
CC1100
has
a
balanced RF
input/output, the chip can be connected to a
single-ended antenna with few external low
cost capacitors and inductors.
29 PCB
Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be filled
with metallization connected to ground using
several vias.
best routing is from the power line (or power
plane) to the decoupling capacitor and then to
the
CC1100
supply pin. Supply power filtering is
very important.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias. In the CC1100EM
5 vias inside the exposed die attached pad.
These vias should be “tented” (covered with
solder mask) on the component side of the
PCB to avoid migration of solder through the
vias during the solder reflow process.
Each decoupling capacitor ground pad should
be connected to the ground plane using a
separate via.
Direct connections between
neighboring power pins will increase noise
coupling and should be avoided unless
absolutely necessary.
The external components should ideally be as
small as possible (0402 is recommended) and
surface
mount
devices
are
highly
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%.
recommended. Please note that components
smaller than those specified may have
differing characteristics.
Precaution should be used when placing the
microcontroller in order to avoid noise
interfering with the RF circuitry.
See Figure 29 for top
solder resist and top
paste masks.
A CC1100/1150DK Development Kit with a
fully assembled CC1100EM Evaluation
Module is available. It is strongly advised that
this reference layout is followed very closely in
order to get the best performance. The
schematic, BOM and layout Gerber files are all
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed to decouple. Each decoupling
capacitor should be connected to the power
line (or power plane) by separate vias. The
SWRS038D
Page 54 of 92
CC1100
Figure 29: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias
30 General
Purpose / Test Output Control Pins
The three digital output pins GDO0, GDO1,
and GDO2 are general control pins configured
pin is then proportional to temperature. See
specifications.
with
signals that can be monitored on the GDO
pins. These signals can be used as inputs to
the MCU. GDO1 is the same pin as the SO pin
on the SPI interface, thus the output
programmed on this pin will only be valid when
CSn is high. The default value for GDO1 is 3-
stated, which is useful when the SPI interface
is shared with other devices.
GDO0 and GDO2 pins will be hardwired to 0
(1) and
the GDO1 pin will be hardwired to 1
(0) in the SLEEP state. These signals will be
low.
higher the GDO pins will work as programmed
also in SLEEP state. As an example, GDO1 is
The default value for
GDO0 is a 135-141 kHz
clock output (XOSC frequency divided by
192). Since the XOSC is turned on at power-
on-reset, this can be used to clock the MCU in
systems with only one crystal. When the MCU
is up and running, it can change the clock
high
impedance
in
all
states
if
An on-chip analog temperature sensor is
enabled by writing the value 128 (0x80) to the
SWRS038D
Page 55 of 92
CC1100
GDOx
_CFG[5:0]
Description
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
is drained below the same threshold.
Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is
reached. De-asserts when the RX FIFO is empty.
Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX
FIFO is below the same threshold.
Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO
threshold.
4 (0x04)
5 (0x05)
Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert
when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.
Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO.
Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.
Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting)
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To
check for PLL lock the lock detector output should be used as an interrupt for the MCU.
Serial Clock. Synchronous to the data in synchronous serial mode.
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
In RX mode, data is set up on the falling edge by
CC1100
when
GDOx_INV=
0
.
In TX mode, data is sampled by
CC1100
on the rising edge of the serial clock when
GDOx_INV=0
.
12 (0x0C)
Serial Synchronous Data Output. Used for synchronous serial mode.
13 (0x0D)
Serial Data Output. Used for asynchronous serial mode.
14 (0x0E)
Carrier sense. High if RSSI level is above threshold.
15 (0x0F)
CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
23 (0x17)
24 (0x18)
25 (0x19)
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
Reserved – used for test.
Reserved – used for test.
26 (0x1A)
Reserved – used for test.
PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch
27 (0x1B)
LNA_PD. Note: LNA_PD will have the same signal level in SLEEP a
nd RX states. To control an ex
ternal LNA or RX/TX
switch in applications where the SLEEP state is used it is recommended to use
GDOx_CFGx=0x2
F
instead.
28 (0x1C)
30 (0x1E)
Reserved – used for test.
31 (0x1F)
Reserved – used for test.
32 (0x20)
33 (0x21)
34 (0x22)
35 (0x23)
36 (0x24)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29)
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
Reserved – used for test.
WOR_EVNT0
WOR_EVNT1
Reserved – used for test.
CLK_32k
Reserved – used for test.
CHIP_RDYn
42 (0x2A)
Reserved – used for test.
43 (0x2B)
XOSC_STABLE
44 (0x2C)
Reserved – used for test.
45 (0x2D)
GDO0
_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E)
High impedance (3-state)
47 (0x2F)
HW to 0 (HW1 achieved by setting
GDOx_INV=1
).
Can be used to control an external LNA/PA or RX/TX switch.
48 (0x30)
49 (0x31)
50 (0x32)
51 (0x33)
52 (0x34)
53 (0x35)
54 (0x36)
55 (0x37)
56 (0x38)
57 (0x39)
CLK_XOSC/1
CLK_XOSC/1.5
CLK_XOSC/2
CLK_XOSC/3
CLK_XOSC/4
CLK_XOSC/6
CLK_XOSC/8
CLK_XOSC/12
CLK_XOSC/16
CLK_XOSC/24
Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any
time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must
be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
To optimize rf performance, these signal should not be used while the radio is in RX or TX mode.
58 (0x3A)
CLK_XOSC/32
59 (0x3B)
CLK_XOSC/48
60 (0x3C)
CLK_XOSC/64
61 (0x3D)
CLK_XOSC/96
62 (0x3E)
CLK_XOSC/128
63 (0x3F)
CLK_XOSC/192
Table 34: GDOx Signal Selection (x = 0, 1, or 2)
SWRS038D
Page 56 of 92
CC1100
31 Asynchronous
and Synchronous Serial Operation
Several features and modes of operation have
been included in the
CC1100
to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller, and
simplify software development.
31.2 Synchronous
Serial Operation
to
1
enables synchronous serial mode. In the
synchronous serial mode, data is transferred
on a two wire serial interface. The
CC1100
provides a clock that is used to set up new
data on the data input line or sample data on
the data output line. Data input (TX data) is the
GDO0 pin. This pin will automatically be
configured as an input when TX is active. The
data output pin can be any of the GDO pins;
fields.
31.1 Asynchronous
Operation
For backward compatibility with systems
already using the asynchronous data transfer
from other Chipcon products, asynchronous
transfer is also included in
CC1100
. When
asynchronous transfer is enabled, several of
the support mechanisms for the MCU that are
included in
CC1100
will be disabled, such as
packet handling hardware, buffering in the
FIFO, and so on. The asynchronous transfer
mode does not allow the use of the data
whitener, interleaver, and FEC, and it is not
possible to use Manchester encoding.
Preamble and sync word insertion/detection
may or may not be active, dependent on the
If preamble and sync word is disabled, all
other packet handler features and FEC should
also be disabled. The MCU must then handle
preamble and sync word insertion and
detection in software. If preamble and sync
word insertion/detection is left on, all packet
handling features and FEC can be used. One
exception is that the address filtering feature is
unavailable in synchronous serial mode.
Note that MSK is not supported for
asynchronous transfer.
Setting
to
3
When using the packet handling features in
synchronous serial mode, the
CC1100
will insert
and detect the preamble and sync word and
the MCU will only provide/get the data
enables asynchronous serial mode.
In TX, the GDO0 pin is used for data input (TX
data). Data output can be on GDO0, GDO1, or
fields.
payload.
This
is
equivalent
to
the
recommended FIFO operation mode.
The
CC1100
modulator samples the level of the
asynchronous input 8 times faster than the
programmed data rate. The timing requirement
for the asynchronous stream is that the error in
the bit period must be less than one eighth of
the programmed data rate.
32 System
Considerations and Guidelines
32.1 SRD
Regulations
MHz, 868 MHz, or 915 MHz frequency bands
are EN 300
220 (Europe)
and FCC CFR47
part 15 (USA). A summary of the most
important aspects of these regulations can be
International regulations and national laws
regulate the use of radio receivers and
transmitters. Short Range Devices (SRDs) for
license free operation below 1 GHz are usually
operated in the 433 MHz, 868 MHz or 915
MHz frequency bands. The
CC1100
is
specifically designed for such use with its 300 –
348 MHz, 400 – 464 MHz, and 800 – 928 MHz
operating ranges. The most important
regulations when using the
CC1100
in the 433
Please note that compliance with regulations is
dependent on complete system performance.
It is the customer’s responsibility to ensure that
the system complies with regulations.
SWRS038D
Page 57 of 92
CC1100
32.2 Frequency
Hopping and Multi-
Channel Systems
time is reduced from approximately 720 µs to
approximately 150 µs. The blanking interval
between each frequency hop is then
approximately 240 us.
The 433 MHz, 868 MHz, or 915 MHz bands
are shared by many systems both in industrial,
office, and home environments. It is therefore
recommended to use frequency hopping
spread spectrum (FHSS) or a multi-channel
protocol because the frequency diversity
makes the system more robust with respect to
interference from other systems operating in
the same frequency band. FHSS also combats
multipath fading.
There is a trade off between blanking time and
memory space needed for storing calibration
data in non-volatile memory. Solution 2) above
gives the shortest blanking interval, but
requires more memory space to store
calibration
values.
Solution
3)
gives
approximately 570 µs smaller blanking interval
than solution 1).
Note that the recommended settings for
frequency. This means that one should always
use SmartRF
®
Studio [7] to get the
correct
settings for a specific frequency before doing a
calibration, regardless of which calibration
method is being used.
CC1100
is highly suited for FHSS or multi-
channel systems due to its agile frequency
synthesizer and effective communication
interface. Using the packet handling support
and data buffering is also beneficial in such
systems as these features will significantly
offload the host controller.
Charge pump current, VCO current, and VCO
capacitance array calibration data is required
for each frequency when implementing
frequency hopping for
CC1100
. There are 3
ways of obtaining the calibration data from the
chip:
0, 1, or 2) content is not retained in SLEEP
state, and thus it is necessary to re-write these
registers when returning from the SLEEP
state.
1) Frequency hopping with calibration for each
hop. The PLL calibration time is approximately
720 µs. The blanking interval between each
frequency hop is then approximately 810 us.
32.3 Wideband
Modulation not Using
Spread Spectrum
Digital modulation systems under FFC part
15.247 includes 2-FSK and GFSK modulation.
A maximum peak output power of 1W (+30
dBm) is allowed if the 6 dB bandwidth of the
modulated signal exceeds 500 kHz. In
addition, the peak power spectral density
conducted to the antenna shall not be greater
than +8 dBm in any 3 kHz band.
2) Fast frequency hopping without calibration
for each hop can be done by calibrating each
frequency at startup and saving the resulting
in MCU memory. Between each frequency
hop, the calibration process can then be
next RF frequency. The PLL turn on time is
approximately 90
µs. The blanking interval
between each frequency hop is then
approximately 90 us. The VCO current
dependent on the RF frequency. Neither is the
charge pump current calibration result
therefore be used for all frequencies.
Operating at high data rates and frequency
separation, the
CC1100
is suited for systems
targeting compliance with digital modulation
system as defined by FFC part 15.247. An
external power amplifier is needed to increase
the output above +10 dBm.
32.4 Data
Burst Transmissions
The high maximum data rate of
CC1100
opens
up for burst transmissions. A low average data
rate link (e.g. 10 kBaud), can be realized using
a higher over-the-air data rate. Buffering the
data and transmitting in bursts at high data
rate (e.g. 500 kBaud) will reduce the time in
active mode, and hence also reduce the
average current consumption significantly.
Reducing the time in active mode will reduce
the likelihood of collisions with other systems
in the same frequency range.
3) Run calibration on a single frequency at
disable the charge pump calibration. After
frequency hop. That is, VCO current and VCO
capacitance calibration is done but not charge
pump current calibration. When charge pump
current calibration is disabled the calibration
SWRS038D
Page 58 of 92
CC1100
32.5 Continuous
Transmissions
32.8 Low
Cost Systems
In data streaming applications the
CC1100
opens up for continuous transmissions at 500
kBaud effective data rate. As the modulation is
done with a closed loop PLL, there is no
limitation in the length of a transmission (open
loop modulation used in some transceivers
often prevents this kind of continuous data
streaming and reduces the effective data rate).
As the
CC1100
provides 500 kBaud multi-
channel performance without any external
filters, a very low cost system can be made.
A differential antenna will eliminate the need
for a balun, and the DC biasing can be
A HC-49 type SMD crystal is used in the
Note that the crystal package strongly
influences the price. In a size constrained PCB
design a smaller, but more expensive, crystal
may be used.
32.6 Crystal
Drift Compensation
The
CC1100
has
a
very fine frequency
used to compensate for frequency offset and
drift.
32.9 Battery
Operated Systems
The frequency offset between an ‘external’
transmitter and the receiver is measured in the
CC1100
and can be read back from the
FREQEST
status register as described in
Section 14.1.
The measured frequency offset
can be used to calibrate the frequency using
the ‘external’ transmitter as the reference. That
is, the received signal of the device will match
the receiver’s channel filter better. In the same
way the centre frequency of the transmitted
signal will match the ‘external’ transmitter’s
signal.
In low power applications, the SLEEP state
with the crystal oscillator core switched off
should be used when the
CC1100
is not active.
It is possible to leave the crystal oscillator core
running in the SLEEP state if start-up time is
critical.
The WOR functionality should be used in low
power applications.
32.10 Increasing Output Power
In some applications it may be necessary to
extend the link range. Adding an external
power amplifier is the most effective way of
doing this.
32.7 Spectrum
Efficient Modulation
CC1100
also has the possibility to use Gaussian
shaped 2-FSK (GFSK). This spectrum-shaping
feature improves adjacent channel power
(ACP) and occupied bandwidth. In ‘true’ 2-FSK
systems with abrupt frequency shifting, the
spectrum is inherently broad. By making the
frequency shift ‘softer’, the spectrum can be
made significantly narrower. Thus, higher data
rates can be transmitted in the same
bandwidth using GFSK.
The power amplifier should be inserted
between the antenna and the balun, and two
T/R switches are needed to disconnect the PA
Antenna
Filter
P
A
Balun
CC1100
T/R
switch
T/R
switch
Figure 30: Block Diagram of
CC1100
Usage with External Power Amplifier
SWRS038D
Page 59 of 92
CC1100
33 Configuration
Registers
There are also 12 Status registers, which are
listed in Table 37. Th
ese registers, which are
read-only, contain information about the status
of
CC1100
.
The configuration of
CC1100
is done by
programming 8-bit registers. The optimum
configuration data based on selected system
parameters are most easily found by using the
descriptions of the registers are given in the
following tables. After chip reset, all the
registers have default values as shown in the
tables. The optimum register setting might
differ from the default value. After a reset all
registers that shall be different from the default
value therefore needs to be programmed
through the
SPI interface.
The two FIFOs are accessed through one 8-bit
register. Write operations write to the TX FIFO,
while read operations read from the RX FIFO.
During the header byte transfer and while
writing data to a register or the TX FIFO, a
status byte is returned on the SO line. This
Table 38 su
mmarizes the SPI address space.
The address to use is given by adding the
base address to the left and the burst and
read/write bits on the top. Note that the burst
bit has different meaning for base addresses
above and below 0x2F.
There are 13 command strobe registers, listed
in Table 35.
Accessing these registers will
initiate the change of an internal state or
mode. There are 47 normal 8-bit configuration
registers are for test purposes only, and need
not be written for normal operation of
CC1100
.
Address
Strobe
Name
Description
0x30
0x31
SRES
Reset chip.
SFSTXON
Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
0x32
0x33
SXOFF
SCAL
Turn off crystal oscillator.
0x34
0x35
SRX
STX
If in RX state and CCA is enabled: Only go to TX if channel is clear.
0x36
0x38
SIDLE
SWOR
Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
0x39
0x3A
0x3B
0x3C
0x3D
SPWD
SFRX
SFTX
Enter power down mode when CSn goes high.
SWORRST Reset
real time clock to Event1 value.
SNOP No
operation. May be used to get access to the chip status byte.
Table 35: Command Strobes
SWRS038D
Page 60 of 92
CC1100
Preserved in
SLEEP State
Details on
Page Number
Address
Register
Description
Yes
Yes
Yes
64
GDO
2
output pin configuration
GDO
1
output pin configuration
0x00
0x01
64
64
GDO
0
output pin configuration
RX FIFO and TX FIFO thresholds
Sync word, high byte
0x02
0x03
0x04
0x05
0x07
0x08
0x09
0x0B
0x0C
0x0D
0x0E
0x0F
0x15
0x16
0x17
0x18
0x19
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2C
0x2D
0x2E
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Sync word, low byte
Packet length
PKTCTRL1
Packet automation control
PKTCTRL0
Packet automation control
ADDR
Device address
Channel number
Frequency synthesizer control
Frequency synthesizer control
Frequency control word, high byte
Frequency control word, middle byte
Frequency control word, low byte
MDMCFG4
Modem configuration
MDMCFG3
Modem configuration
MDMCFG2
Modem configuration
MDMCFG1
Modem configuration
MDMCFG0
Modem configuration
Modem deviation setting
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Frequency Offset Compensation configuration
Bit Synchronization configuration
AGC control
AGC control
AGC control
WOREVT1
High byte Event 0 timeout
WOREVT0
Low byte Event 0 timeout
WORCTRL
Wake On Radio control
Front end RX configuration
Front end TX configuration
Frequency synthesizer calibration
Frequency synthesizer calibration
Frequency synthesizer calibration
Frequency synthesizer calibration
RC oscillator configuration
RC oscillator configuration
Frequency synthesizer calibration control
Production test
No
AGC test
No
Various test settings
No
Various test settings
No
Various test settings
No
Table 36: Configuration Registers Overview
SWRS038D
Page 61 of 92
CC1100
Address
Register
Description
Details on page number
0x30 (0xF0)
0x31 (0xF1)
0x32 (0xF2)
0x33 (0xF3)
0x34 (0xF4)
0x35 (0xF5)
0x36 (0xF6)
0x37 (0xF7)
0x38 (0xF8)
Part number for
CC1100
Current version number
Frequency Offset Estimate
Demodulator estimate for Link Quality
Received signal strength indication
Control state machine state
High byte of WOR timer
Low byte of WOR timer
Current GDOx status and packet status
Current setting from PLL calibration
module
0x39 (0xF9)
0x3A (0xFA)
0x3B (0xFB)
Underflow and number of bytes in the TX
FIFO
Overflow and number of bytes in the RX
FIFO
Table 37: Status Registers Overview
SWRS038D
Page 62 of 92
CC1100
Write
Single Byte
+0x00
Read
Burst
+0x40
Single Byte
+0x80
Burst
+0xC0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Table 38: SPI Address Space
SWRS038D
Page 63 of 92
CC1100
33.1 Configuration
Register Details – Registers with preserved values in SLEEP state
0x00: IOCFG2 –
GDO
2
Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
6
Reserved
R0
0
R/W
Invert output, i.e. select active low (1) / high (0)
GDO2
_INV
GDO2
_CFG[5:0]
5:0
41 (0x29)
R/W
0x01: IOCFG1 –
GDO
1
Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
6
GDO_DS
0
0
R/W
R/W
Set high (1) or low (0) output drive strength on the GDO pins.
Invert output, i.e. select active low (1) / high (0)
GDO1
_INV
GDO1
_CFG[5:0]
5:0
46 (0x2E)
R/W
0x02: IOCFG0 –
GDO
0
Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
TEMP_SENSOR_ENABLE
0
R/W
Enable analog temperature sensor. Write 0 in all other register
bits when using temperature sensor.
6
0
R/W
R/W
Invert output, i.e. select active low (1) / high (0)
GDO0
_INV
5:0
63 (0x3F)
GDO0
_CFG[5:0]
It is recommended to disable the clock output in initialization,
in order to optimize RF performance.
SWRS038D
Page 64 of 92
CC1100
0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds
Bit
Field Name
Reset
R/W
Description
7:4
3:0
Reserved
0
R/W
R/W
Write 0 for compatibility with possible future extensions
FIFO_THR[3:0]
7 (0111)
Set the threshold for the TX FIFO and RX FIFO. The threshold is
exceeded when the number of bytes in the FIFO is equal to or higher
than the threshold value.
Setting
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
Bytes in TX FIFO
Bytes in RX FIFO
61
57
53
49
45
41
37
33
29
25
21
17
13
9
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
5
1
0x04: SYNC1 – Sync Word, High Byte
Bit
Field Name
Reset
R/W
Description
7:0
SYNC[15:8]
211 (0xD3)
R/W
8 MSB of 16-bit sync word
0x05: SYNC0 – Sync Word, Low Byte
Bit
Field Name
Reset
R/W
Description
7:0
SYNC[7:0]
145 (0x91)
R/W
8 LSB of 16-bit sync word
0x06: PKTLEN – Packet Length
Bit
Field Name
Reset
R/W
Description
7:0
PACKET_LENGTH 255
(0xFF)
R/W
Indicates the packet length when fixed packet length mode is enabled.
If variable packet length mode is used, this value indicates the
maximum packet length allowed.
SWRS038D
Page 65 of 92
CC1100
0x07: PKTCTRL1 – Packet Automation Control
Bit
Field Name
Reset
R/W
Description
7:5
PQT[2:0]
0 (0x00)
R/W
Preamble quality estimator threshold. The preamble quality estimator
increases an internal counter by one each time a bit is received that is
different from the previous bit, and decreases the counter by 8 each time
a bit is received that is the same as the last bit.
A threshold of 4·
PQ
T
for this counter is used to gate sync word detection.
When
PQT=0
a sync word is always accepted.
4
3
Reserved
0
0
R0
CRC_AUTOFLUSH
R/W
Enable automatic flush of RX FIFO when CRC in not OK. This requires
that only one packet is in the RXIFIFO and that packet length is limited to
the RX FIFO size.
2
APPEND_STATUS
ADR_CHK[1:0]
1
R/W
R/W
When enabled, two status bytes will be appended to the payload of the
packet. The status bytes contain RSSI and LQI values, as well as CRC
OK.
1:0
0 (00)
Controls address check configuration of received packages.
Setting Address
check configuration
0 (00)
1 (01)
2 (10)
3 (11)
No address check
Address check, no broadcast
Address check and 0 (0x00) broadcast
Address check and 0 (0x00) and 255 (0xFF)
broadcast
SWRS038D
Page 66 of 92
CC1100
0x08: PKTCTRL0 – Packet Automation Control
Bit Field
Name
Reset
R/W Description
7
6
Reserved
R0
WHITE_DATA
1
R/W Turn
data whitening on / off
0: Whitening off
1: Whitening on
5:4 PKT_FORMAT[1:0]
0 (00)
R/W Format
of RX and TX data
Setting Packet
format
0 (00)
1 (01)
Normal mode, use FIFOs for RX and TX
Synchronous serial mode, used for backwards
compatibility. Data in on GDO0
Random TX mode; sends random data using PN9
generator. Used for test.
Works as normal mode, setting 0 (00), in RX.
2 (10)
3 (11)
Asynchronous serial mode. Data in on GDO0 and
Data out on either of the GDO0 pins
3
2
Reserved
CRC_EN
0
1
R0
R/W 1:
CRC calculation in TX and CRC check in RX enabled
0: CRC disabled for TX and RX
1:0 LENGTH_CONFIG[1:0]
1 (01)
R/W Configure
the packet length
Setting Packet
length configuration
0 (00)
Fixed packet length mode. Length configured in
PKTLE
N
register
1 (01)
Variable packet length mode. Packet length
configured by the first byte after sync word
2 (10)
3 (11)
Infinite packet length mode
Reserved
0x09: ADDR – Device Address
Bit Field
Name
Reset
R/W Description
7:0 DEVICE_ADDR[7:0]
0 (0x00)
R/W Address
used for packet filtration. Optional broadcast addresses are 0
(0x00) and 255 (0xFF).
0x0A: CHANNR – Channel Number
Bit Field
Name
Reset
0 (0x00)
R/W Description
7:0 CHAN[7:0]
R/W The
8-bit unsigned channel number, which is multiplied by the
channel spacing setting and added to the base frequency.
SWRS038D
Page 67 of 92
CC1100
0x0B: FSCTRL1 – Frequency Synthesizer Control
Bit
Field Name
Reset
R/W
Description
7:5
4:0
Reserved
R0
FREQ_IF[4:0]
15 (0x0F)
R/W
The desired IF frequency to employ in RX. Subtracted from FS base
frequency in RX and controls the digital complex mixer in the demodulator.
f
XOSC
2
10
f
IF
=
⋅
FREQ
_
IF
The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz
crystal.
0x0C: FSCTRL0 – Frequency Synthesizer Control
Bit
Field Name
Reset
R/W
Description
7:0
FREQOFF[7:0]
0 (0x00)
R/W
Frequency offset added to the base frequency before being used by the
frequency synthesizer. (2s-complement).
Resolution is F
XTAL
/2
14
(1.59kHz-1.65kHz); range is ±202 kHz to ±210 kHz,
dependent of XTAL frequency.
0x0D: FREQ2 – Frequency Control Word, High Byte
Bit
Field Name
Reset
R/W
Description
7:6
FREQ[23:22]
0 (00)
R
FREQ[23:22
]
is always 0 (the
FREQ
2
register is less than 36 with 26-27
MHz crystal)
5:0
FREQ[21:16]
30 (0x1E)
R/W
FREQ[23:22
]
is the base frequency for the frequency synthesiser in
increments of F
XOSC
/2
16
.
f
XOSC
2
16
f
carrier
=
⋅
FREQ
[
23 : 0
]
0x0E: FREQ1 – Frequency Control Word, Middle Byte
Bit
Field Name
Reset
R/W
Description
7:0
FREQ[15:8]
196 (0xC4)
R/W
Ref.
FREQ
2
register
0x0F: FREQ0 – Frequency Control Word, Low Byte
Bit Field
Name
Reset
R/W
Description
7:0 FREQ[7:0]
236 (0xEC)
R/W
Ref.
FREQ
2
register
SWRS038D
Page 68 of 92
CC1100
0x10: MDMCFG4 – Modem Configuration
Bit Field
Name
Reset
R/W
Description
7:6 CHANBW_E[1:0]
5:4 CHANBW_M[1:0]
2 (0x02)
0 (0x00)
R/W
R/W
Sets the decimation ratio for the delta-sigma ADC input stream and thus
the channel bandwidth.
f
XOSC
BW
channel
=
8
⋅
(4
+
CHANBW
_
M
)
·
2
CHANBW
_
E
The default values give 203 kHz channel filter bandwidth, assuming a 26.0
MHz crystal.
3:0 DRATE_E[3:0]
12 (0x0C)
R/W
The exponent of the user specified symbol rate
0x11: MDMCFG3 – Modem Configuration
Bit Field
Name
Reset
R/W
Description
7:0 DRATE_M[7:0]
34 (0x22)
R/W
The mantissa of the user specified symbol rate. The symbol rate is
configured using an unsigned, floating-point number with 9-bit mantissa
and 4-bit exponent. The 9
th
bit is a hidden ‘1’. The resulting data rate is:
(
256
+
DRATE
_
M
⋅
2
DRATE
_
E
)
R
DATA
=
⋅
f
XOSC
2
28
The default values give a data rate of 115.051 kBaud (closest setting to
115.2 kBaud), assuming a 26.0 MHz crystal.
SWRS038D
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CC1100
0x12: MDMCFG2 – Modem Configuration
Bit Field
Name
DEM_DCFILT_OFF
Reset
R/W
Description
7
0
R/W
Disable digital DC blocking filter before demodulator.
0 = Enable (better sensitivity)
1 = Disable (current optimized). Only for data rates
≤
250 kBaud
The recommended IF frequency changes when the DC blocking is
setting.
6:4 MOD_FORMAT[2:0] 0
(000)
R/W
The modulation format of the radio signal
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Modulation format
2-FSK
GFSK
–
ASK/OOK
–
–
–
MSK
ASK is only supported for output powers up to -1 dBm
MSK is only supported for datarates above 26 kBaud
Enables Manchester encoding/decoding.
0 = Disable
3
MANCHESTER_EN
0
R/W
R/W
1 = Enable
2:0 SYNC_MODE[2:0]
2 (010)
Combined sync-word qualifier mode.
The values 0 (000) and 4 (100) disables preamble and sync word
transmission in TX and preamble and sync word detection in RX.
The values 1 (001), 2 (010), 5 (101) and 6 (110) enables 16-bit sync word
transmission in TX and 16-bits sync word detection in RX. Only 15 of 16
bits need to match in RX when using setting 1 (001) or 5 (101). The values
3 (011) and 7 (111) enables repeated sync word transmission in TX and
32-bits sync word detection in RX (only 30 of 32 bits need to match).
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
Sync-word qualifier mode
No preamble/sync
15/16 sync word bits detected
16/16 sync word bits detected
30/32 sync word bits detected
No preamble/sync, carrier-sense
above threshold
5 (101)
6 (110)
7 (111)
15/16 + carrier-sense above threshold
16/16 + carrier-sense above threshold
30/32 + carrier-sense above threshold
SWRS038D
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CC1100
0x13: MDMCFG1– Modem Configuration
Bit
Field Name
Reset
R/W
Description
7
FEC_EN
0
R/W
Enable Forward Error Correction (FEC) with interleaving for
packet payload
0 = Disable
1 = Enable (Only supported for fixed packet length mode, i.e.
6:4
NUM_PREAMBLE[2:0]
2 (010)
R/W
Sets the minimum number of preamble bytes to be transmitted
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Number of preamble bytes
2
3
4
6
8
12
16
24
3:2
1:0
Reserved
R0
CHANSPC_E[1:0]
2 (10)
R/W
2 bit exponent of channel spacing
0x14: MDMCFG0– Modem Configuration
Bit
Field Name
Reset
R/W
Description
7:0
CHANSPC_M[7:0]
248 (0xF8)
R/W
8-bit mantissa of channel spacing. The channel spacing is
f
XOSC
2
18
∆
f
CHANNEL
=
⋅
(
256
+
CHANSPC
_
M
⋅
2
CHANSPC
_
E
)
The default values give 199.951 kHz channel spacing (the
closest setting to 200 kHz), assuming 26.0 MHz crystal
frequency.
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Page 71 of 92
CC1100
0x15: DEVIATN – Modem Deviation Setting
Bit Field
Name
Reset
R/W
Description
7
Reserved
6:4 DEVIATION_E[2:0]
Reserved
2:0 DEVIATION_M[2:0]
R0
4 (0x04)
7 (111)
R/W
R0
Deviation exponent
3
R/W
When MSK modulation is enabled:
Sets fraction of symbol period used for phase change. Refer to the
MSK.
When 2-FSK/GFSK modulation is enabled:
Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The
resulting frequency deviation is given by:
f
xosc
2
17
f
dev
=
⋅
(8
+
DEVIATION
_
M
)
⋅
2
DEVIATION
_
E
The default values give ±47.607 kHz deviation, assuming 26.0 MHz crystal
frequency.
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CC1100
0x16: MCSM2 – Main Radio Control State Machine Configuration
Bit Field
Name
Reset
R/W
Description
7:5 Reserved
R0
Reserved
4
RX_TIME_RSSI
0
R/W
Direct RX termination based on RSSI measurement (carrier sense). For
ASK/OOK modulation, RX times out if there is no carrier sense in the first 8
symbol periods.
3
RX_TIME_QUAL
0
R/W
When the
RX_TIM
E
timer expires, the chip checks if sync word is found
when
RX_TIME_QUAL=0
, or either sync word is found or PQI is set when
RX_TIME_QUAL=1.
Timeout for sync word search in RX for both WOR mode and normal RX
The RX timeout in µs is given by
EVENT0
·C(
RX_TIME
,
WOR_RES
) ·
26/X, where C is given by the table below and X is
the crystal oscillator frequency in MHz:
Setting WOR_RES
= 0
0 (000)
3.6058
WOR_RES = 1
18.0288
9.0144
WOR_RES = 2
32.4519
16.2260
8.1130
WOR_RES = 3
46.8750
23.4375
11.7188
5.8594
1 (001)
1.8029
2 (010)
0.9014
4.5072
3 (011)
0.4507
2.2536
4.0565
4 (100)
0.2254
1.1268
2.0282
2.9297
5 (101)
0.1127
0.5634
1.0141
1.4648
6 (110)
0.0563
0.2817
0.5071
0.7324
7 (111)
Until end of packet
As an example,
EVENT0=34666
,
WOR_RES=
0
and
RX_TIME=
6
corresponds to 1.96 ms RX timeout, 1 s polling interval
and 0.195% duty cycle. Note that
WOR_RE
S
should be 0 or 1
when using WOR because using
WOR_RE
S
> 1 w
ill give a
The duty cycle using WOR is approximated by:
WOR_RES=0
WOR_RES=1
1.95%
9765ppm
4883ppm
2441ppm
NA
Setting
0 (000)
12.50%
1 (001)
6.250%
2 (010)
3.125%
3 (011)
1.563%
4 (100)
0.781%
5 (101)
0.391%
6 (110)
0.195%
7 (111)
NA
NA
NA
Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator
periods. WOR mode does not need to be enabled.
The timeout counter resolution is limited: With
RX_TIME=0
, the timeout count is given by the 13 MSBs of
EVENT0
,
decreasing to the 7MSBs of
EVENT0
with
RX_TIME=6
.
SWRS038D
Page 73 of 92
CC1100
0x17: MCSM1– Main Radio Control State Machine Configuration
Bit Field
Name
Reset
R/W
Description
7:6 Reserved
R0
5:4 CCA_MODE[1:0]
3 (11)
R/W
Selects
CCA_MODE
; Reflected in CCA signal
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Clear channel indication
Always
If RSSI below threshold
Unless currently receiving a packet
If RSSI below threshold unless currently
receiving a packet
3:2 RXOFF_MODE[1:0]
0 (00)
R/W
Select what should happen when a packet has been received
Setting
0 (00)
Next state after finishing packet reception
IDLE
FSTXON
TX
1 (01)
2 (10)
3 (11)
Stay in RX
It is not possible to set
RXOFF_MOD
E
to be TX or FSTXON and at the same
time use CCA.
1:0 TXOFF_MODE[1:0]
0 (00)
R/W
Select what should happen when a packet has been sent (TX)
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Next state after finishing packet transmission
IDLE
FSTXON
Stay in TX (start sending preamble)
RX
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Page 74 of 92
CC1100
0x18: MCSM0– Main Radio Control State Machine Configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
Reserved
R0
FS_AUTOCAL[1:0]
0 (00)
R/W
Automatically calibrate when going to RX or TX, or back to IDLE
Setting When
to perform automatic calibration
0 (00)
1 (01)
Never (manually calibrate using
SCA
L
strobe)
When going from IDLE to RX or TX (or FSTXON)
When going from RX or TX back to IDLE
automatically
2 (10)
3 (11)
Every 4
th
time when going from RX or TX to IDLE
automatically
In some automatic wake-on-radio (WOR) applications, using setting 3 (11)
can significantly reduce current consumption.
3:2
PO_TIMEOUT
1 (01)
R/W
Programs the number of times the six-bit ripple counter must expire after
If XOSC is on (stable) during power-down,
PO_TIMEOU
T
should be set so
that the regulated digital supply voltage has time to stabilize before
time for the volta
ge regulator is 50 us.
If XOSC is off during power-down and the regulated digital supply voltage
has sufficient time to stabilize while waiting for the crystal to be stable,
PO_TIMEOU
T
can be set to 0. For robust operation it is recommended to
use
PO_TIMEOUT=2
.
Setting Expire
count
Timeout after XOSC start
Approx. 2.3 – 2.4
µ
s
Approx. 37 – 39
µ
s
0 (00)
1 (01)
2 (10)
3 (11)
1
16
64
256
Approx. 149 – 155
µ
s
Approx. 597 – 620
µ
s
Exact timeout depends on crystal frequency.
Enables the pin radio control option
1
0
PIN_CTRL_EN
0
0
R/W
R/W
XOSC_FORCE_ON
Force the XOSC to stay on in the SLEEP state.
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Page 75 of 92
CC1100
0x19: FOCCFG – Frequency Offset Compensation Configuration
Bit Field
Name
Reset
R/W
Description
7:6 Reserved
R0
5
FOC_BS_CS_GATE
1
R/W
If set, the demodulator freezes the frequency offset compensation and clock
recovery feedback loops until the CS signal goes high.
4:3 FOC_PRE_K[1:0]
2 (10)
R/W
The frequency compensation loop gain to be used before a sync word is
detected.
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Freq. compensation loop gain before sync word
K
2
K
3
K
4
K
2
FOC_POST_K
1
R/W
R/W
The frequency compensation loop gain to be used after a sync word is
detected.
Setting
Freq. compensation loop gain after sync word
0
1
Same as FOC_PRE_K
K
/2
1:0 FOC_LIMIT[1:0]
2 (10)
The saturation point for the frequency offset compensation algorithm:
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Saturation point (max compensated offset)
±0 (no frequency offset compensation)
±BW
CHAN
/8
±BW
CHAN
/4
±BW
CHAN
/2
Frequency offset compensation is not supported for ASK/OOK; Always use
FOC_LIMIT=0 with these modulation formats.
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CC1100
0x1A: BSCFG – Bit Synchronization Configuration
Bit Field
Name
Reset
R/W
Description
7:6 BS_PRE_KI[1:0]
1 (01)
R/W
The clock recovery feedback loop integral gain to be used before a sync word
is detected (used to correct offsets in data rate):
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Clock recovery loop integral gain before sync word
K
I
2
K
I
3
K
I
4
K
I
5:4 BS_PRE_KP[1:0]
2 (10)
R/W
The clock recovery feedback loop proportional gain to be used before a sync
word is detected.
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Clock recovery loop proportional gain before sync word
K
P
2
K
P
3
K
P
4
K
P
3
2
BS_POST_KI
BS_POST_KP
1
R/W
R/W
R/W
The clock recovery feedback loop integral gain to be used after a sync word is
detected.
Setting
Clock recovery loop integral gain after sync word
0
1
Same as BS_PRE_KI
K
I
/2
1
The clock recovery feedback loop proportional gain to be used after a sync
word is detected.
Setting
Clock recovery loop proportional gain after sync word
0
1
Same as BS_PRE_KP
K
P
1:0 BS_LIMIT[1:0]
0 (00)
The saturation point for the data rate offset compensation algorithm:
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Data rate offset saturation (max data rate difference)
±0 (No data rate offset compensation performed)
±3.125% data rate offset
±6.25% data rate offset
±12.5% data rate offset
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CC1100
0x1B: AGCCTRL2 – AGC Control
Bit
Field Name
Reset
R/W
Description
7:6
MAX_DVGA_GAIN[1:0]
0 (00)
R/W
Reduces the maximum allowable DVGA gain.
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Allowable DVGA settings
All gain settings can be used
The highest gain setting can not be used
The 2 highest gain settings can not be used
The 3 highest gain settings can not be used
5:3
MAX_LNA_GAIN[2:0]
0 (000)
R/W
Sets the maximum allowable LNA + LNA 2 gain relative to the
maximum possible gain.
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Maximum allowable LNA + LNA 2 gain
Maximum possible LNA + LNA 2 gain
Approx. 2.6 dB below maximum possible gain
Approx. 6.1 dB below maximum possible gain
Approx. 7.4 dB below maximum possible gain
Approx. 9.2 dB below maximum possible gain
Approx. 11.5 dB below maximum possible gain
Approx. 14.6 dB below maximum possible gain
Approx. 17.1 dB below maximum possible gain
2:0
MAGN_TARGET[2:0]
3 (011)
R/W
These bits set the target value for the averaged amplitude from the
digital channel filter (1 LSB = 0 dB).
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Target amplitude from channel filter
24 dB
27 dB
30 dB
33 dB
36 dB
38 dB
40 dB
42 dB
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Page 78 of 92
CC1100
0x1C: AGCCTRL1 – AGC Control
Bit Field
Name
Reset
R/W Description
7
6
Reserved
R0
AGC_LNA_PRIORITY
1
R/W Selects
between two different strategies for LNA and LNA 2
gain adjustment. When 1, the LNA gain is decreased first.
When 0, the LNA 2 gain is decreased to minimum before
decreasing LNA gain.
5:4 CARRIER_SENSE_REL_THR[1:0] 0
(00)
R/W Sets
the relative change threshold for asserting carrier sense
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Carrier sense relative threshold
Relative carrier sense threshold disabled
6 dB increase in RSSI value
10 dB increase in RSSI value
14 dB increase in RSSI value
3:0 CARRIER_SENSE_ABS_THR[3:0]
0
R/W Sets
the absolute RSSI
threshold for asserting carrier sense.
The 2-complement signed threshold is programmed in steps of
1 dB and is relative to the MAGN_TARGET setting.
(0000)
Setting
Carrier sense absolute threshold
(Equal to channel filter amplitude when AGC
has not decreased gain)
-8 (1000)
-7 (1001)
…
Absolute carrier sense threshold disabled
7 dB below
MAGN_TARGE
T
setting
…
-1 (1111)
0 (0000)
1 (0001)
…
1 dB below
MAGN_TARGE
T
setting
At
MAGN_TARGE
T
setting
1 dB above
MAGN_TARGE
T
setting
…
7 (0111)
7 dB above
MAGN_TARGE
T
setting
SWRS038D
Page 79 of 92
CC1100
0x1D: AGCCTRL0 – AGC Control
Bit Field
Name
Reset
R/W
Description
7:6 HYST_LEVEL[1:0]
2 (10)
R/W
Sets the level of hysteresis on the magnitude deviation (internal AGC
signal that determine gain changes).
Setting Description
0 (00)
1 (01)
No hysteresis, small symmetric dead zone, high gain
Low hysteresis, small asymmetric dead zone, medium
gain
Medium hysteresis, medium asymmetric dead zone,
medium gain
2 (10)
3 (11)
Large hysteresis, large asymmetric dead zone, low
gain
5:4 WAIT_TIME[1:0]
1 (01)
R/W
Sets the number of channel filter samples from a gain adjustment
has been made until the AGC algorithm starts accumulating new
samples.
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Channel filter samples
8
16
24
32
3:2 AGC_FREEZE[1:0]
0 (00)
R/W
Control when the AGC gain should be frozen.
Setting Function
0 (00)
1 (01)
Normal operation. Always adjust gain when required.
The gain setting is frozen when a sync word has been
found.
Manually freeze the analogue gain setting and
continue to adjust the digital gain.
2 (10)
3 (11)
Manually freezes both the analogue and the digital
gain setting. Used for manually overriding the gain.
1:0 FILTER_LENGTH[1:0]
1 (01)
R/W
Sets the averaging length for the amplitude from the channel filter.
Sets the OOK/ASK decision boundary for OOK/ASK reception.
Setting Channel
filter
samples
OOK decision
0 (00)
1 (01)
2 (10)
3 (11)
8
4 dB
16
32
64
8 dB
12 dB
16 dB
0x1E: WOREVT1 – High Byte Event0 Timeout
Bit Field
Name
Reset
R/W Description
7:0 EVENT0[15:8]
135 (0x87)
R/W
High byte of
EVENT
0
timeout register
750
t
Even
t
0
=
⋅
EVEN
T
0
⋅
2
5
⋅
WOR
_
RES
f
XOSC
SWRS038D
Page 80 of 92
CC1100
0x1F: WOREVT0 –Low Byte Event0 Timeout
Bit
Field Name
Reset
R/W
Description
7:0
EVENT0[7:0]
107 (0x6B)
R/W
Low byte of
EVENT
0
timeout register.
The default
EVENT
0
value gives 1.0s timeout, assuming a 26.0 MHz
crystal.
0x20: WORCTRL – Wake On Radio Control
Bit
Field Name
Reset
R/W
Description
7
RC_PD
1
R/W
Power down signal to RC oscillator. When written to 0, automatic initial
calibration will be performed
6:4
EVENT1[2:0]
7 (111)
R/W
Timeout setting from register block. Decoded to Event 1 timeout. RC
oscillator clock frequency equals F
XOSC
/750, which is 34.7 – 36 kHz,
depending on crystal frequency. The table below lists the number of clock
periods after Event 0 before Event 1 times out.
Setting t
Event1
0 (000)
4 (0.111 – 0.115 ms)
1 (001)
6 (0.167 – 0.173 ms)
2 (010)
8 (0.222 – 0.230 ms)
3 (011)
12 (0.333 – 0.346 ms)
4 (100)
16 (0.444 – 0.462 ms)
5 (101)
24 (0.667 – 0.692 ms)
6 (110)
32 (0.889 – 0.923 ms)
7 (111)
48 (1.333 – 1.385 ms)
Enables (1) or disables (0) the RC oscillator calibration.
3
RC_CAL
1
R/W
R0
2
Reserved
WOR_RES
1:0
0 (00)
R/W
Controls the Event 0 resolution as well as maximum timeout of the WOR
module and maximum timeout under normal RX operation::
Setting Resolution
(1 LSB)
Max timeout
0 (00)
1 (01)
2 (10)
3 (11)
1 period (28
µ
s – 29
µ
s)
1.8 – 1.9 seconds
2
5
periods (0.89ms –0.92 ms)
58 – 61 seconds
2
10
periods (28 – 30 ms)
2
15
periods (0.91 – 0.94 s)
31 – 32 minutes
16.5 – 17.2 hours
Note that
WOR_RE
S
should be 0 or 1 when using WOR because
WOR_RE
S
> 1 will give a very low duty cycle.
In normal RX operation all settings of
WOR_RE
S
can be used.
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Page 81 of 92
CC1100
0x21: FREND1 – Front End RX Configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
3:2
1:0
LNA_CURRENT[1:0]
1 (01)
1 (01)
1 (01)
2 (10)
R/W
R/W
R/W
R/W
Adjusts front-end LNA PTAT current output
Adjusts front-end PTAT outputs
LNA2MIX_CURRENT[1:0]
LODIV_BUF_CURRENT_RX[1:0]
MIX_CURRENT[1:0]
Adjusts current in RX LO buffer (LO input to mixer)
Adjusts current in mixer
0x22: FREND0 – Front End TX Configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
Reserved
R0
LODIV_BUF_CURRENT_TX[1:0]
1 (0x01)
R/W
Adjusts current TX LO buffer (input to PA). The value to
use in this field is given by the SmartRF
®
Studio software
3
Reserved
R0
2:0
PA_POWER[2:0]
0 (0x00)
R/W
Selects PA power setting. This value is an index to the
ASK TX shaping, and for power ramp-up/ramp-down at the
start/end of transmission in all TX modulation formats.
0x23: FSCAL3 – Frequency Synthesizer Calibration
Bit
Field Name
Reset
R/W
Description
7:6
FSCAL3[7:6]
2 (0x02)
R/W
Frequency synthesizer calibration configuration. The value
to write in this field before calibration is given by the
SmartRF
®
Studio software.
5:4
3:0
CHP_CURR_CAL_EN[1:0]
FSCAL3[3:0]
2 (0x02)
9 (1001)
R/W
R/W
Enable charge pump calibration stage when 1
Frequency synthesizer calibration result register. Digital bit
vector defining the charge pump output current, on an
exponential scale: IOUT =
I
0
·2
FSCAL3[3:0]/4
Fast frequency hopping without calibration for each hop
can be done by calibrating upfront for each frequency and
SWRS038D
Page 82 of 92
CC1100
0x24: FSCAL2 – Frequency Synthesizer Calibration
Bit Field
Name
Reset
R/W
Description
7:6 Reserved
R0
5
VCO_CORE_H_EN
0
R/W
R/W
Choose high (1) / low (0) VCO
4:0 FSCAL2[4:0]
10 (0x0A)
Frequency synthesizer calibration result register. VCO current calibration
result and override value
Fast frequency hopping without calibration for each hop can be done by
0x25: FSCAL1 – Frequency Synthesizer Calibration
Bit Field
Name
Reset
R/W
Description
7:6 Reserved
R0
5:0 FSCAL1[5:0]
32 (0x20)
R/W
Frequency synthesizer calibration result register. Capacitor array setting
for VCO coarse tuning.
Fast frequency hopping without calibration for each hop can be done by
0x26: FSCAL0 – Frequency Synthesizer Calibration
Bit Field
Name
Reset
R/W
Description
7
Reserved
R0
6:0 FSCAL0[6:0]
13 (0x0D)
R/W
Frequency synthesizer calibration control. The value to use in this
0x27: RCCTRL1 – RC Oscillator Configuration
Bit Field
Name
Reset
R/W
Description
7
Reserved
0
R0
6:0 RCCTRL1[6:0]
65 (0x41)
R/W
RC oscillator configuration.
0x28: RCCTRL0 – RC Oscillator Configuration
Bit Field
Name
Reset
R/W
Description
7
Reserved
0
R0
6:0 RCCTRL0[6:0]
0 (0x00)
R/W
RC oscillator configuration.
SWRS038D
Page 83 of 92
CC1100
33.2 Configuration
Register Details – Registers that Lose Programming in SLEEP State
0x29: FSTEST – Frequency Synthesizer Calibration Control
Bit Field
Name
Reset
R/W
Description
7:0 FSTEST[7:0]
89 (0x59)
R/W
For test only. Do not write to this register.
0x2A: PTEST – Production Test
Bit Field
Name
Reset
R/W
Description
7:0 PTEST[7:0]
127 (0x7F)
R/W
Writing 0xBF to this register makes the on-chip temperature sensor
available in the IDLE state. The default 0x7F value should then be
written back before leaving the IDLE state.
Other use of this register is for test only.
0x2B: AGCTEST – AGC Test
Bit Field
Name
Reset
R/W
Description
7:0 AGCTEST[7:0]
63 (0x3F)
R/W
For test only. Do not write to this register.
0x2C: TEST2 – Various Test Settings
Bit Field
Name
Reset
R/W
Description
The value to use in this register is given by the SmartRF
®
Studio
7:0 TEST2[7:0]
136 (0x88)
R/W
0x2D: TEST1 – Various Test Settings
Bit Field
Name
Reset
R/W
Description
The value to use in this register is given by the SmartRF
®
Studio
7:0 TEST1[7:0]
49 (0x31)
R/W
0x2E: TEST0 – Various Test Settings
Bit Field
Name
Reset
R/W
Description
The value to use in this register is given by the SmartRF
®
Studio
7:2 TEST0[7:2]
2 (0x02)
R/W
1
0
VCO_SEL_CAL_EN
TEST0[0]
1
1
R/W
R/W
Enable VCO selection calibration stage when 1
The value to use in this register is given by the SmartRF
®
Studio
SWRS038D
Page 84 of 92
CC1100
33.3 Status
Register Details
0x30 (0xF0): PARTNUM – Chip ID
Bit Field
Name
Reset
R/W
Description
7:0 PARTNUM[7:0]
0 (0x00)
R
Chip part number
0x31 (0xF1): VERSION – Chip ID
Bit Field
Name
Reset
R/W
Description
7:0 VERSION[7:0]
3 (0x03)
R
Chip version number.
0x32 (0xF2): FREQEST – Frequency Offset Estimate from Demodulator
Bit Field
Name
Reset
R/W
Description
7:0 FREQOFF_EST
R
The estimated frequency offset (2’s complement) of the carrier. Resolution is
XTAL
/2
14
(1.59 – 1.65 kHz); range is ±202 kHz to ±210 kHz, dependent of XTAL
F
frequency.
Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK
modulation. This register will read 0 when using ASK or OOK modulation.
0x33 (0xF3): LQI – Demodulator Estimate for Link Quality
Bit Field
Name
Reset
R/W
Description
7
CRC OK
R
The last CRC comparison matched. Cleared when entering/restarting RX
mode.
6:0 LQI_EST[6:0]
R
The Link Quality Indicator estimates how easily a received signal can be
demodulated. Calculated over the 64 symbols following the sync word
0x34 (0xF4): RSSI – Received Signal Strength Indication
Bit Field
Name
Reset
R/W
Description
7:0 RSSI
R
Received signal strength indicator
SWRS038D
Page 85 of 92
CC1100
0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State
Bit
Field Name
Reset
R/W
Description
7:5
4:0
Reserved
R0
R
MARC_STATE[4:0]
Main Radio Control FSM State
Value
State name
SLEEP
State (Figure 16, page 42)
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
SLEEP
IDLE
IDLE
XOFF
XOFF
VCOON_MC
REGON_MC
MANCAL
VCOON
MANCAL
MANCAL
MANCAL
FS_WAKEUP
FS_WAKEUP
CALIBRATE
SETTLING
SETTLING
SETTLING
CALIBRATE
RX
REGON
STARTCAL
BWBOOST
FS_LOCK
IFADCON
12 (0x0C)
ENDCAL
13 (0x0D)
RX
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
RX_END
RX
RX_RST
RX
TXRX_SWITCH
RXFIFO_OVERFLOW
FSTXON
TXRX_SETTLING
RXFIFO_OVERFLOW
FSTXON
TX
TX
TX_END
TX
RXTX_SWITCH
TXFIFO_UNDERFLOW
RXTX_SETTLING
TXFIFO_UNDERFLOW
Note: it is not possible to read back the SLEEP or XOFF state numbers
because setting CSn low will make the chip enter the IDLE mode from the
SLEEP or XOFF states.
0x36 (0xF6): WORTIME1 – High Byte of WOR Time
Bit
Field Name
Reset
R/W
Description
7:0
TIME[15:8]
R
High byte of timer value in WOR module
0x37 (0xF7): WORTIME0 – Low Byte of WOR Time
Bit
Field Name
Reset
R/W
Description
7:0
TIME[7:0]
R
Low byte of timer value in WOR module
SWRS038D
Page 86 of 92
CC1100
0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status
Bit Field
Name
Reset
R/W
Description
7
CRC_OK
R
The last CRC comparison matched. Cleared when entering/restarting RX
mode.
6
5
4
3
2
CS
R
R
R
R
R
Carrier sense
PQT_REACHED
CCA
Preamble Quality reached
Channel is clear
SFD
Sync word found
Current GDO2 value. Note: the reading gives the non-inverted value
GDO2
1
0
Reserved
R0
R
Current GDO0 value. Note: the reading gives the non-inverted value
GDO0
0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module
Bit Field
Name
Reset R/W
Description
7:0 VCO_VC_DAC[7:0]
R
Status register for test only.
0x3A (0xFA): TXBYTES – Underflow and Number of Bytes
Bit Field
Name
Reset R/W
Description
7
TXFIFO_UNDERFLOW
R
R
6:0 NUM_TXBYTES
Number of bytes in TX FIFO
0x3B (0xFB): RXBYTES – Overflow and Number of Bytes
Bit Field
Name
Reset R/W
Description
7
RXFIFO_OVERFLOW
R
R
6:0 NUM_RXBYTES
Number of bytes in RX FIFO
0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result
Bit Field
Name
Reset
R/W
Description
7
Reserved
R0
R
6:0 RCCTRL1_STATUS[6:0]
Contains the value from the last run of the RC oscillator calibration
routine.
SWRS038D
Page 87 of 92
CC1100
0x3D (0xFC): RCCTRL0_STATUS – Last RC Oscillator Calibration Result
Bit Field
Name
Reset
R/W
Description
7
Reserved
R0
R
6:0 RCCTRL0_STATUS[6:0]
Contains the value from the last run of the RC oscillator calibration
routine.
34 Package
Description (QLP 20)
34.1 Recommended
PCB Layout for Package (QLP 20)
Figure 31: Recommended PCB Layout for QLP 20 Package
Note: Figure 31 is an ill
ustration only and not to scale. There are five 10 mil via holes distributed
symmetrically in the ground pad under the package. See also the CC1100EM reference designs
34.2 Soldering
Information
SWRS038D
Page 88 of 92
CC1100
35 Ordering
Information
Orderable
Device
Status Package
Package
Drawing
Package
Qty
Lead
Finish
MSL Peak
Temp (3)
Pins
Eco Plan (2)
(1)
Type
LEVEL3-260C
1 YEAR
Green (RoHS &
no Sb/Br)
CC1100RTKR
CC1100RTK
NRND
QLP
RTK
RTK
20
3000
92
Cu NiPdAu
Cu NiPdAu
LEVEL3-260C
1 YEAR
Green (RoHS &
no Sb/Br)
NRND
QLP
20
Table 39: Ordering Information
SWRS038D
Page 89 of 92
CC1100
36 References
[7] SmartRF
®
Studio (swrc046.zip)
[9] CC1100/CC1150DK,
CC1101DK, and CC2500/CC2550DK Examples and Libraries
User
SWRS038D
Page 90 of 92
CC1100
37 General
Information
37.1 Document
History
Revision
Date
Description/Changes
SWRS038D
2009-05-26 Updated
packet and ordering information.
Removed Product Status Definition, Address Information and TI World Wide Support section.
Removed Low-Cost from datasheet title.
SWRS038C
SWRS038B
2008-05-22 Added
product information on front page
Added info to ordering information
2007-07-09
Changes in the
General Principle of Matrix Interleaving
figure.
Changes in Table:
Bill Of Materials for the Application Circuit
Changes in Figure:
Typical Application and Evaluation Circuit 868/915 MHz
Changed the equation for channel spacing in the MDMCFG0 register.
kbps replaced by kBaud throughout the document.
Some of the sections have been re-written to be easier to read without having any new info
added.
Absolute maximum supply voltage rating increased from 3.6 V to 3.9 V.
Changed the frequency accuracy after calibration for the low power RC oscillator from ±0.3 to
±1 %.
Updates to sensitivity and current consumption numbers listed under
Key Features
.
FSK changed to 2-FSK throughout the document.
Updates to the
Abbreviation
table.
Updates to the
Electrical Specifications
section.
Added info about RX and TX latency.
Added info in the
Pinout Overview
table regarding GDO0 and GDO2.
Changed current consumption in RX and TX in the simplified state diagram.
Added info about default values after reset vs. optimum register settings in the
Configuration
Software
section
Changes to the
SPI Interface Timing Requirements
.
Info added about t
sp,pd
The following figures have been changed:
Configuration Registers Write and Read Operations
,
In the
Register Access
section, the address range is changed.
In the
PATABLE Access
section, info is added regarding limitations on output power
programming when using PA ramping.
In the
Packet Format
section, preamble pattern is changed to 10101010 and info about bug
related to turning off the transmitter in infinite packet length mode is added.
Added info to the
Frequency Offset Compensation
section.
Added info about the initial value of the PN9 sequence in the
Data Whitening
section.
In the
Packet Handling in Transmit Mode
section, info about TX FIFO underflow state is added.
Added section
Packet Handling in Firmware
.
0x00 is added as a valid PATABLE setting in addition to 0x30-0x3F when using ASK.
In the PQT section a change is made as to how much the counter decreases.
The RSSI value is in dBm and not dB.
The whole
CS Absolute Threshold
section has been re-written and the equation calculating the
threshold has been removed.
Added info in the CCA section on what happens if the channel is not clear.
Added info to the LQI section for better understanding.
Removed all references to the voltage regulator in relation with the CHP_RDYn signal, as this
signal is only related to the crystal.
Removed references to the voltage regulator in the figures:
Power-On Reset
and
Power-On
Reset with SRES
. Changes to the SI line in the
Power-On Reset with SRES
figure
Added info on the three automatic calibration options.
Removed the autosync feature from the WOR section and added info on how to exit WOR
mode
.
Also added info about minimum sleep time and references to App. Note 047 together
with info about calibration of the RC oscillator.
The figure:
Event 0 and Event 1 Relationship
is changed for better readability.
Info added to the
Timing
section related to reduced calibration time.
The
Output Power Programming
section is divided into 2 new sections;
Output Power
Programming
and
Shaping and PA Ramping
.
Added info on programming of PATABLE when using OOK, and about PATABLE when entering
SLEEP mode.
2 new figures added to the
Shaping and PA Ramping
section:
Shaping of ASK Signa
l and
PA
Ramping
, together with one new table:
PATABLE Settings Used Together with ASK Shaping
and PA Ramping
.
Power Levels and Frequency Bands
table.
Added section
Layout Recommendations.
In section
General Purpose / Test Output Control Pins
: Added info on GDO pins in SLEEP
SWRS038D
Page 91 of 92
CC1100
Revision
Date
Description/Changes
state.
Better explanation of some of the signals in the
GDOx Signal Selection
table. Also added some
more signals.
Asynchronous transparent mode is called asynchronous serial mode throughout the document.
Removed comments about having to use NRZ coding in synchronous serial mode. Added info
that Manschester encoding cannot be used in this mode.
Added a third calibration method plus additional info about the 3 methods in the
Frequency
Hopping and Multi-Channel Systems
section.
Added info about differential antenna in the
Low Cost Systems
section.
Changes number of commands strobes from 14 to 13.
Changed description of SFRX, SFTX, SWORRST, and SNOP in the
Command Strobes
table.
Changed field name and/or description of the following registers:
PKTCTRL1, MCSM2, MCSM0, WORCTRL, FSCAL3, FSCAL2, FSCAL1, and TEST0.
Changed tray width in the
Tray Specification
table.
Added references.
Updates to
Electrical Specifications
due to increased amount of measurement data.
Updated application circuit for 868 MHz. Updated balun component values.
Updated current consumption figures in state diagrams.
SWRS038A
2006-06-20
Added figures to table on SPI interface timing requirements.
Added information about SPI read.
Added table for channel filter bandwidths.
Added figure showing data whitening.
Updates to text and included new figure in section on arbitrary length configuration.
References to SAFC strobe removed.
Added additional information about support of ASK modulation.
Added information about CRC filtering.
Added information about sync word qualifier.
Added information on RSSI offset, RSSI update rate, RSSI calculation and typical RSSI curves.
Added information on CS and tables with register settings versus CS threshold.
Updates to text and included new figures in section on power-on start-up sequence.
Changes to wake-on-radio current consumption figures under electrical specifications.
Updates to text in section on data FIFO.
Corrected formula for calculation of output frequency in
Frequency Programming
section.
Added information about how to check for PLL lock in section on VCO.
Added typical selectivity curves for selected datarates.
Added information on how to interface external clock signal.
Added optimal match impedances in RF match section.
Better explanation of some of the signals in table of GDO signal selection. Also added some
more signals.
Added information on system considerations.
Added CRC_AUTOFLUSH option in PCTRL1 register.
Added information on timeout for sync word search in RX in register MCSM2.
Changes to wake-on-radio control register WORCTRL. WOR_RES[1:0] settings 10 b and 11b
changed to NA.
Added more detailed information on PO_TIMEOUT in register MCSM0.
Added description of programming bits in registers FOCCFG, BSCFG, AGCCTRL2,
AGCCTRL1, AGCCTRL0, FREND1, FSCAL3.
1.0
2005-04-25 First
preliminary Data Sheet release
Table 40: Document History
SWRS038D
Page 92 of 92
PACKAGE OPTION ADDENDUM
24-Apr-2014
PACKAGING INFORMATION
Orderable Device
CC1100-RTR1
CC1100-RTY1
CC1100RTK
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
VQFN
VQFN
VQFN
VQFN
VQFN
RTK
20
20
20
20
20
3000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
CC1100
NRND
NRND
NRND
NRND
RTK
RTK
RTK
RTK
92
92
Green (RoHS
& no Sb/Br)
-40 to 85
CC1100
CC1100
CC1100
CC1100
Green (RoHS
& no Sb/Br)
-40 to 85
CC1100RTKG3
CC1100RTKR
92
Green (RoHS
& no Sb/Br)
-40 to 85
3000
Green (RoHS
& no Sb/Br)
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
24-Apr-2014
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CC1100RTKR
VQFN
RTK
20
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
VQFN RTK
20
SPQ
Length (mm)
Width (mm)
Height (mm)
350.0 350.0
43.0
CC1100RTKR
3000
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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