Texas-Instruments-CC2541F256RHAR
| Part # | Texas-Instruments-CC2541F256RHAR |
Download  | Texas-Instruments-CC2541F256RHAR |
ZHCS708D
–
J
ANUARY 201
2
–
R
EVISED JUNE 2013
2.4-GHz
Bluetooth™
低能耗和私有片载系统
1
特性
23
•
射频
空格
微控制器
–
–
–
2.4-GHz
Bluetooth
符合低能耗规范和私有的
RF
片载系统
•
–
具有代码预取功能的高性能和低功率
8051
微控
制器内核
支持
250-kbps
，
500-kbps
，
1-Mbps
，
2-Mbps
的数据速率
–
–
–
–
–
系统内可编程闪存，
128
或者
256 KB
在所有功率模式下具有保持功能的
8-KB RAM
支持硬件调试
出色的链路预算，不使用外部前段而支持长距离
应用
–
–
高达
0 dBm
的可编程输出功率
扩展基带自动化，包括自动确认和地址解码
所有功率模式中对所有相关寄存器的保持
出色的接收器灵敏度 （
1 Mbps
时为
–94
dBm
），可选择性，和阻挡性能
•
外设
–
适合于针对符合世界范围内的无线电频率调节系
统：
ETSI EN 300 328
和
EN 300 440 2
类
（欧洲），
FCC CFR47 15
部分（美国），和
ARIB STD-T66
（日本）
–
–
–
–
–
功能强大的
5
通道直接内存访问
(DMA)
通用定时器 （
1
个
16
位，
2
个
8
位）
红外
(IR)
生成电路
•
布局
具有捕捉功能的
32-kHz
睡眠定时器
–
–
–
–
极少的外部组件
精确数字接收到的数字信号强度指示器
(RSSI)
支持
提供参考设计
–
–
电池监视器和温度传感器
6-mm × 6-mm
方形扁平无引脚
(QFN)-40
封装
与
CC2540
引脚兼容 （当不使用
USB
或者
I
2
C
时）
含
8
通道和可配置分辨率的
12
位模数转换器
(ADC)
–
–
高级加密标准
(AES)
安全协处理器
•
低功率
2
个功能强大的支持几个串行协议的通用异步接
收发器
(UART)
–
–
–
–
–
–
工作模式
RX
低至：
17.9 mA
工作模式
TX (0 dBm)
：
18.2 mA
功率模式
1
（
4-µs
唤醒）：
270 µA
功率模式
2
（睡眠定时器打开）：
1 µA
功率模式
3
（外部中断）：
0.5 µA
宽泛的电源电压范围
(2 V–3.6 V)
–
23
个通用
I/O
引脚
(21 × 4 mA
，
2 × 20 mA)
I
2
C
接口
–
–
–
–
2
个具有
LED
驱动功能的
I/O
引脚
安全装置定时器
•
集成的高性能比较器
–
–
RX
低至：
14.7 mA
（
3-V
电源）
•
开发工具
TX (0 dBm)
：
14.3 mA
（
3V
电源）
–
–
–
–
CC2541
评估模块工具包
(CC2541EMK)
空格
空格
空格
空格
空格
CC2541
小型开发工具包
(CC2541DK-MINI)
SmartRF™
软件
提供
IAR
嵌入式
Workbench™
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Bluetooth is a trademark of Bluetooth SIG, Inc..
ZigBee is a registered trademark of ZigBee Alliance.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
版权
© 2012–2013, Texas Instruments Incorporated
ZHCS708D
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ANUARY 201
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软件特性
•
符合针对单模式蓝牙低能耗
(BLE)
解决方案的符
合
Bluetooth
v4.0
协议的堆栈
•
换器
–
完全功率优化堆栈，包括控制器和主机
•
•
•
•
•
•
延长电池寿命高达
20%
–
–
–
–
GAP –
中心设备，外设，或者广播器（包括
组合角色）
在所有工作模式下减少的电流
30-nA
旁通模式电流以支持低功率模式
RF
性能并未改变
属性协议
(ATT) /
通用属性配置文件
(GATT) –
客户端和服务器
小型封装允许小型解决方案尺寸
CC2541
可控
对称式对多重处理
(SMP) – AES-128
加密和
解密
L2CAP
说明
–
示例应用和配置文件
CC2541
是一款针对
Bluetooth
低能耗以及私有
2.4-
GHz
应用的功率优化的真正片载系统
(SoC)
解决方
案。 它使得使用低总体物料清单成本建立强健网络节
点成为可能。
CC2541
将领先
RF
收发器的出色性能
和一个业界标准的增强型
8051 MCU
、系统内可编程
闪存存储器、
8-KB RAM
和很多其它功能强大的特性
和外设组合在一起。
CC2541
非常适合应用于需要超
低能耗的系统。 这由多种不同的运行模式指定。 运行
模式间较短的转换时间进一步使低能耗变为可能。
–
–
针对
GAP
中心和外围作用的一般应用
距离临近，加速计，简单关键字，和电池
GATT
服务
–
–
–
多重配置选项
–
–
单芯片配置，允许应用运行在
CC2541
上
用于运行在一个外部微处理器上的网络处理
器接口
BTool –
用于评估、开发和测试的视窗
(Windows) PC
应用
如果
CC2540
上的
USB
未启用并且
CC2541
上的
I
2
C/
额外
I/O
未启用，那么
CC2541
与
CC2540
在
6-
mm x 6-mm
方形扁平无引脚
(QFN)40
封装内引脚兼
容。 与
CC2540
相比，
CC2541
提供更低
RF
流耗。
CC2541
没有
CC2540
所具有的
USB
接口，并在
TX
模式中提供较低的最大输出功率。
CC2541
还增加了
1
个
HW I
2
C
接口。
应用范围
•
•
•
•
•
•
2.4-GHz
Bluetooth
低能耗系统
私有的
2.4-GHz
系统
人机接口器件（键盘，鼠标，遥控）
体育和休闲设备
移动电话附件
CC2541
与
CC2533
优化
RF4CE IEEE 802.15.4 SoC
引脚兼容。
消费类电子产品
CC2541
有
2
个不同的版本：分别具有
128kB
和
256kB
闪存的的
CC2541F128/F256
。
2
Copyright © 2012–2013, Texas Instruments Incorporated
ZHCS708D
–
J
ANUARY 201
2
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EVISED JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
DCOUPL
RESET
WATCHDOG TIMER
RESET_N
POWER-ON RESET
BROWN OUT
XOS
C
_
Q
2
XOS
C
_
Q
1
32-MHZ
CRYSTAL OSC
CLOCK MUX and
CALIBRATION
SLEEP TIMER
32.768-kHz
CRYSTAL OSC
P2_4
P2_3
P2_2
P2_1
P2_0
POWER MGT. CONTROLLER
DEBUG
INTERFACE
HIGH SPEED
RC-OSC
32-kHz
RC-OSC
PDATA
XRAM
IRAM
SFR
RAM
SRAM
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
UNIFIED
DMA
FLASH CTRL
1-KB SRAM
IRQ
CTRL
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
OP-
FIFOCTRL
RADIO
REGISTERS
AES
ENCRYPTION
and
DECRYPTION
DS
ADC
AUDIO / DC
Link Layer Engine
DEMODULATOR
MODULATOR
I
2
C
SDA
SCL
USART 0
USART 1
RECEIVE
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P RF_N
DIGITAL
ANALOG
MIXED
Figure 1.
Block Diagram
Copyright © 2012–2013, Texas Instruments Incorporated
3
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ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
UNIT
Supply voltage
All supply pins must have the same voltage
3.9
V
Voltage on any digital pin
Input RF level
VDD + 0.3
≤
3.9
V
10
dBm
°C
Storage temperature range
–40
125
All pins, excluding pins 25 and 26, according to human-body
model, JEDEC STD 22, method A114
2
1
kV
kV
V
All pins, according to human-body model, JEDEC STD 22,
method A114
ESD
(2)
According to charged-device model, JEDEC STD 22, method
C101
500
(1) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
CAUTION:
ESD sesnsitive device. Precautions should be used when handling the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
85
UNIT
°C
Operating ambient temperature range, T
A
Operating supply voltage
–40
2
3.6
V
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V,
1 Mbps, GFSK, 250-kHz deviation,
Bluetooth
low energy mode, and 0.1% BER
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
RX mode, standard mode, no peripherals active, low MCU
activity
17.9
RX mode, high-gain mode, no peripherals active, low MCU
activity
20.2
mA
TX mode, –20 dBm output power, no peripherals active, low
MCU activity
16.8
TX mode, 0 dBm output power, no peripherals active, low
MCU activity
18.2
270
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-
MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and
sleep timer active; RAM and register retention
I
core
Core current consumption
Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-
MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep
timer active; RAM and register retention
µA
1
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.5
Low MCU activity: 32-MHz XOSC running. No radio or
peripherals. Limited flash access, no RAM access.
6.7
mA
Timer 1. Timer running, 32-MHz XOSC used
Timer 2. Timer running, 32-MHz XOSC used
Timer 3. Timer running, 32-MHz XOSC used
Timer 4. Timer running, 32-MHz XOSC used
Sleep timer, including 32.753-kHz RCOSC
ADC, when converting
90
90
Peripheral current consumption
(Adds to core current I
core
for each
peripheral unit activated)
60
μ
A
I
peri
70
0.6
1.2
mA
4
Copyright © 2012–2013, Texas Instruments Incorporated
ZHCS708D
–
J
ANUARY 201
2
–
R
EVISED JUNE 2013
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
Power mode 1
→
Active
4
120
500
μ
s
μ
s
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
Power mode 2 or 3
→
Active
Crystal ESR = 16
Ω
. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
μ
s
μ
s
Active
→
TX or RX
With 32-MHz XOSC initially on
Proprietary auto mode
BLE mode
180
130
150
RX/TX turnaround
μ
s
RADIO PART
RF frequency range
Programmable in 1-MHz steps
2379
2496
MHz
2 Mbps, GFSK, 500-kHz deviation
2 Mbps, GFSK, 320-kHz deviation
1 Mbps, GFSK, 250-kHz deviation
1 Mbps, GFSK, 160-kHz deviation
500 kbps, MSK
Data rate and modulation format
250 kbps, GFSK, 160-kHz deviation
250 kbps, MSK
RF RECEIVE SECTION
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V, f
c
= 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Receiver sensitivity
–90
–1
–9
–2
36
41
dBm
dBm
dB
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal at –67 dBm
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
±4 MHz offset, 0.1% BER, wanted signal –67 dBm
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm
In-band blocking rejection
dB
Including both initial tolerance and drift. Sensitivity better than –67dBm,
250 byte payload. BER 0.1%
Frequency error tolerance
(1)
–300
–120
300
120
kHz
Symbol rate error
tolerance
(2)
Maximum packet length. Sensitivity better than–67dBm, 250 byte
payload. BER 0.1%
ppm
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER
Receiver sensitivity
–86
–7
dBm
dBm
dB
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal at –67 dBm
–12
–1
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
±4 MHz offset, 0.1% BER, wanted signal –67 dBm
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm
In-band blocking rejection
34
dB
39
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250 byte payload. BER 0.1%
Frequency error tolerance
(1)
–300
–120
300
120
kHz
Symbol rate error
tolerance
(2)
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
ppm
(1) Difference
between center frequency of the received RF signal and local oscillator frequency
(2) Difference
between incoming symbol rate and the internally generated symbol rate
Copyright © 2012–2013, Texas Instruments Incorporated
5
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RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V, f
c
= 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
1 Mbps, GFSK, 250-kHz Deviation,
Bluetooth
low energy Mode, 0.1% BER
High-gain mode
Receiver sensitivity
(3
)
(
4)
–94
dBm
–88
Standard mode
Saturation
(4)
Co-channel rejection
(4)
BER < 0.1%
5
–6
dBm
dB
Wanted signal –67 dBm
±1 MHz offset, 0.1% BER, wanted signal –67 dBm
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
±3 MHz offset, 0.1% BER, wanted signal –67 dBm
>6 MHz offset, 0.1% BER, wanted signal –67 dBm
Minimum interferer level < 2 GHz (Wanted signal –67 dBm)
Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm)
Minimum interferer level > 3 GHz (Wanted signal –67 dBm)
Minimum interferer level
–2
26
In-band blocking rejection
(4)
dB
34
33
–21
–25
–7
Out-of-band blocking
rejection
(4)
dBm
Intermodulation
(4)
–36
dBm
kHz
Including both initial tolerance and drift. Sensitivity better than -67dBm,
250 byte payload. BER 0.1%
Frequency error tolerance
(5)
–250
–80
250
80
Symbol rate error
tolerance
(6)
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
ppm
1 Mbps, GFSK, 160-kHz Deviation, 0.1% BER
Receiver sensitivity
(7)
–91
0
dBm
dBm
dB
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal 10 dB above sensitivity level
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
±3-MHz offset, 0.1% BER, wanted signal -–67 dBm
>6-MHz offset, 0.1% BER, wanted signal –67 dBm
–9
2
24
27
32
In-band blocking rejection
dB
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Frequency error tolerance
(5)
–200
–80
200
80
kHz
Symbol rate error
tolerance
(6)
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
ppm
500 kbps, MSK, 0.1% BER
Receiver sensitivity
(7)
Saturation
–99
0
dBm
dBm
dB
BER < 0.1%
Co-channel rejection
Wanted signal –67 dBm
–5
20
27
28
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
In-band blocking rejection
dB
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Frequency error tolerance
Symbol rate error tolerance
–150
–80
150
80
kHz
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
ppm
(3) The
receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
(4) Results
based on standard-gain mode.
(5) Difference
between center frequency of the received RF signal and local oscillator frequency
(6) Difference
between incoming symbol rate and the internally generated symbol rate
(7) Results
based on high-gain mode.
6
Copyright © 2012–2013, Texas Instruments Incorporated
ZHCS708D
–
J
ANUARY 201
2
–
R
EVISED JUNE 2013
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V, f
c
= 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
250 kbps, GFSK, 160 kHz Deviation, 0.1% BER
(8)
Receiver sensitivity
–98
0
dBm
dBm
dB
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal -67 dBm
–3
23
28
29
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
In-band blocking rejection
dB
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
Frequency error tolerance
(9)
–150
–80
150
80
kHz
Symbol rate error
tolerance
(10)
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
ppm
250 kbps, MSK, 0.1% BER
(11)
Receiver sensitivity
–99
0
dBm
dBm
dB
Saturation
BER < 0.1%
Co-channel rejection
Wanted signal -67 dBm
–5
20
29
30
±1-MHz offset, 0.1% BER, wanted signal –67 dBm
±2-MHz offset, 0.1% BER, wanted signal –67 dBm
>2-MHz offset, 0.1% BER, wanted signal –67 dBm
In-band blocking rejection
Frequency error tolerance
dB
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
250-byte payload. BER 0.1%
–150
–80
150
80
kHz
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
payload. BER 0.1%
Symbol rate error tolerance
ppm
ALL RATES/FORMATS
Spurious emission in RX.
Conducted measurement
f < 1 GHz
f > 1 GHz
–67
–57
dBm
dBm
Spurious emission in RX.
Conducted measurement
(8) Results
based on standard-gain mode.
(9) Difference
between center frequency of the received RF signal and local oscillator frequency
(10) Difference
between incoming symbol rate and the internally generated symbol rate
(11) Results
based on high-gain mode.
Copyright © 2012–2013, Texas Instruments Incorporated
7
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V and f
c
= 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dBm
dB
Delivered to a single-ended 50-
Ω
load through a balun using
maximum recommended output power setting
0
Output power
Delivered to a single-ended 50-
Ω
load through a balun using
minimum recommended output power setting
–23
23
Programmable output power
Delivered to a single-ended 50-
Ω
load through a balun using
range
minimum recommended output power setting
f < 1 GHz
–52
–48
dBm
dBm
Spurious emission conducted
f > 1 GHz
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
Optimum load impedance
70 +j30
Ω
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC
resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect
both from the signal trace to a good RF ground.
CURRENT CONSUMPTION WITH TPS62730
Measured on Texas Instruments CC2541 TPA62730 EM reference design with T
A
= 25°C, VDD = 3 V and f
c
= 2440 MHz,
1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy Mode, 1% BER
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RX mode, standard mode, no peripherals active, low MCU activity, MCU
at 1 MHz
14.7
RX mode, high-gain mode, no peripherals active, low MCU activity,
MCU at 1 MHz
16.7
13.1
Current consumption
mA
TX mode, –20 dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHz
TX mode, 0 dBm output power, no peripherals active, low MCU activity,
MCU at 1 MHz
14.3
(1) 0.1%
BER maps to 30.8% PER
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V
PARAMETER
Crystal frequency
TEST CONDITIONS
MIN
TYP
MAX UNIT
32
MHz
Crystal frequency accuracy
requirement
(1)
–40
40 ppm
ESR
C
0
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
6
1
60
7
Ω
pF
pF
ms
C
L
10
16
0.25
The crystal oscillator must be in power down for a guard
time before it is used again. This requirement is valid for
all modes of operation. The need for power-down guard
time can vary with crystal type and load.
Power-down guard time
3
ms
(1) Including
aging and temperature dependency, as specified by [1]
8
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32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Crystal frequency
32.768
kHz
Crystal frequency accuracy requirement
(1)
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
–40
40
130
2
ppm
k
Ω
pF
pF
s
ESR
C
0
40
0.9
12
C
L
16
0.4
(1) Including
aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V.
PARAMETER
Calibrated frequency
(1)
TEST CONDITIONS
MIN
TYP
32.753
±0.2%
0.4
MAX UNIT
kHz
Frequency accuracy after calibration
Temperature coefficient
(2)
Supply-voltage coefficient
(3)
Calibration time
(4)
%/°C
%/V
ms
3
2
(1) The
calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
(2) Frequency
drift when temperature changes after calibration
(3) Frequency
drift when supply voltage changes after calibration
(4) When
the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
16
MAX
UNIT
Frequency
(1)
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy
Start-up time
±18%
±0.6%
10
μ
s
μ
s
Initial calibration time
(2)
50
(1) The
calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
(2) When
the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
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RSSI CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Reduced gain by AGC algorithm
64
64
79
99
±6
1
Useful RSSI range
(1)
dB
High gain by AGC algorithm
Reduced gain by AGC algorithm
RSSI offset
(1)
dBm
High gain by AGC algorithm
Absolute uncalibrated accuracy
(1)
Step size (LSB value)
dB
dB
All Other Rates/Formats
Standard mode
64
64
98
107
±3
1
Useful RSSI rang
e
(1)
High-gain mode
dB
Standard mode
RSSI offset
(1)
dBm
High-gain mode
Absolute uncalibrated accuracy
(1)
Step size (LSB value)
dB
dB
(1) Assuming
CC2541 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V and f
c
= 2440 MHz
PARAMETER
TEST CONDITIONS
At ±1-MHz offset from carrier
MIN
TYP
–109
–112
–119
MAX
UNIT
Phase noise, unmodulated carrier
At ±3-MHz offset from carrier
At ±5-MHz offset from carrier
dBc/Hz
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2541 EM reference design with T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12-bit
/ 1°C
0.1 V
°C
Output
1480
4.5
1
Temperature coefficient
Voltage coefficient
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
Initial accuracy without calibration
Accuracy using 1-point calibration
Current consumption when enabled
±10
±5
°C
0.5
mA
COMPARATOR CHARACTERISTICS
T
A
= 25°C, VDD = 3 V. All measurement results are obtained using the CC2541 reference designs, post-calibration.
PARAMETER
Common-mode maximum voltage
Common-mode minimum voltage
Input offset voltage
TEST CONDITIONS
MIN
TYP MAX
UNIT
VDD
–0.3
1
V
mV
µV/°C
mV/V
nA
Offset vs temperature
Offset vs operating voltage
Supply current
16
4
230
0.15
Hysteresis
mV
10
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ADC CHARACTERISTICS
T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
MIN
0
TYP
MAX
VDD
VDD
VDD
UNIT
V
Input voltage
External reference voltage
0
V
External reference voltage differential
VDD is voltage on AVDD5 pin
0
V
Input resistance, signal
Full-scale signal
(1)
Simulated using 4-MHz clock speed
Peak-to-peak, defines 0 dBFS
197
2.97
5.7
k
Ω
V
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
9.3
10.3
6.5
ENOB
(1)
Effective number of bits
bits
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
9.7
10-bit setting, clocked by RCOSC
12-bit setting, clocked by RCOSC
7-bit setting, both single and differential
Single ended input, 12-bit setting, –6 dBFS
(1)
Differential input, 12-bit setting, –6 dBFS
(1)
Single-ended input, 12-bit setting
(1)
Differential input, 12-bit setting
(1)
Single-ended input, 12-bit setting, –6 dBFS
(1)
Differential input, 12-bit setting, –6 dBFS
(1)
10.9
0–20
–75.2
–86.6
70.2
79.3
78.8
88.9
Useful power bandwidth
Total harmonic distortion
kHz
dB
THD
Signal to nonharmonic ratio
dB
dB
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
CMRR
Common-mode rejection ratio
Crosstalk
>84
>84
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
dB
Offset
Midscale
–3
0.68%
0.05
0.9
mV
Gain error
12-bit setting, mean
(1)
12-bit setting, maximum
(1)
12-bit setting, mean
(1)
DNL
INL
Differential nonlinearity
Integral nonlinearity
LSB
LSB
4.6
12-bit setting, maximum
(1)
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Single ended input, 7-bit setting
(1)
Single ended input, 9-bit setting
(1)
Single ended input, 10-bit settin
g
(1)
Single ended input, 12-bit settin
g
(1)
Differential input, 7-bit settin
g
(1)
Differential input, 9-bit settin
g
(1)
Differential input, 10-bit setting
(1)
Differential input, 12-bit setting
(1)
7-bit setting
13.3
10
29
35.4
46.8
57.5
66.6
40.7
51.6
61.8
70.8
20
SINAD
(–THD+N)
Signal-to-noise-and-distortion
dB
9-bit setting
36
Conversion time
μ
s
10-bit setting
68
12-bit setting
132
(1) Measured
with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (continued)
T
A
= 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
4
MAX
UNIT
mA
Power consumption
Internal reference VDD coefficient
mV/V
Internal reference temperature
coefficient
0.4
mV/10°C
V
Internal reference voltage
1.24
CONTROL INPUT AC CHARACTERISTICS
T
A
= –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
System clock, f
SYSCLK
t
SYSCLK
= 1/ f
SYSCLK
16
32
MHz
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
RESET_N low duration
Interrupt pulse duration
1
µs
ns
an interrupt request.
20
RESE
T
_
N
1
2
Px.n
T0299-01
Figure 2.
Control Input AC Characteristics
12
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SPI AC CHARACTERISTICS
T
A
= –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
250
250
TYP MAX
UNIT
Master, RX and TX
Slave, RX and TX
Master
t
1
SCK period
ns
SCK duty cycle
SSN low to SCK
50%
Master
63
63
63
63
t
2
t
3
ns
Slave
Master
SCK to SSN high
ns
Slave
t
4
t
5
t
6
t
7
MOSI early out
MOSI late out
MISO setup
MISO hold
Master, load = 10 pF
Master, load = 10 pF
Master
7
ns
ns
ns
ns
ns
ns
ns
ns
10
90
10
Master
SCK duty cycle
MOSI setup
MOSI hold
Slave
50%
t
10
t
11
t
9
Slave
35
10
Slave
MISO late out
Slave, load = 10 pF
Master, TX only
Master, RX and TX
Slave, RX only
Slave, RX and TX
95
8
4
Operating frequency
MHz
8
4
SCK
t
2
t
3
SSN
t
4
t
5
MOSI
D0
X
D1
t
6
t
7
MISO
X
D0
X
T0478-01
Figure 3.
SPI Master AC Characteristics
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SCK
t
2
t
3
SSN
t
8
t
9
MISO
D0
X
D1
t
10
t
11
MOSI
X
D0
X
T0479-01
Figure 4.
SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
T
A
= –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
UNIT
MHz
ns
f
clk_dbg
t
1
t
2
35
35
ns
EXT_RESET_N low to first falling edge on debug clock (see
t
3
167
ns
t
4
t
5
t
6
t
7
t
8
83
83
2
ns
ns
ns
ns
ns
4
Load = 10 pF
30
Time
DEBU
G
_
C
LK
P2_2
t
1
t
2
1/f
clk_dbg
T0436-01
Figure 5.
Debug Clock – Basic Timing
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Time
DEBU
G
_
C
LK
P2_2
RESE
T
_
N
t
3
t
4
t
5
T0437-01
Figure 6.
Debug Enable Timing
Time
DEBU
G
_
C
LK
P2_2
DEBU
G
_
DATA
(to CC2541)
P2_1
DEBU
G
_
DATA
(from CC2541)
P2_1
t
6
t
7
t
8
Figure 7.
Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
T
A
= –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
Input capture pulse duration
1.5
t
SYSCLK
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DC CHARACTERISTICS
T
A
= 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Logic-0 input voltage
0.5
Logic-1 input voltage
2.4
–50
–50
V
Logic-0 input current
Input equals 0 V
50
50
nA
nA
k
Ω
V
Logic-1 input current
Input equals VDD
I/O-pin pullup and pulldown resistors
Logic-0 output voltage, 4- mA pins
Logic-1 output voltage, 4-mA pins
Logic-0 output voltage, 20- mA pins
Logic-1 output voltage, 20-mA pins
20
Output load 4 mA
Output load 4 mA
Output load 20 mA
Output load 20 mA
0.5
0.5
2.5
2.5
V
V
V
DEVICE INFORMATION
PIN DESCRIPTIONS
CC2541
RHA Package
(Top View)
40 39 38 37 36 35 34 33 32 31
GND
SCL
R_BIAS
1
2
30
29
28
27
26
25
24
23
22
21
AVDD4
AVDD1
AVDD2
RF_N
SDA
3
NC
4
P1_5
P1_4
P1_3
P1_2
P1_1
DVDD2
5
GND
Ground Pad
RF_P
6
7
AVDD3
XOSC_Q2
XOSC_Q1
8
9
10
AVDD5
11 12 13 14 15 16 17 18 19 20
NOTE: The
exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 8.
Pinout Top View
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PIN DESCRIPTIONS
PIN NAME
AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVDD6
DCOUPL
DVDD1
DVDD2
GND
PIN
28
27
24
29
21
31
40
39
10
1
PIN TYPE
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Power (digital)
Power (digital)
Power (digital)
Ground pin
Ground
DESCRIPTION
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
2-V–3.6-V digital power-supply connection
2-V–3.6-V digital power-supply connection
Connect to GND
GND
—
4
The ground pad must be connected to a solid ground plane.
NC
Unused pins
Digital I/O
Not connected
P0_0
19
18
17
16
15
14
13
12
11
9
Port 0.0
P0_1
Digital I/O
Port 0.1
P0_2
Digital I/O
Port 0.2
P0_3
Digital I/O
Port 0.3
P0_4
Digital I/O
Port 0.4
P0_5
Digital I/O
Port 0.5
P0_6
Digital I/O
Port 0.6
P0_7
Digital I/O
Port 0.7
P1_0
Digital I/O
Port 1.0 – 20-mA drive capability
Port 1.1 – 20-mA drive capability
Port 1.2
P1_1
Digital I/O
P1_2
8
Digital I/O
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
37
36
35
34
33
Digital I/O
Port 1.6
P1_7
Digital I/O
Port 1.7
P2_0
Digital I/O
Port 2.0
P2_1/DD
P2_2/DC
Digital I/O
Port 2.1 / debug data
Port 2.2 / debug clock
Port 2.3/32.768 kHz XOSC
Digital I/O
P2_3/
Digital I/O, Analog I/O
OSC32K_Q2
P2_4/
32
Digital I/O, Analog I/O
Port 2.4/32.768 kHz XOSC
OSC32K_Q1
RBIAS
30
20
26
Analog I/O
Digital input
RF I/O
External precision bias resistor for reference current
Reset, active-low
RESET_N
RF_N
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
SCL
25
2
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
Can be used as I
2
C clock pin or digital I/O. Leave floating if not used. If grounded
disable pull up
Can be used as I
2
C data pin or digital I/O. Leave floating if not used. If grounded
disable pull up
I
2
C clock or digital I/O
I
2
C clock or digital I/O
SDA
3
XOSC_Q1
XOSC_Q2
22
23
Analog I/O
Analog I/O
32-MHz crystal oscillator pin 1 or external clock input
32-MHz crystal oscillator pin 2
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BLOCK DIAGRAM
A block diagram of the CC2541 is shown in
Figure 9
. The modules can be roughly divided into one of three
categories: CPU-related modules; modules
related to
power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
DCOUPL
RESET
WATCHDOG TIMER
RESET_N
POWER-ON RESET
BROWN OUT
XOS
C
_
Q
2
XOS
C
_
Q
1
32-MHZ
CRYSTAL OSC
CLOCK MUX and
CALIBRATION
SLEEP TIMER
32.768-kHz
CRYSTAL OSC
P2_4
P2_3
P2_2
P2_1
P2_0
POWER MGT. CONTROLLER
DEBUG
INTERFACE
HIGH SPEED
RC-OSC
32-kHz
RC-OSC
PDATA
XRAM
IRAM
SFR
RAM
SRAM
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
UNIFIED
DMA
FLASH CTRL
1-KB SRAM
IRQ
CTRL
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
OP-
FIFOCTRL
RADIO
REGISTERS
AES
ENCRYPTION
and
DECRYPTION
DS
ADC
AUDIO / DC
Link Layer Engine
DEMODULATOR
MODULATOR
I
2
C
SDA
SCL
USART 0
USART 1
RECEIVE
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P RF_N
DIGITAL
ANALOG
MIXED
Figure 9.
CC2541 Block Diagram
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BLOCK DESCRIPTIONS
A block diagram of the CC2541 is shown in
Figure 9
. The modules can be roughly divided into one of three
categories: CPU-related modules; modules
related to
power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
CPU and Memory
The
8051 CPU core
is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The
memory arbiter
is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The
SFR bus
is drawn conceptually in
Figure 9
as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the
block diagram
also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The
8-KB SRAM
maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and
mode 3).
The
128/256 KB flash block
provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a
flash controller
that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile five-channel
DMA controller
is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,
ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers
between a single SFR or XREG address and flash/SRAM.
Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth
device. Designers are free to use this address, or provide their own, as described in the
Bluetooth
specfication.
The
interrupt controller
services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the
device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.
The
debug interface
implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators
are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code
breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-
circuit debugging and external flash programming elegantly.
The
I/O controller
is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The
sleep timer
is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an
internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode
3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1
or mode 2.
A built-in
watchdog timer
allows the CC2541 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
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Timer 1
is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2
is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter
that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also
used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which
transmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers that
can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4
are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1
are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The
AES encryption/decryption core
allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The
ADC
supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a single-
ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The
I
2
C
module provides a digital peripheral connection with two pins and supports both master and slave
operation. I
2
C support is compliant with the NXP I
2
C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well as
master and slave modes.
The ultralow-power
analog comparator
enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
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TYPICAL CHARACTERISTICS
RX CURRENT
vs
TEMPERATURE
TX CURRENT
vs
TEMPERATURE
19
18.5
18
19.5
1 Mbps GFSK 250 kHz
TX Power Setting = 0 dBm
V
CC
= 3 V
Standard Gain Setting
Input = −70 dBm
V
CC
= 3 V
19
18.5
18
17.5
17
17.5
17
16.5
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
G001
G002
Figure 10.
Figure 11.
RX SENSITIVITY
vs
TEMPERATURE
TX POWER
vs
TEMPERATURE
−84
−86
−88
−90
4.0
2.0
1 Mbps GFSK 250 kHz
Standard Gain Setting
V
CC
= 3 V
TX Power Setting = 0 dBm
V
CC
= 3 V
0.0
−2.0
−4.0
−92
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
G003
G004
Figure 12.
Figure 13.
RX CURRENT
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
20
19.5
19
20
19.5
19
1 Mbps GFSK 250 kHz
Standard Gain Setting
Input = −70 dBm
T
A
= 25°C
TX Power Setting = 0 dBm
T
A
= 25°C
18.5
18
18.5
18
17.5
17
17.5
17
16.5
16.5
16
16
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage (V)
Voltage (V)
G005
G006
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
vs
TX POWER
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
−84
−86
−88
−90
−92
4
2
1 Mbps GFSK 250 kHz
Standard Gain Setting
T
A
= 25°C
TX Power Setting = 0 dBm
T
A
= 25°C
0
−2
−4
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage (V)
Voltage (V)
G007
G008
Figure 16.
Figure 17.
RX SENSITIVITY
vs
FREQUENCY
TX POWER
vs
FREQUENCY
−84
−86
−88
−90
−92
4
2
1 Mbps GFSK 250 kHz
Standard Gain Setting
T
A
= 25°C
TX Power Setting = 0 dBm
T
A
= 25°C
V
CC
= 3 V
V
CC
= 3 V
0
−2
−4
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
G009
G010
Figure 18.
Figure 19.
Table 1.
Output Power
(1
)
(
2)
TXPOWER Setting
0xE1
Typical Output Power (dBm)
0
0xD1
–2
0xC1
–4
0xB1
–6
0xA1
–8
0x91
–10
–12
–14
–16
–18
–20
–23
0x81
0x71
0x61
0x51
0x41
0x31
(1) Measured
on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V and f
c
= 2440 MHz. See
SWRU191
for
recommended register settings.
(2) 1
Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy mode, 1% BER
22
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Table 2. Output Power and Current Consumption
Typical Current Consumption
(mA)
(1)
Typical Current Consumption
With TPS62730 (mA)
(2)
Typical Output Power (dBm)
0
18.2
16.8
14.3
13.1
–20
(1) Measured
on Texas Instruments CC2541 EM reference design with T
A
= 25°C, VDD = 3 V and f
c
=
(2) Measured
on Texas Instruments CC2541 TPS62730 EM reference design with T
A
= 25°C, VDD = 3 V
TYPICAL CURRENT SAVINGS WHEN USING TPS62730
Current Consumption TX 0 dBm
0
Current Consumption RX SG
CLKCONMOD 0xBF
25
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
25
20
15
10
5
DC/DC OFF
DC/DC OFF
DC/DC ON
DC/DC ON
Current Savings
20
15
10
5
Current Savings
0
0
0
0
2.1
2.4
2.7 3
Supply (V)
3.3
3.6
2.1
2.4
2.7 3
Supply (V)
3.3
3.6
Figure 20. Current Savings in TX at Room
Temperature
Figure 21. Current Savings in RX at Room
Temperature
The application note (
SWRA365
) has information regarding the CC2541 and TPS62730 combo board and the
current savings that can be achieved using the combo board.
Copyright © 2012–2013, Texas Instruments Incorporated
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2541. A typical application circuit is shown in
32-kHz Crystal
(1)
C331
2-V to 3.6-V Power Supply
C401
C321
R301
RBIAS
30
GND
SCL
1
2
3
4
5
6
7
8
9
AVDD4
29
AVDD1
28
AVDD2
27
Antenna
(50
W
)
SDA
NC
RF_N
RF_P
26
25
P1_5
P1_4
P1_3
P1_2
P1_1
CC2541
DIE ATTACH PAD
AVDD3
24
XOSC_Q2
23
22
XOSC_Q1
AVDD5
21
10
DVDD2
XTAL1
C221
C231
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in
the standby state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 22.
CC2541 Application Circuit
Table 3. Overview of External Components (Excluding Supply Decoupling Capacitors)
Component
C401
Description
Value
1 µF
Decoupling capacitor for the internal 1.8-V digital voltage regulator
Precision resistor ±1%, used for internal biasing
R301
56 k
Ω
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541EM,
for recommended balun.
24
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Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See
32-MHz CRYSTAL OSCILLATOR
for details. The load capacitance seen by the 32-MHz crystal is
given by:
1
C
L
=
+
C
parasitic
1
1
+
C
221
C
231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
C
L
=
+
C
parasitic
1
1
+
C
321
C
331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1.
Bluetooth
® Core Technical Specification document, version 4.0
2. CC253x
System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee
®
Applications/CC2541 System-on-
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standard-
based wireless applications for use in industrial and consumer applications. Our selection includes RF
transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the
sub-1- and 2.4-GHz frequency bands.
In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and university
programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance
to interact with fellow engineers from all over the world.
With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas
Instruments offers the broadest low-power RF portfolio. We make RF easy!
The following subsections point to where to find more information.
Copyright © 2012–2013, Texas Instruments Incorporated
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Texas Instruments Low-Power RF Web Site
•
•
•
Forums, videos, and blogs
RF design help
E2E interaction
Texas Instruments Low-Power RF Developer Network
Texas Instruments has launched an extensive network of low-power RF development partners to help customers
speed up their application development. The network consists of recommended companies, RF consultants, and
independent design houses that provide a series of hardware module products and design services, including:
•
•
•
RF circuit, low-power RF, and ZigBee
®
design services
Low-power RF and ZigBee module solutions and development tools
RF certification services and RF circuit manufacturing
Need help with modules, engineering services or development tools?
Search the Low-Power RF Developer Network tool to find a suitable partner.
Low-Power RF eNewsletter
The Low-Power RF eNewsletter keeps you up-to-date on new products, news releases, developers’ news, and
other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articles
include links to get more online information.
Sign up today on
Spacer
REVISION HISTORY
Changes from Original (January 2012) to Revision A
Page
Page
Changes from Revision A (February 2012) to Revision B
•
•
Changes from Revision B (August 2012) to Revision C
Page
•
•
•
Changed pin XOSC_Q1 Pin Type From Analog O To: Analog I/O, and changed the Pin Description …………………………
17
Changes from Revision C (November 2012) to Revision D
Page
•
•
•
Changed the RF TRANSMIT SECTION, Programmable output power range TYP value From: 20 To: 23
……………………
8
26
Copyright © 2012–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
5-Feb-2014
PACKAGING INFORMATION
Orderable Device
CC2541F128RHAR
CC2541F128RHAT
CC2541F256RHAR
CC2541F256RHAT
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
RHA
40
40
40
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
CC2541
F128
ACTIVE
ACTIVE
ACTIVE
RHA
RHA
RHA
250
2500
250
Green (RoHS
& no Sb/Br)
CC2541
F128
Green (RoHS
& no Sb/Br)
CC2541
F256
Green (RoHS
& no Sb/Br)
CC2541
F256
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
5-Feb-2014
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
22-Feb-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CC2541F128RHAR
CC2541F128RHAT
CC2541F256RHAR
CC2541F256RHAT
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
40
40
40
40
2500
250
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
22-Feb-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2541F128RHAR
CC2541F128RHAT
CC2541F256RHAR
CC2541F256RHAT
VQFN
VQFN
VQFN
VQFN
RHA
RHA
RHA
RHA
40
40
40
40
2500
250
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
28.6
28.6
28.6
28.6
2500
250
Pack Materials-Page 2
重要声明
德州仪器
(TI)
及其下属子公司有权根据
JESD46
最新标准
,
对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48
最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息
,
并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的
TI
销售条款与条件。
TI
保证其所销售的组件的性能符合产品销售时
TI
半导体产品销售条件与条款的适用规范。仅在
TI
保证的范围内，且
TI
认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI
对应用帮助或客户产品设计不承担任何义务。客户应对其使用
TI
组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI
不对任何
TI
专利权、版权、屏蔽作品权或其它与使用了
TI
组件或服务的组合设备、机器或流程相关的
TI
知识产权中授予 的直接或隐含权
限作出任何保证或解释。
TI
所发布的与第三方产品或服务有关的信息，不能构成从
TI
获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是
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对于
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的产品手册或数据表中
TI
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复制。
TI
对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售
TI
组件或服务时，如果对该组件或服务参数的陈述与
TI
标明的参数相比存在差异或虚假成分，则会失去相关
TI
组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。
TI
对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由
TI
提供，但他们将独力负责满足与其产品及在其应用中使用
TI
产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何
TI
组件而
对
TI
及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对
TI
组件进行特别的促销。
TI
的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI
组件未获得用于
FDA Class III
（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些
TI
特别注明属于军用等级或
“
增强型塑料
”
的
TI
组件才是设计或专门用于军事
/
航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的
TI
组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI
已明确指定符合
ISO/TS16949
要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到
ISO/TS16949
要
求，
TI
不承担任何责任。
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