Texas-Instruments-CC2640R2FRSMR
| Part # | Texas-Instruments-CC2640R2FRSMR |
Download  | Texas-Instruments-CC2640R2FRSMR |
ZHCSFW7
–
D
ECEMBER 2016
CC2640R2F SimpleLink™
Bluetooth
®
低功耗
无线
MCU
1
器件概述
1.1
特性
1
装选项
•
微控制器
–
强大的
ARM
®
Cortex
®
-M3
– EEMBC
CoreMark
®
评分：
142
–
高达
48MHz
的时钟速度
–
支持八个电容感测按钮
–
集成温度传感器
•
外部系统
–
片上内部
DC-DC
转换器
–
极少的外部组件
– 275KB
非易失性存储器，包括
128KB
系统内可
编程闪存
–
高达
28KB
系统
SRAM
，其中
20KB
为超低泄漏
静态随机存取存储器
(SRAM)
–
无缝集成
SimpleLink™CC2590
和
CC2592
范围
扩展器
– 8KB
SRAM
，适用于缓存或系统
RAM
使用
– 2
引脚
cJTAG
和
JTAG
调试
–
支持无线升级
(OTA)
–
与采用
4mm × 4mm
和
5mm × 5mm VQFN
封装
的
SimpleLink CC13xx
引脚兼容
•
低功耗
–
宽电源电压范围
•
超低功耗传感器控制器
–
正常工作电压：
1.8V
至
3.8V
–
外部稳压器模式：
1.7V
至
1.95V
–
有源模式
RX
：
5.9mA
–
可独立于系统其余部分自主运行
– 16
位架构
– 2KB
超低泄漏代码和数据
SRAM
–
有源模式
TX (0dBm)
：
6.1mA
–
有源模式
TX (+5dBm)
：
9.1mA
–
有源模式
MCU
：
61µA/MHz
–
有源模式
MCU
：
48.5 CoreMark/mA
–
有源模式传感器控制器：
0.4mA + 8.2
μ
A/MHz
•
在
ROM
中存储高效代码尺寸架构，装载驱动程
序、
TI-RTOS
和 蓝牙
®
软件，为应用程序提供更多
闪存空间
•
封装符合
RoHS
标准
– 2.7mm
× 2.7mm YFV DSBGA34
封装（
14
个
GPIO
）
– 4mm
× 4mm RSM VQFN32
封装（
10
个
GPIO
）
–
待机电流：
1.1
μ
A
（
RTC
运行，
RAM/CPU
保
持）
– 5mm
× 5mm RHB VQFN32
封装（
15
个
GPIO
）
– 7mm
× 7mm RGZ VQFN48
封装（
31
个
GPIO
）
–
关断电流：
100nA
（发生外部事件时唤醒）
•
射频
(RF)
部分
– 2.4GHz
RF
收发器，符合
Bluetooth
低功耗
(BLE) 4.2
和
5
规范
–
出色的接收器灵敏度（
BLE
对应
–97dBm
）、可
选择性和阻断性能
•
外设
–
所有数字外设引脚均可连接任意
GPIO
–
四个通用定时器模块
（
8 × 16
位或
4 × 32
位，均采用脉宽调制
(PWM)
）
– 12
位模数转换器
(ADC)
、
200MSPS
、
8
通道模
拟多路复用器
– 102dB
(BLE)
的链路预算
–
最高达
+5dBm
的可编程输出功率
–
单端或差分
RF
接口
–
适用于符合各项全球射频规范的系统
– ETSI
EN 300 328
（欧洲）
– EN
300 440 2
类（欧洲）
– FCC
CFR47
第
15
部分（美国）
– ARIB
STD-T66
（日本）
•
工具和开发环境
–
持续时间比较器
–
超低功耗模拟比较器
–
可编程电流源
– UART
– 2
个同步串行接口
(SSI)
（
SPI
、
MICROWIRE
和
TI
）
–
功能全面的开发套件
–
针对不同
RF
配置的
– I2C
– SmartRF™
工具产品组合
– Sensor
Controller Studio
– IAR
Embedded Workbench
®
（用于
ARM
）
– Code
Composer Studio™
– CCS
Cloud
– I2S
–
实时时钟
(RTC)
– AES-128
安全模块
–
真随机数发生器
(TRNG)
– 10
、
14
、
15
或
31
个
GPIO
，具体取决于所用封
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ZHCSFW7
–
D
ECEMBER 2016
1.2
应用
•
•
•
家庭和楼宇自动化
•
•
健康和医疗
–
–
–
–
–
已联网家用电器
照明
–
–
–
–
–
温度计
SpO2
安全锁
血糖仪和血压计
体重秤
网关
安防系统
助听器
工业
运动和健身设备
–
–
–
–
–
物流
–
–
–
–
–
–
活动监视器和健身追踪器
心率监视器
生产制造自动化
资产跟踪和管理
HMI
和远程显示
访问控制
跑步和自行车传感器
运动手表
健身房器械
团体运动装备
零售
–
–
–
–
信标
•
HID
广告
–
–
–
语音远程控制
电子货架标签
(ESL)
和价格标签
销售点和支付系统
游戏
键盘和鼠标
1.3
说明
CC2640R2F
器件是一款无线微控制器
(MCU)
，主要适用于
Bluetooth
®
4.2
和
Bluetooth 5
低功耗 应用。
此器件属于
SimpleLink™ CC26xx
系列中的经济高效型超低功耗
2.4GHz RF
器件。它具有极低的有源
RF
和
MCU
电流以及低功耗模式流耗，可确保卓越的电池使用寿命，适合小型纽扣电池供电以及在能源采集型
应用中 使用。
SimpleLink Bluetooth
低功耗
CC2640R2F
器件含有一个
32
位
ARM
®
Cortex
®
-M3
内核（与主处理器工作
频率同为
48MHz
），并且具有丰富的外设功能集，其中包括一个独特的超低功耗传感器控制器。此传感器
控制器非常适合连接外部传感器，还适合用于在系统其余部分处于睡眠模式的情况下自主收集模拟和数字数
据。因此，
CC2640R2F
器件成为 注重 电池使用寿命、小型尺寸和简便实用性的各类应用的理想选择。
CC2640R2F
无线
MCU
的电源和时钟管理以及无线系统需要采用特定配置并由软件处理才能正确运行，这
已在
TI-RTOS
中实现。
TI
建议将此软件框架应用于针对器件的全部应用程序开发过程。完整的
TI-RTOS
和
这款
Bluetooth
低功耗控制器和主机库嵌入在
ROM
中，并在
ARM
®
Cortex
®
-M0
处理器上单独运行。此架
构可改善整体系统性能和功耗，并释放大量闪存以供应用。
器件信息
(1)
封装
产品型号
封装尺寸（标称值）
7.00mm x 7.00mm
5.00mm x 5.00mm
4.00mm x 4.00mm
2.70mm × 2.70mm
CC2640R2FRGZ
CC2640R2FRHB
CC2640R2FRSM
CC2640R2FYFV
VQFN (48)
VQFN (32)
VQFN (32)
芯片尺寸球状引脚栅格阵列
(DSBGA) (34)
2
器件概述
版权
© 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
1.4
功能框图
中的功能框图
SimpleLink CC26xx Wireless MCU
RF Core
cJTAG
Main CPU:
ROM
ADC
ADC
ARM
Cortex-M3
128-KB
Flash
Digital PLL
DSP modem
8-KB
cache
Up to 48 MHz
61 µA/MHz
4-KB
SRAM
ARM
Cortex-M0
20-KB
SRAM
ROM
General Peripherals / Modules
Sensor Controller
2
4× 32-bit Timers
I C
Sensor Controller Engine
UART
I2S
2× SSI (SPI, µW, TI)
Watchdog Timer
12-bit ADC, 200 ks/s
2× Comparator
10 / 14 / 15 / 31 GPIOs
AES
TRNG
2
SPI-I C
Digital Sensor IF
Temp. / Batt. Monitor
Constant Current Source
32 ch. µDMA
RTC
Time-to-digital Converter
2-KB SRAM
DC-DC Converter
Copyright © 2016, Texas Instruments Incorporated
图
1-1.
方框图
版权
© 2016, Texas Instruments Incorporated
器件概述
3
ZHCSFW7
–
D
ECEMBER 2016
内容
1
2
3
4
6
4.5
Signal Descriptions – YFV (Chip Scale, DSBGA)
4.6
5
7
8
7.2
5 × 5 External Differential (5XD) Application Circuit
4 × 4 External Single-ended (4XS) Application
7.3
9
2
修订历史记录
日期
修订版本
注释
2016
年
12
月
SWRS204*
最初发布版本
4
修订历史记录
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
3 Device
Comparison
Table 3-1. Device Family Overview
Device
PHY Support
Bluetooth low energy (Normal, High
Speed, Long Range)
Bluetooth low energy (Normal)
Multi-Protocol
(3)
Flash (KB)
RAM (KB)
GPIO
Package
(1)
CC2640R2Fxxx
(2)
128
20
31, 15, 14, 10
RGZ, RHB, YFV, RSM
CC2640F128xxx
CC2650F128xxx
CC2630F128xxx
CC2620F128xxx
128
128
128
128
20
20
20
20
31, 15, 10
31, 15, 10
31, 15, 10
31, 10
RGZ, RHB, RSM
RGZ, RHB, RSM
RGZ, RHB, RSM
RGZ, RSM
IEEE 802.15.4 (/6LoWPAN)
IEEE 802.15.4 (RF4CE)
(1) Package
designator replaces the xxx in device name to form a complete device name, RGZ is 7-mm × 7-mm VQFN48, RHB is
5-mm × 5-mm VQFN32, RSM is 4-mm × 4-mm VQFN32, and YFV is 2.7-mm × 2.7-mm DSBGA.
(2) CC2640R2Fxxx
devices contain Bluetooth 4.2 low energy Host & Controller libraries in ROM, leaving more of the 128KB flash available
for the customer application when used with supported BLE-Stack software protocol stack releases. Actual use of ROM and flash by the
protocol stack may vary depending on device software configuration. See
www.ti.com
and
Table 3-2
for more details.
(3) The
CC2650 device supports all PHYs and can be reflashed to run all the supported standards.
Table 3-2. Typical
(1)
Flash Memory Available for Customer Applications
Device
Simple BLE Peripheral (BT 4.0)
(2)
Simple BLE Peripheral (BT 4.2
)
(2) (3)
CC2640R2Fxxx
(4)
83 KB
41 KB
80 KB
31 KB
CC2640F128xxx, CC2650F128xxx
(1) Actual
use of ROM and flash by the protocol stack will vary depending on device software configuration. The values in this table are
provided as guidance only.
(2) Application
example with two services (GAP and Simple Profile). Compiled using IAR.
(3) BT4.2
configuration including Secure Pairing, Privacy 1.2, and Data Length Extension
(4) BLE
applications running on the CC2640R2F device make use of up to 115 KB of system ROM and up to 32 KB of RF Core ROM in
order to minimize the flash usage. The maximum amount of nonvolatile memory available for BLE applications on CC2640R2F is thus
275 KB (128-KB flash + 147-KB ROM).
3.1 Related
Products
The wireless
connectivity portfolio offers a wide selection of low-power RF solutions suitable
for a broad range of applications. The offerings range from fully customized solutions to turn
key offerings with pre-certified hardware and software (protocol).
Long-range, low-power wireless connectivity solutions are offered in a wide range of
Sub-1 GHz ISM bands.
Review products
that are frequently purchased or used in conjunction with this product.
connection to the LaunchPad ecosystem with the SimpleLink ultra-low power CC26xx family
of devices. Compared to the CC2650 LaunchPad, the CC2640R2 LaunchPad provides the
following:
•
•
•
More free flash memory for the user application in the CC2640R2 wireless MCU
Out-of-the-box support for Bluetooth 4.2 specification
4× faster Over-the-Air download speed compared to Bluetooth 4.1
The new SensorTag IoT kit invites you to realize your
cloud-connected product idea. The
new SensorTag now includes 10 low-power MEMS sensors in a tiny red package. And it is
expandable with DevPacks to make it easy to add your own sensors or actuators.
TI Designs Reference
Design Library is a robust reference design library divning analog,
embedded processor and connectivity. Created by TI experts to help you jump-start your
system design, all TI Designs include schematic or block diagrams, BOMs, and design files
Copyright © 2016, Texas Instruments Incorporated
Device Comparison
5
ZHCSFW7
–
D
ECEMBER 2016
4 Terminal
Configuration and Functions
4.1 Pin
Diagram – RGZ Package
DIO_24
37
DIO_25
38
DIO_26
39
DIO_27
40
DIO_28
41
DIO_29
42
DIO_30
43
VDDS 44
24
JTAG_TMSC
23 DCOUPL
22 VDDS3
21 DIO_15
20 DIO_14
19 DIO_13
18 DIO_12
17 DIO_11
16 DIO_10
15 DIO_9
VDDR 45
X24M_N 46
X24M_P 47
VDDR_RF 48
14 DIO_8
13 VDDS2
Figure 4-1. RGZ Package
48-Pin VQFN
(7-mm × 7-mm) Pinout, 0.5-mm Pitch
•
•
•
•
•
•
Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 24, JTAG_TMSC
Pin 26, DIO_16
Pin 27, DIO_17
•
•
•
•
•
•
•
•
Pin 36, DIO_23
Pin 37, DIO_24
Pin 38, DIO_25
Pin 39, DIO_26
Pin 40, DIO_27
Pin 41, DIO_28
Pin 42, DIO_29
Pin 43, DIO_30
6
Terminal Configuration and Functions
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
4.2 Signal
Descriptions – RGZ Package
Table 4-1. Signal Descriptions – RGZ Package
NAME
NO.
33
23
5
TYPE
DESCRIPTION
Output from internal DC-DC
(1)
1.27-V regulated digital-supply decoupling capacitor
(2)
DCDC_SW
DCOUPL
DIO_0
Power
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO, Sensor Controller
DIO_1
6
GPIO, Sensor Controller
DIO_2
7
GPIO, Sensor Controller
DIO_3
8
GPIO, Sensor Controller
DIO_4
9
GPIO, Sensor Controller
DIO_5
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
24
25
35
GPIO, Sensor Controller, high-drive capability
DIO_6
GPIO, Sensor Controller, high-drive capability
DIO_7
GPIO, Sensor Controller, high-drive capability
DIO_8
GPIO
DIO_9
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
JTAG_TMSC
JTAG_TCKC
RESET_N
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
GPIO
GPIO
GPIO
GPIO
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital I/O
Digital I/O
Digital input
JTAG TMSC, high-drive capability
JTAG TCKC
Reset, active-low. No internal pullup.
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RF_P
RF_N
1
2
RF I/O
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
VDDR
45
48
44
Power
Power
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
3)
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
4)
1.8-V to 3.8-V main chip supply
(1)
VDDR_RF
VDDS
(2) Do
not supply external circuitry from this pin.
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
Copyright © 2016, Texas Instruments Incorporated
Terminal Configuration and Functions
7
ZHCSFW7
–
D
ECEMBER 2016
Table 4-1. Signal Descriptions – RGZ Package (continued)
NAME
NO.
13
22
34
3
TYPE
Power
DESCRIPTION
VDDS2
1.8-V to 3.8-V DIO supply
(1)
1.8-V to 3.8-V DIO supply
(1)
1.8-V to 3.8-V DC-DC supply
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
VDDS3
Power
VDDS_DCDC
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
Power
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
4
46
47
8
Terminal Configuration and Functions
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
4.3 Pin
Diagram – RHB Package
DIO_12
25
DIO_13
26
DIO_14
27
VDDS 28
16
DIO_6
15
DIO_5
14 JTAG_TCKC
13
JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10
DIO_4
9
DIO_3
Figure 4-2. RHB Package
32-Pin VQFN
(5-mm × 5-mm) Pinout, 0.5-mm Pitch
•
•
•
•
•
•
Pin 8, DIO_2
Pin 9, DIO_3
Pin 10, DIO_4
Pin 13, JTAG_TMSC
Pin 15, DIO_5
Pin 16, DIO_6
•
•
•
•
•
•
•
•
Pin 20, DIO_7
Pin 21, DIO_8
Pin 22, DIO_9
Pin 23, DIO_10
Pin 24, DIO_11
Pin 25, DIO_12
Pin 26, DIO_13
Pin 27, DIO_14
Copyright © 2016, Texas Instruments Incorporated
Terminal Configuration and Functions
9
ZHCSFW7
–
D
ECEMBER 2016
4.4 Signal
Descriptions – RHB Package
Table 4-2. Signal Descriptions – RHB Package
NAME
NO.
17
12
6
TYPE
DESCRIPTION
Output from internal DC-DC
(1)
1.27-V regulated digital-supply decoupling
(2)
DCDC_SW
DCOUPL
DIO_0
Power
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO, Sensor Controller
DIO_1
7
GPIO, Sensor Controller
DIO_2
8
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, High drive capability, JTAG_TDO
GPIO, High drive capability, JTAG_TDI
DIO_3
9
DIO_4
10
15
16
20
21
22
23
24
25
26
27
13
14
19
DIO_5
DIO_6
DIO_7
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital I/O
Digital I/O
Digital input
JTAG TMSC, high-drive capability
JTAG TCKC
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX
3
RF I/O
Power
Optional bias pin for the RF LNA
VDDR
29
32
28
11
18
4
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC
(3
)
(
2)
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
4)
1.8-V to 3.8-V main chip supply
(1)
VDDR_RF
VDDS
Power
Power
VDDS2
Power
1.8-V to 3.8-V GPIO suppl
y
(1)
VDDS_DCDC
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
Power
1.8-V to 3.8-V DC-DC supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
32-kHz crystal oscillator pin 1
5
32-kHz crystal oscillator pin 2
30
31
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
(2) Do
not supply external circuitry from this pin.
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
10
Terminal Configuration and Functions
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
4.5 Pin
Diagram – YFV (Chip Scale, DSBGA) Package
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
E2
F2
A3
B3
C3
D3
E3
F3
A4
B4
C4
D4
E4
F4
B5
C5
D5
E5
F5
B6
C6
D6
E6
F6
Figure 4-3. YFV (2.7-mm × 2.7-mm) Pinout, Top View
4.6 Signal
Descriptions – YFV (Chip Scale, DSBGA) Package
Table 4-3. Signal Descriptions – YFV Package
NAME
NO.
D1
F3
C5
F6
D5
E5
F5
E3
F1
D2
D3
A1
C2
B2
D4
B3
E4
F2
E2
TYPE
DESCRIPTION
Output from internal DC-DC
(1)
1.27-V regulated digital-supply decoupling
(2)
DCDC_SW
DCOUPL
DIO_0
Power
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO, Sensor Controller
DIO_1
GPIO, Sensor Controller
DIO_2
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, High-drive capability, JTAG_TDO
GPIO, High-drive capability, JTAG_TDI
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital I/O
Digital I/O
Digital input
JTAG TMSC, high-drive capability
JTAG TCKC
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_N
RF_P
B6
B5
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
(2) Do
not supply external circuitry from this pin.
Copyright © 2016, Texas Instruments Incorporated
Terminal Configuration and Functions
11
ZHCSFW7
–
D
ECEMBER 2016
Table 4-3. Signal Descriptions – YFV Package (continued)
NAME
NO.
A3
B4
A2
F4
TYPE
Power
DESCRIPTION
VDDR
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC
(3
)
(
2)
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC
(4
)
(
2)
1.8-V to 3.8-V main chip supply
(1)
VDDR_RF
VDDS
Power
Power
VDDS2
Power
1.8-V to 3.8-V GPIO suppl
y
(1)
VDDS_DCDC
X32K_Q1
X32K_Q2
X24M_N
X24M_P
C1
D6
E6
C3
C4
Power
1.8-V to 3.8-V DC-DC supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
A4, B1, C6,
E1
GND
Power
Ground
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
12
Terminal Configuration and Functions
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
4.7 Pin
Diagram – RSM Package
DIO_8
25
DIO_9
26
16
DIO_4
15
DIO_3
VDDS 27
14 JTAG_TCKC
13
JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 28
VSS 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10
DIO_2
9
DIO_1
Figure 4-4. RSM Package
32-Pin VQFN
(4-mm × 4-mm) Pinout, 0.4-mm Pitch
•
•
•
•
•
•
Pin 8, DIO_0
Pin 9, DIO_1
Pin 10, DIO_2
Pin 13, JTAG_TMSC
Pin 15, DIO_3
Pin 16, DIO_4
•
•
•
•
•
Pin 22, DIO_5
Pin 23, DIO_6
Pin 24, DIO_7
Pin 25, DIO_8
Pin 26, DIO_9
Copyright © 2016, Texas Instruments Incorporated
Terminal Configuration and Functions
13
ZHCSFW7
–
D
ECEMBER 2016
4.8 Signal
Descriptions – RSM Package
Table 4-4. Signal Descriptions – RSM Package
NAME
NO.
TYPE
DESCRIPTION
Output from internal DC-DC.
(1)
. Tie to ground for external regulator mode
(1.7-V to 1.95-V operation)
DCDC_SW
18
Power
DCOUPL
DIO_0
12
8
Power
1.27-V regulated digital-supply decoupling capacitor
(2)
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, High-drive capability, JTAG_TDO
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
DIO_1
9
DIO_2
10
15
16
22
23
24
25
26
13
14
21
DIO_3
DIO_4
GPIO, High-drive capability, JTAG_TDI
DIO_5
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_6
DIO_7
DIO_8
DIO_9
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital I/O
Digital I/O
JTAG TMSC
JTAG TCKC
Digital Input
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX
VDDR
4
RF I/O
Power
Power
Power
Power
Optional bias pin for the RF LNA
28
32
27
11
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC
.
(2
)
(
3)
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
4)
1.8-V to 3.8-V main chip supply
(1)
VDDR_RF
VDDS
VDDS2
1.8-V to 3.8-V GPIO suppl
y
(1)
1.8-V to 3.8-V DC-DC supply. Tie to ground for external regulator mode
(1.7-V to 1.95-V operation).
VDDS_DCDC
VSS
19
Power
Power
3, 7, 17, 20,
29
Ground
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
5
6
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
30
31
(2) Do
not supply external circuitry from this pin.
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
14
Terminal Configuration and Functions
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
5 Specifications
5.1 Absolute
Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1
)
(
2)
MIN
MAX UNIT
VDDR supplied by internal DC-DC regulator or
internal GLDO. VDDS_DCDC connected to VDDS on
PCB.
Supply voltage (VDDS, VDDS2,
and VDDS3)
–0.3
4.1
V
Supply voltage (VDDS
(3)
and
VDDR)
External regulator mode (VDDS and VDDR pins
connected on PCB)
–0.3
2.25
V
Voltage on any digital pin
(4
)
(
5)
–0.3
–0.3
–0.3
–0.3
–0.3
VDDSx + 0.3, max 4.1
V
V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P
Voltage scaling enabled
VDDR + 0.3, max 2.25
VDDS
1.49
Voltage on ADC input (V
in
)
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
V
VDDS / 2.9
5
Input RF level
T
stg
dBm
°C
Storage temperature
–40
150
(1) All
voltage values are with respect to ground, unless otherwise noted.
(2) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) In
external regulator mode, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including
analog-capable DIO.
(5) Each
pin is referenced to a specific VDDSx (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see
Table 6-3
.
5.2 ESD
Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS001
(1)
All pins
±2500
V
ESD
Electrostatic discharge
V
RF pins
±750
±750
Charged device model (CDM), per JESD22-C101
(2)
Non-RF pins
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Ambient temperature
–40
85
°C
Operating supply
voltage (VDDS and
VDDR), external
regulator mode
For operation in 1.8-V systems
(VDDS and VDDR pins connected on PCB, internal DC-DC cannot be used)
1.7
1.95
V
Operating supply
voltage VDDS
1.8
1.8
3.8
3.8
V
V
Operating supply
voltages VDDS2 and
VDDS3
For operation in battery-powered and 3.3-V systems
(internal DC-DC can be used to minimize power consumption)
VDDS < 2.7 V
Operating supply
voltages VDDS2 and
VDDS3
VDDS
≥
2.7 V
1.9
3.8
V
Copyright © 2016, Texas Instruments Incorporated
Specifications
15
ZHCSFW7
–
D
ECEMBER 2016
5.4 Power
Consumption Summary
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V with internal DC-DC converter, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
100
150
1.1
MAX
UNIT
Reset. RESET_N pin asserted or VDDS below
Power-on-Reset threshold
nA
Shutdown. No clocks running, no retention
Standby. With RTC, CPU, RAM and (partial)
register retention. RCOSC_LF
Standby. With RTC, CPU, RAM and (partial)
register retention. XOSC_LF
1.3
2.8
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. RCOSC_LF
µA
I
core
Core current consumption
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. XOSC_LF
3.0
Idle. Supply Systems and RAM powered.
550
1.45 mA +
31 µA/MHz
Active. Core running CoreMark
(1)
Radio RX
5.9
6.1
6.1
9.1
Radio RX
(2)
Radio TX, 0-dBm output power
(1)
Radio TX, 5-dBm output power
(2)
mA
Peripheral Current Consumption (Adds to core current I
core
for each peripheral unit activated)
(3)
Peripheral power domain
Serial power domain
Delta current with domain enabled
Delta current with domain enabled
20
13
µA
µA
Delta current with power domain enabled, clock
enabled, RF core idle
RF Core
237
µA
µDMA
Timers
I
2
C
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
130
113
12
µA
µA
µA
µA
µA
µA
I
peri
I2S
36
SSI
93
UART
164
(1) Single-ended
RF mode is optimized for size and power consumption. Measured on CC2650EM-4XS.
(2) Differential
RF mode is optimized for RF performance. Measured on CC2650EM-5XD.
(3) I
peri
is not supported in Standby or Shutdown.
5.5 General
Characteristics
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
FLASH MEMORY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supported flash erase cycles before
failure
100
k Cycles
Maximum number of write operations
per row before erase
(1)
write
operations
83
Years at
105°C
Flash retention
105°C
11.4
Flash page/sector erase current
Flash page/sector size
Flash write current
Flash page/sector erase time
(2)
Flash write time
(2)
Average delta current
12.6
4
mA
KB
mA
ms
µs
Average delta current, 4 bytes at a time
4 bytes at a time
8.15
8
8
(1) Each
row is 2048 bits (or 256 Bytes) wide.
(2) This
number is dependent on Flash aging and will increase over time and erase cycles.
16
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
5.6 125-kbps
Coded (Bluetooth 5) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–103
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
>5
dBm
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
Data rate error tolerance
–260
–260
–140
310
260
150
kHz
ppm
ppm
dB
Difference between incoming data rate and the
internally generated data rate (37-byte packets)
Difference between incoming data rate and the
internally generated data rate (255-byte packets)
Wanted signal at –79 dBm, modulated interferer in
channel, BER = 10
–3
(1)
Co-channel rejection
–3
9 / 5
(2)
Wanted signal at –79 dBm, modulated interferer at
±1 MHz, BER = 10
–3
(1)
Selectivity, ±1 MHz
dB
Wanted signal at –79 dBm, modulated interferer at
±2 MHz, Image frequency is at –2 MHz, BER = 10
–3
(1)
Selectivity, ±2 MHz
43 / 32
(2)
47 / 42
(2)
46 / 47
(2)
49 / 46
(2)
50 / 47
(2)
32
dB
Wanted signal at –79 dBm, modulated interferer at
±3 MHz, BER = 10
–3
(1)
Selectivity, ±3 MHz
dB
Wanted signal at –79 dBm, modulated interferer at
±4 MHz, BER = 10
–3
(1)
Selectivity, ±4 MHz
dB
Wanted signal at –79 dBm, modulated interferer at
±6 MHz, BER = 10
–3
(1)
Selectivity, ±6 MHz
dB
Alternate channel rejection, ±7
Wanted signal at –79 dBm, modulated interferer at
≥
dB
MHz
(1)
±7 MHz, BER = 10
–3
Wanted signal at –79 dBm, modulated interferer at
image frequency, BER = 10
–3
Selectivity, image frequency
(1)
dB
Note that Image frequency + 1 MHz is the Co-
channel –1 MHz. Wanted signal at –79 dBm,
modulated interferer at ±1 MHz from image
frequency, BER = 10
–3
Selectivity, image frequency
±1 MHz
(1)
5 / 32
(2)
dB
dB
Blocker rejection, ±8 MHz and
Wanted signal at –79 dBm, modulated interferer at
>46
above
(1)
±8 MHz and above, BER = 10
–3
30 MHz to 2000 MHz
(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
–40
–19
–22
dBm
dBm
dBm
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
Wanted signal at 2402 MHz, –76 dBm. Two
interferers at 2405 and 2408 MHz respectively, at
the given power level
Intermodulation
–42
dBm
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
(3) Excluding
one exception at F
wanted
/ 2, per Bluetooth Specification.
Copyright © 2016, Texas Instruments Incorporated
Specifications
17
ZHCSFW7
–
D
ECEMBER 2016
5.7 125-kbps
Coded (Bluetooth 5) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
Output power, lowest setting
2
dBm
Delivered to a single-ended 50-
Ω
load through a balun
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
–21
–43
–65
–76
–46
dBm
dBm
dBm
dBm
dBm
Spurious emission conducted
measurement
(1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
5.8 500-kbps
Coded (Bluetooth 5) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–101
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
>5
dBm
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
Data rate error tolerance
–240
–500
–310
240
500
330
kHz
ppm
ppm
dB
Difference between incoming data rate and the
internally generated data rate (37-byte packets)
Difference between incoming data rate and the
internally generated data rate (255-byte packets)
Wanted signal at –72 dBm, modulated interferer in
channel, BER = 10
–3
(1)
Co-channel rejection
–5
9 / 5
(2)
Wanted signal at –72 dBm, modulated interferer at
±1 MHz, BER = 10
–3
(1)
Selectivity, ±1 MHz
dB
Wanted signal at –72 dBm, modulated interferer at
±2 MHz, Image frequency is at –2 MHz, BER = 10
–3
(1)
Selectivity, ±2 MHz
41 / 31
(2)
44 / 41
(2)
44 / 44
(2)
44 / 44
(2)
44 / 44
(2)
31
dB
Wanted signal at –72 dBm, modulated interferer at
±3 MHz, BER = 10
–3
(1)
Selectivity, ±3 MHz
dB
Wanted signal at –72 dBm, modulated interferer at
±4 MHz, BER = 10
–3
(1)
Selectivity, ±4 MHz
dB
Wanted signal at –72 dBm, modulated interferer at
±6 MHz, BER = 10
–3
(1)
Selectivity, ±6 MHz
dB
Alternate channel rejection,
±7 MHz
(1)
Wanted signal at –72 dBm, modulated interferer at
dB
≥
±7 MHz, BER = 10
–3
Wanted signal at –72 dBm, modulated interferer at
image frequency, BER = 10
–3
Selectivity, image frequency
(1)
dB
Note that Image frequency + 1 MHz is the Co-
channel –1 MHz. Wanted signal at –72 dBm,
modulated interferer at ±1 MHz from image
frequency, BER = 10
–3
Selectivity, image frequency
±1 MHz
(1)
5 / 41
(2)
dB
dB
Blocker rejection, ±8 MHz and
Wanted signal at –72 dBm, modulated interferer at
44
above
(1)
±8 MHz and above, BER = 10
–3
30 MHz to 2000 MHz
(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
–35
–19
–19
dBm
dBm
dBm
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
(3) Excluding
one exception at F
wanted
/ 2, per Bluetooth Specification.
18
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
500-kbps Coded (Bluetooth 5) – RX
(continued)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal at 2402 MHz, –69 dBm. Two
interferers at 2405 and 2408 MHz respectively, at
the given power level
Intermodulation
–37
dBm
5.9 500-kbps
Coded (Bluetooth 5) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
Output power, lowest setting
2
dBm
Delivered to a single-ended 50-
Ω
load through a balun
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
–21
–43
–65
–76
–46
dBm
dBm
dBm
dBm
dBm
Spurious emission conducted
measurement
(1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
5.10 1-Mbps
GFSK (Bluetooth low energy) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–97
dBm
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, BER = 10
–3
Receiver sensitivity
–96
4
dBm
dBm
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, BER = 10
–3
Receiver saturation
0
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
Co-channel rejection
(1)
Selectivity, ±1 MHz
(1)
Selectivity, ±2 MHz
(1)
Selectivity, ±3 MHz
(1)
Selectivity, ±4 MHz
(1)
Selectivity, ±5 MHz or more
(1)
Selectivity, image frequency
(1)
–350
–750
350
750
kHz
ppm
dB
Difference between incoming data rate and the
internally generated data rate
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10
–3
–6
7 / 3
(2)
34 / 25
(2)
38 / 26
(2)
42 / 29
(2)
32
Wanted signal at –67 dBm, modulated interferer at
±1 MHz, BER = 10
–3
dB
Wanted signal at –67 dBm, modulated interferer at
±2 MHz, BER = 10
–3
dB
Wanted signal at –67 dBm, modulated interferer at
±3 MHz, BER = 10
–3
dB
Wanted signal at –67 dBm, modulated interferer at
±4 MHz, BER = 10
–3
dB
Wanted signal at –67 dBm, modulated interferer at
dB
≥
±5 MHz, BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
image frequency, BER = 10
–3
25
dB
Selectivity, image frequency
±1 MHz
(1)
Wanted signal at –67 dBm, modulated interferer at
±1 MHz from image frequency, BER = 10
–3
3 / 26
(2)
dB
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
Copyright © 2016, Texas Instruments Incorporated
Specifications
19
ZHCSFW7
–
D
ECEMBER 2016
1-Mbps GFSK (Bluetooth low energy) – RX
(continued)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
30 MHz to 2000 MHz
MIN
TYP
–20
–5
MAX UNIT
dBm
(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
dBm
–8
dBm
–8
dBm
Wanted signal at 2402 MHz, –64 dBm. Two
interferers at 2405 and 2408 MHz respectively, at
the given power level
Intermodulation
–34
–71
dBm
dBm
Conducted measurement in a 50-
Ω
single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions,
30 to 1000 MHz
Conducted measurement in a 50-
Ω
single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions,
1 to 12.75 GHz
–62
dBm
RSSI dynamic range
RSSI accuracy
70
±4
dB
dB
(3) Excluding
one exception at F
wanted
/ 2, per Bluetooth Specification.
5.11 1-Mbps
GFSK (Bluetooth low energy) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
Output power, lowest setting
2
dBm
Delivered to a single-ended 50-
Ω
load through a balun
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
–21
–43
–65
–76
–46
dBm
dBm
dBm
dBm
dBm
Spurious emission conducted
measurement
(1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
5.12 2-Mbps
GFSK (Bluetooth 5) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–92
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
4
dBm
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
Co-channel rejection
(1)
Selectivity, ±2 MHz
(1)
–300
500
kHz
ppm
dB
Difference between incoming data rate and the
internally generated data rate
–1000
1000
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10
–3
–7
Wanted signal at –67 dBm, modulated interferer at
±2 MHz, Image frequency is at –2 MHz BER = 10
–3
8 / 4
(2)
dB
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
20
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
2-Mbps GFSK (Bluetooth 5) – RX
(continued)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal at –67 dBm, modulated interferer at
±4 MHz, BER = 10
–3
Selectivity, ±4 MHz
(1)
31 / 26
(2)
dB
Wanted signal at –67 dBm, modulated interferer at
±6 MHz, BER = 10
–3
Selectivity, ±6 MHz
(1)
37 / 38
(2)
37 / 36
(2)
4
dB
dB
dB
Alternate channel rejection,
±7 MHz
(1)
Wanted signal at –67 dBm, modulated interferer at
≥
±7 MHz, BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
image frequency, BER = 10
–3
Selectivity, image frequency
(1)
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at
±2 MHz from image frequency, BER = 10
–3
Selectivity, image frequency
±2 MHz
(1)
–7 / 26
(2)
dB
Out-of-band blocking
(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
–33
–15
–12
–10
dBm
dBm
dBm
dBm
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2405 and 2408 MHz respectively, at the given power
level
Intermodulation
–45
dBm
(3) Excluding
one exception at F
wanted
/ 2, per Bluetooth Specification.
Copyright © 2016, Texas Instruments Incorporated
Specifications
21
ZHCSFW7
–
D
ECEMBER 2016
5.13 2-Mbps
GFSK (Bluetooth 5) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
Output power, lowest setting
2
dBm
Delivered to a single-ended 50-
Ω
load through a balun
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
–21
–43
–65
–76
–46
dBm
dBm
dBm
dBm
dBm
Spurious emission conducted
measurement
(1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
5.14 24-MHz
Crystal Oscillator (XOSC_HF)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
6 pF < C
L
≤
9 pF
MIN
TYP
MAX
60
UNIT
Ω
ESR Equivalent series resistance
(2)
ESR Equivalent series resistance
(2)
20
5 pF < C
L
≤
6 pF
80
Ω
Relates to load capacitance
(C
L
in Farads)
L
M
Motional inductance
(2)
< 1.6 × 10
–24
/ C
L
H
2
C
L
Crystal load capacitance
(2)
Crystal frequency
(2
)
(
3)
Crystal frequency tolerance
(2
)
(
4)
Start-up time
(3
)
(
5)
5
9
pF
MHz
ppm
µs
24
–40
40
150
(1) Probing
or otherwise stopping the XTAL while the DC-DC converter is enabled may cause permanent damage to the device.
(2) The
crystal manufacturer’s specification must satisfy this requirement
(3) Measured
on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V
(4) Includes
initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per
specification.
(5) Kick-started
based on a temperature and aging compensated RCOSC_HF using precharge injection.
5.15 32.768-kHz
Crystal Oscillator (XOSC_LF)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
Crystal frequency
(1)
TEST CONDITIONS
MIN
–500
6
TYP
MAX
UNIT
32.768
kHz
Crystal frequency tolerance, Bluetooth low-
energy applications
(1
)
(
2)
ESR Equivalent series resistance
(1)
C
L
Crystal load capacitance
(1)
500
ppm
30
100
12
k
Ω
pF
(1) The
crystal manufacturer’s specification must satisfy this requirement
(2) Includes
initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per
Bluetooth specification.
22
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
5.16 48-MHz
RC Oscillator (RCOSC_HF)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
48
MAX
UNIT
Frequency
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy
(1)
Start-up time
±1%
±0.25%
5
µs
(1) Accuracy
relative to the calibration source (XOSC_HF).
5.17 32-kHz
RC Oscillator (RCOSC_LF)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
Calibrated frequency
(1)
Temperature coefficient
TEST CONDITIONS
MIN
TYP
32.8
50
MAX
UNIT
kHz
ppm/°C
(1) The
frequency accuracy of the Real Time Clock (RTC) is not directly dependent on the frequency accuracy of the 32-kHz RC Oscillator.
The RTC can be calibrated to an accuracy within ±500 ppm of 32.768 kHz by measuring the frequency error of RCOSC_LF relative to
XOSC_HF and compensating the RTC tick speed. The procedure is explained in
Running Bluetooth® Low Energy on CC2640 Without
5.18 ADC
Characteristics
T
c
= 25°C, V
DDS
= 3.0 V and voltage scaling enabled, unless otherwise noted.
(1)
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX UNIT
0
VDDS
V
12
Bits
ksps
LSB
LSB
LSB
LSB
Sample rate
200
Offset
Internal 4.3-V equivalent reference
(2)
Internal 4.3-V equivalent reference
(2)
2
2.4
>–1
±3
Gain error
DNL
(3)
Differential nonlinearity
INL
(4)
Integral nonlinearity
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
9.6-kHz input tone
9.8
10
ENOB
Effective number of bits
VDDS as reference, 200 ksps, 9.6-kHz input tone
Bits
dB
dB
dB
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
9.6-kHz input tone
11.1
–65
–69
–71
THD
Total harmonic distortion
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
60
63
69
9.6-kHz input tone
Signal-to-noise
and
Distortion ratio
SINAD,
SNDR
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
9.6-kHz input tone
67
72
73
Spurious-free dynamic
range
SFDR
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
(1) Using
IEEE Std 1241™-2010 for terminology and test methods.
(2) Input
signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) No
missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see
Figure 5-21
).
Copyright © 2016, Texas Instruments Incorporated
Specifications
23
ZHCSFW7
–
D
ECEMBER 2016
ADC Characteristics
(continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
clock-
cycles
Conversion time
Serial conversion, time-to-output, 24-MHz clock
50
Current consumption
Current consumption
Internal 4.3-V equivalent reference
(2)
VDDS as reference
0.66
0.75
mA
mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should
be initiated through the TIRTOS API in order to include the
gain/offset compensation factors stored in FCFG1.
Reference voltage
4.3
(2
)
(
5)
V
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TIRTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is
derived from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage
1.48
V
VDDS as reference (Also known as
RELATIVE
) (input
voltage scaling enabled)
Reference voltage
Reference voltage
VDDS
V
V
VDDS as reference (Also known as
RELATIVE
) (input
voltage scaling disabled)
VDDS /
2.82
(5)
200 ksps, voltage scaling enabled. Capacitive input, Input
impedance depends on sampling frequency and sampling
time
Input impedance
>1
M
Ω
5.19 Temperature
Sensor
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Range
4
–40
85
°C
Accuracy
±5
°C
Supply voltage coefficient
(1)
3.2
°C/V
(1) Automatically
compensated when using supplied driver libraries.
5.20 Battery
Monitor
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
50
1.8
3.8
Accuracy
13
mV
5.21 Continuous
Time Comparator
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
VDDS
VDDS
UNIT
V
Input voltage range
External reference voltage
0
V
Internal reference voltage
Offset
DCOUPL as reference
1.27
3
V
mV
mV
µs
Hysteresis
<2
Decision time
Current consumption when enabled
(1)
Step from –10 mV to 10 mV
0.72
8.6
µA
(1) Additionally,
the bias module must be enabled when running in standby mode.
24
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
5.22 Low-Power
Clocked Comparator
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range
0
VDDS
V
Clock frequency
32
1.49–1.51
1.01–1.03
0.78–0.79
1.25–1.28
0.63–0.65
0.42–0.44
0.33–0.34
<2
kHz
Internal reference voltage, VDDS / 2
Internal reference voltage, VDDS / 3
Internal reference voltage, VDDS / 4
Internal reference voltage, DCOUPL / 1
Internal reference voltage, DCOUPL / 2
Internal reference voltage, DCOUPL / 3
Internal reference voltage, DCOUPL / 4
Offset
V
V
V
V
V
V
V
mV
Hysteresis
<5
mV
Decision time
Step from –50 mV to 50 mV
<1
clock-cycle
nA
Current consumption when enabled
362
5.23 Programmable
Current Source
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
Current source programmable output range
Resolution
0.25–20
0.25
µA
Including current source at maximum
programmable output
Current consumption
(1)
23
µA
(1) Additionally,
the bias module must be enabled when running in standby mode.
5.24 Synchronous
Serial Interface (SSI)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
S1
(1)
t
clk_per
(SSIClk period)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
system
clocks
Device operating as SLAVE
12
65024
S2
(1)
t
clk_high
(SSIClk high time)
S3
(1)
t
clk_low
(SSIClk low time)
Device operating as SLAVE
Device operating as SLAVE
0.5
0.5
t
clk_per
t
clk_per
One-way communication to SLAVE –
Device operating as MASTER
system
clocks
S1 (TX only)
(1)
t
clk_per
(SSIClk period)
S1 (TX and RX)
(1)
t
clk_per
(SSIClk period)
4
8
65024
65024
Normal duplex operation –
Device operating as MASTER
system
clocks
S2
(1)
t
clk_high
(SSIClk high time)
S3
(1)
t
clk_low
(SSIClk low time)
Device operating as MASTER
Device operating as MASTER
0.5
0.5
t
clk_per
t
clk_per
Copyright © 2016, Texas Instruments Incorporated
Specifications
25
ZHCSFW7
–
D
ECEMBER 2016
S1
S2
SSIClk
SSIFss
S3
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
26
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
5.25 DC
Characteristics
PARAMETER
TEST CONDITIONS
T
A
= 25°C, V
DDS
= 1.8 V
MIN
1.32
1.32
TYP
MAX
UNIT
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.54
0.26
1.58
0.21
71.7
21.1
V
V
0.32
0.32
V
IOCURR = 1
V
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
µA
µA
GPIO pulldown current
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
IH = 1, transition voltage for input read as 0
→
1
IH = 1, transition voltage for input read as 1
→
0
0.88
1.07
V
V
GPIO low-to-high input transition,
with hysteresis
GPIO high-to-low input transition,
with hysteresis
0.74
0.33
V
V
GPIO input hysteresis
IH = 1, difference between 0
→
1 and 1
→
0 points
T
A
= 25°C, V
DDS
= 3.0 V
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.68
0.33
2.72
0.28
V
V
V
V
IOCURR = 1
T
A
= 25°C, V
DDS
= 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
277
µA
Copyright © 2016, Texas Instruments Incorporated
Specifications
27
ZHCSFW7
–
D
ECEMBER 2016
DC Characteristics
(continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
113
µA
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
IH = 1, transition voltage for input read as 0
→
1
IH = 1, transition voltage for input read as 1
→
0
1.67
1.94
V
V
GPIO low-to-high input transition,
with hysteresis
GPIO high-to-low input transition,
with hysteresis
1.54
0.4
V
V
GPIO input hysteresis
IH = 1, difference between 0
→
1 and 1
→
0 points
T
A
= 25°C
Lowest GPIO input voltage reliably interpreted as a
«High»
VIH
VIL
0.8 VDDS
(1)
VDDS
(1)
Highest GPIO input voltage reliably interpreted as a
«Low»
0.2
(1) Each
GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in
节
8.3
for more details.
5.26 Thermal
Resistance Characteristics
NAME
DESCRIPTION
RSM (°C/W)
(1) (2)
RHB (°C/W)
(1) (2)
RGZ (°C/W)
(1) (2)
YFV (°C/W)
(1) (2)
R
θ
JA
Junction-to-ambient thermal resistance
36.9
30.3
7.6
32.8
24.0
6.8
29.6
15.7
6.2
76.2
0.3
R
θ
JC(top)
Junction-to-case (top) thermal resistance
R
θ
JB
Psi
JT
Psi
JB
Junction-to-board thermal resistance
16.3
1.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
0.3
0.3
7.4
6.8
6.2
16.3
N/A
R
θ
JC(bot)
Junction-to-case (bottom) thermal resistance
2.1
1.9
1.9
(1) °C/W
= degrees Celsius per watt.
(2) These
values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [R
θ
JC
] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2,
Integrated Circuits Thermal Test Method Environmental Conditions – Natural Convection (Still Air)
.
JESD51-3,
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
.
JESD51-7,
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
.
JESD51-9,
Test Boards for Area Array Surface Mount Package Thermal Measurements
.
For RSM, RHB, and RGZ, power dissipation of 2 W and an ambient temperature of 70ºC is assumed. For YFV, power dissipation of 1.3
W and ambient temperature of 25ºC is assumed.
28
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
5.27 Timing
Requirements
MIN
0
NOM
MAX
100
20
UNIT
mV/µs
mV/µs
mV/µs
Rising supply-voltage slew rate
Falling supply-voltage slew rate
Falling supply-voltage slew rate, with low-power flash settings
(1)
0
3
No limitation for negative
temperature gradient, or
outside standby mode
Positive temperature gradient in standby
(2)
5
°C/s
µs
CONTROL INPUT AC CHARACTERISTICS
(3)
RESET_N low duration
1
(1) For
smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see
Figure 7-1
) must be used to ensure compliance with this slew rate.
(2) Applications
using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
(3) T
A
= –40°C to +85°C, V
DDS
= 1.7 V to 3.8 V, unless otherwise noted.
5.28 Switching
Characteristics
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
WAKEUP AND TIMING
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Idle
→
Active
14
151
µs
µs
µs
Standby
→
Active
Shutdown
→
Active
1015
Copyright © 2016, Texas Instruments Incorporated
Specifications
29
ZHCSFW7
–
D
ECEMBER 2016
5.29 Typical
Characteristics
-95
-96
-94
-95
-96
-97
-98
-99
-97
-98
-99
-100
Sensitivity 4XS
Sensitivity 5XD
BLE 5XD Sensitivity
BLE 4XS Sensitivity
-101
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
1.8
2.3
2.8
3.3
3.8
Temperature (
è
C)
VDDS (V)
D004
Figure 5-4. BLE Sensitivity vs Temperature
Figure 5-5. BLE Sensitivity vs Supply Voltage (VDDS)
6
-95
-95.5
-96
Sensitivity 5XD
Sensitivity 4XS
5
4
-96.5
-97
4XS 2-dBm Setting
5XD 5-dBm Setting
3
2
1
0
-97.5
-98
-98.5
-99
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (
è
C)
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
D020
Figure 5-6. BLE Sensitivity vs Channel Frequency
Figure 5-7. TX Output Power vs Temperature
8
6
5-dBm setting (5XD)
0-dBm setting (4XS)
7
6
5
4
3
2
1
0
5
4
3
2
1
5XD 5
–
dBm Setting
4XS 2
–
dBm Setting
0
-1
2400 2410 2420 2430 2440 2450 2460 2470 2480
1.8
2.3
2.8
VDDS (V)
3.3
3.8
Frequency (MHz)
D021
D003
Figure 5-9. TX Output Power
vs Channel Frequency
Figure 5-8. TX Output Power vs Supply Voltage (VDDS)
30
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
Typical Characteristics
(continued)
16
10.5
10
9.5
9
4XS 0-dBm Setting
4XS 2-dBm Setting
5XD 5-dBm Setting
4XS
5XD
15
14
13
12
11
10
9
8.5
8
7.5
7
6.5
6
8
7
5.5
5
6
5
4.5
4
4
1.8
2
2.2 2.4 2.6 2.8
VDDS (V)
3
3.2 3.4 3.6 3.8
1.8
2.05
2.3
2.55
2.8
3.05
3.3
3.55
3.8
Voltage (V)
D015
D016
Figure 5-10. TX Current Consumption
vs Supply Voltage (VDDS)
Figure 5-11. RX Mode Current vs Supply Voltage (VDDS)
7
12
10
8
5XD RX Current
4XS RX Current
6.8
6.6
6.4
6.2
6
6
4
5.8
5.6
2
5XD 5
–
dBm Setting
4XS 2
–
dBm Setting
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (
è
C)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
D001
Temperature (
è
C)
D002
Figure 5-12. RX Mode Current Consumption vs Temperature
Figure 5-13. TX Mode Current Consumption vs Temperature
5
3.1
Active Mode Current
Active Mode Current
4.5
4
3.05
3
3.5
3
2.95
2.9
2.5
2
1.8
2.85
2.3
2.8
3.3
3.8
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
VDDS (V)
D007
Temperature (
è
C)
D006
Figure 5-15. Active Mode (MCU Running, No Peripherals) Current
Consumption vs Supply Voltage (VDDS)
Figure 5-14. Active Mode (MCU Running, No Peripherals)
Current Consumption vs Temperature
Copyright © 2016, Texas Instruments Incorporated
Specifications
31
ZHCSFW7
–
D
ECEMBER 2016
Typical Characteristics
(continued)
1006.4
1006.2
1006
11.4
Fs= 200 kHz, No Averaging
Fs= 200 kHz, 32 samples averaging
11.2
11
10.8
10.6
10.4
10.2
10
1005.8
1005.6
1005.4
1005.2
1005
9.8
9.6
9.4
1004.8
20
0
3
00 500
1000 2000
5000 10000
20000
100000
1.8
2.3
2.8
3.3
3.8
Input Frequency (Hz)
VDDS (V)
D009
D012
Figure 5-16. SoC ADC Effective Number of Bits vs Input
Frequency (Internal Reference, Scaling enabled)
Figure 5-17. SoC ADC Output vs Supply Voltage (Fixed Input,
Internal Reference)
10.5
1007.5
1007
ENOB Internal Reference (No Averaging)
ENOB Internal Reference (32 Samples Averaging)
10.4
10.3
10.2
10.1
10
1006.5
1006
9.9
1005.5
1005
9.8
9.7
1004.5
9.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
1k
10k
100k 200k
Temperature (
è
C)
Sampling Frequency (Hz)
D013
D009A
Figure 5-18. SoC ADC Output vs Temperature (Fixed Input,
Internal Reference)
Figure 5-19. SoC ADC ENOB vs Sampling Frequency
(Scaling enabled, input frequency = FS / 10)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
Temperature (
è
C)
D021
Figure 5-20. Standby Mode Supply Current vs Temperature
32
Specifications
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
Typical Characteristics
(continued)
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
D010
ADC Code
Figure 5-21. SoC ADC DNL vs ADC Code (Internal Reference)
3
2
1
0
-1
-2
-3
-4
0
200 400 600 800
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200
ADC Code
D011
Figure 5-22. SoC ADC INL vs ADC Code (Internal Reference)
Copyright © 2016, Texas Instruments Incorporated
Specifications
33
ZHCSFW7
–
D
ECEMBER 2016
6 Detailed
Description
6.1 Overview
6.2 Functional
Block Diagram
SimpleLink CC26xx Wireless MCU
RF Core
cJTAG
Main CPU:
ROM
ADC
ADC
ARM
Cortex-M3
128-KB
Flash
Digital PLL
DSP modem
8-KB
cache
Up to 48 MHz
61 µA/MHz
4-KB
SRAM
ARM
Cortex-M0
20-KB
SRAM
ROM
General Peripherals / Modules
Sensor Controller
2
4× 32-bit Timers
I C
Sensor Controller Engine
UART
I2S
2× SSI (SPI, µW, TI)
Watchdog Timer
12-bit ADC, 200 ks/s
2× Comparator
10 / 14 / 15 / 31 GPIOs
AES
TRNG
2
SPI-I C
Digital Sensor IF
Temp. / Batt. Monitor
Constant Current Source
32 ch. µDMA
RTC
Time-to-digital Converter
2-KB SRAM
DC-DC Converter
Copyright © 2016, Texas Instruments Incorporated
34
Detailed Description
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
6.3 Main
CPU
The SimpleLink CC2640R2F Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs
the application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
CM3 features include the following:
•
•
•
32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
Outstanding processing performance combined with fast interrupt handling
ARM Thumb
®
-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
–
–
Single-cycle multiply instruction and hardware divide
Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
–
Unaligned data access, enabling data to be efficiently packed into memory
•
•
•
•
•
•
•
•
•
•
•
•
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system, and memories
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Enhanced system debug with extensive breakpoint and trace capabilities
Serial wire trace reduces the number of pins required for debugging and tracing
Migration from the ARM7™ processor family for better performance and power efficiency
Optimized for single-cycle flash memory use
Ultralow-power consumption with integrated sleep modes
1.25 DMIPS per MHz
6.4 RF
Core
The RF Core contains an ARM Cortex-M0 processor that interfaces the analog RF and base-band
circuitries, handles data to and from the system side, and assembles the information bits in a given packet
structure. The RF core offers a high level, command-based API to the main CPU.
The RF core is capable of autonomously handling the time-critical aspects of the radio protocols
(Bluetooth low energy) thus offloading the main CPU and leaving more resources for the user application.
The RF core has a dedicated 4-KB SRAM block and runs initially from separate ROM memory. The ARM
Cortex-M0 processor is not programmable by customers.
Copyright © 2016, Texas Instruments Incorporated
Detailed Description
35
ZHCSFW7
–
D
ECEMBER 2016
6.5 Sensor
Controller
The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals
in this domain may be controlled by the Sensor Controller Engine, which is a proprietary power-optimized
CPU. This CPU can read and monitor sensors or perform other tasks autonomously, thereby significantly
reducing power consumption and offloading the main CM3 CPU. The GPIOs that can be connected to the
The Sensor Controller is set up using a PC-based configuration tool, called Sensor Controller Studio, and
potential use cases may be (but are not limited to):
•
•
•
•
•
•
•
•
•
Analog sensors using integrated ADC
Digital sensors using GPIOs, bit-banged I
2
C, and SPI
UART communication for sensor reading or debugging
Capacitive sensing
Waveform generation
Pulse counting
Keyboard scan
Quadrature decoder for polling rotation sensors
Oscillator calibration
NOTE
Texas Instruments provides application examples for some of these use cases, but not for all
of them.
The peripherals in the Sensor Controller include the following:
•
The low-power clocked comparator can be used to wake the device from any state in which the
comparator is active. A configurable internal reference can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
•
Capacitive sensing functionality is implemented through the use of a constant current source, a time-
to-digital converter, and a comparator. The continuous time comparator in this block can also be used
as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller will take
care of baseline tracking, hysteresis, filtering and other related functions.
•
The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC
can be triggered by many different sources, including timers, I/O pins, software, the analog
comparator, and the RTC.
•
•
The Sensor Controller also includes a SPI–I
2
C digital interface.
The analog modules can be connected to up to eight different GPIOs.
The peripherals in the Sensor Controller can also be controlled from the main application processor.
36
Detailed Description
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
Table 6-1. GPIOs Connected to the Sensor Controller
(1)
ANALOG
CAPABLE
7 × 7 RGZ
DIO NUMBER
5 × 5 RHB
DIO NUMBER
2.7 × 2.7 YFV
DIO NUMBER
4 × 4 RSM
DIO NUMBER
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
30
29
28
27
26
25
24
23
7
14
13
12
11
9
13
12
11
9
9
8
7
6
5
2
1
0
10
8
10
8
7
7
4
4
6
3
3
5
2
2
4
1
1
3
0
0
2
1
0
(1) Depending
on the package size, up to 16 pins can be connected to the Sensor Controller. Up to 8 of
these pins can be connected to analog modules.
6.6 Memory
The flash memory provides nonvolatile storage for code and data. The flash memory is in-system
programmable.
The SRAM (static RAM) can be used for both storage of data and execution of code and is split into two
4-KB blocks and two 6-KB blocks. Retention of the RAM contents in standby mode can be enabled or
disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled,
the 8-KB cache can be used as a general-purpose RAM.
The ROM provides preprogrammed embedded TI RTOS kernel, Driverlib and lower layer protocol stack
software (Bluetooth low energy Controller). It also contains a bootloader that can be used to reprogram
the device using SPI or UART. For CC2640R2Fxxx devices, the ROM contains Bluetooth 4.2 low energy
host- and controller software libraries, leaving more of the flash memory available for the customer
application.
6.7 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface.
Copyright © 2016, Texas Instruments Incorporated
Detailed Description
37
ZHCSFW7
–
D
ECEMBER 2016
6.8 Power
Management
To minimize power consumption, the CC2640R2F device supports a number of power modes and power
Table 6-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Active
Off
Off
Off
Off
Flash
On
Available
On
Off
SRAM
On
On
Off
Off
Radio
Available
Available
On
Off
Off
Off
Supply System
Current
Wake-up Time to CPU Active
(1)
Register Retention
SRAM Retention
On
Duty Cycled
1 µA
Off
Off
1.45 mA + 31 µA/MHz
550 µA
14 µs
Full
0.15 µA
1015 µs
No
0.1 µA
1015 µs
No
–
151 µs
Partial
Full
Full
Full
Full
No
No
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
High-Speed Clock
Low-Speed Clock
Off
Off
Off
Off
Off
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
Available
Available
Active
Available
Available
Available
Available
Available
Active
Off
Off
Off
Off
Off
Sensor Controller
Available
Available
Available
Available
Duty Cycled
Active
Wake up on RTC
Off
Off
Wake up on Pin Edge
Wake up on Reset Pin
Brown Out Detector (BOD)
Power On Reset (POR)
Available
Available
Off
Off
Available
N/A
Active
Active
Active
N/A
(1) Not
including RTOS overhead
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event will bring the processor back into active mode.
In standby mode, only the always-on domain (AON) is active. An external wake-up event, RTC event, or
sensor-controller event is required to bring the device back to active mode. MCU peripherals with retention
do not need to be reconfigured when waking up again, and the CPU continues execution from where it
went into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is turned off entirely, including the AON domain and the Sensor Controller.
The I/Os are latched with the value they had before entering shutdown mode. A change of state on any
I/O pin defined as a
wake-up from Shutdown pin
wakes up the device and functions as a reset trigger. The
CPU can differentiate between a reset in this way, a reset-by-reset pin, or a power-on-reset by reading the
reset status register. The only state retained in this mode is the latched I/O state and the Flash memory
contents.
The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independently of the main CPU, which means that the main CPU does not have to wake up, for
example, to execute an ADC sample or poll a digital sensor over SPI. The main CPU saves both current
and wake-up time that would otherwise be wasted. The Sensor Controller Studio enables the user to
configure the sensor controller and choose which peripherals are controlled and which conditions wake up
the main CPU.
38
Detailed Description
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
6.9 Clock
Systems
The CC2640R2F supports two external and two internal clock sources.
A 24-MHz crystal is required as the frequency reference for the radio. This signal is doubled internally to
create a 48-MHz clock.
The 32-kHz crystal is optional.
Bluetooth
low energy requires a slow-speed clock with better than
±500 ppm accuracy if the device is to enter any sleep mode while maintaining a connection. The internal
32-kHz RC oscillator can in some use cases be compensated to meet the requirements. The low-speed
crystal oscillator is designed for use with a 32-kHz watch-type crystal.
The internal high-speed oscillator (48-MHz) can be used as a clock source for the CPU subsystem.
The internal low-speed oscillator (32.768-kHz) can be used as a reference if the low-power crystal
oscillator is not used.
The 32-kHz clock source can be used as external clocking reference through GPIO.
6.10 General
Peripherals and Modules
The I/O controller controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and Texas
Instruments synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.
The UART implements a universal asynchronous receiver/transmitter function. It supports flexible baud-
rate generation up to a maximum of 3 Mbps .
Timer 0 is a general-purpose timer module (GPTM), which provides two 16-bit timers. The GPTM can be
configured to operate as a single 32-bit timer, dual 16-bit timers or as a PWM module.
Timer 1, Timer 2, and Timer 3 are also GPTMs. Each of these timers is functionally equivalent to Timer 0.
In addition to these four timers, the RF core has its own timer to handle timing for RF protocols; the RF
timer can be synchronized to the RTC.
The I
2
C interface is used to communicate with devices compatible with the I
2
C standard. The I
2
C interface
is capable of 100-kHz and 400-kHz operation, and can serve as both I
2
C master and I
2
C slave.
The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys,
initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring
oscillators that create unpredictable output to feed a complex nonlinear combinatorial circuit.
The watchdog timer is used to regain control if the system fails due to a software error after an external
device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
Copyright © 2016, Texas Instruments Incorporated
Detailed Description
39
ZHCSFW7
–
D
ECEMBER 2016
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to
offload data transfer tasks from the CM3 CPU, allowing for more efficient use of the processor and the
available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The
µDMA controller has dedicated channels for each supported on-chip module and can be programmed to
automatically perform transfers between peripherals and memory as the peripheral is ready to transfer
more data. Some features of the µDMA controller include the following (this is not an exhaustive list):
•
•
Highly flexible and configurable channel operation of up to 32 channels
Transfer modes:
–
–
–
–
Memory-to-memory
Memory-to-peripheral
Peripheral-to-memory
Peripheral-to-peripheral
•
Data sizes of 8, 16, and 32 bits
The AON domain contains circuitry that is always enabled, except for in Shutdown (where the digital
supply is off). This circuitry includes the following:
•
The RTC can be used to wake the device from any state where it is active. The RTC contains three
compare and one capture registers. With software support, the RTC can be used for clock and
calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be
compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used
instead of a crystal.
•
The battery monitor and temperature sensor are accessible by software and give a battery status
indication as well as a coarse temperature measure.
6.11 Voltage
Supply Domains
The CC2640R2F device can interface to two or three different voltage domains depending on the package
type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output
pin is set with respect to the corresponding supply pin (VDDS, VDDS2 or VDDS3).
Table 6-3
lists the pin-
to-VDDS mapping.
Table 6-3. Pin Function to VDDS Mapping Table
Package
VQFN 4 × 4
(RSM)
VQFN 7 × 7 (RGZ)
VQFN 5 × 5 (RHB)
DSBGA (YFV)
DIO 23–30
Reset_N
DIO 7–14
Reset_N
DIO 5–9
Reset_N
DIO 7–13
Reset_N
VDDS
(1)
VDDS2
VDDS3
DIO 0–6
JTAG
DIO 0–4
JTAG
DIO 0–6
JTAG
DIO 0–11
DIO 12–22
JTAG
N/A
N/A
N/A
(1) VDDS_DCDC
must be connected to VDDS on the PCB.
6.12 System
Architecture
Depending on the product configuration, CC26xx can function either as a Wireless Network Processor
(WNP—an IC running the wireless protocol stack, with the application running on a separate MCU), or as
a System-on-Chip (SoC), with the application and protocol stack running on the ARM CM3 core inside the
device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second
case, the application must be written according to the application framework supplied with the wireless
protocol stack.
40
Detailed Description
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
7 Application,
Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application
Information
Very few external components are required for the operation of the CC2640R2F device. This section
provides some general information about the various configuration options when using the CC2640R2F in
an application, and then shows two examples of application circuits with schematics and layout. This is
only a small selection of the many application circuit examples available as complete reference designs
Figure 7-1
shows the various RF front-end configuration options. The RF front end can be used in
differential- or single-ended configurations with the options of having internal or external biasing. These
options allow for various trade-offs between cost, board space, and RF performance. Differential operation
with external bias gives the best performance while single-ended operation with internal bias gives the
least amount of external components and the lowest power consumption. Reference designs exist for
each of these options.
Red = Not necessary if internal bias is used
6.8 pF
!ntenna
(50 hꢀm)
Pin 3 (RXTX)
2.4 nH
1 pF
To VDDR
pins
Pin 2 (RF N)
Pin 1 (RF P)
2 nH
1 pF
2 nH
6.2
œ
6.8 nH
2.4
œ
2.7 nH
10µF
12 pC
Optional
inductor.
Only
needed for
DCDC
Differential
operation
1 pF
10µH
operation
!ntenna
(50 hꢀm)
Red = Not necessary if internal bias is used
CC26xx
Pin 2 (RF N)
DCDC_SW
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
15 nH
(GND exposed die
attached pad
)
Pin 1 (RF P)
2 nH
VDDS_DCDC
input
decoupling
10µF
œ
22µF
Single ended
operation
12 pC
1.2 pF
1.2 pF
!ntenna
(50 hꢀm)
Red = Not necessary if internal bias is used
Pin 3 (RXTX)
15 nH
24MHz
XTAL
2 nH
Pin 2 (RF N)
(Load caps
on chip)
12 pC
1.2 pF
1.2 pF
Single ended
operation with 2
antennas
!ntenna
(50 hꢀm)
15 nH
2 nH
Pin 1 (RF P)
12 pC
1.2 pF
1.2 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. CC2640R2F Application Circuit
Copyright © 2016, Texas Instruments Incorporated
Application, Implementation, and Layout
41
ZHCSFW7
–
D
ECEMBER 2016
Figure 7-2
shows the various supply voltage configuration options. Not all power supply decoupling
capacitors or digital I/Os are shown. Exact pin positions will vary between the different package options.
For a detailed overview of power supply decoupling and wiring, see the TI reference designs and the
Internal DC-DC Regulator
Internal LDO Regulator
External Regulator
To All VDDR Pins
To All VDDR Pins
1.7 V
œ
1.95 V to All VDDR- and VDDS Pins Except VDDS_DCDC
9xt.
wegulator
10
ꢀ
F
10
ꢀ
F
2.2
ꢀ
F
VDDS
VDDS
VDDS
VDDS
10
ꢀ
H
CC26xx
CC26xx
CC26xx
DCDC_SW Pin
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
NC
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
DCDC_SW Pin
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
(GND Exposed Die
Attached Pad)
(GND Exposed Die
Attached Pad)
(GND Exposed Die
Attached Pad)
VDDS_DCDC Pin
VDDS_DCDC Pin
VDDS_DCDC Pin
VDDS_DCDC
Input Decoupling
10
ꢀ
F
œ
22
ꢀ
F
VDDS_DCDC
Input Decoupling
10
ꢀ
F
œ
22
ꢀ
F
24-MHz XTAL
(Load Caps
on Chip)
24-MHz XTAL
(Load Caps on Chip)
24-MHz XTAL
(Load Caps on Chip)
1.8 V
œ
3.8 V
1.8 V
œ
3.8 V
to All VDDS Pins
Supply Voltage
To All VDDS Pins
Copyright © 2016, Texas Instruments Incorporated
Figure 7-2. Supply Voltage Configurations
42
Application, Implementation, and Layout
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
7.2 5
× 5 External Differential (5XD) Application Circuit
VDD_EB
VDDS
VDDS Decoupling Capacitors
VDDR
VDDR Decoupling Capacitors
BLM18HE152SN1
1
Pin 18
C6
10 µF
Pin 28
C4
100 nF
Pin 11
C3
100 nF
2
L1
Pin 32
Pin 29
C9
100 nF
DCDC_SW
2
1
FL1
C7
C2
DNM
10 uH
C8
10 µF
C10
100 nF
C16
100 nF
DNM
Place L1 and
C8 close to pin 17
VDDS
VDDR
U1
DIO_0
DIO_1
6
7
28
11
18
29
32
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
DIO_10
DIO_
1
1
DIO_12
DIO_13
DIO_14
VDDS
VDDS2
DIO_2
DIO_3
DIO_4
8
C31
6.8 pF
VDDS_DCDC
VDDR
VDDR
9
R
X
_
TX
RFN
10
15
16
20
21
22
23
24
25
26
27
50-Ω
DIO_5/JTAG_TDO
DIO_6/JTAG_TDI
DIO_7
1
DCDC_SW
17
Antenna
DCDC_SW
L21
2.4 nH
DIO_8
DIO_9
VDDS
C21
3
2
1
R
X
_
TX
RF_N
RF_P
2
DIO_10
DIO_
1
1
DIO_12
DIO_13
DIO_14
1
2
R1
1 pF
L11
L12
L13
1
2
1
2
L10
6.2 nH
100 k
31
30
X
2
4M_P
X
2
4M_N
X
2
4M_P
X
2
4M_N
nRESET
C122 nH
DNM
C13 2
nH
1 pF
RFP
1
2
19
14
13
RESET_N
J
T
AG_TCKC
J
T
AG_TMSC
5
4
J
T
AG_TCK
J
T
AG_TMS
X
3
2K_Q2
X
3
2K_Q1
2.7 nH
C
1
1
C20
100 nF
12
33
1 pF
DCOUPL
C19
1 µF
VSS
CC2650F128RHB
Y2
24 MHz
Y1
32.768 kHz
1
3
C17
C18 C22
12 pF
DNM
C23
2
4
12 pF
DNM
Copyright © 2016, Texas Instruments Incorporated
Figure 7-3.
5 × 5 External Differential (5XD) Application Circuit
Copyright © 2016, Texas Instruments Incorporated
Application, Implementation, and Layout
43
ZHCSFW7
–
D
ECEMBER 2016
7.2.1 Layout
Figure 7-4. 5 × 5 External Differential (5XD) Layout
44
Application, Implementation, and Layout
Copyright © 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
7.3 4
× 4 External Single-ended (4XS) Application Circuit
VDD_EB
VDDR
VDDS
VDDS Decoupling Capacitors
VDDR Decoupling Capacitors
FL1
L1
Pin 11
Pin 27
Pin 19
Pin 28
Pin 32
DCDC_SW
2
1
1
2
BLM18HE152SN1
10 µH
C2
C5
10 µF
C8
C10
C16
C6
C3
100 nF
C4
C9
DNM
100 nF
10 µF
100 nF
DNM
100 nF
100 nF
Place L1 and
C8 close to pin 18
VDDS
VDDR
U1
DIO_0
27
8
9
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
VDDS
RF_N used for RX biasing.
DIO_1
DIO_2
11
19
28
32
VDDS2
VDDS_DCDC
VDDR
10
15
16
22
23
24
25
26
L21 may be removed at the
cost of 1 dB degraded
sensitivity
DIO_3/JTAG_TDO
DIO_4/JTAG_TDI
DIO_5
50-Ω
Antenna
VDDS
VDDR
DCDC_SW
DIO_6
18
DCDC_SW
DIO_7
R1
100 k
DIO_8
L21
1 2
4
DIO_9
R
X
/
T
X
RF_N
RF_P
C14
nRESET
2
1
L12
15 nH
nRESET
RF_P
1
2
21
14
13
RESET_N
J
T
AG_TCK
J
T
AG_TMS
J
T
AG_TCKC
J
T
AG_TMSC
2 nH
C12
C13
12 pF
X
2
4M_P
X
2
4M_N
31
30
C20
X
2
4M_P
X
2
4M_N
12
1.2 pF
1.2 pF
100 nF
DCOUPL
6
5
3
7
X
3
2K_Q2
X
3
2K_Q1
VSS
VSS
VSS
VSS
VSS
EGP
C19
1 µF
17
20
29
33
CC26
X
X
_
4
X
4
Y2
24 MHz
Y1
32.768 kHz
1
3
C22
DNM
C23
DNM
C17
12 pF
C18
2
4
12 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-5. 4 × 4 External Single-ended (4XS) Application Circuit
Copyright © 2016, Texas Instruments Incorporated
Application, Implementation, and Layout
45
ZHCSFW7
–
D
ECEMBER 2016
7.3.1 Layout
Figure 7-6. 4 × 4 External Single-ended (4XS) Layout
46
Application, Implementation, and Layout
版权
© 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
8
器件和文档支持
8.1
器件命名规则
为了标明产品开发周期的各个产品阶段，
TI
为所有预生产部件号或日期代码标记分配了前缀。每个器件都具
有以下三个前缀
/
标识中的一个：
X
、
P
或无（无前缀）（例如
CC2640R2F
正在批量生产，因此未分配前缀
/
标识）。
器件开发进化流程：
X
试验器件不一定代表最终器件的电气规范标准并且不可使用生产组装流程。
原型器件不一定是最终芯片模型并且不一定符合最终电气标准规范。
完全合格的芯片模型的生产版本。
P
无
生产器件已进行完全特性化，并且器件的质量和可靠性已经完全论证。
TI
的标准保修证书适用。
预测显示原型器件（
X
或者
P
）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未定义，
德州仪器
(TI)
建议不要将这些器件用于任何生产系统。只有合格的生产器件将被使用。
TI
器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀表示封装类型（例如，）。
要获得
CC2640R2F
器件（
RSM
、
RHB
、
RGZ
或
YFV
封装类型）的订购部件号，请参见本文档的封装选
CC26 xx
yyy
zzz
(R/T)
PREFIX
X = Experimental device
Blank = Qualified device
R = Large Reel
T = Small Reel
DEVICE FAMILY
SimpleLink™ Multistandard
Wireless MCU
DEVICE
PACKAGE DESIGNATOR
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RHB = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
RSM = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
YFV =
34-pin DSBGA (Die-Size Ball Grid Array)
40 = Bluetooth
ROM version
F128 = ROM version 1
R2F = ROM version 2
图
8-1.
器件命名规则
版权
© 2016, Texas Instruments Incorporated
器件和文档支持
47
ZHCSFW7
–
D
ECEMBER 2016
8.2
工具与软件
德州仪器
(TI)
提供大量的开发工具，其中包括评估处理器性能、生成代码、开发算法工具、以及完全集成和
调试软件及硬件模块的工具。
以下产品支持开发
CC2640R2F
器件 应用的开发提供支持：
软件工具：
SmartRF Studio
是一款
PC
应用程序，可帮助无线电系统设计人员评估早期设计过程的
RF-IC
。
•
•
•
•
测试无线数据包收发功能，连续波收发功能
将相关数据写入支持的评估板或调试器，评估定制板上的
RF
性能
可以不搭配任何硬件使用，但此时只能生成、编辑并导出无线配置设置
可与德州仪器
(TI) CCxxxx
系列
RF-IC
的多款开发套件搭配使用
Sensor Controller Studio
为
CC26xx
传感器控制器提供开发环境。此传感器控制器是
CC26xx
系列中的一
款专用功率优化型
CPU
，可独立于系统
CPU
状态自主执行简单的后台任务。
•
•
•
允许使用
C
语言这类编程语言实现传感器控制器任务算法
输出传感器控制器接口驱动程序，其中整合了生成的传感器控制器机械代码和相关定义
通过使用集成传感器控制器任务测试和调试功能实现快速开发这有助于实现有效的传感器数据和算法验
证可视化。
IDE
和编译器：
Code Composer Studio
：
•
•
•
•
带有项目管理工具和编辑器的集成开发环境
Code Composer Studio (CCS) 7.0
及更高版本内置对
CC26xx
系列器件的支持功能
优先支持的
XDS
调试器：
XDS100v3
、
XDS110
和
XDS200
与
TI-RTOS
高度集成，支持
TI-RTOS
对象视图
IAR ARM Embedded Workbench
•
•
•
•
•
带有项目管理工具和编辑器的集成开发环境
IAR EWARM 7.80.1
及更高版本内置对
CC26xx
系列器件的支持功能
广泛的调试器支持，支持
XDS100v3
、
XDS200
、
IAR I-Jet
和
Segger J-Link
带有项目管理工具和编辑器的集成开发环境
价和购买信息，请联系最近的
TI
销售办事处或授权分销商。
48
器件和文档支持
版权
© 2016, Texas Instruments Incorporated
ZHCSFW7
–
D
ECEMBER 2016
8.3
文档支持
(Alert me)
注册后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含
的修订历史记录。
下面列出了描述
CC2640R2F
器件、相关外设和其他技术材料的最新文档。
技术参考手册
空白
8.4
德州仪器
(TI)
低功耗射频网站
德州仪器
(TI)
的低功耗射频网站提供所有最新产品、应用和设计笔记、
FAQ
部分、新闻资讯以及活动更
8.5
低功耗射频电子新闻简报
通过低功耗射频电子新闻简报，您能够了解到最新的产品、新闻稿、开发者相关新闻以及关于德州仪器
(TI)
低功耗射频产品其它新闻和活动。低功耗射频电子新闻简报文章包含可获取更多在线信息的链接。
8.6
社区资源
下列链接提供到
TI
社区资源的连接。 链接的内容由各个分销商
“
按照原样
”
提供。 这些内容并不构成
TI
技术
explore ideas and help solve problems with fellow engineers.
和增长。
•
•
•
论坛、视频和博客
射频设计帮助
E2E
交流互动
请点击此处
加入我们。
发。此网络中包括推荐的公司、射频顾问和独立设计工作室，他们可提供一系列硬件模块产品
和设计服务，其中包括：
•
•
•
射频电路、低功耗射频和
ZigBee
设计服务
低功耗射频和
ZigBee
模块解决方案以及开发工具
射频认证服务和射频电路制造
如果需要有关模块、工程服务或开发工具的帮助：
版权
© 2016, Texas Instruments Incorporated
器件和文档支持
49
ZHCSFW7
–
D
ECEMBER 2016
8.7
其他信息
德州仪器
(TI)
为汽车、工业和消费类应用中所使用的专有应用和标准无线 应用 提供各种经济实用的低功耗
射频 解决方案。其中包括适用于
1GHz
以下频段和
2.4GHz
频段的射频收发器、射频发送器、射频前端和
片上系统以及各种软件解决方案。
此外，德州仪器
(TI)
还提供广泛的相关支持，例如开发工具、技术文档、参考设计、应用专业技术、客户支
持、第三方服务以及大学计划。
低功耗射频
E2E
在线社区设有技术支持论坛并提供视频和博客，您有机会在此与全球同领域工程师交流互
动。
凭借丰富的供选产品解决方案、可实现的最终应用以及广泛的技术支持，德州仪器
(TI)
能够为您提供最全面
的低功耗射频产品组合。
8.8
商标
SimpleLink, SmartRF, Code Composer Studio, LaunchPad, E2E are trademarks of Texas Instruments.
ARM7 is a trademark of ARM Limited (or its subsidiaries).
ARM, Cortex, ARM Thumb are registered trademarks of ARM Limited (or its subsidiaries).
蓝牙
is a registered trademark of Bluetooth SIG, Inc.
CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium.
IAR Embedded Workbench is a registered trademark of IAR Systems AB.
IEEE Std 1241 is a trademark of Institute of Electrical and Electronics Engineers, Incorporated.
All other trademarks are the property of their respective owners.
8.9
静电放电警告
ESD
可能会损坏该集成电路。德州仪器
(TI)
建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序
,
可
能会损坏集成电路。
ESD
的损坏小至导致微小的性能降级
,
大至整个器件故障。 精密的集成电路可能更容易受到损坏
,
这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.10
出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
8.11 Glossary
9
机械、封装和可订购信息
9.1
封装信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知
且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
50
机械、封装和可订购信息
版权
© 2016, Texas Instruments Incorporated
重要声明
德州仪器
(TI)
公司有权按照最新发布的
JESD46
对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的
JESD48
提
供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。
他条款可能适用于其他类型
TI
产品及服务的使用或销售。
复制
TI
数据表上
TI
信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。
TI
对该等复制文
件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售
TI
产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去
相关
TI
产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。
TI
对此类虚假陈述不承担任何责任。
买方和在系统中整合
TI
产品的其他开发人员（总称
“
设计人员
”
）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且
应全权 负责并确保 应用的安全性， 及设计人员的 应用 （包括应用中使用的所有
TI
产品）应符合所有适用的法律法规及其他相关要求。设计
人员就自己设计的 应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够
(1)
预见故障的危险后果，
(2)
监视故障及其后
果，以及
(3)
降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含
TI
产品的任何 应用前， 将彻底测试该等 应用
和 该等应用中所用
TI
产品的 功能。
TI
提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称
“TI
资
源
”
），旨在帮助设计人员开发整合了
TI
产品的 应用， 如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、
访问或使用任何特定的
TI
资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定
TI
资源。
TI
所提供的
TI
资源，并未扩大或以其他方式修改
TI
对
TI
产品的公开适用的质保及质保免责声明；也未导致
TI
承担任何额外的义务或责任。
TI
有权对其
TI
资源进行纠正、增强、改进和其他修改。除特定
TI
资源的公开文档中明确列出的测试外，
TI
未进行任何其他测试。
设计人员只有在开发包含该等
TI
资源所列
TI
产品的 应用时， 才被授权使用、复制和修改任何相关单项
TI
资源。但并未依据禁止反言原则或
其他法理授予您任何
TI
知识产权的任何其他明示或默示的许可，也未授予您
TI
或第三方的任何技术或知识产权的许可，该等产权包括但不限
于任何专利权、版权、屏蔽作品权或与使用
TI
产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务
的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用
TI
资源可能需要您向第三方获得对该等第三方专利或其他知识产权
的许可。
TI
资源系
“
按原样
”
提供。
TI
兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡
发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。
TI
不负责任何申索，包括但不限于因组合产品所致或
与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于
TI
资源或其他地方。对因
TI
资源或其使用引起或与之有关
的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管
TI
是否获悉可能会产生上述损害赔
偿，
TI
概不负责。
除
TI
已明确指出特定产品已达到特定行业标准（例如
ISO/TS 16949
和
ISO 26262
）的要求外，
TI
不对未达到任何该等行业标准要求而承担
任何责任。
如果
TI
明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的
应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将
任何
TI
产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是
指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设
备）。此类设备包括但不限于，美国食品药品监督管理局认定为
III
类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备的
所有医疗设备。
TI
可能明确指定某些产品具备某些特定资格（例如
Q100
、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的
应用选择适合的 产品， 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。
设计人员同意向
TI
及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和
/
或责任。
IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道
1568
号中建大厦
32
楼，邮政编码：
200122
Copyright © 2017
德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
14-Dec-2017
PACKAGING INFORMATION
Orderable Device
CC2640R2FRGZR
CC2640R2FRGZT
CC2640R2FRHBR
CC2640R2FRHBT
CC2640R2FRSMR
CC2640R2FRSMT
CC2640R2FYFVR
CC2640R2FYFVT
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
DSBGA
DSBGA
RGZ
48
48
32
32
32
32
34
34
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CC2640
R2F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RGZ
RHB
RHB
RSM
RSM
YFV
YFV
250
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2640
R2F
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2640
R2F
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2640
R2F
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2640
R2F
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2640
R2F
2500
250
Green (RoHS
& no Sb/Br)
SNAGCU
CC2640
Green (RoHS
& no Sb/Br)
SNAGCU
CC2640
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
14-Dec-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
D: Max = 2.714 mm, Min =2.654 mm
E: Max = 2.714 mm, Min =2.654 mm
IMPORTANT NOTICE
重要声明
德州仪器
(TI)
公司有权按照最新发布的
JESD46
对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的
JESD48
提
供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。
他条款可能适用于其他类型
TI
产品及服务的使用或销售。
复制
TI
数据表上
TI
信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。
TI
对该等复制文
件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售
TI
产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去
相关
TI
产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。
TI
对此类虚假陈述不承担任何责任。
买方和在系统中整合
TI
产品的其他开发人员（总称
“
设计人员
”
）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且
应全权 负责并确保 应用的安全性， 及设计人员的 应用 （包括应用中使用的所有
TI
产品）应符合所有适用的法律法规及其他相关要求。设计
人员就自己设计的 应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够
(1)
预见故障的危险后果，
(2)
监视故障及其后
果，以及
(3)
降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含
TI
产品的任何 应用前， 将彻底测试该等 应用
和 该等应用中所用
TI
产品的 功能。
TI
提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称
“TI
资
源
”
），旨在帮助设计人员开发整合了
TI
产品的 应用， 如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、
访问或使用任何特定的
TI
资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定
TI
资源。
TI
所提供的
TI
资源，并未扩大或以其他方式修改
TI
对
TI
产品的公开适用的质保及质保免责声明；也未导致
TI
承担任何额外的义务或责任。
TI
有权对其
TI
资源进行纠正、增强、改进和其他修改。除特定
TI
资源的公开文档中明确列出的测试外，
TI
未进行任何其他测试。
设计人员只有在开发包含该等
TI
资源所列
TI
产品的 应用时， 才被授权使用、复制和修改任何相关单项
TI
资源。但并未依据禁止反言原则或
其他法理授予您任何
TI
知识产权的任何其他明示或默示的许可，也未授予您
TI
或第三方的任何技术或知识产权的许可，该等产权包括但不限
于任何专利权、版权、屏蔽作品权或与使用
TI
产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务
的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用
TI
资源可能需要您向第三方获得对该等第三方专利或其他知识产权
的许可。
TI
资源系
“
按原样
”
提供。
TI
兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡
发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。
TI
不负责任何申索，包括但不限于因组合产品所致或
与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于
TI
资源或其他地方。对因
TI
资源或其使用引起或与之有关
的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管
TI
是否获悉可能会产生上述损害赔
偿，
TI
概不负责。
除
TI
已明确指出特定产品已达到特定行业标准（例如
ISO/TS 16949
和
ISO 26262
）的要求外，
TI
不对未达到任何该等行业标准要求而承担
任何责任。
如果
TI
明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的
应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将
任何
TI
产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是
指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设
备）。此类设备包括但不限于，美国食品药品监督管理局认定为
III
类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备的
所有医疗设备。
TI
可能明确指定某些产品具备某些特定资格（例如
Q100
、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的
应用选择适合的 产品， 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。
设计人员同意向
TI
及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和
/
或责任。
邮寄地址：上海市浦东新区世纪大道
1568
号中建大厦
32
楼，邮政编码：
200122
Copyright © 2017
德州仪器半导体技术（上海）有限公司
