Texas-Instruments-CC2650F128RGZT
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CC2650 S
i
m
p
l
eLink™
M
u
l
tistandard
W
i
reless
M
CU
1 Device
Overview
1.1 Features
1
– Very
Few External Components
– Seamless
Integration With the SimpleLink™
CC2590 and CC2592 Range Extenders
– Pin
Compatible With the SimpleLink CC13xx in
4-mm × 4-mm and 5-mm × 5-mm VQFN
Packages
• Microcontroller
– Powerful
ARM
®
Cortex
®
-M3
– EEMBC
CoreMark
®
Score: 142
– Up
to 48-MHz Clock Speed
– 128KB
of In-System Programmable Flash
– 8KB
of SRAM for Cache
– 20KB
of Ultralow-Leakage SRAM
– 2-Pin
cJTAG and JTAG Debugging
– Supports
Over-The-Air Upgrade (OTA)
• Ultralow-Power
Sensor Controller
• Low
Power
– Wide
Supply Voltage Range
•
•
Normal Operation: 1.8 to 3.8 V
External Regulator Mode: 1.7 to 1.95 V
– Active-Mode
RX: 5.9 mA
– Can
Run Autonomous From the Rest of the
System
– 16-Bit
Architecture
– 2KB
of Ultralow-Leakage SRAM for Code and
Data
– Active-Mode
TX at 0 dBm: 6.1 mA
– Active-Mode
TX at +5 dBm: 9.1 mA
– Active-Mode
MCU: 61 µA/MHz
– Active-Mode
MCU: 48.5 CoreMark/mA
– Active-Mode
Sensor Controller: 8.2 µA/MHz
• Efficient
Code Size Architecture, Placing Drivers,
Bluetooth
®
Low Energy Controller, IEEE 802.15.4
MAC, and Bootloader in ROM
– Standby:
1 µA (RTC Running and RAM/CPU
Retention)
– Shutdown:
100 nA (Wake Up on External
Events)
• RF
Section
• RoHS-Compliant
Packages
– 4-mm
× 4-mm RSM VQFN32 (10 GPIOs)
– 5-mm
× 5-mm RHB VQFN32 (15 GPIOs)
– 7-mm
× 7-mm RGZ VQFN48 (31 GPIOs)
• Peripherals
– 2.4-GHz
RF Transceiver Compatible With
Bluetooth
Low Energy (BLE) 4.2 Specification
and IEEE 802.15.4 PHY and MAC
– Excellent
Receiver Sensitivity (–97 dBm for BLE
and –100 dBm for 802.15.4), Selectivity, and
Blocking Performance
– Link
budget of 102 dB/105 dB (BLE/802.15.4)
– Programmable
Output Power up to +5 dBm
– Single-Ended
or Differential RF Interface
– Suitable
for Systems Targeting Compliance With
Worldwide Radio Frequency Regulations
– All
Digital Peripheral Pins Can Be Routed to
Any GPIO
– Four
General-Purpose Timer Modules
(Eight 16-Bit or Four 32-Bit Timers, PWM Each)
– 12-Bit
ADC, 200-ksamples/s, 8-Channel Analog
MUX
– Continuous
Time Comparator
– Ultralow-Power
Analog Comparator
– Programmable
Current Source
– UART
– 2×
SSI (SPI, MICROWIRE, TI)
– I2C
•
•
•
•
ETSI EN 300 328 (Europe)
EN 300 440 Class 2 (Europe)
FCC CFR47 Part 15 (US)
ARIB STD-T66 (Japan)
– I2S
• Tools
and Development Environment
– Real-Time
Clock (RTC)
– AES-128
Security Module
– True
Random Number Generator (TRNG)
– 10,
15, or 31 GPIOs, Depending on Package
Option
– Full-Feature
and Low-Cost Development Kits
– Multiple
Reference Designs for Different RF
Configurations
– Packet
Sniffer PC Software
– Sensor
Controller Studio
– SmartRF™
Studio
– SmartRF
Flash Programmer 2
– IAR
Embedded Workbench
®
for ARM
– Code
Composer Studio™
– Support
for Eight Capacitive-Sensing Buttons
– Integrated
Temperature Sensor
• External
System
– On-Chip
internal DC-DC Converter
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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1.2 Applications
•
•
•
•
•
•
Consumer Electronics
Mobile Phone Accessories
Sports and Fitness Equipment
HID Applications
•
•
•
•
•
•
Alarm and Security
Electronic Shelf Labeling
Proximity Tags
Medical
Home and Building Automation
Lighting Control
Remote Controls
Wireless Sensor Networks
1.3 Description
The CC2650 device is a wireless MCU targeting
Bluetooth
, ZigBee
®
and 6LoWPAN, and ZigBee RF4CE
remote control applications.
The device is a member of the CC26xx family of cost-effective, ultralow power, 2.4-GHz RF devices. Very
low active RF and MCU current and low-power mode current consumption provide excellent battery
lifetime and allow for operation on small coin cell batteries and in energy-harvesting applications.
The CC2650 device contains a 32-bit ARM Cortex-M3 processor that runs at 48 MHz as the main
processor and a rich peripheral feature set that includes a unique ultralow power sensor controller. This
sensor controller is ideal for interfacing external sensors and for collecting analog and digital data
autonomously while the rest of the system is in sleep mode. Thus, the CC2650 device is ideal for
applications within a whole range of products including industrial, consumer electronics, and medical.
The
Bluetooth
Low Energy controller and the IEEE 802.15.4 MAC are embedded into ROM and are partly
running on a separate ARM Cortex-M0 processor. This architecture improves overall system performance
and power consumption and frees up flash memory for the application.
Device Information
(1)
PART NUMBER
CC2650F128RGZ
CC2650F128RHB
CC2650F128RSM
PACKAGE
VQFN (48)
VQFN (32)
VQFN (32)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
5.00 mm × 5.00 mm
4.00 mm × 4.00 mm
2
Device Overview
Copyright © 2015–2016, Texas Instruments Incorporated
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1.4 Functional
Block Diagram
Figure 1-1
shows a block diagram for the CC2650.
SimpleLink
TM
CC26xx wireless MCU
RF core
cJTAG
Main CPU
ROM
ADC
ADC
ARM
®
128KB
Cortex
®
-M3
Flash
Digital PLL
DSP modem
4KB
8KB
cache
ARM
®
SRAM
Cortex
®
-M0
20KB
SRAM
ROM
G
eneral peripherals / modules
S
ensor controller
I
2
C
4− 32-bit
Timers
Sensor controller
engine
UART
I2S
2− SSI (SPI, µW, TI)
Watchdog timer
12-bit ADC, 200 ks/s
2x comparator
10 / 15 / 31 GPIOs
AES
TRNG
SPI-I
2
C digital sensor IF
Constant current source
Time-to-digital converter
2KB SRAM
Temp. / batt. monitor
32 ch.
µ
DMA
RTC
DC-DC converter
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Block Diagram
Copyright © 2015–2016, Texas Instruments Incorporated
Device Overview
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Table of Contents
1
2
3
6
4
5
7
8
5.6
1-Mbps GFSK (
Bluetooth
low energy Technology) –
1-Mbps GFSK (
Bluetooth
low energy Technology) –
7.2
5 × 5 External Differential (5XD) Application Circuit
4 × 4 External Single-ended (4XS) Application
5.7
7.3
5.12 IEEE
802.15.4 (Offset Q-PSK DSSS, 250 kbps) –
5.13 IEEE
802.15.4 (Offset Q-PSK DSSS, 250 kbps) –
8.4
9
Mechanical Packaging and Orderable
4
Table of Contents
Copyright © 2015–2016, Texas Instruments Incorporated
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2 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from October 16, 2015 to July 5, 2016
Page
•
•
•
•
•
•
•
•
•
•
Changes from February 21, 2015 to October 15, 2015
Page
•
•
•
•
•
•
•
•
•
•
•
•
Copyright © 2015–2016, Texas Instruments Incorporated
Revision History
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3 Device
Comparison
Table 3-1. Device Family Overview
FLASH
RAM (KB)
(KB)
DEVICE
PHY SUPPORT
GPIO
PACKAGE
(1)
CC2650F128xxx
CC2640F128xxx
CC2630F128xxx
CC2620F128xxx
Multi-Protocol
(2)
128
128
128
128
20
20
20
20
31, 15, 10
31, 15, 10
31, 15, 10
31, 10
RGZ, RHB, RSM
RGZ, RHB, RSM
RGZ, RHB, RSM
RGZ, RSM
Bluetooth
low energy (Normal)
IEEE 802.15.4 Zigbee(/6LoWPAN)
IEEE 802.15.4 (RF4CE)
(1) Package
designator replaces the xxx in device name to form a complete device name, RGZ is 7-mm × 7-mm VQFN48, RHB is
5-mm × 5-mm VQFN32, and RSM is 4-mm × 4-mm VQFN32.
(2) The
CC2650 device supports all PHYs and can be reflashed to run all the supported standards.
3.1 Related
Products
solutions suitable
for a broad range of application. The offerings range from fully customized
solutions to turn key offerings with pre-certified hardware and software (protocol).
Sub-1 GHz
Long-range, low power wireless connectivity solutions are offered in a wide range of Sub-1
GHz ISM bands.
Bluetooth® Smart connectivity to the LaunchPad
kit ecosystem with the SimpleLink ultra-low
power CC26xx family of devices. This LaunchPad kit also supports development for multi-
protocol support for the SimpleLink multi-standard CC2650 wireless MCU and the rest of
CC26xx family of products: CC2630 wireless MCU for ZigBee
®
/6LoWPAN and CC2640
wireless MCU for
Bluetooth
®
Smart.
Reference Designs for CC2650
TI Designs Reference Design Library is a robust reference design library
divning analog, embedded
processor and connectivity. Created by TI experts to help you
jump-start your system design, all TI Designs include schematic or block diagrams, BOMs
and design files to speed your time to market. Search and download designs at
6
Device Comparison
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4 Terminal
Configuration and Functions
4.1 Pin
Diagram – RGZ Package
DIO_24
37
DIO_25
38
DIO_26
39
DIO_27
40
DIO_28
41
DIO_29
42
DIO_30
43
VDDS 44
24
JTAG_TMSC
23 DCOUPL
22 VDDS3
21 DIO_15
20 DIO_14
19 DIO_13
18 DIO_12
17 DIO_11
16 DIO_10
15 DIO_9
VDDR 45
X24M_N 46
X24M_P 47
VDDR_RF 48
14 DIO_8
13 VDDS2
Note: I/O
pins marked in
bold
have high drive capabilities. I/O pins marked in
italics
have analog capabilities.
Figure 4-1. RGZ Package
48-Pin VQFN
(7-mm × 7-mm) Pinout, 0.5-mm Pitch
4.2 Signal
Descriptions – RGZ Package
Table 4-1. Signal Descriptions – RGZ Package
NAME
DCDC_SW
DCOUPL
DIO_0
NO.
33
23
5
TYPE
DESCRIPTION
Power
Output from internal DC-DC
(1)
1.27-V regulated digital-supply decoupling capacitor
(2)
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
DIO_1
6
DIO_2
7
DIO_3
8
DIO_4
9
DIO_5
10
11
12
14
15
16
DIO_6
DIO_7
DIO_8
DIO_9
GPIO
DIO_10
GPIO
(2) Do
not supply external circuitry from this pin.
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Terminal Configuration and Functions
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Table 4-1. Signal Descriptions – RGZ Package (continued)
NAME
NO.
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
24
25
35
TYPE
DESCRIPTION
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
GPIO
GPIO
GPIO
GPIO
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital I/O
Digital I/O
Digital input
JTAG TMSC, high-drive capability
JTAG TCKC
Reset, active-low. No internal pullup.
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RF_P
RF_N
1
2
RF I/O
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
VDDR
45
48
44
13
22
34
3
Power
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
3)
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
4)
1.8-V to 3.8-V main chip supply
(1)
1.8-V to 3.8-V DIO supply
(1)
1.8-V to 3.8-V DIO supply
(1)
VDDR_RF
VDDS
Power
VDDS2
Power
VDDS3
Power
VDDS_DCDC
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
Power
1.8-V to 3.8-V DC-DC supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
32-kHz crystal oscillator pin 1
4
32-kHz crystal oscillator pin 2
46
47
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
8
Terminal Configuration and Functions
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4.3 Pin
Diagram – RHB Package
DIO_12
25
DIO_13
26
DIO_14
27
VDDS 28
16
DIO_6
15
DIO_5
14 JTAG_TCKC
13
JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10
DIO_4
9
DIO_3
Note: I/O
pins marked in
bold
have high drive capabilities. I/O pins marked in
italics
have analog capabilities.
Figure 4-2. RHB Package
32-Pin VQFN
(5-mm × 5-mm) Pinout, 0.5-mm Pitch
4.4 Signal
Descriptions – RHB Package
Table 4-2. Signal Descriptions – RHB Package
NAME
NO.
17
12
6
TYPE
DESCRIPTION
Output from internal DC-DC
(1)
1.27-V regulated digital-supply decoupling
(2)
DCDC_SW
DCOUPL
DIO_0
Power
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO, Sensor Controller
DIO_1
7
GPIO, Sensor Controller
DIO_2
8
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, High drive capability, JTAG_TDO
GPIO, High drive capability, JTAG_TDI
DIO_3
9
DIO_4
10
15
16
20
21
22
23
24
25
26
27
13
14
DIO_5
DIO_6
DIO_7
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
JTAG_TMSC
JTAG_TCKC
Digital I/O
Digital I/O
JTAG TMSC, high-drive capability
JTAG TCKC
(2) Do
not supply external circuitry from this pin.
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Terminal Configuration and Functions
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Table 4-2. Signal Descriptions – RHB Package (continued)
NAME
NO.
TYPE
DESCRIPTION
RESET_N
19
Digital input
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX
3
RF I/O
Power
Optional bias pin for the RF LNA
VDDR
29
32
28
11
18
4
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC
(3
)
(
2)
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
4)
1.8-V to 3.8-V main chip supply
(1)
VDDR_RF
VDDS
Power
Power
VDDS2
Power
1.8-V to 3.8-V GPIO suppl
y
(1)
VDDS_DCDC
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
Power
1.8-V to 3.8-V DC-DC supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
32-kHz crystal oscillator pin 1
5
32-kHz crystal oscillator pin 2
30
31
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
10
Terminal Configuration and Functions
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4.5 Pin
Diagram – RSM Package
DIO_8
25
DIO_9
26
16
DIO_4
15
DIO_3
VDDS 27
14 JTAG_TCKC
13
JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 28
VSS 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10
DIO_2
9
DIO_1
Note: I/O
pins marked in
bold
have high drive capabilities. I/O pins marked in
italics
have analog capabilities.
Figure 4-3. RSM Package
32-Pin VQFN
(4-mm × 4-mm) Pinout, 0.4-mm Pitch
4.6 Signal
Descriptions – RSM Package
Table 4-3. Signal Descriptions – RSM Package
NAME
NO.
TYPE
DESCRIPTION
Output from internal DC-DC.
(1)
. Tie to ground for external regulator mode
(1.7-V to 1.95-V operation)
DCDC_SW
18
Power
DCOUPL
DIO_0
12
8
Power
1.27-V regulated digital-supply decoupling capacitor
(2)
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, High drive capability, JTAG_TDO
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
DIO_1
9
DIO_2
10
15
16
22
23
24
25
26
13
14
21
DIO_3
DIO_4
GPIO, High drive capability, JTAG_TDI
DIO_5
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
Digital/Analog I/O
GPIO, Sensor Controller, Analog
DIO_6
DIO_7
DIO_8
DIO_9
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital I/O
Digital I/O
JTAG TMSC
JTAG TCKC
Digital Input
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
(2) Do
not supply external circuitry from this pin.
Copyright © 2015–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
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Table 4-3. Signal Descriptions – RSM Package (continued)
NAME
NO.
4
TYPE
RF I/O
Power
Power
Power
Power
DESCRIPTION
RX_TX
VDDR
Optional bias pin for the RF LNA
(2
)
(
3)
28
32
27
11
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC.
1.7-V to 1.95-V supply, typically connect to output of internal DC-D
C
(2
)
(
4)
1.8-V to 3.8-V main chip supply
(1)
VDDR_RF
VDDS
VDDS2
1.8-V to 3.8-V GPIO suppl
y
(1)
1.8-V to 3.8-V DC-DC supply. Tie to ground for external regulator mode
(1.7-V to 1.95-V operation).
VDDS_DCDC
VSS
19
Power
Power
3, 7, 17, 20,
29
Ground
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
5
6
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
30
31
(3) If
internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If
internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
12
Terminal Configuration and Functions
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5 Specifications
5.1 Absolute
Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1
)
(
2)
MIN
MAX UNIT
VDDR supplied by internal DC-DC regulator or
internal GLDO. VDDS_DCDC connected to VDDS on
PCB.
Supply voltage (VDDS, VDDS2,
and VDDS3)
–0.3
4.1
V
Supply voltage (VDDS
(3)
and
VDDR)
External regulator mode (VDDS and VDDR pins
connected on PCB)
–0.3
2.25
V
Voltage on any digital pin
(4
)
(
5)
–0.3
–0.3
–0.3
–0.3
–0.3
VDDSx + 0.3, max 4.1
V
V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P
Voltage scaling enabled
VDDR + 0.3, max 2.25
VDDS
1.49
Voltage on ADC input (V
in
)
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
V
VDDS / 2.9
5
Input RF level
T
stg
dBm
°C
Storage temperature
–40
150
(1) All
voltage values are with respect to ground, unless otherwise noted.
(2) Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) In
external regulator mode, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including
analog-capable DIO.
(5) Each
pin is referenced to a specific VDDSx (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see
Table 6-3
.
5.2 ESD
Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS001
(1)
All pins
±2500
Electrostatic discharge
(ESD) performance
V
ESD
V
RF pins
±750
±750
Charged device model (CDM), per JESD22-C101
(2)
Non-RF pins
(1) JEDEC
document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC
document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended
Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Ambient temperature range
–40
85
°C
Operating supply voltage
(VDDS and VDDR), external
regulator mode
For operation in 1.8-V systems
(VDDS and VDDR pins connected on PCB, internal DC-
DC cannot be used)
1.7
1.95
V
Operating supply voltage VDDS
1.8
3.8
3.8
V
V
For operation in battery-powered and 3.3-V systems
(internal DC-DC can be used to minimize power
consumption)
Operating supply voltages
VDDS2 and VDDS3
0.7 × VDDS, min 1.8
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
13
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
5.4 Power
Consumption Summary
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V with internal DC-DC converter, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
100
150
1
MAX
UNIT
Reset. RESET_N pin asserted or VDDS below
Power-on-Reset threshold
nA
Shutdown. No clocks running, no retention
Standby. With RTC, CPU, RAM and (partial)
register retention. RCOSC_LF
Standby. With RTC, CPU, RAM and (partial)
register retention. XOSC_LF
1.2
2.5
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. RCOSC_LF
µA
I
core
Core current consumption
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. XOSC_LF
2.7
Idle. Supply Systems and RAM powered.
550
1.45 mA +
31 µA/MHz
Active. Core running CoreMark
(1)
Radio RX
5.9
6.1
6.1
9.1
Radio RX
(2)
Radio TX, 0-dBm output power
(1)
Radio TX, 5-dBm output power
(2)
mA
Peripheral Current Consumption (Adds to core current I
core
for each peripheral unit activated)
(3)
Peripheral power domain
Serial power domain
Delta current with domain enabled
Delta current with domain enabled
20
13
µA
µA
Delta current with power domain enabled, clock
enabled, RF core idle
RF Core
237
µA
µDMA
Timers
I
2
C
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
130
113
12
µA
µA
µA
µA
µA
µA
I
peri
I2S
36
SSI
93
UART
164
(1) Single-ended
RF mode is optimized for size and power consumption. Measured on CC2650EM-4XS.
(2) Differential
RF mode is optimized for RF performance. Measured on CC2650EM-5XD.
(3) I
peri
is not supported in Standby or Shutdown.
5.5 General
Characteristics
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
FLASH MEMORY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supported flash erase cycles before
failure
100
k Cycles
Flash page/sector erase current
Flash page/sector size
Flash write current
Flash page/sector erase time
(1)
Flash write time
(1)
Average delta current
12.6
4
mA
KB
mA
ms
µs
Average delta current, 4 bytes at a time
8.15
8
4 bytes at a time
8
(1) This
number is dependent on Flash aging and will increase over time and erase cycles.
14
Specifications
Copyright © 2015–2016, Texas Instruments Incorporated
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
5.6 1-Mbps
GFSK (
Bluetooth
low energy Technology) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–97
dBm
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, BER = 10
–3
Receiver sensitivity
–96
4
dBm
dBm
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, BER = 10
–3
Receiver saturation
0
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
–350
–750
350
750
kHz
Difference between incoming data rate and the
internally generated data rate
ppm
Wanted signal at –67 dBm, modulated interferer in
(1)
Co-channel rejection
channel,
–6
dB
dB
dB
dB
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
(1)
Selectivity, ±1 MHz
±1 MHz,
7 / 3
(2)
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
(1)
Selectivity, ±2 MHz
±2 MHz,
34 / 25
(2)
38 / 26
(2)
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
(1)
Selectivity, ±3 MHz
±3 MHz,
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
(1)
Selectivity, ±4 MHz
±4 MHz,
42 / 29
(2)
32
dB
dB
dB
dB
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
≥
Selectivity, ±5 MHz or more
(1)
±5 MHz, BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
Selectivity, Image frequency
(1)
image frequency,
BER = 10
–3
25
Selectivity, Image frequency
±1 MHz
(1)
Wanted signal at –67 dBm, modulated interferer at
3 / 26
(2)
±1 MHz from image frequency, BER = 10
–3
30 MHz to 2000 MHz
(3)
Out-of-band blocking
–20
–5
dBm
dBm
dBm
dBm
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
–8
3000 MHz to 12.75 GHz
–8
Wanted signal at 2402 MHz, –64 dBm. Two
interferers at 2405 and 2408 MHz respectively, at
the given power level
Intermodulation
–34
–71
dBm
Conducted measurement in a 50-
Ω
single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions,
30 to 1000 MHz
dBm
Conducted measurement in a 50
Ω
single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions,
1 to 12.75 GHz
–62
dBm
RSSI dynamic range
RSSI accuracy
70
±4
dB
dB
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
(3) Excluding
one exception at F
wanted
/ 2, per
Bluetooth
Specification.
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
15
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
5.7 1-Mbps
GFSK (
Bluetooth
low energy Technology) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
Output power, lowest setting
2
dBm
Delivered to a single-ended 50-
Ω
load through a balun
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
–21
–43
–65
–76
–46
dBm
dBm
dBm
dBm
dBm
Spurious emission conducted
measurement
(1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
5.8 2-Mbps
GFSK (
Bluetooth
5) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–92
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
4
dBm
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
–300
500
kHz
Difference between incoming data rate and the
internally generated data rate
–1000
1000
ppm
Wanted signal at –67 dBm, modulated interferer in
(1)
Co-channel rejection
channel,
–7
dB
dB
dB
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
±2 MHz, Image frequency is at -2 MHz
BER = 10
–3
(1)
Selectivity, ±2 MHz
8 / 4
(2)
Wanted signal at –67 dBm, modulated interferer at
(1)
Selectivity, ±4 MHz
±4 MHz,
31 / 26
(2)
BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
(1)
Selectivity, ±6 MHz
±6 MHz,
37 / 38
(2)
37 / 36
(2)
4
dB
dB
dB
BER = 10
–3
Alternate channel rejection, ±7
Wanted signal at –67 dBm, modulated interferer at
≥
MHz
(1)
±7 MHz, BER = 10
–3
Wanted signal at –67 dBm, modulated interferer at
Selectivity, Image frequency
(1)
image frequency,
BER = 10
–3
Note that Image frequency + 2 MHz is the Co-
Selectivity, Image frequency
±2 MHz
(1)
channel. Wanted signal at –67 dBm, modulated
interferer at ±2 MHz from image frequency, BER =
10
–3
-7 / 26
(2)
dB
(3)
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
–33
–15
–12
–10
dBm
dBm
dBm
dBm
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
Wanted signal at 2402 MHz, –64 dBm. Two
interferers at 2405 and 2408 MHz respectively, at
the given power level
Intermodulation
–45
dBm
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
(3) Excluding
one exception at F
wanted
/ 2, per
Bluetooth
Specification.
16
Specifications
Copyright © 2015–2016, Texas Instruments Incorporated
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
5.9 2-Mbps
GFSK (
Bluetooth
5) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
Output power, lowest setting
2
dBm
Delivered to a single-ended 50-
Ω
load through a balun
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
–21
–43
–65
–76
–46
dBm
dBm
dBm
dBm
dBm
Spurious emission conducted
measurement
(1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
5.10 5-Mbps
(Proprietary) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver sensitivity
–81
dBm
Differential mode. Measured at the CC2650EM-5XD
SMA connector, BER = 10
–3
Receiver saturation
-11
dBm
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
–300
–200
300
200
kHz
Difference between incoming data rate and the
internally generated data rate
ppm
Wanted signal 11 dB above sensitivity level,
modulated interferer in channel,
BER = 10
–3
(1)
Co-channel rejection
–19
9 / 9
(2)
dB
dB
dB
Wanted signal 11 dB above sensitivity level,
modulated interferer at ±4 MHz
BER = 10
–3
(1)
Selectivity, ±4 MHz
Wanted signal 11 dB above sensitivity level,
modulated interferer at ±5 MHz,
BER = 10
–3
(1)
Selectivity, ±5 MHz
19 / 19
(2)
Wanted signal 11 dB above sensitivity level,
modulated interferer at ±8 MHz,
BER = 10
–3
(1)
Selectivity, ±8 MHz
28 / 28
(2)
33 / 33
(2)
37/ 37
(2)
dB
dB
dB
Wanted signal 11 dB above sensitivity level,
modulated interferer at ±10 MHz, BER = 10
–3
Selectivity, ±10 MHz
(1)
Selectivity, ±12 MHz
(1)
Wanted signal 11 dB above sensitivity level,
modulated interferer at ±12 MHz,
BER = 10
–3
Wanted signal 11 dB above sensitivity level,
modulated interferer at ±15 MHz,
BER = 10
–3
Selectivity, ±15 MHz
(1)
43/ 43
(2)
40
dB
dB
Blocker rejection ±10 MHz
Wanted signal 3dB above sensitivity limit , CW
interferer at ±10 MHz and above, BER = 10
–3
(1)
and above
(1) Numbers
given as I/C dB.
(2) X
/ Y, where X is +N MHz and Y is –N MHz.
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
17
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
5.11 5-Mbps
(Proprietary) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, f
RF
= 2440 MHz, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode, delivered to a single-ended 50-
Ω
load
through a balun
Output power, highest setting
5
dBm
Measured on CC2650EM-4XS, delivered to a single-ended
50-
Ω
load
Output power, highest setting
2
dBm
Output power, lowest setting
Occupied bandwidth
Delivered to a single-ended 50-
Ω
load through a balun
95% BW
–21
2.4
dBm
MHz
MHz
dBm
dBm
dBm
dBm
Occupied bandwidth
99% BW
3.7
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
–43
–65
–76
–46
Spurious emission conducted
measurement
(1)
(1) Suitable
for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
18
Specifications
Copyright © 2015–2016, Texas Instruments Incorporated
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
5.12 IEEE
802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, PER = 1%
Receiver sensitivity
–100
dBm
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, PER = 1%
Receiver sensitivity
–97
+4
dBm
dBm
dB
Measured at the CC2650EM-5XD SMA connector,
PER = 1%
Receiver saturation
Wanted signal at –82 dBm, modulated interferer at
±5 MHz, PER = 1%
Adjacent channel rejection
Alternate channel rejection
39
Wanted signal at –82 dBm, modulated interferer at
±10 MHz, PER = 1%
52
dB
Wanted signal at –82 dBm, undesired signal is IEEE
802.15.4 modulated channel, stepped through all
channels 2405 to 2480 MHz, PER = 1%
Channel rejection, ±15 MHz or
more
57
dB
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
64
64
65
68
63
63
65
67
dB
dB
dB
dB
dB
dB
dB
dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Conducted measurement in a 50-
Ω
single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions, 30 MHz to
1000 MHz
–71
–62
dBm
dBm
Conducted measurement in a 50
Ω
single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions, 1 GHz to
12.75 GHz
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Symbol rate error tolerance
>200
ppm
ppm
Difference between incoming symbol rate and the
internally generated symbol rate
>1000
RSSI dynamic range
RSSI accuracy
100
±4
dB
dB
5.13 IEEE
802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output power, highest setting
Delivered to a single-ended 50-
Ω
load through a balun
5
dBm
Measured on CC2650EM-4XS, delivered to a single-
ended 50-
Ω
load
Output power, highest setting
2
dBm
dBm
Output power, lowest setting
Error vector magnitude
Delivered to a single-ended 50-
Ω
load through a balun
–21
2%
At maximum output power
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
19
SWRS158B
–
F
EBRUARY 201
5
–
R
EVISED JULY 2016
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX
(continued)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
MIN
TYP
–43
–65
–76
–46
MAX
UNIT
dBm
Spurious emission conducted
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328
and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
5.14 24-MHz
Crystal Oscillator (XOSC_HF)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
Ω
ESR Equivalent series resistance
(2)
ESR Equivalent series resistance
(2)
6 pF < C
L
≤
9 pF
5 pF < C
L
≤
6 pF
20
80
Ω
Relates to load capacitance
(C
L
in Farads)
L
M
Motional inductance
(2)
< 1.6 × 10
–24
/ C
L
H
2
C
L
Crystal load capacitance
(2)
Crystal frequency
(2
)
(
3)
Crystal frequency tolerance
(2
)
(
4)
Start-up time
(3
)
(
5)
5
9
pF
MHz
ppm
µs
24
–40
40
150
(1) Probing
or otherwise stopping the XTAL while the DC-DC converter is enabled may cause permanent damage to the device.
(2) The
crystal manufacturer’s specification must satisfy this requirement
(3) Measured
on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V
(4) Includes
initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per
Bluetooth
and IEEE 802.15.4 specification.
(5) Kick-started
based on a temperature and aging compensated RCOSC_HF using precharge injection.
5.15 32.768-kHz
Crystal Oscillator (XOSC_LF)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
Crystal frequency
(1)
TEST CONDITIONS
MIN
–500
6
TYP
MAX
UNIT
32.768
kHz
Crystal frequency tolerance,
Bluetooth
low-
500
ppm
energy applications
(1
)
(
2)
ESR Equivalent series resistance
(1)
C
L
Crystal load capacitance
(1)
30
100
12
k
Ω
pF
(1) The
crystal manufacturer’s specification must satisfy this requirement
(2) Includes
initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per
Bluetooth
and IEEE 802.15.4 specification.
20
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5.16 48-MHz
RC Oscillator (RCOSC_HF)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
48
MAX
UNIT
Frequency
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy
(1)
Start-up time
±1%
±0.25%
5
µs
(1) Accuracy
relative to the calibration source (XOSC_HF).
5.17 32-kHz
RC Oscillator (RCOSC_LF)
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
Calibrated frequency
(1)
Temperature coefficient
TEST CONDITIONS
MIN
TYP
32.8
50
MAX
UNIT
kHz
ppm/°C
(1) The
frequency accuracy of the Real Time Clock (RTC) is not directly dependent on the frequency accuracy of the 32-kHz RC Oscillator.
The RTC can be calibrated to an accuracy within ±500 ppm of 32.768 kHz by
measuring the frequency error of RCOSC_LF relative to
XOSC_HF and compensating the RTC tick speed. The procedure is explained in
Running Bluetooth
®
Low Energy on CC2640 Without
5.18 ADC
Characteristics
T
c
= 25°C, V
DDS
= 3.0 V and voltage scaling enabled, unless otherwise noted.
(1)
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX UNIT
0
VDDS
V
12
Bits
ksps
LSB
LSB
LSB
LSB
Sample rate
200
Offset
Internal 4.3-V equivalent reference
(2)
Internal 4.3-V equivalent reference
(2)
2
2.4
>–1
±3
Gain error
DNL
(3)
Differential nonlinearity
INL
(4)
Integral nonlinearity
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
9.6-kHz input tone
9.8
10
ENOB
Effective number of bits
VDDS as reference, 200 ksps, 9.6-kHz input tone
Bits
dB
dB
dB
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
9.6-kHz input tone
11.1
–65
–69
–71
THD
Total harmonic distortion
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
60
63
69
9.6-kHz input tone
Signal-to-noise
and
Distortion ratio
SINAD,
SNDR
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference
(2)
, 200 ksps,
9.6-kHz input tone
67
72
73
Spurious-free dynamic
range
SFDR
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
(1) Using
IEEE Std 1241™-2010 for terminology and test methods.
(2) Input
signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) No
missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see
Figure 5-25
).
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
21
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ADC Characteristics
(continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
clock-
cycles
Conversion time
Serial conversion, time-to-output, 24-MHz clock
50
Current consumption
Current consumption
Internal 4.3-V equivalent reference
(2)
VDDS as reference
0.66
0.75
mA
mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should
be initiated through the TIRTOS API in order to include the
gain/offset compensation factors stored in FCFG1.
Reference voltage
4.3
(2
)
(
5)
V
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TIRTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is
derived from the scaled value (4.3V) as follows:
Vref=4.3V*1408/4095
Reference voltage
1.48
V
VDDS as reference (Also known as
RELATIVE
) (input
voltage scaling enabled)
Reference voltage
Reference voltage
VDDS
V
V
VDDS as reference (Also known as
RELATIVE
) (input
voltage scaling disabled)
VDDS /
2.82
(5)
200 ksps, voltage scaling enabled. Capacitive input, Input
impedance depends on sampling frequency and sampling
time
Input Impedance
>1
M
Ω
22
Specifications
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5.19 Temperature
Sensor
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Range
4
–40
85
°C
Accuracy
±5
°C
Supply voltage coefficient
(1)
3.2
°C/V
(1) Automatically
compensated when using supplied driver libraries.
5.20 Battery
Monitor
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
50
1.8
3.8
Accuracy
13
mV
5.21 Continuous
Time Comparator
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
VDDS
VDDS
UNIT
V
Input voltage range
External reference voltage
0
V
Internal reference voltage
Offset
DCOUPL as reference
1.27
3
V
mV
mV
µs
Hysteresis
<2
Decision time
Current consumption when enabled
(1)
Step from –10 mV to 10 mV
0.72
8.6
µA
(1) Additionally,
the bias module must be enabled when running in standby mode.
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
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5.22 Low-Power
Clocked Comparator
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range
0
VDDS
V
Clock frequency
32
1.49 – 1.51
1.01 – 1.03
0.78 – 0.79
1.25 – 1.28
0.63 – 0.65
0.42 – 0.44
0.33 – 0.34
<2
kHz
Internal reference voltage, VDDS / 2
Internal reference voltage, VDDS / 3
Internal reference voltage, VDDS / 4
Internal reference voltage, DCOUPL / 1
Internal reference voltage, DCOUPL / 2
Internal reference voltage, DCOUPL / 3
Internal reference voltage, DCOUPL / 4
Offset
V
V
V
V
V
V
V
mV
Hysteresis
<5
mV
Decision time
Step from –50 mV to 50 mV
<1
clock-cycle
nA
Current consumption when enabled
362
5.23 Programmable
Current Source
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
Current source programmable output range
Resolution
0.25 – 20
0.25
µA
Including current source at maximum
programmable output
Current consumption
(1)
23
µA
(1) Additionally,
the bias module must be enabled when running in standby mode.
5.24 Synchronous
Serial Interface (SSI)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
S1
(1)
t
clk_per
(SSIClk period)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
system
clocks
Device operating as SLAVE
12
65024
(1)
S2
t
(SSIClk high time)
Device operating as SLAVE
Device operating as SLAVE
0.5
0.5
t
clk_per
t
clk_per
clk_high
S3
(1)
t
clk_low
(SSIClk low time)
One-way communication to SLAVE –
Device operating as MASTER
system
clocks
S1 (TX only)
(1)
t
clk_per
(SSIClk period)
4
8
65024
65024
Normal duplex operation – Device
operating as MASTER
system
clocks
S1 (TX and RX)
(1)
t
clk_per
(SSIClk period)
(1)
S2
S3
t
(SSIClk high time)
(SSIClk low time)
Device operating as MASTER
Device operating as MASTER
0.5
0.5
t
clk_per
t
clk_per
clk_high
(1)
t
clk_low
24
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S1
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
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S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
5.25 DC
Characteristics
PARAMETER
TEST CONDITIONS
T
A
= 25°C, V
DDS
= 1.8 V
MIN
1.32
1.32
TYP
MAX
UNIT
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.54
0.26
1.58
0.21
71.7
21.1
V
V
0.32
0.32
V
IOCURR = 1
V
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
µA
µA
GPIO pulldown current
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
0.88
1.07
V
V
GPIO low-to-high input transition,
with hysteresis
IH = 1, transition voltage for input read as 0
→
1
GPIO high-to-low input transition,
with hysteresis
IH = 1, transition voltage for input read as 1
→
0
IH = 1, difference between 0
→
1 and 1
→
0 points
0.74
0.33
V
V
GPIO input hysteresis
26
Specifications
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DC Characteristics
(continued)
PARAMETER
TEST CONDITIONS
T
A
= 25°C, V
DDS
= 3.0 V
MIN
TYP
MAX
UNIT
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.68
0.33
2.72
0.28
V
V
V
V
IOCURR = 1
T
A
= 25°C, V
DDS
= 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
277
113
µA
µA
GPIO pulldown current
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
IH = 1, transition voltage for input read as 0
→
1
IH = 1, transition voltage for input read as 1
→
0
1.67
1.94
V
V
GPIO low-to-high input transition,
with hysteresis
GPIO high-to-low input transition,
with hysteresis
1.54
0.4
V
V
GPIO input hysteresis
IH = 1, difference between 0
→
1 and 1
→
0 points
T
A
= 25°C
Lowest GPIO input voltage reliably interpreted as a
«High»
VIH
VIL
0.8 VDDS
(1)
VDDS
(1)
Highest GPIO input voltage reliably interpreted as a
«Low»
0.2
(1) Each
GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in
Section 8.3
for more details.
5.26 Thermal
Resistance Characteristics
NAME
R
θ
JA
DESCRIPTION
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RSM (°C/W)
(1) (2)
RHB (°C/W)
(1) (2)
RGZ (°C/W)
(1) (2)
36.9
30.3
7.6
32.8
24.0
6.8
29.6
15.7
6.2
R
θ
JC(top)
R
θ
JB
Psi
JT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
0.3
0.3
Psi
JB
7.4
6.8
6.2
R
θ
JC(bot)
2.1
1.9
1.9
(1) °C/W
= degrees Celsius per watt.
(2) These
values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [R
θ
JC
] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2,
Integrated Circuits Thermal Test Method Environmental Conditions – Natural Convection (Still Air)
.
JESD51-3,
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
.
JESD51-7,
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
.
JESD51-9,
Test Boards for Area Array Surface Mount Package Thermal Measurements
.
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
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5.27 Timing
Requirements
MIN
0
NOM
MAX
100
20
UNIT
mV/µs
mV/µs
mV/µs
Rising supply-voltage slew rate
Falling supply-voltage slew rate
Falling supply-voltage slew rate, with low-power flash settings
(1)
0
3
No limitation for negative
temperature gradient, or
outside standby mode
Positive temperature gradient in standby
(2)
5
°C/s
µs
CONTROL INPUT AC CHARACTERISTICS
(3)
RESET_N low duration
1
(1) For
smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see
Figure 7-1
) must be used to ensure compliance with this slew rate.
(2) Applications
using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
(3) T
A
= –40°C to 85°C, V
DDS
= 1.7 V to 3.8 V, unless otherwise noted.
5.28 Switching
Characteristics
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
WAKEUP AND TIMING
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Idle
→
Active
14
151
µs
µs
µs
Standby
→
Active
Shutdown
→
Active
1015
28
Specifications
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5.29 Typical
Characteristics
-95
-96
-94
-95
-96
-97
-98
-99
-97
-98
-99
-100
-101
-102
-103
Sensitivity 4XS
Sensitivity 5XD
Sensitivity 4XS
Sensitivity 5XD
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (
è
C)
Temperature (
è
C)
Figure 5-4. BLE Sensitivity vs Temperature
Figure 5-5. IEEE 802.15.4 Sensitivity vs Temperature
-95
-96
-95
IEEE 802.15.4 5XD Sensitivity
IEEE 802.15.4 4XS Sensitivity
-96
-97
-97
-98
-98
-99
-99
-100
-100
BLE 5XD Sensitivity
BLE 4XS Sensitivity
-101
-101
1.8
2.3
2.8
3.3
3.8
1.8
2.3
2.8
3.3
3.8
VDDS (V)
VDDS (V)
D004
D005
Figure 5-6. BLE Sensitivity vs Supply Voltage (VDDS)
Figure 5-7. IEEE 802.15.4 Sensitivity vs Supply Voltage (VDDS)
-95
-95
Sensitivity 4XS
Sensitivity 5XD
Sensitivity 5XD
Sensitivity 4XS
-95.5
-96
-96
-97
-98
-96.5
-97
-97.5
-98
-99
-100
-98.5
-99
-101
2400 2410 2420 2430 2440 2450 2460 2470 2480
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
Frequency (MHz)
D019
D020
Figure 5-8. IEEE 802.15.4 Sensitivity vs Channel Frequency
Figure 5-9. BLE Sensitivity vs Channel Frequency
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Typical Characteristics
(continued)
6
6
5
4
3
2
1
0
5
4
4XS 2-dBm Setting
5XD 5-dBm Setting
3
2
1
0
5XD 5
–
dBm Setting
4XS 2
–
dBm Setting
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (
è
C)
1.8
2.3
2.8
3.3
3.8
VDDS (V)
D003
Figure 5-10. TX Output Power vs Temperature
Figure 5-11. TX Output Power vs Supply Voltage (VDDS)
8
16
5-dBm setting (5XD)
0-dBm setting (4XS)
4XS 0-dBm Setting
4XS 2-dBm Setting
5XD 5-dBm Setting
15
7
6
14
13
12
11
10
9
5
4
3
2
8
7
1
6
0
5
-1
4
2400 2410 2420 2430 2440 2450 2460 2470 2480
1.8
2
2.2 2.4 2.6 2.8
VDDS (V)
3
3.2 3.4 3.6 3.8
Frequency (MHz)
D021
D015
Figure 5-12. TX Output Power
vs Channel Frequency
Figure 5-13. TX Current Consumption
vs Supply Voltage (VDDS)
10.5
7
4XS
5XD
5XD RX Current
4XS RX Current
10
9.5
9
6.8
6.6
6.4
6.2
6
8.5
8
7.5
7
6.5
6
5.5
5
5.8
5.6
4.5
4
1.8
2.05
2.3
2.55
2.8
3.05
3.3
3.55
3.8
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Voltage (V)
Temperature (
è
C)
D016
D001
Figure 5-14. RX Mode Current vs Supply Voltage (VDDS)
Figure 5-15. RX Mode Current Consumption vs Temperature
30
Specifications
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Typical Characteristics
(continued)
12
3.1
3.05
3
Active Mode Current
10
8
6
2.95
2.9
4
2
5XD 5
–
dBm Setting
4XS 2
–
dBm Setting
2.85
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (
è
C)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (
è
C)
D006
D002
Figure 5-17. Active Mode (MCU Running, No Peripherals)
Current Consumption vs Temperature
Figure 5-16. TX Mode Current Consumption vs Temperature
5
4
Active Mode Current
Standby Mode Current
3.5
4.5
4
3
2.5
2
3.5
3
1.5
1
2.5
0.5
0
2
1.8
2.3
2.8
3.3
3.8
-20 -10
0
10 20 30 40 50 60 70 80
VDDS (V)
Temperature (
è
C)
D007
D008
Figure 5-18. Active Mode (MCU Running, No Peripherals) Current
Figure 5-19. Standby Mode Current Consumption With RCOSC
Consumption vs Supply Voltage (VDDS)
RTC vs Temperature
1006.4
1006.2
1006
11.4
11.2
11
Fs= 200 kHz, No Averaging
Fs= 200 kHz, 32 samples averaging
10.8
10.6
10.4
10.2
10
1005.8
1005.6
1005.4
1005.2
1005
9.8
9.6
9.4
1004.8
20
0
3
00 500
1000 2000
5000 10000
20000
100000
1.8
2.3
2.8
3.3
3.8
Input Frequency (Hz)
VDDS (V)
D009
D012
Figure 5-20. SoC ADC Effective Number of Bits vs Input
Frequency (Internal Reference, No Scaling)
Figure 5-21. SoC ADC Output vs Supply Voltage (Fixed Input,
Internal Reference, No Scaling)
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Typical Characteristics
(continued)
10.5
10.4
10.3
10.2
10.1
10
1007.5
ENOB Internal Reference (No Averaging)
ENOB Internal Reference (32 Samples Averaging)
1007
1006.5
1006
9.9
1005.5
1005
9.8
9.7
1004.5
9.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
1k
10k
100k 200k
Temperature (
è
C)
Sampling Frequency (Hz)
D013
D009A
Figure 5-22. SoC ADC Output vs Temperature (Fixed Input,
Internal Reference, No Scaling)
Figure 5-23. SoC ADC ENOB vs Sampling Frequency
(Input Frequency = FS / 10)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
Temperature (
è
C)
D021
Figure 5-24. Standby Mode Supply Current vs Temperature
32
Specifications
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Typical Characteristics
(continued)
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
D010
ADC Code
Figure 5-25. SoC ADC DNL vs ADC Code (Internal Reference, No Scaling)
3
2
1
0
-1
-2
-3
-4
0
200 400 600 800
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200
ADC Code
D011
Figure 5-26. SoC ADC INL vs ADC Code (Internal Reference, No Scaling)
Copyright © 2015–2016, Texas Instruments Incorporated
Specifications
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6 Detailed
Description
6.1 Overview
6.2 Functional
Block Diagram
SimpleLink
TM
CC26xx wireless MCU
RF core
cJTAG
Main CPU
ROM
ADC
ADC
ARM
®
128KB
Flash
Cortex
®
-M3
Digital PLL
DSP modem
8KB
cache
4KB
SRAM
ARM
®
Cortex
®
-M0
20KB
SRAM
ROM
G
eneral peripherals / modules
S
ensor controller
I
2
C
4− 32-bit
Timers
Sensor controller
engine
UART
I2S
2− SSI (SPI, µW, TI)
Watchdog timer
12-bit ADC, 200 ks/s
2x comparator
10 / 15 / 31 GPIOs
AES
TRNG
SPI-I
2
C digital sensor IF
Constant current source
Time-to-digital converter
2KB SRAM
Temp. / batt. monitor
32 ch.
µ
DMA
RTC
DC-DC converter
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6.3 Main
CPU
The SimpleLink CC2650 Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the
application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
CM3 features include the following:
•
•
•
32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
Outstanding processing performance combined with fast interrupt handling
ARM Thumb
®
-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
–
–
Single-cycle multiply instruction and hardware divide
Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
–
Unaligned data access, enabling data to be efficiently packed into memory
•
•
•
•
•
•
•
•
•
•
•
•
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system, and memories
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Enhanced system debug with extensive breakpoint and trace capabilities
Serial wire trace reduces the number of pins required for debugging and tracing
Migration from the ARM7™ processor family for better performance and power efficiency
Optimized for single-cycle flash memory use
Ultralow-power consumption with integrated sleep modes
1.25 DMIPS per MHz
6.4 RF
Core
The RF Core contains an ARM Cortex-M0 processor that interfaces the analog RF and base-band
circuitries, handles data to and from the system side, and assembles the information bits in a given packet
structure. The RF core offers a high level, command-based API to the main CPU.
The RF core is capable of autonomously handling the time-critical aspects of the radio protocols (802.15.4
RF4CE and ZigBee,
Bluetooth
Low Energy) thus offloading the main CPU and leaving more resources for
the user application.
The RF core has a dedicated 4-KB SRAM block and runs initially from separate ROM memory. The ARM
Cortex-M0 processor is not programmable by customers.
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6.5 Sensor
Controller
The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals
in this domain may be controlled by the Sensor Controller Engine which is a proprietary power-optimized
CPU. This CPU can read and monitor sensors or perform other tasks autonomously, thereby significantly
reducing power consumption and offloading the main CM3 CPU.
The Sensor Controller is set up using a PC-based configuration tool, called Sensor Controller Studio, and
potential use cases may be (but are not limited to):
•
•
•
•
•
•
•
•
•
Analog sensors using integrated ADC
Digital sensors using GPIOs, bit-banged I
2
C, and SPI
UART communication for sensor reading or debugging
Capacitive sensing
Waveform generation
Pulse counting
Keyboard scan
Quadrature decoder for polling rotation sensors
Oscillator calibration
NOTE
Texas Instruments provides application examples for some of these use cases, but not for all
of them.
The peripherals in the Sensor Controller include the following:
•
The low-power clocked comparator can be used to wake the device from any state in which the
comparator is active. A configurable internal reference can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
•
Capacitive sensing functionality is implemented through the use of a constant current source, a time-
to-digital converter, and a comparator. The continuous time comparator in this block can also be used
as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller will take
care of baseline tracking, hysteresis, filtering and other related functions.
•
The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC
can be triggered by many different sources, including timers, I/O pins, software, the analog
comparator, and the RTC.
•
•
The Sensor Controller also includes a SPI–I
2
C digital interface.
The analog modules can be connected to up to eight different GPIOs.
The peripherals in the Sensor Controller can also be controlled from the main application processor.
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Table 6-1. GPIOs Connected to the Sensor Controller
(1)
7 × 7 RGZ
DIO NUMBER
5 × 5 RHB
DIO NUMBER
4 × 4 RSM
DIO NUMBER
ANALOG CAPABLE
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
30
29
28
27
26
25
24
23
7
14
13
12
11
9
9
8
7
6
5
2
1
0
10
8
7
4
6
3
5
2
4
1
3
0
2
1
0
(1) Depending
on the package size, up to 16 pins can be connected to the Sensor Controller. Up to 8 of
these pins can be connected to analog modules.
6.6 Memory
The flash memory provides nonvolatile storage for code and data. The flash memory is in-system
programmable.
The SRAM (static RAM) can be used for both storage of data and execution of code and is split into two
4-KB blocks and two 6-KB blocks. Retention of the RAM contents in standby mode can be enabled or
disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled,
the 8-KB cache can be used as a general-purpose RAM.
The ROM provides preprogrammed embedded TI RTOS kernel, Driverlib and lower layer protocol stack
software (802.15.4 MAC and
Bluetooth
Low Energy Controller). It also contains a bootloader that can be
used to reprogram the device using SPI or UART.
6.7 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface.
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6.8 Power
Management
To minimize power consumption, the CC2650 device supports a number of power modes and power
Table 6-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Active
Off
Off
Off
Off
Flash
On
Available
On
Off
SRAM
On
On
Off
Off
Radio
Available
Available
On
Off
Off
Off
Supply System
Current
Wake-up Time to CPU Active
(1)
Register Retention
SRAM Retention
On
Duty Cycled
1 µA
Off
Off
1.45 mA + 31 µA/MHz
550 µA
14 µs
Full
0.15 µA
1015 µs
No
0.1 µA
1015 µs
No
–
151 µs
Partial
Full
Full
Full
Full
No
No
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
High-Speed Clock
Low-Speed Clock
Off
Off
Off
Off
Off
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
Available
Available
Active
Available
Available
Available
Available
Available
Active
Off
Available
Available
Available
Available
Duty Cycled
(2)
Active
Off
Off
Off
Off
Sensor Controller
Wake up on RTC
Off
Off
Wake up on Pin Edge
Wake up on Reset Pin
Brown Out Detector (BOD)
Power On Reset (POR)
Available
Available
Off
Off
Available
N/A
Active
Active
Active
N/A
(1) Not
including RTOS overhead
(2) The
Brown Out Detector is disabled between recharge periods in STANDBY. Lowering the supply voltage below the BOD threshold
between two recharge periods while in STANDBY may cause the BOD to lock the device upon wake-up until a Reset/POR releases it.
To avoid this, it is recommended that STANDBY mode is avoided if there is a risk that the supply voltage (VDDS) may drop below the
specified operating voltage range. For the same reason, it is also good practice to ensure that a power cycling operation, such as a
battery replacement, triggers a Power-on-reset by ensuring that the VDDS decoupling network is fully depleted before applying supply
voltage again (for example, inserting new batteries).
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event will bring the processor back into active mode.
In standby mode, only the always-on domain (AON) is active. An external wake event, RTC event, or
sensor-controller event is required to bring the device back to active mode. MCU peripherals with retention
do not need to be reconfigured when waking up again, and the CPU continues execution from where it
went into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is turned off entirely, including the AON domain and the Sensor Controller.
The I/Os are latched with the value they had before entering shutdown mode. A change of state on any
I/O pin defined as a
wake from Shutdown pin
wakes up the device and functions as a reset trigger. The
CPU can differentiate between a reset in this way, a reset-by-reset pin, or a power-on-reset by reading the
reset status register. The only state retained in this mode is the latched I/O state and the Flash memory
contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independently of the main CPU, which means that the main CPU does not have to wake up, for
example, to execute an ADC sample or poll a digital sensor over SPI. The main CPU saves both current
and wake-up time that would otherwise be wasted. The Sensor Controller Studio enables the user to
configure the sensor controller and choose which peripherals are controlled and which conditions wake up
the main CPU.
6.9 Clock
Systems
The CC2650 supports two external and two internal clock sources.
A 24-MHz crystal is required as the frequency reference for the radio. This signal is doubled internally to
create a 48-MHz clock.
The 32-kHz crystal is optional.
Bluetooth
low energy requires a slow-speed clock with better than
±500 ppm accuracy if the device is to enter any sleep mode while maintaining a connection. The internal
32-kHz RC oscillator can in some use cases be compensated to meet the requirements. The low-speed
crystal oscillator is designed for use with a 32-kHz watch-type crystal.
The internal high-speed oscillator (48-MHz) can be used as a clock source for the CPU subsystem.
The internal low-speed oscillator (32.768-kHz) can be used as a reference if the low-power crystal
oscillator is not used.
The 32-kHz clock source can be used as external clocking reference through GPIO.
6.10 General
Peripherals and Modules
The I/O controller controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and Texas
Instruments synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.
The UART implements a universal asynchronous receiver/transmitter function. It supports flexible baud-
rate generation up to a maximum of 3 Mbps and is compatible with the
Bluetooth
HCI specifications.
Timer 0 is a general-purpose timer module (GPTM), which provides two 16-bit timers. The GPTM can be
configured to operate as a single 32-bit timer, dual 16-bit timers or as a PWM module.
Timer 1, Timer 2, and Timer 3 are also GPTMs. Each of these timers is functionally equivalent to Timer 0.
In addition to these four timers, the RF core has its own timer to handle timing for RF protocols; the RF
timer can be synchronized to the RTC.
The I
2
C interface is used to communicate with devices compatible with the I
2
C standard. The I
2
C interface
is capable of 100-kHz and 400-kHz operation, and can serve as both I
2
C master and I
2
C slave.
The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys,
initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring
oscillators that create unpredictable output to feed a complex nonlinear combinatorial circuit.
The watchdog timer is used to regain control if the system fails due to a software error after an external
device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
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The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to
offload data transfer tasks from the CM3 CPU, allowing for more efficient use of the processor and the
available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The
µDMA controller has dedicated channels for each supported on-chip module and can be programmed to
automatically perform transfers between peripherals and memory as the peripheral is ready to transfer
more data. Some features of the µDMA controller include the following (this is not an exhaustive list):
•
•
Highly flexible and configurable channel operation of up to 32 channels
Transfer modes:
–
–
–
–
Memory-to-memory
Memory-to-peripheral
Peripheral-to-memory
Peripheral-to-peripheral
•
Data sizes of 8, 16, and 32 bits
The AON domain contains circuitry that is always enabled, except for in Shutdown (where the digital
supply is off). This circuitry includes the following:
•
The RTC can be used to wake the device from any state where it is active. The RTC contains three
compare and one capture registers. With software support, the RTC can be used for clock and
calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be
compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used
instead of a crystal.
•
The battery monitor and temperature sensor are accessible by software and give a battery status
indication as well as a coarse temperature measure.
6.11 Voltage
Supply Domains
The CC2650 device can interface to two or three different voltage domains depending on the package
type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output
pin is set with respect to the corresponding supply pin (VDDS, VDDS2 or VDDS3). lists the pin-to-VDDS
mapping.
Table 6-3. Pin function to VDDS mapping table
Package
VQFN 7 × 7 (RGZ)
VQFN 5 × 5 (RHB)
VQFN 4 × 4 (RSM)
DIO 23–30
Reset_N
DIO 7–14
Reset_N
DIO 5–9
Reset_N
VDDS
(1)
VDDS2
VDDS3
DIO 0–6
JTAG
DIO 0–4
JTAG
DIO 0–11
DIO 12–22
JTAG
N/A
N/A
(1) VDDS_DCDC
must be connected to VDDS on the PCB
6.12 System
Architecture
Depending on the product configuration, CC26xx can function either as a Wireless Network Processor
(WNP—an IC running the wireless protocol stack, with the application running on a separate MCU), or as
a System-on-Chip (SoC), with the application and protocol stack running on the ARM CM3 core inside the
device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second
case, the application must be written according to the application framework supplied with the wireless
protocol stack.
40
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7 Application,
Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application
Information
Very few external components are required for the operation of the CC2650 device. This section provides
some general information about the various configuration options when using the CC2650 in an
application, and then shows two examples of application circuits with schematics and layout. This is only a
small selection of the many application circuit examples available as complete reference designs from the
Figure 7-1
shows the various RF front-end configuration options. The RF front end can be used in
differential- or single-ended configurations with the options of having internal or external biasing. These
options allow for various trade-offs between cost, board space, and RF performance. Differential operation
with external bias gives the best performance while single-ended operation with internal bias gives the
least amount of external components and the lowest power consumption. Reference designs exist for
each of these options.
Red = Not necessary if internal bias is used
6.8 pF
!ntenna
(50 hꢀm)
Pin 3 (RXTX)
2.4 nH
1 pF
To VDDR
pins
Pin 2 (RF N)
Pin 1 (RF P)
2 nH
1 pF
2 nH
6.2
œ
6.8 nH
2.4
œ
2.7 nH
10µF
12 pC
Optional
inductor.
Only
needed for
DCDC
Differential
operation
1 pF
10µH
operation
!ntenna
(50 hꢀm)
Red = Not necessary if internal bias is used
CC26xx
Pin 2 (RF N)
DCDC_SW
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
15 nH
(GND exposed die
attached pad
)
Pin 1 (RF P)
2 nH
VDDS_DCDC
input
decoupling
10µF
œ
22µF
Single ended
operation
12 pC
1.2 pF
1.2 pF
!ntenna
(50 hꢀm)
Red = Not necessary if internal bias is used
Pin 3 (RXTX)
15 nH
24MHz
XTAL
2 nH
Pin 2 (RF N)
(Load caps
on chip)
12 pC
1.2 pF
1.2 pF
Single ended
operation with 2
antennas
!ntenna
(50 hꢀm)
15 nH
2 nH
Pin 1 (RF P)
12 pC
1.2 pF
1.2 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. CC2650 Application Circuit
Copyright © 2015–2016, Texas Instruments Incorporated
Application, Implementation, and Layout
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Figure 7-2
shows the various supply voltage configuration options. Not all power supply decoupling
capacitors or digital I/Os are shown. Exact pin positions will vary between the different package options.
For a detailed overview of power supply decoupling and wiring, see the TI reference designs and the
Internal DC-DC Regulator
Internal LDO Regulator
External Regulator
To All VDDR Pins
To All VDDR Pins
1.7 V
œ
1.95 V to All VDDR- and VDDS Pins Except VDDS_DCDC
9xt.
wegulator
10
ꢀ
F
10
ꢀ
F
2.2
ꢀ
F
VDDS
VDDS
VDDS
VDDS
10
ꢀ
H
CC26xx
CC26xx
CC26xx
DCDC_SW Pin
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
NC
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
DCDC_SW Pin
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
(GND Exposed Die
Attached Pad)
(GND Exposed Die
Attached Pad)
(GND Exposed Die
Attached Pad)
VDDS_DCDC Pin
VDDS_DCDC Pin
VDDS_DCDC Pin
VDDS_DCDC
Input Decoupling
10
ꢀ
F
œ
22
ꢀ
F
VDDS_DCDC
Input Decoupling
10
ꢀ
F
œ
22
ꢀ
F
24-MHz XTAL
(Load Caps
on Chip)
24-MHz XTAL
(Load Caps on Chip)
24-MHz XTAL
(Load Caps on Chip)
1.8 V
œ
3.8 V
1.8 V
œ
3.8 V
to All VDDS Pins
Supply Voltage
To All VDDS Pins
Copyright © 2016, Texas Instruments Incorporated
Figure 7-2. Supply Voltage Configurations
42
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7.2 5
× 5 External Differential (5XD) Application Circuit
VDD_EB
VDDS
VDDS Decoupling Capacitors
VDDR
VDDR Decoupling Capacitors
BLM18HE152SN1
1
Pin 18
C6
10 µF
Pin 28
C4
100 nF
Pin 11
C3
100 nF
2
L1
Pin 32
Pin 29
C9
100 nF
DCDC_SW
2
1
FL1
C7
C2
DNM
10 uH
C8
10 µF
C10
100 nF
C16
100 nF
DNM
Place L1 and
C8 close to pin 17
VDDS
VDDR
U1
DIO_0
DIO_1
6
7
28
11
18
29
32
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
DIO_10
DIO_
1
1
DIO_12
DIO_13
DIO_14
VDDS
VDDS2
DIO_2
DIO_3
DIO_4
8
C31
6.8 pF
VDDS_DCDC
VDDR
VDDR
9
R
X
_
TX
RFN
10
15
16
20
21
22
23
24
25
26
27
50-Ω
DIO_5/JTAG_TDO
DIO_6/JTAG_TDI
DIO_7
1
DCDC_SW
17
Antenna
DCDC_SW
L21
2.4 nH
DIO_8
DIO_9
VDDS
C21
3
2
1
R
X
_
TX
RF_N
RF_P
2
DIO_10
DIO_
1
1
DIO_12
DIO_13
DIO_14
1
2
R1
1 pF
L11
L12
L13
1
2
1
2
L10
6.2 nH
100 k
31
30
X
2
4M_P
X
2
4M_N
X
2
4M_P
X
2
4M_N
nRESET
C122 nH
DNM
C13 2
nH
1 pF
RFP
1
2
19
14
13
RESET_N
J
T
AG_TCKC
J
T
AG_TMSC
5
4
J
T
AG_TCK
J
T
AG_TMS
X
3
2K_Q2
X
3
2K_Q1
2.7 nH
C
1
1
C20
100 nF
12
33
1 pF
DCOUPL
C19
1 µF
VSS
CC2650F128RHB
Y2
24 MHz
Y1
32.768 kHz
1
3
C17
C18 C22
12 pF
DNM
C23
2
4
12 pF
DNM
Copyright © 2016, Texas Instruments Incorporated
Figure 7-3.
5 × 5 External Differential (5XD) Application Circuit
Copyright © 2015–2016, Texas Instruments Incorporated
Application, Implementation, and Layout
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7.2.1 Layout
Figure 7-4. 5 × 5 External Differential (5XD) Layout
44
Application, Implementation, and Layout
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EVISED JULY 2016
7.3 4
× 4 External Single-ended (4XS) Application Circuit
VDD_EB
VDDR
VDDS
VDDS Decoupling Capacitors
VDDR Decoupling Capacitors
FL1
L1
Pin 11
Pin 27
Pin 19
Pin 28
Pin 32
DCDC_SW
2
1
1
2
BLM18HE152SN1
10 µH
C2
C5
10 µF
C8
C10
C16
100 nF
C6
C3
100 nF
C4
C9
DNM
100 nF
10 µF
DNM
100 nF
100 nF
Place L1 and
C8 close to pin 18
VDDS
VDDR
U1
DIO_0
27
8
9
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
VDDS
RF_N used for RX biasing.
L21 may be removed at the
cost of 1 dB degraded
sensitivity
DIO_1
DIO_2
11
19
28
32
VDDS2
VDDS_DCDC
VDDR
10
15
16
22
23
24
25
26
DIO_3/JTAG_TDO
DIO_4/JTAG_TDI
DIO_5
50-Ω
Antenna
VDDS
VDDR
DCDC_SW
DIO_6
18
DCDC_SW
DIO_7
R1
100 k
DIO_8
L21
1 2
4
DIO_9
R
X
/
T
X
RF_N
RF_P
C14
nRESET
2
1
L12
15 nH
nRESET
RF_P
1
2
21
14
13
RESET_N
J
T
AG_TCK
J
T
AG_TMS
J
T
AG_TCKC
J
T
AG_TMSC
2 nH
C12
C13
12 pF
X
2
4M_P
X
2
4M_N
31
30
C20
X
2
4M_P
X
2
4M_N
12
1.2 pF
1.2 pF
100 nF
DCOUPL
6
5
3
7
X
3
2K_Q2
X
3
2K_Q1
VSS
VSS
VSS
VSS
VSS
EGP
C19
1 µF
17
20
29
33
CC26
X
X
_
4
X
4
Y2
24 MHz
Y1
32.768 kHz
1
3
C22
DNM
C23
DNM
C17
12 pF
C18
2
4
12 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-5. 4 × 4 External Single-ended (4XS) Application Circuit
Copyright © 2015–2016, Texas Instruments Incorporated
Application, Implementation, and Layout
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7.3.1 Layout
Figure 7-6. 4 × 4 External Single-ended (4XS) Layout
46
Application, Implementation, and Layout
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8 Device
and Documentation Support
8.1 Device
Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and
date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example,
CC2650 is in production; therefore, no prefix/identification is assigned).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device’s electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example,
RSM
).
For orderable part numbers of the
CC2650
device in the
RSM, RHB or RGZ
package types, see the
representative.
yyy (R/T)
CC26 xx
F128
PREFIX
X = Experimental device
Blank = Qualified device
R = Large Reel
T = Small Reel
DEVICE FAMILY
SimpleLink™ Multistandard
Wireless MCU
DEVICE
PACKAGE DESIGNATOR
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RHB = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
RSM = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
20 = RF4CE
30 = Zigbee
40 =
Bluetooth
50 = Multi-Protocol
ROM version 1
Flash = 128KB
Figure 8-1. Device Nomenclature
Copyright © 2015–2016, Texas Instruments Incorporated
Device and Documentation Support
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8.2 Tools
and Software
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules.
The following products support development of the CC2650 device applications:
Software Tools:
SmartRF Studio is a PC application that helps designers of radio systems to easily evaluate the RF-IC at
an early stage in the design process.
•
•
•
Test functions for sending and receiving radio packets, continuous wave transmit and receive
Evaluate RF performance on custom boards by wiring it to a supported evaluation board or debugger
Can also be used without any hardware, but then only to generate, edit and export radio configuration
settings
•
Can be used in combination with several development kits for Texas Instruments’ CCxxxx RF-ICs
Sensor Controller Studio provides a development environment for the CC26xx Sensor Controller. The
Sensor Controller is a proprietary, power-optimized CPU in the CC26xx, which can perform simple
background tasks autonomously and independent of the System CPU state.
•
•
Allows for Sensor Controller task algorithms to be implemented using a C-like programming language
Outputs a Sensor Controller Interface driver, which incorporates the generated Sensor Controller
machine code and associated definitions
•
Allows for rapid development by using the integrated Sensor Controller task testing and debugging
functionality. This allows for live visualization of sensor data and algorithm verification.
IDEs and Compilers:
Code Composer Studio:
•
•
•
•
Integrated development environment with project management tools and editor
Code Composer Studio (CCS) 6.1 and later has built-in support for the CC26xx device family
Best support for XDS debuggers; XDS100v3, XDS110 and XDS200
High integration with TI-RTOS with support for TI-RTOS Object View
IAR Embedded Workbench for ARM
•
•
•
•
•
Integrated development environment with project management tools and editor
IAR EWARM 7.30.3 and later has built-in support for the CC26xx device family
Broad debugger support, supporting XDS100v3, XDS200, IAR I-Jet and Segger J-Link
Integrated development environment with project management tools and editor
For a complete listing of development-support tools for the CC2650 platform, visit the Texas Instruments
website at
www.ti.com
. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
48
Device and Documentation Support
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8.3 Documentation
Support
(
CC2650
). In the upper right corner, click on Alert me to register and receive a weekly digest of any
product information that has changed. For change details, review the revision history included in any
revised document.
The current documentation that describes the CC2650 devices, related peripherals, and other technical
collateral is listed in the following.
Technical Reference Manual
SPACER
Errata
8.4 Texas
Instruments Low-Power RF Website
Texas Instruments’ Low-Power RF website has all the latest products, application and design notes, FAQ
8.5 Low-Power
RF eNewsletter
The Low-Power RF eNewsletter is up-to-date on new products, news releases, developers’ news, and
other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter
articles include links to get more online information.
8.6 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views;
collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
•
•
•
Forums, videos, and blogs
RF design help
E2E interaction
RF development partners
to help customers speed up their application development. The
network consists of recommended companies, RF consultants, and independent design
houses that provide a series of hardware module products and design services, including:
•
•
•
RF circuit, low-power RF, and ZigBee design services
Low-power RF and ZigBee module solutions and development tools
RF certification services and RF circuit manufacturing
For help with modules, engineering services or development tools:
a
suitable partner.
Copyright © 2015–2016, Texas Instruments Incorporated
Device and Documentation Support
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8.7 Additional
Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and
standard-based wireless applications for use in industrial and consumer applications. The selection
includes RF transceivers, RF transmitters, RF front ends, and Systems-on-Chips as well as various
software solutions for the sub-1-GHz and 2.4-GHz frequency bands.
In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and
university programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the
chance to interact with engineers from all over the world.
With a broad selection of product solutions, end-application possibilities, and a range of technical support,
Texas Instruments offers the broadest low-power RF portfolio.
8.8 Trademarks
SimpleLink, SmartRF, Code Composer Studio, E2E are trademarks of Texas Instruments.
ARM7 is a trademark of ARM Limited (or its subsidiaries).
ARM, Cortex, ARM Thumb are registered trademarks of ARM Limited (or its subsidiaries).
Bluetooth
is a registered trademark of Bluetooth SIG, Inc.
CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium.
IAR Embedded Workbench is a registered trademark of IAR Systems AB.
IEEE Std 1241 is a trademark of Institute of Electrical and Electronics Engineers, Incorporated.
ZigBee is a registered trademark of ZigBee Alliance, Inc.
All other trademarks are the property of their respective owners.
8.9 Electrostatic
Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.10 Export
Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from Disclosing party under
this Agreement, or any direct product of such technology, to any destination to which such export or re-
export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from
U.S. Department of Commerce and other competent Government authorities to the extent required by
those laws.
8.11 Glossary
This glossary lists and explains terms, acronyms and definitions.
9 Mechanical
Packaging and Orderable Information
9.1 Packaging
Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
50
Mechanical Packaging and Orderable Information
Copyright © 2015–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
22-Jul-2017
PACKAGING INFORMATION
Orderable Device
CC2650F128RGZR
CC2650F128RGZT
CC2650F128RHBR
CC2650F128RHBT
CC2650F128RSMR
CC2650F128RSMT
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
48
48
32
32
32
32
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
CC2650
F128
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RGZ
RHB
RHB
RSM
RSM
250
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2650
F128
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2650
F128
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2650
F128
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2650
F128
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
CC2650
F128
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
22-Jul-2017
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
18-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width
(mm) (mm) (mm) (mm) (mm)
Quadrant
(mm) W1
(mm)
CC2650F128RGZR
CC2650F128RGZT
CC2650F128RHBR
CC2650F128RHBT
CC2650F128RSMR
CC2650F128RSMT
CC2650F128RSMT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RHB
RHB
RSM
RSM
RSM
48
48
32
32
32
32
32
2500
250
330.0
180.0
330.0
180.0
330.0
180.0
180.0
16.4
16.4
12.4
12.4
12.4
12.4
12.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
8.0
16.0
16.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
5.3
5.3
1.1
5.3
5.3
1.1
8.0
3000
250
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
8.0
8.0
250
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
18-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2650F128RGZR
CC2650F128RGZT
CC2650F128RHBR
CC2650F128RHBT
CC2650F128RSMR
CC2650F128RSMT
CC2650F128RSMT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RHB
RHB
RSM
RSM
RSM
48
48
32
32
32
32
32
2500
250
336.6
210.0
336.6
210.0
336.6
210.0
210.0
336.6
185.0
336.6
185.0
336.6
185.0
185.0
31.8
35.0
31.8
35.0
31.8
35.0
35.0
3000
250
3000
250
250
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (
http://www.ti.com/sc/docs/stdterms.htm
) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
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TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
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TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
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Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
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Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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