Texas-Instruments-CSD16301Q2
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CSD16301Q2 25-V N-Channel NexFET™ Power MOSFET
1 Features
Product Summary
1
•
•
•
•
•
•
Ultra-Low Q
g
and Q
gd
T
A
= 25°C
V
DS
TYPICAL VALUE
UNIT
V
Low Thermal Resistance
Lead-Free Terminal Plating
RoHS Compliant
Drain-to-Source Voltage
Gate Charge Total (4.5 V)
Gate Charge Gate-to-Drain
25
2
Q
g
nC
nC
Q
gd
0.4
V
GS
= 3 V
V
GS
= 4.5 V
V
GS
= 8 V
1.1
27
23
19
Halogen Free
R
DS(on)
Drain-to-Source On Resistance
m
Ω
SON 2-mm × 2-mm Plastic Package
V
GS(th)
Threshold Voltage
V
2 Applications
•
•
DC-DC Converters
Battery and Load Management Applications
DEVICE
QTY
MEDIA
PACKAGE
SHIP
CSD16301Q2
CSD16301Q2T
3000
250
SON
Tape
and
Reel
3 Description
7-Inch Reel
2.00-mm × 2.00-mm
Plastic Package
This 25-V, 19-m
Ω
, 2-mm × 2-mm SON NexFET™
power MOSFET has been designed to minimize
losses in power conversion and load management
applications. The 2-mm × 2-mm SON package offers
excellent thermal performance for the size of the
package.
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
T
A
= 25°C
VALUE
UNIT
V
V
DS
V
GS
Drain-to-Source Voltage
25
Top View
Gate-to-Source Voltage
+10 / –8
5
V
Continuous Drain Current (Package Limited)
Continuous Drain Current (Silicon Limited),
T
C
= 25°C
I
D
20
A
D
D
G
1
2
3
6
5
4
D
D
S
D
8.2
85
I
DM
P
D
T
J
,
A
2.5
15
W
Power Dissipation, T
C
= 25°C
Operating Junction,
–55 to 150
10
°C
T
STG
Storage Temperature
S
Avalanche Energy, Single Pulse
I
D
= 14 A, L = 0.1 mH, R
G
= 25
Ω
E
AS
mJ
(1) Typical
R
θ
JA
= 50°C/W on a 1-in
2
, 2-oz Cu pad on a 0.06-in
thick FR4 PCB.
P0108-01
.
.
(2) Max
R
θ
JC
= 8.4°C/W, pulse duration
≤
100
μ
s, duty cycle
≤
1%.
R
DS(on)
vs V
GS
Gate Charge
80
70
60
50
40
30
20
10
0
8
I
D
= 4 A
T
C
= 25
è
C, I
D
= 4 A
T
C
= 125
è
C, I
D
= 4 A
V
DS
= 12.5 V
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
3.5
V
GS
– Gate-to-Source Voltage (V)
Q
g
– Gate Charge (nC)
D007
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
7
Mechanical, Packaging, and Orderable
6
4 Revision
History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2011) to Revision D
Page
•
•
•
•
•
•
•
•
•
•
Added silicon limited continuous drain current to
Absolute Maximum Ratings
table …………………………………………………….
1
Changes from Revision B (April 2010) to Revision C
Page
•
Changes from Revision A (December 2009) to Revision B
Page
•
Changes from Original (October 2009) to Revision A
Page
•
Changed the Electrical Characteristics table – V
GS(th)
MAX value From: 1.4V To 1.55V………………………………………………..
3
2
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5 Specifications
5.1 Electrical
Characteristics
T
A
= 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
D
= 250
μ
A
V
GS
= 0 V, V
DS
= 20 V
V
DS
= 0 V, V
GS
= +10/–8 V
V
DS
= V
GS
, I
DS
= 250
μ
A
V
GS
= 3 V, I
DS
= 4 A
25
V
μ
A
nA
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
1
100
I
GSS
V
GS(th)
0.9
1.1 1.55
27
23
34
29
24
R
DS(on)
Drain-to-source on resistance
V
GS
= 4.5 V, I
DS
= 4 A
V
GS
= 8 V, I
DS
= 4 A
m
Ω
19
g
fs
Transconductance
V
DS
= 15 V, I
DS
= 4 A
16.5
S
DYNAMIC CHARACTERISTICS
C
ISS
C
OSS
C
RSS
R
g
Input capacitance
260
165
13
340
215
17
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
V
GS
= 0 V, V
DS
= 12.5 V, ƒ = 1 MHz
1.3
2.0
0.4
0.6
0.3
3.0
2.7
4.4
4.1
1.7
2.6
2.8
Q
g
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Qg(th)
Q
OSS
t
d(on)
t
r
V
DS
= 10 V, I
DS
= 4 A
V
DS
= 12.5 V, V
GS
= 0 V
Turnon delay time
Rise time
V
DS
= 12.5 V, V
GS
= 4.5 V, I
DS
= 4 A
R
G
= 2
Ω
t
d(off)
t
f
Turnoff delay time
Fall time
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
DS
= 4 A, V
GS
= 0 V
0.8
5.1
11
1
V
nC
ns
V
DD
= 12.5 V, I
F
= 4 A, di/dt = 200 A/
μ
s
5.2 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
(1)
Junction-to-ambient thermal resistance
(1
)
(
2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
R
θ
JC
R
θ
JA
8.4
65
(1)
R
θ
JC
is determined with the device mounted on a 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board design.
(2) Device
mounted on FR4 material with 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu.
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GATE
Source
GATE
Source
Max R
θ
JA
= 250°C/W
Max R
θ
JA
= 65°C/W
when mounted on 1 in
2
(6.45 cm
2
) of 2-oz
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
(0.071-mm) thick Cu.
DRAIN
DRAIN
M0164-02
M0164-01
5.3 Typical
MOSFET Characteristics
T
A
= 25°C (unless otherwise specified)
Figure 1. Transient Thermal Impedance
4
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise specified)
10
11
10
9
T
C
= 125°C
T
C
= 25°C
T
C
= -55°C
9
8
7
6
5
4
3
8
7
6
5
4
3
2
2
V
GS
= 3 V
V
GS
= 4.5 V
V
GS
= 8 V
1
0
1
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
V
DS
– Drain-to-Source Voltage (V)
1
1.25
1.5
1.75
2
2.25
2.5
V
GS
– Gate-to-Source Voltage (V)
D002
D003
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
8
7
6
5
4
3
2
1
0
1000
100
10
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
1
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
Q
g
– Gate Charge (nC)
V
DS
– Drain-to-Source Voltage (V)
D004
D005
I
D
= 4 A
V
DS
= 50 V
Figure 4. Gate Charge
Figure 5. Capacitance
1.5
1.3
1.1
0.9
0.7
0.5
80
70
60
50
40
30
20
10
0
T
C
= 25
è
C, I
D
= 4 A
T
C
= 125
è
C, I
D
= 4 A
-75 -50 -25
0
25
50
75 100
125 150 175
0
1
2
3
4
5
6
7
8
9
10
T
C
– Case Temperature (
è
C)
V
GS
– Gate-to-Source Voltage (V)
D006
D007
I
D
= 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise specified)
1.8
10
1
T
C
= 25°C
T
C
= 125°C
1.6
1.4
1.2
1
0.1
0.01
0.001
0.0001
0.8
0.6
-75 -50 -25
0
25
50
75 100
125 150 175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature (°C)
V
SD
– Source-to-Drain Voltage (V)
D008
D009
V
GS
= 4.5 V
I
D
= 4 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
10
1
T
C
= 125°C
T
C
= 25°C
100
10
1
100 ms
10 ms
1 ms
100 µs
10 µs
0.1
0.1
1
10
100
0.01
0.1
1
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
D011
D010
Single pulse, max R
θ
JC
= 8.4°C/W
Figure 11. Single Pulse Unclamped Inductive Switching
Figure 10. Maximum Safe Operating Area
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100 125 150 175
T
C
– Case Temperature (
è
C)
D012
Figure 12. Maximum Drain Current vs Temperature
6
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6 Device
and Documentation Support
6.1 Receiving
Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on
Alert me
to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community
Resources
The following links connect to TI community resources. Linked contents are provided “AS IS” by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI’s views; see TI’s
Terms of
Use
.
among engineers.
At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support
TI’s Design Support
Quickly find helpful E2E forums along with design support tools and
contact
information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic
Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2009–2016, Texas Instruments Incorporated
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7 Mechanical,
Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q2
Package Dimensions
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8 MAX
C
SEATING PLANE
0.05
0.00
0.75±0.1
PKG
(0.2)
(0.2) TYP
(0.47)
0.3±0.05
3
4
7
4X
0.65
(0.5)
PKG
2X
1.3
8
0.95±0.1
6
1
(0.2)
0.35
0.25
6X
PIN 1 ID
(45 X0.3)
1±0.1
0.1
C A
C
B
0.3
0.2
0.05
6X
1. All
linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This
drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical
performance.
8
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7.2 Recommended
PCB Pattern
(1)
PKG
6X (0.45)
1
6
8
6X (0.3)
PKG
(0.95)
(0.325)
4X (0.65)
(0.65)
4
7
3
(0.3)
(R0.05) TYP
(0.095)
(0.75)
(1.95)
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
1. For
recommended circuit layout for PCB designs, see
Reducing Ringing Through PCB Layout Techniques
(SLPA005).
2. This
package is designed to be soldered to a thermal pad on the board. For more information, see
QFN/SON
PCB Attachment
(SLUA271).
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7.3 Recommended
Stencil Pattern
(0.9)
PKG
METAL
ALL AROUND, TYP
6X (0.45)
1
6X (0.3)
6
8
(0.86)
(0.325)
PKG
4X (0.65)
(0.65)
7
(0.29)
3
4
(R0.05) TYP
(0.095)
(0.7)
(1.95)
1. All
linear dimensions are in millimeters.
2. Laser
cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
10
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7.4 Q2
Tape and Reel Information
4.00 0.10
2.00 0.0ꢀ
Ø 1.ꢀ0
0.10
10° Max
4.00 0.10
Ø 1.00
0.2ꢀ
1.00 0.0ꢀ
0.2ꢀ4 0.02
10° Max
2.30 0.0ꢀ
M0168-01
Notes:
1. Measured
from centerline of sprocket hole to centerline of pocket.
2. Cumulative
tolerance of 10 sprocket holes is ±0.2.
3. Other
material available.
4. Typical
SR of form tape Max 10
9
OHM/SQ.
5. All
dimensions are in mm, unless otherwise specified.
Copyright © 2009–2016, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
17-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
CSD16301Q2
ACTIVE
WSON
DQK
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 150
1631
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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been so designated is solely at the Buyer’s risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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