Texas-Instruments-CSD16325Q5
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SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
N
–
C
hannel NexFET™
Power MOSFETs
1
FEATURES
PRODUCT SUMMARY
2
•
•
•
•
•
•
•
•
Optimized for 5V Gate Drive
V
DS
Q
g
Drain to Source Voltage
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
25
18
V
Ultralow Q
g
and Q
gd
nC
nC
m
Ω
m
Ω
m
Ω
V
Low Thermal Resistance
Avalanche Rated
Q
gd
3.5
V
GS
= 3V
2.1
1.7
1.5
R
DS(on)
Drain to Source On Resistance
V
GS
= 4.5V
V
GS
= 8V
Pb Free Terminal Plating
RoHS Compliant
V
GS(th)
Threshold Voltage
1.1
Halogen Free
SON 5-mm × 6-mm Plastic Package
ORDERING INFORMATION
Device
CSD16325Q5
Package
Media
Qty
Ship
APPLICATIONS
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
2500
•
Point-of-Load Synchronous Buck in
Networking, Telecom and Computing Systems
•
Optimized for Synchronous FET Applications
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C unless otherwise stated
VALUE
UNIT
V
DESCRIPTION
V
DS
V
GS
Drain to Source Voltage
25
Gate to Source Voltage
+10 / –8
100
V
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications
and optimized for 5V gate drive applications.
Continuous Drain Current, T
C
= 25°C
A
I
D
33
A
I
DM
P
D
T
J
,
200
A
Top View
3.1
W
Operating Junction and Storage
–55 to 150
500
°C
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
T
STG
Temperature Range
Avalanche Energy, single pulse
I
D
= 100A, L = 0.1mH, R
G
= 25
Ω
E
AS
mJ
(1) Typical
R
q
JA
=
38°C/W on 1-inch
2
(6.45-cm
2
), 2-oz.
(0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4
PCB.
D
D
(2) Pulse
duration
≤
300
m
s, duty cycle
≤
2%
P0094-01
R
DS(on)
vs V
GS
Gate Charge
10
5
4
3
2
1
0
I
= 30A
I
= 30A
9
8
7
6
5
4
3
2
1
0
D
D
V
= 12.5V
DS
T
= 125
°
C
C
T
3
= 25
°
C
C
0
5
10
15
20
25
30
35
40
0
1
2
4
5
6
7
8
9
10
Q
− Gate Charge − nC
V
− Gate to Source Voltage − V
g
GS
G003
G006
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise stated)
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN TYP
MAX UNIT
BV
DSS
I
DSS
Drain to Source Voltage
V
GS
= 0V, I
D
= 250
m
A
25
V
m
A
nA
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
V
GS
= 0V, V
DS
= 20V
V
DS
= 0V, V
GS
= +10/–8V
V
DS
= V
GS
, I
D
= 250
m
A
V
GS
= 3V, I
D
= 30A
1
100
1.4
2.9
2.2
2
I
GSS
V
GS(th)
0.9
1.1
2.1
1.7
1.5
159
m
Ω
m
Ω
m
Ω
S
R
DS(on)
Drain to Source On Resistance
Transconductance
V
GS
= 4.5V, I
D
= 30A
V
GS
= 8V, I
D
= 30A
g
fs
V
DS
= 15V, I
D
= 30A
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
3070 4000
2190 2850
pF
pF
pF
Ω
V
GS
= 0V, V
DS
= 12.5V,
f = 1MHz
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5V)
Gate Charge – Gate to Drain
Gate Charge – Gate to Source
Gate Charge at Vth
Output Charge
120
1.6
18
150
3.2
25
Q
g
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
3.5
6.6
3.3
43
V
DS
= 12.5V,
I
DS
= 30A
V
DS
= 13V, V
GS
= 0V
Turn On Delay Time
Rise Time
10.5
16
V
DS
= 12.5V, V
GS
= 4.5V,
I
DS
= 30A, R
G
=2
Ω
t
d(off)
t
f
Turn Off Delay Time
Fall Time
32
12
Diode Characteristics
V
SD
Q
rr
t
rr
Diode Forward Voltage
I
DS
= 30A, V
GS
= 0V
0.8
63
47
1
V
Reverse Recovery Charge
Reverse Recovery Time
V
DD
= 10V, I
F
= 30A, di/dt = 300A/
m
s
V
DD
= 10V, I
F
= 30A, di/dt = 300A/
m
s
nC
ns
THERMAL CHARACTERISTICS
(T
A
= 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case
(1)
Thermal Resistance Junction to Ambient
(1) (2)
q
JC
is determined with the device mounted on a 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. R
q
JC
is specified by design, whereas R
q
JA
is determined by the user’s board design.
(2) Device
mounted on FR4 material with 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu.
MIN
TYP
MAX UNIT
°C/W
50 °C/W
R
q
JC
R
q
JA
1
(1)
R
2
Copyright © 2009–2010, Texas Instruments Incorporated
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
GATE
Source
GATE
Source
Max R
q
JA
= 50°C/W
when mounted on
1 inch
2
(6.45 cm
2
) of
2-oz. (0.071-mm thick)
Cu.
Max R
q
JA
= 126°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
Text
Text
Text
and
and
and
br
br
br
Added
Added
Added
for
for
for
Spacing
Spacing
Spacing
Text and br Added for Spacing
TYPICAL MOSFET CHARACTERISTICS
(T
A
= 25°C unless otherwise stated)
10
1
0.5
0.3
0.1
0.1
0.01
0.05
Duty Cycle = t
1
/t
2
0.02
0.01
P
t
1
t
2
0.001
0.0001
Single Pulse
Typical R
q
JA
= 101
°
C/W (min Cu)
T
J
= P x Z
q
JA
x R
q
JA
0.001
0.01
0.1
1
10
100
1k
t
p
– Pulse Duration–s
G012
Figure 1.
Transient Thermal Impedance
Copyright © 2009–2010, Texas Instruments Incorporated
3
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(T
A
= 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
V
= 5V
GS = 8V
DS
V
T
= 125
°
C
GS = 4.5V
C
V
GS = 3V
T
= 25
°
C
C
V
V
GS = 2V
GS = 2.5V
T
= -55
°
C
C
0.0
0.5
1.0
1.5
2.0
1.00
1.25
1.50
1.75
2.00
2.25
2.50
V
− Drain to Source Voltage − V
V
− Gate to Source Voltage − V
DS
GS
G001
G002
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
I
= 30A
f = 1MHz
= 0V
D
V
V
= 12.5V
GS
DS
C
= C
+ C
ds dg
oss
C
= C
+ C
gd
iss
gs
C
= C
gd
rss
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
Q
− Gate Charge − nC
V
− Drain to Source Voltage − V
g
DS
G003
G004
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
Figure 5. Capacitance
TEXT ADDED FOR SPACING
1.6
5
4
3
2
1
0
I
= 30A
I
= 250
m
A
D
D
1.4
1.2
1.0
T
= 125
°
C
C
0.8
0.6
0.4
0.2
0.0
T
3
= 25
°
C
C
−75
−25
25
75
125
175
0
1
2
4
5
6
7
8
9
10
T
− Case
T
e
mperature −
°
C
V
− Gate to Source Voltage − V
C
GS
G005
G006
Figure 6. Threshold Voltage vs. Temperature
Figure 7. On-State Resistance vs. Gate to Source Voltage
4
Copyright © 2009–2010, Texas Instruments Incorporated
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(T
A
= 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
1.4
1.2
1.0
0.8
100
10
I
= 30A
D
V
= 4.5V
GS
1
T
= 125
°
C
C
0.1
T
= 25
°
C
C
0.6
0.4
0.2
0.0
0.01
0.001
0.0001
−75
−25
25
75
125
175
0.0
0.2
0.4
0.6
0.8
1.0
T
− Case
T
e
mperature −
°
C
V
− Source to Drain Voltage − V
C
G007
SD
G008
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1k
100
10
1k
100
1ms
T
= 25
°
C
C
10
10ms
100ms
1
Area Limited
by R
1s
DS(on)
T
= 125
°
C
C
0.1
Single Pulse
DC
Typical R
= 101
°
C/W (min Cu)
q
JA
1
0.01
0.01
0.1
t
1
10
100
0.01
0.1
1
10
100
− Time in Avalanche − ms
V
− Drain
T
o
S
ource Voltage − V
(AV)
DS
G010
G009
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
120
100
80
60
40
20
0
−50 −25
0
25
50
75
100 125 150 175
T
− Case
T
e
mperature −
°
C
C
G011
Figure 12.
Maximum Drain Current vs. Temperature
Copyright © 2009–2010, Texas Instruments Incorporated
5
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
MECHANICAL DATA
Q5 Package Dimensions
K
L
L
E1
c1
E2
q
Top View
Side View
Bottom View
q
E1
Front View
M0140-01
MILLIMETERS
MAX
INCHES
DIM
MIN
MIN
MAX
0.039
0.018
0.010
0.010
0.201
0.178
0.201
0.240
0.162
A
b
0.950
0.360
0.150
0.150
4.900
4.320
4.900
5.900
3.920
1.050
0.037
0.014
0.006
0.006
0.193
0.170
0.193
0.232
0.154
0.460
c
0.250
c1
D1
D2
E
0.250
5.100
4.520
5.100
E1
E2
e
6.100
4.12
1.27 TYP
0.710
0.050
L
0.510
0.00
0.020
0.028
q
6
Copyright © 2009–2010, Texas Instruments Incorporated
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
MILLIMETERS
INCHES
DIM
Recommended PCB Pattern
MIN
MAX
6.305
4.56
4.56
0.7
MIN
MAX
0.248
0.18
F1
F1
F2
6.205
4.46
4.46
0.65
0.62
0.63
0.7
0.244
0.176
0.176
0.026
0.024
0.025
0.028
0.026
0.024
0.193
0.176
F7
F6
F3
0.18
F4
0.028
0.026
0.027
0.031
0.028
0.026
0.197
0.18
F5
0.67
0.68
0.8
F6
F7
F8
0.65
0.62
4.9
0.7
F9
0.67
5
F10
F11
4.46
4.56
F10
M0139-01
For recommended circuit layout for PCB designs, see application note
SLPA005
–
Reducing Ringing Through
PCB Layout Techniques
.
Q5 Tape and Reel Information
K0
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50
0.10
B0 = 5.30
0.10
K0 = 1.40
0.10
M0138-01
Notes:
1. 10-sprocket
hole-pitch cumulative tolerance ±0.2
2. Camber
not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material:
black static-dissipative polystyrene
4. All
dimensions are in mm, unless otherwise specified.
5. A0
and B0 measured on a plane 0.3mm above the bottom of the pocket
6. MSL1
260°C (IR and convection) PbF reflow compatible
Copyright © 2009–2010, Texas Instruments Incorporated
7
SLPS218C
–
A
UGUST 200
9
–
R
EVISED APRIL 2010
REVISION HISTORY
Changes from Original (August 2009) to Revision A
Page
•
Changes from Revision A (September 2009) to Revision B
Page
•
•
•
•
•
•
Changed Note 1 of the ABSOLUTE MAXIMUM RATINGS From: R
q
JA
= 38°C/W To: Typical R
q
JA
= 38°C/W ………………..
1
Changes from Revision B (April 2010) to Revision C
Page
•
•
Changed R
DS(on)
– V
GS
= 3V in the Electrical Characteristics table From: 2.7 to 2.9 in the max column …………………………
2
8
Copyright © 2009–2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
7-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
CSD16325Q5
ACTIVE
VSON-CLIP
DQH
8
2500 Pb-Free
(RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD16325
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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