Texas-Instruments-CSD16327Q3T
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CSD16327Q3 25V N
沟道
NexFET™
功率
MOSFET
1
特性
产品概要
1
•
•
•
•
•
•
•
•
针对
5V
栅极驱动器进行优化
T
A
= 25°C
典型值
25
单位
V
超低
Q
g
和
Q
gd
低热阻
V
DS
Q
g
漏源电压
总栅极电荷
(4.5V)
栅极电荷（栅极到漏极）
6.2
nC
nC
雪崩级
Q
gd
1.1
V
GS
=3V
5
4
无铅引脚镀层
符合
RoHS
标准
无卤素
R
DS(on)
漏源导通电阻
V
GS
= 4.5V
V
GS
= 8V
m
Ω
3.4
V
GS(th)
阈值电压
1.2
V
小外形尺寸无引线
(SON) 3.3mm × 3.3mm
塑料封
装
.
2
应用范围
器件
包装介质
数量
封装
发货
CSD16327Q3
CSD16327Q3T
13
英寸卷带
7
英寸卷带
2500
小外形尺寸无引线
(SON)
3.30mm × 3.30mm
塑料封装
•
用于网络、电信和计算系统中的 应用的 负载点同
步降压转换器
卷带式
250
•
已针对控制或同步
FET
应用进行优化
(1)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3
说明
这款
25V
、
3.4m
Ω
、
SON 3.3mm × 3.3mm NexFET™
功率
MOSFET
旨在最大限度降低功率转换应用中的功
率损耗并经优化以适用于
5V
栅极驱动器 应用。
绝对最大额定值
T
A
= 25°C
值
25
单位
V
V
DS
V
GS
漏源电压
栅源电压
+10 / –8
60
V
顶视图
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），
T
C
= 25°C
时
测得
I
D
112
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
22
240
2.8
74
I
DM
P
D
A
W
功率耗散，
T
C
= 25°C
T
J
、 工作结温、
D
–55
至
150
°C
T
stg
储存温度
D
雪崩能量，单脉冲
I
D
= 50A
，
L = 0.1mH
，
R
G
= 25
Ω
P0095-01
E
AS
125
mJ
(1) R
θ
JA
= 45°C/W
，这是在一块厚度为
0.06
英寸环氧树脂
(FR4)
印刷电路板
(PCB)
上的
1
英寸，
2
盎司覆铜上测得的典型值。
(2)
最大
R
θ
JC
= 1.7°C/W
，脉宽
≤
100
μ
s
，占空比
≤
1%
。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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R
DS(on)
与
V
GS
对比
栅极电荷
16
8
7
6
5
4
3
2
1
0
I
D
= 24 A
DS
= 12.5 V
T
C
= 25
è
C, I
D
= 24 A
T
C
= 125
è
C, I
D
= 24 A
V
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
V
GS
– Gate-to-Source Voltage (V)
Q
g
– Gate Charge (nC)
D007
D004
2
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© 2011–2016, Texas Instruments Incorporated
ZHCS656A
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目录
1
2
3
4
5
7
6
4
修订历史记录
Changes from Original (December 2011) to Revision A
Page
•
•
•
•
•
•
•
•
•
版权
© 2011–2016, Texas Instruments Incorporated
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5 Specifications
5.1 Electrical
Characteristics
T
A
= 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BV
DSS
I
DSS
Drain-to-source voltage
V
GS
= 0 V, I
D
= 250
μ
A
25
V
μ
A
nA
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
V
GS
= 0 V, V
DS
= 20 V
V
DS
= 0 V, V
GS
= +10 / –8 V
V
DS
= V
GS
, I
D
= 250
μ
A
V
GS
= 3 V, I
D
= 24 A
1
100
1.4
6.5
4.8
4.0
I
GSS
V
GS(th)
0.9
1.2
5
R
DS(on)
Drain-to-source on-resistance
V
GS
= 4.5 V, I
D
= 24 A
V
GS
= 8 V, I
D
= 24 A
4
m
Ω
3.4
96
g
fs
Transconductance
V
DS
= 12.5 V, I
D
= 24 A
S
DYNAMIC CHARACTERISTICS
C
ISS
C
OSS
C
RSS
R
g
Input capacitance
1020
740
50
1300
960
65
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at V
th
Output charge
V
GS
= 0 V, V
DS
= 12.5 V, ƒ = 1 MHz
1.4
6.2
1.1
1.8
1
2.8
Q
g
8.4
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Qg(th)
Q
OSS
t
d(on)
t
r
V
DS
= 12.5 V, I
D
= 24 A
V
DS
= 12.5 V, V
GS
= 0 V
14
Turnon delay time
Rise time
5.3
15
V
DS
= 12.5 V, V
GS
= 4.5 V I
D
= 24 A
R
G
= 2
Ω
t
d(off)
t
f
Turnoff delay time
Fall time
13
6.3
DIODE CHARACTERISTICS
V
SD
Q
rr
t
rr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
I
S
= 24 A, V
GS
= 0 V
0.85
21
1
V
V
DD
= 12.5 V, I
F
= 24 A, di/dt = 300 A/
μ
s
V
DD
= 12.5 V, I
F
= 24 A, di/dt = 300 A/
μ
s
nC
ns
16
5.2 Thermal
Information
T
A
= 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance
(1)
Junction-to-ambient thermal resistance
(1
)
(
2)
MIN
TYP
MAX
1.7
UNIT
°C/W
°C/W
R
θ
JC
R
θ
JA
55
(1)
R
θ
JC
is determined with the device mounted on a 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. R
θ
JC
is specified by design, whereas R
θ
JA
is determined by the user’s board design.
(2) Device
mounted on FR4 material with 1-in
2
(6.45-cm
2
), 2-oz (0.071-mm) thick Cu.
4
Copyright © 2011–2016, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
θ
JA
= 160°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
Max R
θ
JA
= 55°C/W
when mounted on 1-in
2
(6.45-cm
2
) of 2-oz
(0.071-mm) thick Cu.
DRAIN
DRAIN
M0161-02
M0161-01
5.3 Typical
MOSFET Characteristics
T
A
= 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2011–2016, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
100
100
80
60
40
20
0
T
C
= 125°C
T
C
= 25°C
T
C
= -55°C
90
80
70
60
50
40
30
20
V
GS
= 3 V
V
GS
= 4.5 V
V
GS
= 8 V
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
DS
– Drain-to-Source Voltage (V)
1
1
1.25
1.5
1.75
2
2.25
2.5
2.75
V
GS
– Gate-to-Source Voltage (V)
D002
D003
V
DS
= 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
8
7
6
5
4
3
2
1
0
10000
1000
100
C
iss
= C
gd
+ C
gs
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
10
0
2
4
6
8
10
12
0
5
10
15
20
25
Q
g
– Gate Charge (nC)
V
DS
– Drain-to-Source Voltage (V)
D004
D005
I
D
= 24 A
V
DS
= 12.5 V
Figure 4. Gate Charge
Figure 5. Capacitance
1.6
1.4
1.2
1
16
14
12
10
8
T
C
= 25
è
C, I
D
= 24 A
T
C
= 125
è
C, I
D
= 24 A
6
4
0.8
2
0.6
0
0
-75 -50 -25
0
25
50
75 100
125 150 175
1
2
3
4
5
6
7
8
9
10
T
C
– Case Temperature (
è
C)
V
GS
– Gate-to-Source Voltage (V)
D006
D007
I
D
= 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
6
Copyright © 2011–2016, Texas Instruments Incorporated
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Typical MOSFET Characteristics (continued)
T
A
= 25°C (unless otherwise stated)
1.6
100
10
V
GS
= 4.5 V
T
C
= 25°C
T
C
= 125°C
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.2
0.4
0.6
0.8
1
-75 -50 -25
0
25
50
75 100
125 150 175
V
SD
– Source-to-Drain Voltage (V)
T
C
– Case Temperature (°C)
D008
D009
I
D
= 24 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
1000
100
100
10
1
100 ms
10 ms
1 ms
100 µs
10 µs
T
C
= 25
è
C
T
C
= 125
è
C
0.1
0.1
10
0.01
1
10
100
0.1
1
V
DS
– Drain-to-Source Voltage (V)
T
AV
– Time in Avalanche (ms)
D010
D011
Single pulse, max R
θ
JC
= 1.7°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
70
60
50
40
30
20
10
0
-50
-25
0
25
50
75
100 125 150 175
T
C
– Case Temperature (
è
C)
D012
Figure 12. Maximum Drain Current vs Temperature
Copyright © 2011–2016, Texas Instruments Incorporated
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6
器件和文档支持
6.1
接收文档更新通知
如需接收文档更新通知，请导航至
TI.com
上的器件产品文件夹。单击右上角的
通知我
进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
6.2
社区资源
下列链接提供到
TI
社区资源的连接。链接的内容由各个分销商
“
按照原样
”
提供。这些内容并不构成
TI
技术规范，
e2e.ti.com
中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI
参考设计支持
可帮助您快速查找有帮助的
E2E
论坛、设计支持工具以及技术支持的联系信息。
6.3
商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4
静电放电警告
这些装置包含有限的内置
ESD
保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止
MOS
门极遭受静电损
伤。
6.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
8
版权
© 2011–2016, Texas Instruments Incorporated
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7
机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
7.1 Q3
封装尺寸
毫米
标称值
英寸
标称值
DIM
最小值
0.950
0.000
0.280
最大值
1.100
0.050
0.400
最小值
0.037
0.000
0.011
最大值
0.043
0.002
0.016
A
A1
b
1.000
0.000
0.340
0.039
0.000
0.013
0.310
（标
称值）
0.012
（标称
值）
b1
c
D
0.150
3.200
1.650
0.150
0.300
3.200
2.350
0.200
3.300
1.750
0.200
0.350
3.300
2.450
0.250
3.400
1.800
0.250
0.400
3.400
2.550
0.006
0.126
0.065
0.006
0.012
0.126
0.093
0.008
0.130
0.010
0.134
0.071
0.010
0.016
0.134
0.100
D2
d
0.069
0.008
d1
E
0.014
0.130
E2
0.096
0.650
典型
值
0.026
典型值
e
H
K
0.35
0.450
0.550
0.014
0.018
0.022
0.650
典型
值
0.026
典型值
L
L1
θ
0.35
0
0.450
—
0.550
0.014
0.018
—
0.022
0
0
0
0
0
0
0
—
—
版权
© 2011–2016, Texas Instruments Incorporated
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7.2
建议
PCB
布局
7.3
建议模版开孔
全部尺寸单位为
mm
，除非另外注明。
10
版权
© 2011–2016, Texas Instruments Incorporated
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7.4 Q3
卷带信息
4.00 0.ꢀ0
ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
+0.ꢀ0
–0.00
Ø ꢀ.ꢃ0
3.60
M0ꢀ44-0ꢀ
注：
1. 10
个链齿孔间距的累积容差为
±0.2
。
2.
每
100mm
长度的外倾角不能超过
1mm
，在
250mm
长度上不累积。
3.
材料：黑色抗静电聚苯乙烯。
4.
全部尺寸单位为
mm
，除非另外注明。
5.
厚度：
0.30 ± 0.05mm
。
6. MSL1
260°C
（红外
(IR)
和传导）无铅回流焊兼容。
版权
© 2011–2016, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD16327Q3
CSD16327Q3T
ACTIVE
VSON-CLIP
VSON-CLIP
DQG
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD16327
CSD16327
ACTIVE
DQG
RoHS-Exempt
& Green
SN
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may
reference these types of products as “Pb-Free”.
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
重要声明和免责声明
TI
均以
“
原样
”
提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用
TI
产品进行设计使用。您将对以下行为独自承担全部责任：
(1)
针对您的应用选择合适的
TI
产品；
(2)
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