Texas-Instruments-CSD17301Q5A
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SLPS215C
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30V, N-Channel NexFET™
Power MOSFETs
1
FEATURES
PRODUCT SUMMARY
2
•
•
•
•
•
•
•
•
Optimized for 5V Gate Drive
V
DS
Q
g
Drain to Source Voltage
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
30
19
V
Ultralow Q
g
and Q
gd
nC
nC
m
Ω
m
Ω
m
Ω
V
Low Thermal Resistance
Avalanche Rated
Q
gd
4.3
V
GS
= 3V
2.9
2.3
2
R
DS(on)
Drain to Source On Resistance
V
GS
= 4.5V
V
GS
= 8V
Pb Free Terminal Plating
RoHS Compliant
V
GS(th)
Threshold Voltage
1.1
Halogen Free
SON 5-mm × 6-mm Plastic Package
ORDERING INFORMATION
Device
CSD17301Q5A
Package
Media
Qty
Ship
APPLICATIONS
SON 5-mm × 6-mm
Plastic Package
13-inch
reel
Tape and
Reel
2500
•
Notebook Point of Load
•
Point-of-Load Synchronous Buck in
Networking, Telecom and Computing Systems
ABSOLUTE MAXIMUM RATINGS
•
Optimized for Synchronous FET Applications
T
A
= 25°C unless otherwise stated
VALUE
UNIT
V
V
DS
V
GS
Drain to Source Voltage
30
DESCRIPTION
Gate to Source Voltage
+10 / –8
100
V
Continuous Drain Current, T
C
= 25°C
A
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications,
and optimized for 5V gate drive applications.
I
D
28
A
I
DM
P
D
T
J
,
181
A
3.2
W
Top View
Operating Junction and Storage
–55 to 150
414
°C
T
STG
Temperature Range
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
Avalanche Energy, single pulse
I
D
= 91A, L = 0.1mH, R
G
= 25
Ω
E
AS
mJ
(1) Typical
R
q
JA
=
39°C/W on 1-inch
2
(6.45-cm
2
), 2-oz.
(0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4
PCB.
D
D
(2) Pulse
duration
≤
300
m
s, duty cycle
≤
2%
P0093-01
R
DS(on)
vs V
GS
GATE CHARGE
10
9
8
7
6
5
4
3
2
1
0
8
I
D
= 25A
I
D
= 25A
V
DS
= 15V
7
6
5
4
3
2
1
0
T
C
= 125
°
C
T
C
= 25
°
C
0
1
2
3
4
5
6
7
8
9
10
0
5
10
15
20
25
30
V
GS
– Gate-to-Source Voltage – V
Q
g
– Gate Charge – nC
G006
G003
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Static Characteristics
BV
DSS
I
DSS
Drain to Source Voltage
V
GS
= 0V, I
D
= 250
m
A
30
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
V
GS
= 0V, V
DS
= 24V
V
DS
= 0V, V
GS
= +10 / –8V
V
DS
= V
GS
, I
D
= 250
m
A
V
GS
= 3V, I
D
= 25A
1
100
1.55
3.7
3
m
A
nA
V
I
GSS
V
GS(th)
0.9
1.1
2.9
2.3
2
m
Ω
m
Ω
m
Ω
S
R
DS(on)
Drain to Source On Resistance
Transconductance
V
GS
= 4.5V, I
D
= 25A
V
GS
= 8V, I
D
= 25A
2.6
g
fs
V
DS
= 15V, I
D
= 25A
149
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
2660
1420
80
3480
1850
105
2.6
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
V
GS
= 0V, V
DS
= 15V, f = 1MHz
1.3
Q
g
19
25
nC
nC
nC
nC
nC
ns
ns
ns
ns
Q
gd
Q
gs
Q
g(th)
Q
oss
t
d(on)
t
r
4.3
V
DS
= 15V, I
D
= 25A
5.7
2.9
V
DS
= 14V, V
GS
= 0V
35
Turn On Delay Time
Rise Time
10.7
16.2
28
V
DS
= 15V, V
GS
= 4.5V, I
D
= 25A, R
G
= 2
Ω
t
d(off)
t
f
Turn Off Delay Time
Fall Time
10.5
Diode Characteristics
V
SD
Q
rr
t
rr
Diode Forward Voltage
I
SD
= 25A, V
GS
= 0V
0.8
50
33
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
V
DD
= 14V, I
F
= 25A, di/dt = 300A/
m
s
THERMAL CHARACTERISTICS
(T
A
= 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case
(1)
Thermal Resistance Junction to Ambient
(1
)
(
2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
R
q
JC
R
q
JA
2.2
49
(1)
R
q
JC
is determined with the device mounted on a 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. R
q
JC
is specified by design, whereas R
q
JA
is determined by the user’s board design.
(2) Device
mounted on FR4 material with 1-inch
2
(6.45-cm
2
), 2-oz. (0.071-mm thick) Cu.
2
Copyright © 2010, Texas Instruments Incorporated
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GATE
Source
GATE
Source
Max R
q
JA
= 120°C/W
when mounted on
minimum pad area of 2
oz. Cu.
Max R
q
JA
= 49°C/W
when mounted on
1inch
2
of 2 oz. Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(T
A
= 25°C unless otherwise stated)
10
1
0.5
0.3
Duty Cycle = t
1
/t
2
0.1
0.1
0.05
P
0.02
0.01
t
1
0.01
t
2
Typical R
q
JA
= 96
°
C/W (min Cu)
T
J
= P
´
Z
q
JA
´
R
q
JA
Single Pulse
0.001
0.001
0.01
0.1
1
10
100
1k
t
p
– Pulse Duration – s
G012
Figure 1.
Transient Thermal Impedance
Copyright © 2010, Texas Instruments Incorporated
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TYPICAL MOSFET CHARACTERISTICS (continued)
(T
A
= 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
DS
= 5V
V
GS
= 8V
V
GS
= 4.5V
V
GS
= 3V
T
C
= 125
°
C
T
C
= 25
°
C
V
GS
= 2.5V
T
C
= -55
°
C
V
GS
= 2V
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
2.5
3
V
DS
– Drain-to-Source Voltage – V
V
GS
– Gate-to-Source Voltage – V
G001
G002
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
I
D
= 25A
V
DS
= 15V
f = 1MHz
V
GS
= 0V
C
oss
= C
ds
+ C
gd
C
iss
= C
gd
+ C
gs
C
rss
= C
gd
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Q
g
– Gate Charge – nC
V
DS
– Drain-to-Source Voltage – V
G003
G004
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.4
1.2
1
10
9
8
7
6
5
4
3
2
1
0
I
D
= 250
µ
A
I
D
= 25A
0.8
0.6
0.4
0.2
0
T
C
= 125
°
C
T
C
= 25
°
C
-75
-25
25
75
125
175
0
1
2
3
4
5
6
7
8
9
10
T
C
– Case Temperature –
°
C
V
GS
– Gate-to-Source Voltage – V
G005
G006
Figure 6. Threshold Voltage vs. Temperature
Figure 7. On Resistance vs. Gate Voltage
4
Copyright © 2010, Texas Instruments Incorporated
SLPS215C
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ANUARY 201
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TYPICAL MOSFET CHARACTERISTICS (continued)
(T
A
= 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.8
1.6
1.4
1.2
1
100
10
I
D
= 25A
V
GS
= 4.5V
1
T
C
= 125
°
C
0.1
T
C
= 25
°
C
0.8
0.6
0.4
0.2
0.01
0.001
0.0001
-75
-25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
T
C
– Case Temperature –
°
C
V
SD
– Source-to-Drain Voltage – V
G007
G008
Figure 8. On Resistance vs. Temperature
TEXT ADDED FOR SPACING
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
1k
100
10
1k
100
10
1ms
T
C
= 25
°
C
10ms
1
1
0
0
0
0
m
1
s
1s
1
T
C
= 125
°
C
Area Limited
by R
DS(on)
0.1
0.01
Single Pulse
Typical R
θ
JA
= 96
°
C/W (min Cu)
DC
1
0.01
0.1
1
10
100
0.01
0.1
1
10
100
V
DS
– Drain-to-Source Voltage – V
t
(AV)
– Time in Avalanche – ms
G009
G010
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125 150 175
T
C
– Case Temperature –
°
C
G011
Figure 12.
Maximum Drain Current vs. Temperature
Copyright © 2010, Texas Instruments Incorporated
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MECHANICAL DATA
Q5A Package Dimensions
E2
L
H
K
q
L1
Top View
Side View
Bottom View
q
E1
E
Front View
M0135-01
MILLIMETERS
NOM
1.00
DIM
MIN
0.90
0.33
0.20
4.80
3.61
5.90
5.70
3.38
1.17
0.41
1.10
0.51
0.06
0°
MAX
1.10
0.51
0.34
5.00
4.02
6.10
5.80
3.78
1.37
0.71
A
b
0.41
c
0.25
D1
D2
E
4.90
3.81
6.00
E1
E2
e
5.75
3.58
1.27
H
0.56
K
L
0.61
0.13
0.71
0.20
12°
L1
q
6
Copyright © 2010, Texas Instruments Incorporated
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MILLIMETERS
INCHES
DIM
Recommended PCB Pattern
MIN
MAX
6.305
4.56
4.56
0.7
MIN
MAX
0.248
0.18
F1
F1
F2
6.205
4.46
4.46
0.65
0.62
0.63
0.7
0.244
0.176
0.176
0.026
0.024
0.025
0.028
0.026
0.024
0.193
0.176
F7
F6
F3
0.18
F4
0.028
0.026
0.027
0.031
0.028
0.026
0.197
0.18
F5
0.67
0.68
0.8
F6
F7
F8
0.65
0.62
4.9
0.7
F9
0.67
5
F10
F11
4.46
4.56
F10
M0139-01
For recommended circuit layout for PCB designs, see application note
SLPA005
–
Reducing Ringing Through
PCB Layout Techniques
.
Q5A Tape and Reel Information
K0
4.00 0.10
ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50
0.10
B0 = 5.30
0.10
K0 = 1.40
0.10
M0138-01
Notes:
1. 10-sprocket
hole-pitch cumulative tolerance ±0.2
2. Camber
not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material:
black static-dissipative polystyrene
4. All
dimensions are in mm (unless otherwise specified)
5. A0
and B0 measured on a plane 0.3mm above the bottom of the pocket
Copyright © 2010, Texas Instruments Incorporated
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REVISION HISTORY
Changes from Original (January) to Revision A
Page
•
•
Changed the Abs Max Ratings table, Avalanche Energy, single pulse From: I
D
= 85A, L = 0.1mH, R
G
= 25
Ω
Value =
Changes from Revision A (February 2010) to Revision B
Page
•
•
•
Updated the Q5A Package Dimensions table. DIM c MAX was 0.30, DIM D2 MAX was 3.96, DIM e MIN was blank
Deleted Note 6 from the Q5A Tape and Reel Information – “MSL1 260°C (IR and convection) PbF reflow
Changes from Revision B (July 2010) to Revision C
Page
•
Changed the Abs Max Ratings table, Pulsed Drain Current value From: 118 To: 181 ………………………………………………..
1
8
Copyright © 2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
7-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status Package
Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
CSD17301Q5A
ACTIVE
VSONP
DQJ
8
2500 Pb-Free
(RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD17301
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
(2)
Eco Plan – The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) – please check
http://www.ti.com/productcontent
for the latest availability
information and additional product content details.
TBD:
The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS):
TI’s terms “Lead-Free” or “Pb-Free” mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt):
This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based
die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br):
TI defines “Green” to mean Pb-Free (RoHS compatible), and free of Bromine (Br)
and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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