Texas-Instruments-CSD17484F4T

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Texas-Instruments-CSD17484F4T

ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
CSD17484F4 30V N
沟
道
FemtoFET

™

MOSFET  
产品概要  
1
特性  
T

A

= 25°C  
典型值  
单位  
V

DS  

Q

g  

30  
V
漏源电压  
• 低导通电阻  
• 超
低
Q

g

和
Q

gd  

• 低阈值电压  
• 超小封装尺寸
(
0402
外壳尺寸
)  
–
1.0mm × 0.6mm  
• 超薄型封装  
920  
75  
pC  
pC  
总栅极电
荷
(4.5V)  
Q

gd  

栅极电荷
(
栅极到漏极
)  
漏源导通电阻  
V

GS

= 1.8V  
170  
125  
107  
99  
V

GS

= 2.5V  
V

GS

= 4.5V  
V

GS

= 8.0V  
R

DS(on)  

m
Ω  
– 厚度
为
0.2mm  
V

GS(th)  

0.85  
V
阈值电压  
• 集成
型
ESD
保护二极管  
– 额定
值
> 4kV HBM  
– 额定
值
> 2kV CDM  
• 无铅且无卤素  
器件信息

介质  
器件  
数量  
封装  
配送  
CSD17484F4  
3000  
Femto (0402)  
卷带  
包装  
1.00mm × 0.60mm  
7
英寸卷带  
• 符
合
RoHS  
CSD17484F4T  
250  
基板栅格阵
列
(LGA)  
2
应用  
(1)
如需了解所有可用封装
,
请参阅数据表末尾的可订购产品附  
录。  
• 针对负载开关应用进行了优化  
• 针对通用开关应用进行了优化  
• 电池应用  
绝对最大额定值  
T

A

= 25°C  
值
30  
12  
单位  
V
• 手持式和移动类应用  
V

DS  

V

GS  

I

D  

漏源电压  
3
说明  
V
栅源电压  
持续漏极电流

脉冲漏极电流

持续栅极钳位电流  
脉冲栅极钳位电流

功率耗散  
3.0  
18  
35  
350  
500  
4
A
A
该
99m
Ω、
30V N
沟道
FemtoFET

™

MOSFET
经过设  
计和优化
,
能够最大限度地减小在许多手持式和移动应  
用中占用的空间。这项技术能够在替代标准小信号  
MOSFET
的同时将封装尺寸减小至
少
60%
。  
I

DM  

I

G  

mA  
mW  
kV  
P

D  

人体放电模
型
(HBM)  
充电器件模
型
(CDM)  
V

(ESD)  

2
T

J

、  
T

stg  

工作结温
,  
贮存温度  
–
55
至  
150  
°C  
雪崩能量
,
单脉
冲
I

D

= 7.1 A
,  
L = 0.1mH
,
R

G

= 25
Ω  
E

AS  

2.5  
mJ  
0.20 mm  
(1)
典
型
R

θ
JA

= 85°C/W
(
在
0.06
英
寸
(1.52mm)
厚
的
FR4 PCB  
上安
装
1
平方英
寸
(6.45cm

2

)
、
2oz
、  
0.071mm
厚的铜焊盘时
)
。  
(2)
脉冲持续时
间
≤
100
μ
s
,
占空
比
≤
1%
。  
0.60 mm  
1.00 mm  
D
图
3-1.
典型器件尺寸  
G
S
图
3-2.
顶视图  
本文档旨在为方便起见
,
提供有
关
TI
产品中文版本的信息
,
以确认产品的概要。有关适用的官方英文版本的最新信息
,
请访问  

www.ti.com

,
其内容始终优先。
TI
不保证翻译的准确性和有效性。在实际设计之前
,
请务必参考最新版本的英文版本。  
English Data Sheet:

 
 
 
 
 
 

ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
Table of Contents  
4 Revision History  
Changes from Revision C (December 2019) to Revision D (February 2022)  
Page  
•
Added FemtoFET Surface Mount Guide note……………………………………………………………………………………….

Changes from Revision B (September 2017) to Revision C (December 2019)  
Page  
•
Changed On-State Resistance vs Gate-to-Source Voltage by truncating V

GS

from 20 V to 12 V…………………
.

Changes from Revision A (August 2017) to Revision B (September 2017)  
Page  
•
Deleted the
CSD68830F4 Embossed Carrier
T
a
pe Dimensions
section……………………………………………………

Changes from Revision * (May 2015) to Revision A (August 2017)  
Page  
•
Added the

and the

sections
………………………………………………………………………………………………
.

•
Updated the

section……………………………………………………………………………………………………………………

Copyright © 2022
T
e
xas Instruments Incorporated  
2
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
5 Specifications  
5.1 Electrical Characteristics  
T

A

= 25°C (unless otherwise stated)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
STATIC CHARACTERISTICS  
BV

DSS  

I

DSS  

Drain-to-source voltage  
30  
V
nA  
nA  
V
V

GS

= 0
V
,
I

DS

= 250
μ
A  
Drain-to-source leakage current  
Gate-to-source leakage current  
Gate-to-source threshold voltage  
V

GS

= 0
V
,
V

DS

= 24 V  
V

DS

= 0
V
,
V

GS

= 12 V  
V

DS

= V

GS

, I

DS

= 250
μ
A  
V

GS

= 1.8
V
,
I

DS

= 0.5 A  
V

GS

= 2.5
V
,
I

DS

= 0.5 A  
V

GS

= 4.5
V
,
I

DS

= 0.5 A  
V

GS

= 8
V
,
I

DS

= 0.5 A  
V

DS

= 15
V
,
I

DS

= 0.5 A  
100  
50  
I

GSS  

V

GS(th)  

0.65  
0.85  
170  
125  
107  
99  
1.10  
270  
160  
128  
121  
R

DS(on)  

Drain-to-source on-resistance  
Transconductance  
m
Ω  
g

fs  

4
S
DYNAMIC CHARACTERISTICS  
C

iss  

C

oss  

C

rss  

R

G  

Input capacitance  
150  
44  
195  
57  
pF  
pF  
pF  
V

GS

= 0
V
,
V

DS

= 15
V
,  
ƒ
= 1 MHz  
Output capacitance  
Reverse transfer capacitance  
Series gate resistance  
Gate charge total (4.5 V)  
Gate charge total (8.0 V)  
Gate charge gate-to-drain  
Gate charge gate-to-source  
Gate charge at V

th  

Output charge  
2.2  
8
2.9  
Ω
Q

g  

920  
1570  
75  
1200  
2040  
pC  
pC  
pC  
pC  
pC  
pC  
ns  
Q

g  

Q

gd  

Q

gs  

Q

g(th)  

Q

oss  

t

d(on)  

t

r  

V

DS

= 15
V
,
I

DS

= 0.5 A  
V

DS

= 15
V
,
V

GS

= 0 V  
280  
140  
1400  
3
Turnon delay time  
Rise time  
1
ns  
V

DS

= 15
V
,
V

GS

= 4.5
V
,  
I

DS

= 0.5 A, R

G

= 2
Ω  
t

d(off)  

t

f  

Turnoff delay time  
11  
ns  
Fall time  
4
ns  
DIODE CHARACTERISTICS  
V

SD  

Q

rr  

t

rr  

Diode forward voltage  
Reverse recovery charge  
Reverse recovery time  
I

SD

= 0.5 A, V

GS

= 0 V  
0.73  
1300  
6.2  
0.9  
V
pC  
ns  
V

DS

= 15
V
,
I

F

= 0.5 A, di/dt = 300 A/
μ
s  
5.2 Thermal Information  
T

A

= 25°C (unless otherwise stated)  
THERMAL METRIC  
Junction-to-ambient thermal resistance

Junction-to-ambient thermal resistance

TYPICAL VALUES  
UNIT  
85  
R

θ
JA  

°C/W  
245  
(1) Device
 
mounted on FR4 material with 1-in

2

(6.45-cm

2

), 2-oz (0.071-mm) thick Cu.  
(2) Device
 
mounted on FR4 material with minimum Cu mounting area.  
Copyright © 2022
T
e
xas Instruments Incorporated  
3
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
5.3 Typical MOSFET Characteristics  
T

A

= 25°C (unless otherwise stated)  
10  
10  
9
8
7
6
5
4
3
2
1
0
V

GS

= 1.8 V  
V

GS

= 2.5 V  
V

GS

= 3.8 V  
V

GS

= 4.5 V  
T

C

= 125°C  
T

C

= 25°C  
T

C

= -55°C  
9
8
7
6
5
4
3
2
1
0
0
0.25  
0.5  
V

DS

– Drain-to-Source Voltage (V)  
0.75  
1
1.25  
1.5  
1.75  
2
0
0.5  
1
V

GS

– Gate-to-Source Voltage (V)  
1.5  
2
2.5  
3
3.5  
4
D002  
D003  
V

DS

= 5 V  
图
5-1. Saturation Characteristics  
图
5-2. Transfer Characteristics  
图
5-3. Transient Thermal Impedance  
Copyright © 2022
T
e
xas Instruments Incorporated  
4
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
8
7
6
5
4
3
2
1
1000  
100  
10  
C

iss

= C

gd

+ C

gs  

C

oss

= C

ds

+ C

gd  

C

rss

= C

gd  

1
0
0
0
3
6
9
12  
15  
18  
21  
V

DS

– Drain-to-Source Voltage (V)  
24  
27  
30  
0.2  
0.4  
0.6  
0.8  
1
Q

g

– Gate Charge (nC)  
1.2  
1.4  
1.6  
D005  
D004  
图
5-5. Capacitance  
I

D

= 0.5 A  
V

DS

= 15 V  
图
5-4. Gate Charge  
1.15  
1.05  
0.95  
0.85  
0.75  
0.65  
0.55  
0.45  
0.35  
250  
225  
200  
175  
150  
125  
100  
75  
T

C

= 25
è
C, I

D

= 0.5 A  
T

C

= 125
è
C, I

D

= 0.5 A  
50  
-75 -50 -25  
0
25  
50  
T

C

– Case Temperature (°C)  
75 100
 
125 150 175  
0
2
4
6
8
V

GS

– Gate-to-Source Voltage (V)  
10  
12  
D006  
D007  
I

D

= 250 µA  
图
5-7. On-State Resistance vs Gate-to-Source  
Voltage  
图
5-6. Threshold Voltage vs Temperature  
10  
1.5  
T

C

= 25
è
C  
T

C

= 125
è
C  
V

GS

= 2.5 V  
V

GS

= 4.5 V  
1.4  
1.3  
1.2  
1.1  
1
1
0.1  
0.01  
0.9  
0.8  
0.7  
0.001  
0.0001  
0
0.2  
0.4  
0.6  
V

SD

– Source-To-Drain Voltage (V)  
0.8  
1
-75 -50 -25  
0
25  
50  
75 100
 
125 150 175  
D009  
T

C

– Case Temperature (
è
C)  
D008  
图
5-9. Typical Diode Forward Voltage  
I

D

= 0.5 A  
图
5-8. Normalized On-State Resistance vs  
Temperature  
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e
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
100  
10  
1
100  
10  
1
T

C

= 25
è
C  
T

C

= 125
è
C  
0.1  
100 ms  
10 ms  
1 ms  
100 µs  
10 µs  
0.01  
0.01  
0.1  
0.001  
0.1  
V

DS

– Drain-To-Source Voltage (V)  
1
10  
50  
0.01 0.1  
T

AV

– Time in Avalanche (ms)  
1
D010  
D011  
Single pulse, typical R

θ
JA

= 85°C/W  
图
5-11. Single Pulse Unclamped Inductive  
Switching  
图
5-10. Maximum Safe Operating Area  
3.5  
3
2.5  
2
1.5  
1
0.5  
0
-50  
-25  
0
25  
50  
T

A

– Ambient Temperature (°C)  
75  
100 125 150 175  
D012  
图
5-12. Maximum Drain Current vs Temperature  
Copyright © 2022
T
e
xas Instruments Incorporated  
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
6 Device and Documentation Support  
6.1 Receiving Notification of Documentation Updates  
To
r
eceive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on
Alert me
to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
6.2 Trademarks  
FemtoFET

™

is a trademark of
T
e
xas Instruments.  
所有商标均为其各自所有者的财产。  
Copyright © 2022
T
e
xas Instruments Incorporated  
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
7 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
7.1 Mechanical Dimensions  
A. All
 
linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).  
B. This
 
drawing is subject to change without notice.  
C. This
 
package is a PB-free solder land design.  
表
7-1. Pin Configuration  
POSITION  
DESIGNATION  
Pin 1  
Gate  
Pin 2  
Source  
Pin 3  
Drain  
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ZHCSDO7D

–
MAY 2015
–
REVISED FEBRUARY 2022  
7.2 Recommended Minimum PCB Layout  
(0.25)  
2X (0.25)  
PKG  
0.05 MIN  
ALL AROUND  
2X (0.15)  
1
3
SYMM  
(0.5)  
(0.35)  
2
(R0.05) TYP  
SOLDER MASK  
OPENING  
(0.65)  
METAL UNDER  
SOLDER MASK  
LAND PATTERN EXAMPLE  
A. All
 
dimensions are in millimeters.  
B. For
 
more information, see

(SLRA003D).  
7.3 Recommended Stencil Pattern  
2X (0.25)  
PKG  
2X (0.2)  
(0.25)  
1
SYMM  
3
(0.4)  
(0.5)  
2
2X (0.15)  
(R0.05) TYP  
(0.65)  
2X SOLDER MASK EDGE  
A. All
 
dimensions are in millimeters.  
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PACKAGE OPTION ADDENDUM  
24-Feb-2022  
PACKAGING INFORMATION  
Orderable Device  
Status Package
 
Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
CSD17484F4  
ACTIVE  
ACTIVE  
PICOSTAR  
PICOSTAR  
YJJ  
YJJ  
3
3
3000 RoHS
 
& Green  
250 RoHS
 
& Green  
NIAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-55 to 150  
-55 to 150  
G2  
G2  
CSD17484F4T  
NIAU  

(1)

The marketing status values are defined as follows:  
ACTIVE:
Product device recommended for new designs.  
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE:
TI has discontinued the production of the device.  

(2)

RoHS:
TI defines “RoHS” to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, “RoHS” products are suitable for use in specified lead-free processes. TI may  
reference these types of products as “Pb-Free”.  
RoHS Exempt:
TI defines “RoHS Exempt” to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green:
TI defines “Green” to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  

(3)

MSL, Peak Temp. – The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a “~” will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material – Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:
The information provided on this page represents TI’s knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI’s liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  

PACKAGE OPTION ADDENDUM  
24-Feb-2022  
Addendum-Page 2  

PACKAGE MATERIALS INFORMATION  
24-Feb-2022  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width
 
(mm) (mm) (mm) (mm) (mm)
 
Quadrant  
(mm) W1
 
(mm)  
CSD17484F4  
PICOST  
AR  
YJJ  
YJJ  
3
3
3000  
250  
178.0  
9.2  
0.7  
1.1  
0.28  
4.0  
8.0  
Q2  
CSD17484F4T  
PICOST  
AR  
178.0  
9.2  
0.7  
1.1  
0.28  
4.0  
8.0  
Q2  
Pack Materials-Page 1  

PACKAGE MATERIALS INFORMATION  
24-Feb-2022  
*All dimensions are nominal  
Device  
Package Type
 
Package Drawing
 
Pins  
SPQ  
Length (mm)
 
Width (mm)
 
Height (mm)  
CSD17484F4  
PICOSTAR  
PICOSTAR  
YJJ  
YJJ  
3
3
3000  
250  
220.0  
220.0  
220.0  
220.0  
35.0  
35.0  
CSD17484F4T  
Pack Materials-Page 2  

重要声明和免责声明  
TI“
按原样
”
提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,  
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用
TI
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